1 /* 2 * QEMU generic PowerPC hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "cpu.h" 26 #include "hw/hw.h" 27 #include "hw/ppc/ppc.h" 28 #include "hw/ppc/ppc_e500.h" 29 #include "qemu/timer.h" 30 #include "sysemu/sysemu.h" 31 #include "sysemu/cpus.h" 32 #include "qemu/log.h" 33 #include "qemu/error-report.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_ppc.h" 36 #include "trace.h" 37 38 //#define PPC_DEBUG_IRQ 39 //#define PPC_DEBUG_TB 40 41 #ifdef PPC_DEBUG_IRQ 42 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) 43 #else 44 # define LOG_IRQ(...) do { } while (0) 45 #endif 46 47 48 #ifdef PPC_DEBUG_TB 49 # define LOG_TB(...) qemu_log(__VA_ARGS__) 50 #else 51 # define LOG_TB(...) do { } while (0) 52 #endif 53 54 static void cpu_ppc_tb_stop (CPUPPCState *env); 55 static void cpu_ppc_tb_start (CPUPPCState *env); 56 57 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) 58 { 59 CPUState *cs = CPU(cpu); 60 CPUPPCState *env = &cpu->env; 61 unsigned int old_pending; 62 bool locked = false; 63 64 /* We may already have the BQL if coming from the reset path */ 65 if (!qemu_mutex_iothread_locked()) { 66 locked = true; 67 qemu_mutex_lock_iothread(); 68 } 69 70 old_pending = env->pending_interrupts; 71 72 if (level) { 73 env->pending_interrupts |= 1 << n_IRQ; 74 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 75 } else { 76 env->pending_interrupts &= ~(1 << n_IRQ); 77 if (env->pending_interrupts == 0) { 78 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 79 } 80 } 81 82 if (old_pending != env->pending_interrupts) { 83 kvmppc_set_interrupt(cpu, n_IRQ, level); 84 } 85 86 87 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 88 "req %08x\n", __func__, env, n_IRQ, level, 89 env->pending_interrupts, CPU(cpu)->interrupt_request); 90 91 if (locked) { 92 qemu_mutex_unlock_iothread(); 93 } 94 } 95 96 /* PowerPC 6xx / 7xx internal IRQ controller */ 97 static void ppc6xx_set_irq(void *opaque, int pin, int level) 98 { 99 PowerPCCPU *cpu = opaque; 100 CPUPPCState *env = &cpu->env; 101 int cur_level; 102 103 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 104 env, pin, level); 105 cur_level = (env->irq_input_state >> pin) & 1; 106 /* Don't generate spurious events */ 107 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 108 CPUState *cs = CPU(cpu); 109 110 switch (pin) { 111 case PPC6xx_INPUT_TBEN: 112 /* Level sensitive - active high */ 113 LOG_IRQ("%s: %s the time base\n", 114 __func__, level ? "start" : "stop"); 115 if (level) { 116 cpu_ppc_tb_start(env); 117 } else { 118 cpu_ppc_tb_stop(env); 119 } 120 case PPC6xx_INPUT_INT: 121 /* Level sensitive - active high */ 122 LOG_IRQ("%s: set the external IRQ state to %d\n", 123 __func__, level); 124 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 125 break; 126 case PPC6xx_INPUT_SMI: 127 /* Level sensitive - active high */ 128 LOG_IRQ("%s: set the SMI IRQ state to %d\n", 129 __func__, level); 130 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); 131 break; 132 case PPC6xx_INPUT_MCP: 133 /* Negative edge sensitive */ 134 /* XXX: TODO: actual reaction may depends on HID0 status 135 * 603/604/740/750: check HID0[EMCP] 136 */ 137 if (cur_level == 1 && level == 0) { 138 LOG_IRQ("%s: raise machine check state\n", 139 __func__); 140 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 141 } 142 break; 143 case PPC6xx_INPUT_CKSTP_IN: 144 /* Level sensitive - active low */ 145 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 146 /* XXX: Note that the only way to restart the CPU is to reset it */ 147 if (level) { 148 LOG_IRQ("%s: stop the CPU\n", __func__); 149 cs->halted = 1; 150 } 151 break; 152 case PPC6xx_INPUT_HRESET: 153 /* Level sensitive - active low */ 154 if (level) { 155 LOG_IRQ("%s: reset the CPU\n", __func__); 156 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 157 } 158 break; 159 case PPC6xx_INPUT_SRESET: 160 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 161 __func__, level); 162 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 163 break; 164 default: 165 /* Unknown pin - do nothing */ 166 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 167 return; 168 } 169 if (level) 170 env->irq_input_state |= 1 << pin; 171 else 172 env->irq_input_state &= ~(1 << pin); 173 } 174 } 175 176 void ppc6xx_irq_init(PowerPCCPU *cpu) 177 { 178 CPUPPCState *env = &cpu->env; 179 180 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, 181 PPC6xx_INPUT_NB); 182 } 183 184 #if defined(TARGET_PPC64) 185 /* PowerPC 970 internal IRQ controller */ 186 static void ppc970_set_irq(void *opaque, int pin, int level) 187 { 188 PowerPCCPU *cpu = opaque; 189 CPUPPCState *env = &cpu->env; 190 int cur_level; 191 192 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 193 env, pin, level); 194 cur_level = (env->irq_input_state >> pin) & 1; 195 /* Don't generate spurious events */ 196 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 197 CPUState *cs = CPU(cpu); 198 199 switch (pin) { 200 case PPC970_INPUT_INT: 201 /* Level sensitive - active high */ 202 LOG_IRQ("%s: set the external IRQ state to %d\n", 203 __func__, level); 204 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 205 break; 206 case PPC970_INPUT_THINT: 207 /* Level sensitive - active high */ 208 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, 209 level); 210 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); 211 break; 212 case PPC970_INPUT_MCP: 213 /* Negative edge sensitive */ 214 /* XXX: TODO: actual reaction may depends on HID0 status 215 * 603/604/740/750: check HID0[EMCP] 216 */ 217 if (cur_level == 1 && level == 0) { 218 LOG_IRQ("%s: raise machine check state\n", 219 __func__); 220 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 221 } 222 break; 223 case PPC970_INPUT_CKSTP: 224 /* Level sensitive - active low */ 225 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 226 if (level) { 227 LOG_IRQ("%s: stop the CPU\n", __func__); 228 cs->halted = 1; 229 } else { 230 LOG_IRQ("%s: restart the CPU\n", __func__); 231 cs->halted = 0; 232 qemu_cpu_kick(cs); 233 } 234 break; 235 case PPC970_INPUT_HRESET: 236 /* Level sensitive - active low */ 237 if (level) { 238 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 239 } 240 break; 241 case PPC970_INPUT_SRESET: 242 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 243 __func__, level); 244 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 245 break; 246 case PPC970_INPUT_TBEN: 247 LOG_IRQ("%s: set the TBEN state to %d\n", __func__, 248 level); 249 /* XXX: TODO */ 250 break; 251 default: 252 /* Unknown pin - do nothing */ 253 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 254 return; 255 } 256 if (level) 257 env->irq_input_state |= 1 << pin; 258 else 259 env->irq_input_state &= ~(1 << pin); 260 } 261 } 262 263 void ppc970_irq_init(PowerPCCPU *cpu) 264 { 265 CPUPPCState *env = &cpu->env; 266 267 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, 268 PPC970_INPUT_NB); 269 } 270 271 /* POWER7 internal IRQ controller */ 272 static void power7_set_irq(void *opaque, int pin, int level) 273 { 274 PowerPCCPU *cpu = opaque; 275 CPUPPCState *env = &cpu->env; 276 277 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 278 env, pin, level); 279 280 switch (pin) { 281 case POWER7_INPUT_INT: 282 /* Level sensitive - active high */ 283 LOG_IRQ("%s: set the external IRQ state to %d\n", 284 __func__, level); 285 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 286 break; 287 default: 288 /* Unknown pin - do nothing */ 289 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 290 return; 291 } 292 if (level) { 293 env->irq_input_state |= 1 << pin; 294 } else { 295 env->irq_input_state &= ~(1 << pin); 296 } 297 } 298 299 void ppcPOWER7_irq_init(PowerPCCPU *cpu) 300 { 301 CPUPPCState *env = &cpu->env; 302 303 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, 304 POWER7_INPUT_NB); 305 } 306 307 /* POWER9 internal IRQ controller */ 308 static void power9_set_irq(void *opaque, int pin, int level) 309 { 310 PowerPCCPU *cpu = opaque; 311 CPUPPCState *env = &cpu->env; 312 313 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 314 env, pin, level); 315 316 switch (pin) { 317 case POWER9_INPUT_INT: 318 /* Level sensitive - active high */ 319 LOG_IRQ("%s: set the external IRQ state to %d\n", 320 __func__, level); 321 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 322 break; 323 case POWER9_INPUT_HINT: 324 /* Level sensitive - active high */ 325 LOG_IRQ("%s: set the external IRQ state to %d\n", 326 __func__, level); 327 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level); 328 break; 329 default: 330 /* Unknown pin - do nothing */ 331 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 332 return; 333 } 334 if (level) { 335 env->irq_input_state |= 1 << pin; 336 } else { 337 env->irq_input_state &= ~(1 << pin); 338 } 339 } 340 341 void ppcPOWER9_irq_init(PowerPCCPU *cpu) 342 { 343 CPUPPCState *env = &cpu->env; 344 345 env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu, 346 POWER9_INPUT_NB); 347 } 348 #endif /* defined(TARGET_PPC64) */ 349 350 void ppc40x_core_reset(PowerPCCPU *cpu) 351 { 352 CPUPPCState *env = &cpu->env; 353 target_ulong dbsr; 354 355 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n"); 356 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 357 dbsr = env->spr[SPR_40x_DBSR]; 358 dbsr &= ~0x00000300; 359 dbsr |= 0x00000100; 360 env->spr[SPR_40x_DBSR] = dbsr; 361 } 362 363 void ppc40x_chip_reset(PowerPCCPU *cpu) 364 { 365 CPUPPCState *env = &cpu->env; 366 target_ulong dbsr; 367 368 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n"); 369 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 370 /* XXX: TODO reset all internal peripherals */ 371 dbsr = env->spr[SPR_40x_DBSR]; 372 dbsr &= ~0x00000300; 373 dbsr |= 0x00000200; 374 env->spr[SPR_40x_DBSR] = dbsr; 375 } 376 377 void ppc40x_system_reset(PowerPCCPU *cpu) 378 { 379 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n"); 380 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 381 } 382 383 void store_40x_dbcr0(CPUPPCState *env, uint32_t val) 384 { 385 PowerPCCPU *cpu = env_archcpu(env); 386 387 switch ((val >> 28) & 0x3) { 388 case 0x0: 389 /* No action */ 390 break; 391 case 0x1: 392 /* Core reset */ 393 ppc40x_core_reset(cpu); 394 break; 395 case 0x2: 396 /* Chip reset */ 397 ppc40x_chip_reset(cpu); 398 break; 399 case 0x3: 400 /* System reset */ 401 ppc40x_system_reset(cpu); 402 break; 403 } 404 } 405 406 /* PowerPC 40x internal IRQ controller */ 407 static void ppc40x_set_irq(void *opaque, int pin, int level) 408 { 409 PowerPCCPU *cpu = opaque; 410 CPUPPCState *env = &cpu->env; 411 int cur_level; 412 413 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 414 env, pin, level); 415 cur_level = (env->irq_input_state >> pin) & 1; 416 /* Don't generate spurious events */ 417 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 418 CPUState *cs = CPU(cpu); 419 420 switch (pin) { 421 case PPC40x_INPUT_RESET_SYS: 422 if (level) { 423 LOG_IRQ("%s: reset the PowerPC system\n", 424 __func__); 425 ppc40x_system_reset(cpu); 426 } 427 break; 428 case PPC40x_INPUT_RESET_CHIP: 429 if (level) { 430 LOG_IRQ("%s: reset the PowerPC chip\n", __func__); 431 ppc40x_chip_reset(cpu); 432 } 433 break; 434 case PPC40x_INPUT_RESET_CORE: 435 /* XXX: TODO: update DBSR[MRR] */ 436 if (level) { 437 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 438 ppc40x_core_reset(cpu); 439 } 440 break; 441 case PPC40x_INPUT_CINT: 442 /* Level sensitive - active high */ 443 LOG_IRQ("%s: set the critical IRQ state to %d\n", 444 __func__, level); 445 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 446 break; 447 case PPC40x_INPUT_INT: 448 /* Level sensitive - active high */ 449 LOG_IRQ("%s: set the external IRQ state to %d\n", 450 __func__, level); 451 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 452 break; 453 case PPC40x_INPUT_HALT: 454 /* Level sensitive - active low */ 455 if (level) { 456 LOG_IRQ("%s: stop the CPU\n", __func__); 457 cs->halted = 1; 458 } else { 459 LOG_IRQ("%s: restart the CPU\n", __func__); 460 cs->halted = 0; 461 qemu_cpu_kick(cs); 462 } 463 break; 464 case PPC40x_INPUT_DEBUG: 465 /* Level sensitive - active high */ 466 LOG_IRQ("%s: set the debug pin state to %d\n", 467 __func__, level); 468 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 469 break; 470 default: 471 /* Unknown pin - do nothing */ 472 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 473 return; 474 } 475 if (level) 476 env->irq_input_state |= 1 << pin; 477 else 478 env->irq_input_state &= ~(1 << pin); 479 } 480 } 481 482 void ppc40x_irq_init(PowerPCCPU *cpu) 483 { 484 CPUPPCState *env = &cpu->env; 485 486 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, 487 cpu, PPC40x_INPUT_NB); 488 } 489 490 /* PowerPC E500 internal IRQ controller */ 491 static void ppce500_set_irq(void *opaque, int pin, int level) 492 { 493 PowerPCCPU *cpu = opaque; 494 CPUPPCState *env = &cpu->env; 495 int cur_level; 496 497 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 498 env, pin, level); 499 cur_level = (env->irq_input_state >> pin) & 1; 500 /* Don't generate spurious events */ 501 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 502 switch (pin) { 503 case PPCE500_INPUT_MCK: 504 if (level) { 505 LOG_IRQ("%s: reset the PowerPC system\n", 506 __func__); 507 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 508 } 509 break; 510 case PPCE500_INPUT_RESET_CORE: 511 if (level) { 512 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 513 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); 514 } 515 break; 516 case PPCE500_INPUT_CINT: 517 /* Level sensitive - active high */ 518 LOG_IRQ("%s: set the critical IRQ state to %d\n", 519 __func__, level); 520 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 521 break; 522 case PPCE500_INPUT_INT: 523 /* Level sensitive - active high */ 524 LOG_IRQ("%s: set the core IRQ state to %d\n", 525 __func__, level); 526 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 527 break; 528 case PPCE500_INPUT_DEBUG: 529 /* Level sensitive - active high */ 530 LOG_IRQ("%s: set the debug pin state to %d\n", 531 __func__, level); 532 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 533 break; 534 default: 535 /* Unknown pin - do nothing */ 536 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 537 return; 538 } 539 if (level) 540 env->irq_input_state |= 1 << pin; 541 else 542 env->irq_input_state &= ~(1 << pin); 543 } 544 } 545 546 void ppce500_irq_init(PowerPCCPU *cpu) 547 { 548 CPUPPCState *env = &cpu->env; 549 550 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, 551 cpu, PPCE500_INPUT_NB); 552 } 553 554 /* Enable or Disable the E500 EPR capability */ 555 void ppce500_set_mpic_proxy(bool enabled) 556 { 557 CPUState *cs; 558 559 CPU_FOREACH(cs) { 560 PowerPCCPU *cpu = POWERPC_CPU(cs); 561 562 cpu->env.mpic_proxy = enabled; 563 if (kvm_enabled()) { 564 kvmppc_set_mpic_proxy(cpu, enabled); 565 } 566 } 567 } 568 569 /*****************************************************************************/ 570 /* PowerPC time base and decrementer emulation */ 571 572 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) 573 { 574 /* TB time in tb periods */ 575 return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset; 576 } 577 578 uint64_t cpu_ppc_load_tbl (CPUPPCState *env) 579 { 580 ppc_tb_t *tb_env = env->tb_env; 581 uint64_t tb; 582 583 if (kvm_enabled()) { 584 return env->spr[SPR_TBL]; 585 } 586 587 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 588 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 589 590 return tb; 591 } 592 593 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) 594 { 595 ppc_tb_t *tb_env = env->tb_env; 596 uint64_t tb; 597 598 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 599 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 600 601 return tb >> 32; 602 } 603 604 uint32_t cpu_ppc_load_tbu (CPUPPCState *env) 605 { 606 if (kvm_enabled()) { 607 return env->spr[SPR_TBU]; 608 } 609 610 return _cpu_ppc_load_tbu(env); 611 } 612 613 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, 614 int64_t *tb_offsetp, uint64_t value) 615 { 616 *tb_offsetp = value - 617 muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND); 618 619 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", 620 __func__, value, *tb_offsetp); 621 } 622 623 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) 624 { 625 ppc_tb_t *tb_env = env->tb_env; 626 uint64_t tb; 627 628 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 629 tb &= 0xFFFFFFFF00000000ULL; 630 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 631 &tb_env->tb_offset, tb | (uint64_t)value); 632 } 633 634 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) 635 { 636 ppc_tb_t *tb_env = env->tb_env; 637 uint64_t tb; 638 639 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 640 tb &= 0x00000000FFFFFFFFULL; 641 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 642 &tb_env->tb_offset, ((uint64_t)value << 32) | tb); 643 } 644 645 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) 646 { 647 _cpu_ppc_store_tbu(env, value); 648 } 649 650 uint64_t cpu_ppc_load_atbl (CPUPPCState *env) 651 { 652 ppc_tb_t *tb_env = env->tb_env; 653 uint64_t tb; 654 655 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 656 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 657 658 return tb; 659 } 660 661 uint32_t cpu_ppc_load_atbu (CPUPPCState *env) 662 { 663 ppc_tb_t *tb_env = env->tb_env; 664 uint64_t tb; 665 666 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 667 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 668 669 return tb >> 32; 670 } 671 672 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) 673 { 674 ppc_tb_t *tb_env = env->tb_env; 675 uint64_t tb; 676 677 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 678 tb &= 0xFFFFFFFF00000000ULL; 679 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 680 &tb_env->atb_offset, tb | (uint64_t)value); 681 } 682 683 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) 684 { 685 ppc_tb_t *tb_env = env->tb_env; 686 uint64_t tb; 687 688 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 689 tb &= 0x00000000FFFFFFFFULL; 690 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 691 &tb_env->atb_offset, ((uint64_t)value << 32) | tb); 692 } 693 694 static void cpu_ppc_tb_stop (CPUPPCState *env) 695 { 696 ppc_tb_t *tb_env = env->tb_env; 697 uint64_t tb, atb, vmclk; 698 699 /* If the time base is already frozen, do nothing */ 700 if (tb_env->tb_freq != 0) { 701 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 702 /* Get the time base */ 703 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); 704 /* Get the alternate time base */ 705 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); 706 /* Store the time base value (ie compute the current offset) */ 707 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 708 /* Store the alternate time base value (compute the current offset) */ 709 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 710 /* Set the time base frequency to zero */ 711 tb_env->tb_freq = 0; 712 /* Now, the time bases are frozen to tb_offset / atb_offset value */ 713 } 714 } 715 716 static void cpu_ppc_tb_start (CPUPPCState *env) 717 { 718 ppc_tb_t *tb_env = env->tb_env; 719 uint64_t tb, atb, vmclk; 720 721 /* If the time base is not frozen, do nothing */ 722 if (tb_env->tb_freq == 0) { 723 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 724 /* Get the time base from tb_offset */ 725 tb = tb_env->tb_offset; 726 /* Get the alternate time base from atb_offset */ 727 atb = tb_env->atb_offset; 728 /* Restore the tb frequency from the decrementer frequency */ 729 tb_env->tb_freq = tb_env->decr_freq; 730 /* Store the time base value */ 731 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 732 /* Store the alternate time base value */ 733 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 734 } 735 } 736 737 bool ppc_decr_clear_on_delivery(CPUPPCState *env) 738 { 739 ppc_tb_t *tb_env = env->tb_env; 740 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; 741 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); 742 } 743 744 static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) 745 { 746 ppc_tb_t *tb_env = env->tb_env; 747 int64_t decr, diff; 748 749 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 750 if (diff >= 0) { 751 decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 752 } else if (tb_env->flags & PPC_TIMER_BOOKE) { 753 decr = 0; 754 } else { 755 decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 756 } 757 LOG_TB("%s: %016" PRIx64 "\n", __func__, decr); 758 759 return decr; 760 } 761 762 target_ulong cpu_ppc_load_decr(CPUPPCState *env) 763 { 764 ppc_tb_t *tb_env = env->tb_env; 765 uint64_t decr; 766 767 if (kvm_enabled()) { 768 return env->spr[SPR_DECR]; 769 } 770 771 decr = _cpu_ppc_load_decr(env, tb_env->decr_next); 772 773 /* 774 * If large decrementer is enabled then the decrementer is signed extened 775 * to 64 bits, otherwise it is a 32 bit value. 776 */ 777 if (env->spr[SPR_LPCR] & LPCR_LD) { 778 return decr; 779 } 780 return (uint32_t) decr; 781 } 782 783 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) 784 { 785 PowerPCCPU *cpu = env_archcpu(env); 786 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 787 ppc_tb_t *tb_env = env->tb_env; 788 uint64_t hdecr; 789 790 hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next); 791 792 /* 793 * If we have a large decrementer (POWER9 or later) then hdecr is sign 794 * extended to 64 bits, otherwise it is 32 bits. 795 */ 796 if (pcc->lrg_decr_bits > 32) { 797 return hdecr; 798 } 799 return (uint32_t) hdecr; 800 } 801 802 uint64_t cpu_ppc_load_purr (CPUPPCState *env) 803 { 804 ppc_tb_t *tb_env = env->tb_env; 805 uint64_t diff; 806 807 diff = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - tb_env->purr_start; 808 809 return tb_env->purr_load + 810 muldiv64(diff, tb_env->tb_freq, NANOSECONDS_PER_SECOND); 811 } 812 813 /* When decrementer expires, 814 * all we need to do is generate or queue a CPU exception 815 */ 816 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) 817 { 818 /* Raise it */ 819 LOG_TB("raise decrementer exception\n"); 820 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); 821 } 822 823 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) 824 { 825 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); 826 } 827 828 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) 829 { 830 CPUPPCState *env = &cpu->env; 831 832 /* Raise it */ 833 LOG_TB("raise hv decrementer exception\n"); 834 835 /* The architecture specifies that we don't deliver HDEC 836 * interrupts in a PM state. Not only they don't cause a 837 * wakeup but they also get effectively discarded. 838 */ 839 if (!env->resume_as_sreset) { 840 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); 841 } 842 } 843 844 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) 845 { 846 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); 847 } 848 849 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, 850 QEMUTimer *timer, 851 void (*raise_excp)(void *), 852 void (*lower_excp)(PowerPCCPU *), 853 target_ulong decr, target_ulong value, 854 int nr_bits) 855 { 856 CPUPPCState *env = &cpu->env; 857 ppc_tb_t *tb_env = env->tb_env; 858 uint64_t now, next; 859 bool negative; 860 861 /* Truncate value to decr_width and sign extend for simplicity */ 862 value &= ((1ULL << nr_bits) - 1); 863 negative = !!(value & (1ULL << (nr_bits - 1))); 864 if (negative) { 865 value |= (0xFFFFFFFFULL << nr_bits); 866 } 867 868 LOG_TB("%s: " TARGET_FMT_lx " => " TARGET_FMT_lx "\n", __func__, 869 decr, value); 870 871 if (kvm_enabled()) { 872 /* KVM handles decrementer exceptions, we don't need our own timer */ 873 return; 874 } 875 876 /* 877 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC 878 * interrupt. 879 * 880 * If we get a really small DEC value, we can assume that by the time we 881 * handled it we should inject an interrupt already. 882 * 883 * On MSB level based DEC implementations the MSB always means the interrupt 884 * is pending, so raise it on those. 885 * 886 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers 887 * an edge interrupt, so raise it here too. 888 */ 889 if ((value < 3) || 890 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && negative) || 891 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && negative 892 && !(decr & (1ULL << (nr_bits - 1))))) { 893 (*raise_excp)(cpu); 894 return; 895 } 896 897 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ 898 if (!negative && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { 899 (*lower_excp)(cpu); 900 } 901 902 /* Calculate the next timer event */ 903 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 904 next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 905 *nextp = next; 906 907 /* Adjust timer */ 908 timer_mod(timer, next); 909 } 910 911 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, 912 target_ulong value, int nr_bits) 913 { 914 ppc_tb_t *tb_env = cpu->env.tb_env; 915 916 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, 917 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr, 918 value, nr_bits); 919 } 920 921 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) 922 { 923 PowerPCCPU *cpu = env_archcpu(env); 924 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 925 int nr_bits = 32; 926 927 if (env->spr[SPR_LPCR] & LPCR_LD) { 928 nr_bits = pcc->lrg_decr_bits; 929 } 930 931 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits); 932 } 933 934 static void cpu_ppc_decr_cb(void *opaque) 935 { 936 PowerPCCPU *cpu = opaque; 937 938 cpu_ppc_decr_excp(cpu); 939 } 940 941 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr, 942 target_ulong value, int nr_bits) 943 { 944 ppc_tb_t *tb_env = cpu->env.tb_env; 945 946 if (tb_env->hdecr_timer != NULL) { 947 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, 948 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, 949 hdecr, value, nr_bits); 950 } 951 } 952 953 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) 954 { 955 PowerPCCPU *cpu = env_archcpu(env); 956 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 957 958 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 959 pcc->lrg_decr_bits); 960 } 961 962 static void cpu_ppc_hdecr_cb(void *opaque) 963 { 964 PowerPCCPU *cpu = opaque; 965 966 cpu_ppc_hdecr_excp(cpu); 967 } 968 969 static void cpu_ppc_store_purr(PowerPCCPU *cpu, uint64_t value) 970 { 971 ppc_tb_t *tb_env = cpu->env.tb_env; 972 973 tb_env->purr_load = value; 974 tb_env->purr_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 975 } 976 977 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) 978 { 979 CPUPPCState *env = opaque; 980 PowerPCCPU *cpu = env_archcpu(env); 981 ppc_tb_t *tb_env = env->tb_env; 982 983 tb_env->tb_freq = freq; 984 tb_env->decr_freq = freq; 985 /* There is a bug in Linux 2.4 kernels: 986 * if a decrementer exception is pending when it enables msr_ee at startup, 987 * it's not ready to handle it... 988 */ 989 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 990 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 991 cpu_ppc_store_purr(cpu, 0x0000000000000000ULL); 992 } 993 994 static void timebase_save(PPCTimebase *tb) 995 { 996 uint64_t ticks = cpu_get_host_ticks(); 997 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 998 999 if (!first_ppc_cpu->env.tb_env) { 1000 error_report("No timebase object"); 1001 return; 1002 } 1003 1004 /* not used anymore, we keep it for compatibility */ 1005 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); 1006 /* 1007 * tb_offset is only expected to be changed by QEMU so 1008 * there is no need to update it from KVM here 1009 */ 1010 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; 1011 } 1012 1013 static void timebase_load(PPCTimebase *tb) 1014 { 1015 CPUState *cpu; 1016 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1017 int64_t tb_off_adj, tb_off; 1018 unsigned long freq; 1019 1020 if (!first_ppc_cpu->env.tb_env) { 1021 error_report("No timebase object"); 1022 return; 1023 } 1024 1025 freq = first_ppc_cpu->env.tb_env->tb_freq; 1026 1027 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); 1028 1029 tb_off = first_ppc_cpu->env.tb_env->tb_offset; 1030 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, 1031 (tb_off_adj - tb_off) / freq); 1032 1033 /* Set new offset to all CPUs */ 1034 CPU_FOREACH(cpu) { 1035 PowerPCCPU *pcpu = POWERPC_CPU(cpu); 1036 pcpu->env.tb_env->tb_offset = tb_off_adj; 1037 #if defined(CONFIG_KVM) 1038 kvm_set_one_reg(cpu, KVM_REG_PPC_TB_OFFSET, 1039 &pcpu->env.tb_env->tb_offset); 1040 #endif 1041 } 1042 } 1043 1044 void cpu_ppc_clock_vm_state_change(void *opaque, int running, 1045 RunState state) 1046 { 1047 PPCTimebase *tb = opaque; 1048 1049 if (running) { 1050 timebase_load(tb); 1051 } else { 1052 timebase_save(tb); 1053 } 1054 } 1055 1056 /* 1057 * When migrating, read the clock just before migration, 1058 * so that the guest clock counts during the events 1059 * between: 1060 * 1061 * * vm_stop() 1062 * * 1063 * * pre_save() 1064 * 1065 * This reduces clock difference on migration from 5s 1066 * to 0.1s (when max_downtime == 5s), because sending the 1067 * final pages of memory (which happens between vm_stop() 1068 * and pre_save()) takes max_downtime. 1069 */ 1070 static int timebase_pre_save(void *opaque) 1071 { 1072 PPCTimebase *tb = opaque; 1073 1074 timebase_save(tb); 1075 1076 return 0; 1077 } 1078 1079 const VMStateDescription vmstate_ppc_timebase = { 1080 .name = "timebase", 1081 .version_id = 1, 1082 .minimum_version_id = 1, 1083 .minimum_version_id_old = 1, 1084 .pre_save = timebase_pre_save, 1085 .fields = (VMStateField []) { 1086 VMSTATE_UINT64(guest_timebase, PPCTimebase), 1087 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), 1088 VMSTATE_END_OF_LIST() 1089 }, 1090 }; 1091 1092 /* Set up (once) timebase frequency (in Hz) */ 1093 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) 1094 { 1095 PowerPCCPU *cpu = env_archcpu(env); 1096 ppc_tb_t *tb_env; 1097 1098 tb_env = g_malloc0(sizeof(ppc_tb_t)); 1099 env->tb_env = tb_env; 1100 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1101 if (is_book3s_arch2x(env)) { 1102 /* All Book3S 64bit CPUs implement level based DEC logic */ 1103 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; 1104 } 1105 /* Create new timer */ 1106 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); 1107 if (env->has_hv_mode) { 1108 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, 1109 cpu); 1110 } else { 1111 tb_env->hdecr_timer = NULL; 1112 } 1113 cpu_ppc_set_tb_clk(env, freq); 1114 1115 return &cpu_ppc_set_tb_clk; 1116 } 1117 1118 /* Specific helpers for POWER & PowerPC 601 RTC */ 1119 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) 1120 { 1121 _cpu_ppc_store_tbu(env, value); 1122 } 1123 1124 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) 1125 { 1126 return _cpu_ppc_load_tbu(env); 1127 } 1128 1129 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) 1130 { 1131 cpu_ppc_store_tbl(env, value & 0x3FFFFF80); 1132 } 1133 1134 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) 1135 { 1136 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1137 } 1138 1139 /*****************************************************************************/ 1140 /* PowerPC 40x timers */ 1141 1142 /* PIT, FIT & WDT */ 1143 typedef struct ppc40x_timer_t ppc40x_timer_t; 1144 struct ppc40x_timer_t { 1145 uint64_t pit_reload; /* PIT auto-reload value */ 1146 uint64_t fit_next; /* Tick for next FIT interrupt */ 1147 QEMUTimer *fit_timer; 1148 uint64_t wdt_next; /* Tick for next WDT interrupt */ 1149 QEMUTimer *wdt_timer; 1150 1151 /* 405 have the PIT, 440 have a DECR. */ 1152 unsigned int decr_excp; 1153 }; 1154 1155 /* Fixed interval timer */ 1156 static void cpu_4xx_fit_cb (void *opaque) 1157 { 1158 PowerPCCPU *cpu; 1159 CPUPPCState *env; 1160 ppc_tb_t *tb_env; 1161 ppc40x_timer_t *ppc40x_timer; 1162 uint64_t now, next; 1163 1164 env = opaque; 1165 cpu = env_archcpu(env); 1166 tb_env = env->tb_env; 1167 ppc40x_timer = tb_env->opaque; 1168 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1169 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { 1170 case 0: 1171 next = 1 << 9; 1172 break; 1173 case 1: 1174 next = 1 << 13; 1175 break; 1176 case 2: 1177 next = 1 << 17; 1178 break; 1179 case 3: 1180 next = 1 << 21; 1181 break; 1182 default: 1183 /* Cannot occur, but makes gcc happy */ 1184 return; 1185 } 1186 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq); 1187 if (next == now) 1188 next++; 1189 timer_mod(ppc40x_timer->fit_timer, next); 1190 env->spr[SPR_40x_TSR] |= 1 << 26; 1191 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { 1192 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); 1193 } 1194 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1195 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), 1196 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1197 } 1198 1199 /* Programmable interval timer */ 1200 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) 1201 { 1202 ppc40x_timer_t *ppc40x_timer; 1203 uint64_t now, next; 1204 1205 ppc40x_timer = tb_env->opaque; 1206 if (ppc40x_timer->pit_reload <= 1 || 1207 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || 1208 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { 1209 /* Stop PIT */ 1210 LOG_TB("%s: stop PIT\n", __func__); 1211 timer_del(tb_env->decr_timer); 1212 } else { 1213 LOG_TB("%s: start PIT %016" PRIx64 "\n", 1214 __func__, ppc40x_timer->pit_reload); 1215 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1216 next = now + muldiv64(ppc40x_timer->pit_reload, 1217 NANOSECONDS_PER_SECOND, tb_env->decr_freq); 1218 if (is_excp) 1219 next += tb_env->decr_next - now; 1220 if (next == now) 1221 next++; 1222 timer_mod(tb_env->decr_timer, next); 1223 tb_env->decr_next = next; 1224 } 1225 } 1226 1227 static void cpu_4xx_pit_cb (void *opaque) 1228 { 1229 PowerPCCPU *cpu; 1230 CPUPPCState *env; 1231 ppc_tb_t *tb_env; 1232 ppc40x_timer_t *ppc40x_timer; 1233 1234 env = opaque; 1235 cpu = env_archcpu(env); 1236 tb_env = env->tb_env; 1237 ppc40x_timer = tb_env->opaque; 1238 env->spr[SPR_40x_TSR] |= 1 << 27; 1239 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { 1240 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); 1241 } 1242 start_stop_pit(env, tb_env, 1); 1243 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " 1244 "%016" PRIx64 "\n", __func__, 1245 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), 1246 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), 1247 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 1248 ppc40x_timer->pit_reload); 1249 } 1250 1251 /* Watchdog timer */ 1252 static void cpu_4xx_wdt_cb (void *opaque) 1253 { 1254 PowerPCCPU *cpu; 1255 CPUPPCState *env; 1256 ppc_tb_t *tb_env; 1257 ppc40x_timer_t *ppc40x_timer; 1258 uint64_t now, next; 1259 1260 env = opaque; 1261 cpu = env_archcpu(env); 1262 tb_env = env->tb_env; 1263 ppc40x_timer = tb_env->opaque; 1264 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1265 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { 1266 case 0: 1267 next = 1 << 17; 1268 break; 1269 case 1: 1270 next = 1 << 21; 1271 break; 1272 case 2: 1273 next = 1 << 25; 1274 break; 1275 case 3: 1276 next = 1 << 29; 1277 break; 1278 default: 1279 /* Cannot occur, but makes gcc happy */ 1280 return; 1281 } 1282 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 1283 if (next == now) 1284 next++; 1285 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1286 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1287 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { 1288 case 0x0: 1289 case 0x1: 1290 timer_mod(ppc40x_timer->wdt_timer, next); 1291 ppc40x_timer->wdt_next = next; 1292 env->spr[SPR_40x_TSR] |= 1U << 31; 1293 break; 1294 case 0x2: 1295 timer_mod(ppc40x_timer->wdt_timer, next); 1296 ppc40x_timer->wdt_next = next; 1297 env->spr[SPR_40x_TSR] |= 1 << 30; 1298 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { 1299 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); 1300 } 1301 break; 1302 case 0x3: 1303 env->spr[SPR_40x_TSR] &= ~0x30000000; 1304 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; 1305 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { 1306 case 0x0: 1307 /* No reset */ 1308 break; 1309 case 0x1: /* Core reset */ 1310 ppc40x_core_reset(cpu); 1311 break; 1312 case 0x2: /* Chip reset */ 1313 ppc40x_chip_reset(cpu); 1314 break; 1315 case 0x3: /* System reset */ 1316 ppc40x_system_reset(cpu); 1317 break; 1318 } 1319 } 1320 } 1321 1322 void store_40x_pit (CPUPPCState *env, target_ulong val) 1323 { 1324 ppc_tb_t *tb_env; 1325 ppc40x_timer_t *ppc40x_timer; 1326 1327 tb_env = env->tb_env; 1328 ppc40x_timer = tb_env->opaque; 1329 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); 1330 ppc40x_timer->pit_reload = val; 1331 start_stop_pit(env, tb_env, 0); 1332 } 1333 1334 target_ulong load_40x_pit (CPUPPCState *env) 1335 { 1336 return cpu_ppc_load_decr(env); 1337 } 1338 1339 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) 1340 { 1341 CPUPPCState *env = opaque; 1342 ppc_tb_t *tb_env = env->tb_env; 1343 1344 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, 1345 freq); 1346 tb_env->tb_freq = freq; 1347 tb_env->decr_freq = freq; 1348 /* XXX: we should also update all timers */ 1349 } 1350 1351 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, 1352 unsigned int decr_excp) 1353 { 1354 ppc_tb_t *tb_env; 1355 ppc40x_timer_t *ppc40x_timer; 1356 1357 tb_env = g_malloc0(sizeof(ppc_tb_t)); 1358 env->tb_env = tb_env; 1359 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1360 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); 1361 tb_env->tb_freq = freq; 1362 tb_env->decr_freq = freq; 1363 tb_env->opaque = ppc40x_timer; 1364 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); 1365 if (ppc40x_timer != NULL) { 1366 /* We use decr timer for PIT */ 1367 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env); 1368 ppc40x_timer->fit_timer = 1369 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env); 1370 ppc40x_timer->wdt_timer = 1371 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env); 1372 ppc40x_timer->decr_excp = decr_excp; 1373 } 1374 1375 return &ppc_40x_set_tb_clk; 1376 } 1377 1378 /*****************************************************************************/ 1379 /* Embedded PowerPC Device Control Registers */ 1380 typedef struct ppc_dcrn_t ppc_dcrn_t; 1381 struct ppc_dcrn_t { 1382 dcr_read_cb dcr_read; 1383 dcr_write_cb dcr_write; 1384 void *opaque; 1385 }; 1386 1387 /* XXX: on 460, DCR addresses are 32 bits wide, 1388 * using DCRIPR to get the 22 upper bits of the DCR address 1389 */ 1390 #define DCRN_NB 1024 1391 struct ppc_dcr_t { 1392 ppc_dcrn_t dcrn[DCRN_NB]; 1393 int (*read_error)(int dcrn); 1394 int (*write_error)(int dcrn); 1395 }; 1396 1397 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1398 { 1399 ppc_dcrn_t *dcr; 1400 1401 if (dcrn < 0 || dcrn >= DCRN_NB) 1402 goto error; 1403 dcr = &dcr_env->dcrn[dcrn]; 1404 if (dcr->dcr_read == NULL) 1405 goto error; 1406 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); 1407 1408 return 0; 1409 1410 error: 1411 if (dcr_env->read_error != NULL) 1412 return (*dcr_env->read_error)(dcrn); 1413 1414 return -1; 1415 } 1416 1417 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1418 { 1419 ppc_dcrn_t *dcr; 1420 1421 if (dcrn < 0 || dcrn >= DCRN_NB) 1422 goto error; 1423 dcr = &dcr_env->dcrn[dcrn]; 1424 if (dcr->dcr_write == NULL) 1425 goto error; 1426 (*dcr->dcr_write)(dcr->opaque, dcrn, val); 1427 1428 return 0; 1429 1430 error: 1431 if (dcr_env->write_error != NULL) 1432 return (*dcr_env->write_error)(dcrn); 1433 1434 return -1; 1435 } 1436 1437 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, 1438 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 1439 { 1440 ppc_dcr_t *dcr_env; 1441 ppc_dcrn_t *dcr; 1442 1443 dcr_env = env->dcr_env; 1444 if (dcr_env == NULL) 1445 return -1; 1446 if (dcrn < 0 || dcrn >= DCRN_NB) 1447 return -1; 1448 dcr = &dcr_env->dcrn[dcrn]; 1449 if (dcr->opaque != NULL || 1450 dcr->dcr_read != NULL || 1451 dcr->dcr_write != NULL) 1452 return -1; 1453 dcr->opaque = opaque; 1454 dcr->dcr_read = dcr_read; 1455 dcr->dcr_write = dcr_write; 1456 1457 return 0; 1458 } 1459 1460 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), 1461 int (*write_error)(int dcrn)) 1462 { 1463 ppc_dcr_t *dcr_env; 1464 1465 dcr_env = g_malloc0(sizeof(ppc_dcr_t)); 1466 dcr_env->read_error = read_error; 1467 dcr_env->write_error = write_error; 1468 env->dcr_env = dcr_env; 1469 1470 return 0; 1471 } 1472 1473 /*****************************************************************************/ 1474 /* Debug port */ 1475 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) 1476 { 1477 addr &= 0xF; 1478 switch (addr) { 1479 case 0: 1480 printf("%c", val); 1481 break; 1482 case 1: 1483 printf("\n"); 1484 fflush(stdout); 1485 break; 1486 case 2: 1487 printf("Set loglevel to %04" PRIx32 "\n", val); 1488 qemu_set_log(val | 0x100); 1489 break; 1490 } 1491 } 1492 1493 PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 1494 { 1495 CPUState *cs; 1496 1497 CPU_FOREACH(cs) { 1498 PowerPCCPU *cpu = POWERPC_CPU(cs); 1499 CPUPPCState *env = &cpu->env; 1500 1501 if (env->spr_cb[SPR_PIR].default_value == pir) { 1502 return cpu; 1503 } 1504 } 1505 1506 return NULL; 1507 } 1508