1 /* 2 * QEMU generic PowerPC hardware System Emulator 3 * 4 * Copyright (c) 2003-2007 Jocelyn Mayer 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "cpu.h" 27 #include "hw/irq.h" 28 #include "hw/ppc/ppc.h" 29 #include "hw/ppc/ppc_e500.h" 30 #include "qemu/timer.h" 31 #include "sysemu/cpus.h" 32 #include "qemu/log.h" 33 #include "qemu/main-loop.h" 34 #include "qemu/error-report.h" 35 #include "sysemu/kvm.h" 36 #include "sysemu/runstate.h" 37 #include "kvm_ppc.h" 38 #include "migration/vmstate.h" 39 #include "trace.h" 40 41 //#define PPC_DEBUG_IRQ 42 //#define PPC_DEBUG_TB 43 44 #ifdef PPC_DEBUG_IRQ 45 # define LOG_IRQ(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) 46 #else 47 # define LOG_IRQ(...) do { } while (0) 48 #endif 49 50 51 #ifdef PPC_DEBUG_TB 52 # define LOG_TB(...) qemu_log(__VA_ARGS__) 53 #else 54 # define LOG_TB(...) do { } while (0) 55 #endif 56 57 static void cpu_ppc_tb_stop (CPUPPCState *env); 58 static void cpu_ppc_tb_start (CPUPPCState *env); 59 60 void ppc_set_irq(PowerPCCPU *cpu, int n_IRQ, int level) 61 { 62 CPUState *cs = CPU(cpu); 63 CPUPPCState *env = &cpu->env; 64 unsigned int old_pending; 65 bool locked = false; 66 67 /* We may already have the BQL if coming from the reset path */ 68 if (!qemu_mutex_iothread_locked()) { 69 locked = true; 70 qemu_mutex_lock_iothread(); 71 } 72 73 old_pending = env->pending_interrupts; 74 75 if (level) { 76 env->pending_interrupts |= 1 << n_IRQ; 77 cpu_interrupt(cs, CPU_INTERRUPT_HARD); 78 } else { 79 env->pending_interrupts &= ~(1 << n_IRQ); 80 if (env->pending_interrupts == 0) { 81 cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); 82 } 83 } 84 85 if (old_pending != env->pending_interrupts) { 86 kvmppc_set_interrupt(cpu, n_IRQ, level); 87 } 88 89 90 LOG_IRQ("%s: %p n_IRQ %d level %d => pending %08" PRIx32 91 "req %08x\n", __func__, env, n_IRQ, level, 92 env->pending_interrupts, CPU(cpu)->interrupt_request); 93 94 if (locked) { 95 qemu_mutex_unlock_iothread(); 96 } 97 } 98 99 /* PowerPC 6xx / 7xx internal IRQ controller */ 100 static void ppc6xx_set_irq(void *opaque, int pin, int level) 101 { 102 PowerPCCPU *cpu = opaque; 103 CPUPPCState *env = &cpu->env; 104 int cur_level; 105 106 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 107 env, pin, level); 108 cur_level = (env->irq_input_state >> pin) & 1; 109 /* Don't generate spurious events */ 110 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 111 CPUState *cs = CPU(cpu); 112 113 switch (pin) { 114 case PPC6xx_INPUT_TBEN: 115 /* Level sensitive - active high */ 116 LOG_IRQ("%s: %s the time base\n", 117 __func__, level ? "start" : "stop"); 118 if (level) { 119 cpu_ppc_tb_start(env); 120 } else { 121 cpu_ppc_tb_stop(env); 122 } 123 case PPC6xx_INPUT_INT: 124 /* Level sensitive - active high */ 125 LOG_IRQ("%s: set the external IRQ state to %d\n", 126 __func__, level); 127 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 128 break; 129 case PPC6xx_INPUT_SMI: 130 /* Level sensitive - active high */ 131 LOG_IRQ("%s: set the SMI IRQ state to %d\n", 132 __func__, level); 133 ppc_set_irq(cpu, PPC_INTERRUPT_SMI, level); 134 break; 135 case PPC6xx_INPUT_MCP: 136 /* Negative edge sensitive */ 137 /* XXX: TODO: actual reaction may depends on HID0 status 138 * 603/604/740/750: check HID0[EMCP] 139 */ 140 if (cur_level == 1 && level == 0) { 141 LOG_IRQ("%s: raise machine check state\n", 142 __func__); 143 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 144 } 145 break; 146 case PPC6xx_INPUT_CKSTP_IN: 147 /* Level sensitive - active low */ 148 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 149 /* XXX: Note that the only way to restart the CPU is to reset it */ 150 if (level) { 151 LOG_IRQ("%s: stop the CPU\n", __func__); 152 cs->halted = 1; 153 } 154 break; 155 case PPC6xx_INPUT_HRESET: 156 /* Level sensitive - active low */ 157 if (level) { 158 LOG_IRQ("%s: reset the CPU\n", __func__); 159 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 160 } 161 break; 162 case PPC6xx_INPUT_SRESET: 163 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 164 __func__, level); 165 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 166 break; 167 default: 168 /* Unknown pin - do nothing */ 169 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 170 return; 171 } 172 if (level) 173 env->irq_input_state |= 1 << pin; 174 else 175 env->irq_input_state &= ~(1 << pin); 176 } 177 } 178 179 void ppc6xx_irq_init(PowerPCCPU *cpu) 180 { 181 CPUPPCState *env = &cpu->env; 182 183 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, 184 PPC6xx_INPUT_NB); 185 } 186 187 #if defined(TARGET_PPC64) 188 /* PowerPC 970 internal IRQ controller */ 189 static void ppc970_set_irq(void *opaque, int pin, int level) 190 { 191 PowerPCCPU *cpu = opaque; 192 CPUPPCState *env = &cpu->env; 193 int cur_level; 194 195 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 196 env, pin, level); 197 cur_level = (env->irq_input_state >> pin) & 1; 198 /* Don't generate spurious events */ 199 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 200 CPUState *cs = CPU(cpu); 201 202 switch (pin) { 203 case PPC970_INPUT_INT: 204 /* Level sensitive - active high */ 205 LOG_IRQ("%s: set the external IRQ state to %d\n", 206 __func__, level); 207 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 208 break; 209 case PPC970_INPUT_THINT: 210 /* Level sensitive - active high */ 211 LOG_IRQ("%s: set the SMI IRQ state to %d\n", __func__, 212 level); 213 ppc_set_irq(cpu, PPC_INTERRUPT_THERM, level); 214 break; 215 case PPC970_INPUT_MCP: 216 /* Negative edge sensitive */ 217 /* XXX: TODO: actual reaction may depends on HID0 status 218 * 603/604/740/750: check HID0[EMCP] 219 */ 220 if (cur_level == 1 && level == 0) { 221 LOG_IRQ("%s: raise machine check state\n", 222 __func__); 223 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, 1); 224 } 225 break; 226 case PPC970_INPUT_CKSTP: 227 /* Level sensitive - active low */ 228 /* XXX: TODO: relay the signal to CKSTP_OUT pin */ 229 if (level) { 230 LOG_IRQ("%s: stop the CPU\n", __func__); 231 cs->halted = 1; 232 } else { 233 LOG_IRQ("%s: restart the CPU\n", __func__); 234 cs->halted = 0; 235 qemu_cpu_kick(cs); 236 } 237 break; 238 case PPC970_INPUT_HRESET: 239 /* Level sensitive - active low */ 240 if (level) { 241 cpu_interrupt(cs, CPU_INTERRUPT_RESET); 242 } 243 break; 244 case PPC970_INPUT_SRESET: 245 LOG_IRQ("%s: set the RESET IRQ state to %d\n", 246 __func__, level); 247 ppc_set_irq(cpu, PPC_INTERRUPT_RESET, level); 248 break; 249 case PPC970_INPUT_TBEN: 250 LOG_IRQ("%s: set the TBEN state to %d\n", __func__, 251 level); 252 /* XXX: TODO */ 253 break; 254 default: 255 /* Unknown pin - do nothing */ 256 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 257 return; 258 } 259 if (level) 260 env->irq_input_state |= 1 << pin; 261 else 262 env->irq_input_state &= ~(1 << pin); 263 } 264 } 265 266 void ppc970_irq_init(PowerPCCPU *cpu) 267 { 268 CPUPPCState *env = &cpu->env; 269 270 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, 271 PPC970_INPUT_NB); 272 } 273 274 /* POWER7 internal IRQ controller */ 275 static void power7_set_irq(void *opaque, int pin, int level) 276 { 277 PowerPCCPU *cpu = opaque; 278 279 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 280 &cpu->env, pin, level); 281 282 switch (pin) { 283 case POWER7_INPUT_INT: 284 /* Level sensitive - active high */ 285 LOG_IRQ("%s: set the external IRQ state to %d\n", 286 __func__, level); 287 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 288 break; 289 default: 290 /* Unknown pin - do nothing */ 291 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 292 return; 293 } 294 } 295 296 void ppcPOWER7_irq_init(PowerPCCPU *cpu) 297 { 298 CPUPPCState *env = &cpu->env; 299 300 env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, 301 POWER7_INPUT_NB); 302 } 303 304 /* POWER9 internal IRQ controller */ 305 static void power9_set_irq(void *opaque, int pin, int level) 306 { 307 PowerPCCPU *cpu = opaque; 308 309 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 310 &cpu->env, pin, level); 311 312 switch (pin) { 313 case POWER9_INPUT_INT: 314 /* Level sensitive - active high */ 315 LOG_IRQ("%s: set the external IRQ state to %d\n", 316 __func__, level); 317 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 318 break; 319 case POWER9_INPUT_HINT: 320 /* Level sensitive - active high */ 321 LOG_IRQ("%s: set the external IRQ state to %d\n", 322 __func__, level); 323 ppc_set_irq(cpu, PPC_INTERRUPT_HVIRT, level); 324 break; 325 default: 326 /* Unknown pin - do nothing */ 327 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 328 return; 329 } 330 } 331 332 void ppcPOWER9_irq_init(PowerPCCPU *cpu) 333 { 334 CPUPPCState *env = &cpu->env; 335 336 env->irq_inputs = (void **)qemu_allocate_irqs(&power9_set_irq, cpu, 337 POWER9_INPUT_NB); 338 } 339 #endif /* defined(TARGET_PPC64) */ 340 341 void ppc40x_core_reset(PowerPCCPU *cpu) 342 { 343 CPUPPCState *env = &cpu->env; 344 target_ulong dbsr; 345 346 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC core\n"); 347 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 348 dbsr = env->spr[SPR_40x_DBSR]; 349 dbsr &= ~0x00000300; 350 dbsr |= 0x00000100; 351 env->spr[SPR_40x_DBSR] = dbsr; 352 } 353 354 void ppc40x_chip_reset(PowerPCCPU *cpu) 355 { 356 CPUPPCState *env = &cpu->env; 357 target_ulong dbsr; 358 359 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC chip\n"); 360 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_RESET); 361 /* XXX: TODO reset all internal peripherals */ 362 dbsr = env->spr[SPR_40x_DBSR]; 363 dbsr &= ~0x00000300; 364 dbsr |= 0x00000200; 365 env->spr[SPR_40x_DBSR] = dbsr; 366 } 367 368 void ppc40x_system_reset(PowerPCCPU *cpu) 369 { 370 qemu_log_mask(CPU_LOG_RESET, "Reset PowerPC system\n"); 371 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 372 } 373 374 void store_40x_dbcr0(CPUPPCState *env, uint32_t val) 375 { 376 PowerPCCPU *cpu = env_archcpu(env); 377 378 switch ((val >> 28) & 0x3) { 379 case 0x0: 380 /* No action */ 381 break; 382 case 0x1: 383 /* Core reset */ 384 ppc40x_core_reset(cpu); 385 break; 386 case 0x2: 387 /* Chip reset */ 388 ppc40x_chip_reset(cpu); 389 break; 390 case 0x3: 391 /* System reset */ 392 ppc40x_system_reset(cpu); 393 break; 394 } 395 } 396 397 /* PowerPC 40x internal IRQ controller */ 398 static void ppc40x_set_irq(void *opaque, int pin, int level) 399 { 400 PowerPCCPU *cpu = opaque; 401 CPUPPCState *env = &cpu->env; 402 int cur_level; 403 404 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 405 env, pin, level); 406 cur_level = (env->irq_input_state >> pin) & 1; 407 /* Don't generate spurious events */ 408 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 409 CPUState *cs = CPU(cpu); 410 411 switch (pin) { 412 case PPC40x_INPUT_RESET_SYS: 413 if (level) { 414 LOG_IRQ("%s: reset the PowerPC system\n", 415 __func__); 416 ppc40x_system_reset(cpu); 417 } 418 break; 419 case PPC40x_INPUT_RESET_CHIP: 420 if (level) { 421 LOG_IRQ("%s: reset the PowerPC chip\n", __func__); 422 ppc40x_chip_reset(cpu); 423 } 424 break; 425 case PPC40x_INPUT_RESET_CORE: 426 /* XXX: TODO: update DBSR[MRR] */ 427 if (level) { 428 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 429 ppc40x_core_reset(cpu); 430 } 431 break; 432 case PPC40x_INPUT_CINT: 433 /* Level sensitive - active high */ 434 LOG_IRQ("%s: set the critical IRQ state to %d\n", 435 __func__, level); 436 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 437 break; 438 case PPC40x_INPUT_INT: 439 /* Level sensitive - active high */ 440 LOG_IRQ("%s: set the external IRQ state to %d\n", 441 __func__, level); 442 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 443 break; 444 case PPC40x_INPUT_HALT: 445 /* Level sensitive - active low */ 446 if (level) { 447 LOG_IRQ("%s: stop the CPU\n", __func__); 448 cs->halted = 1; 449 } else { 450 LOG_IRQ("%s: restart the CPU\n", __func__); 451 cs->halted = 0; 452 qemu_cpu_kick(cs); 453 } 454 break; 455 case PPC40x_INPUT_DEBUG: 456 /* Level sensitive - active high */ 457 LOG_IRQ("%s: set the debug pin state to %d\n", 458 __func__, level); 459 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 460 break; 461 default: 462 /* Unknown pin - do nothing */ 463 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 464 return; 465 } 466 if (level) 467 env->irq_input_state |= 1 << pin; 468 else 469 env->irq_input_state &= ~(1 << pin); 470 } 471 } 472 473 void ppc40x_irq_init(PowerPCCPU *cpu) 474 { 475 CPUPPCState *env = &cpu->env; 476 477 env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, 478 cpu, PPC40x_INPUT_NB); 479 } 480 481 /* PowerPC E500 internal IRQ controller */ 482 static void ppce500_set_irq(void *opaque, int pin, int level) 483 { 484 PowerPCCPU *cpu = opaque; 485 CPUPPCState *env = &cpu->env; 486 int cur_level; 487 488 LOG_IRQ("%s: env %p pin %d level %d\n", __func__, 489 env, pin, level); 490 cur_level = (env->irq_input_state >> pin) & 1; 491 /* Don't generate spurious events */ 492 if ((cur_level == 1 && level == 0) || (cur_level == 0 && level != 0)) { 493 switch (pin) { 494 case PPCE500_INPUT_MCK: 495 if (level) { 496 LOG_IRQ("%s: reset the PowerPC system\n", 497 __func__); 498 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 499 } 500 break; 501 case PPCE500_INPUT_RESET_CORE: 502 if (level) { 503 LOG_IRQ("%s: reset the PowerPC core\n", __func__); 504 ppc_set_irq(cpu, PPC_INTERRUPT_MCK, level); 505 } 506 break; 507 case PPCE500_INPUT_CINT: 508 /* Level sensitive - active high */ 509 LOG_IRQ("%s: set the critical IRQ state to %d\n", 510 __func__, level); 511 ppc_set_irq(cpu, PPC_INTERRUPT_CEXT, level); 512 break; 513 case PPCE500_INPUT_INT: 514 /* Level sensitive - active high */ 515 LOG_IRQ("%s: set the core IRQ state to %d\n", 516 __func__, level); 517 ppc_set_irq(cpu, PPC_INTERRUPT_EXT, level); 518 break; 519 case PPCE500_INPUT_DEBUG: 520 /* Level sensitive - active high */ 521 LOG_IRQ("%s: set the debug pin state to %d\n", 522 __func__, level); 523 ppc_set_irq(cpu, PPC_INTERRUPT_DEBUG, level); 524 break; 525 default: 526 /* Unknown pin - do nothing */ 527 LOG_IRQ("%s: unknown IRQ pin %d\n", __func__, pin); 528 return; 529 } 530 if (level) 531 env->irq_input_state |= 1 << pin; 532 else 533 env->irq_input_state &= ~(1 << pin); 534 } 535 } 536 537 void ppce500_irq_init(PowerPCCPU *cpu) 538 { 539 CPUPPCState *env = &cpu->env; 540 541 env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, 542 cpu, PPCE500_INPUT_NB); 543 } 544 545 /* Enable or Disable the E500 EPR capability */ 546 void ppce500_set_mpic_proxy(bool enabled) 547 { 548 CPUState *cs; 549 550 CPU_FOREACH(cs) { 551 PowerPCCPU *cpu = POWERPC_CPU(cs); 552 553 cpu->env.mpic_proxy = enabled; 554 if (kvm_enabled()) { 555 kvmppc_set_mpic_proxy(cpu, enabled); 556 } 557 } 558 } 559 560 /*****************************************************************************/ 561 /* PowerPC time base and decrementer emulation */ 562 563 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) 564 { 565 /* TB time in tb periods */ 566 return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset; 567 } 568 569 uint64_t cpu_ppc_load_tbl (CPUPPCState *env) 570 { 571 ppc_tb_t *tb_env = env->tb_env; 572 uint64_t tb; 573 574 if (kvm_enabled()) { 575 return env->spr[SPR_TBL]; 576 } 577 578 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 579 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 580 581 return tb; 582 } 583 584 static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) 585 { 586 ppc_tb_t *tb_env = env->tb_env; 587 uint64_t tb; 588 589 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 590 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 591 592 return tb >> 32; 593 } 594 595 uint32_t cpu_ppc_load_tbu (CPUPPCState *env) 596 { 597 if (kvm_enabled()) { 598 return env->spr[SPR_TBU]; 599 } 600 601 return _cpu_ppc_load_tbu(env); 602 } 603 604 static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, 605 int64_t *tb_offsetp, uint64_t value) 606 { 607 *tb_offsetp = value - 608 muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND); 609 610 LOG_TB("%s: tb %016" PRIx64 " offset %08" PRIx64 "\n", 611 __func__, value, *tb_offsetp); 612 } 613 614 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value) 615 { 616 ppc_tb_t *tb_env = env->tb_env; 617 uint64_t tb; 618 619 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 620 tb &= 0xFFFFFFFF00000000ULL; 621 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 622 &tb_env->tb_offset, tb | (uint64_t)value); 623 } 624 625 static inline void _cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value) 626 { 627 ppc_tb_t *tb_env = env->tb_env; 628 uint64_t tb; 629 630 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); 631 tb &= 0x00000000FFFFFFFFULL; 632 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 633 &tb_env->tb_offset, ((uint64_t)value << 32) | tb); 634 } 635 636 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value) 637 { 638 _cpu_ppc_store_tbu(env, value); 639 } 640 641 uint64_t cpu_ppc_load_atbl (CPUPPCState *env) 642 { 643 ppc_tb_t *tb_env = env->tb_env; 644 uint64_t tb; 645 646 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 647 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 648 649 return tb; 650 } 651 652 uint32_t cpu_ppc_load_atbu (CPUPPCState *env) 653 { 654 ppc_tb_t *tb_env = env->tb_env; 655 uint64_t tb; 656 657 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 658 LOG_TB("%s: tb %016" PRIx64 "\n", __func__, tb); 659 660 return tb >> 32; 661 } 662 663 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value) 664 { 665 ppc_tb_t *tb_env = env->tb_env; 666 uint64_t tb; 667 668 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 669 tb &= 0xFFFFFFFF00000000ULL; 670 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 671 &tb_env->atb_offset, tb | (uint64_t)value); 672 } 673 674 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value) 675 { 676 ppc_tb_t *tb_env = env->tb_env; 677 uint64_t tb; 678 679 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); 680 tb &= 0x00000000FFFFFFFFULL; 681 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 682 &tb_env->atb_offset, ((uint64_t)value << 32) | tb); 683 } 684 685 uint64_t cpu_ppc_load_vtb(CPUPPCState *env) 686 { 687 ppc_tb_t *tb_env = env->tb_env; 688 689 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 690 tb_env->vtb_offset); 691 } 692 693 void cpu_ppc_store_vtb(CPUPPCState *env, uint64_t value) 694 { 695 ppc_tb_t *tb_env = env->tb_env; 696 697 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 698 &tb_env->vtb_offset, value); 699 } 700 701 void cpu_ppc_store_tbu40(CPUPPCState *env, uint64_t value) 702 { 703 ppc_tb_t *tb_env = env->tb_env; 704 uint64_t tb; 705 706 tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 707 tb_env->tb_offset); 708 tb &= 0xFFFFFFUL; 709 tb |= (value & ~0xFFFFFFUL); 710 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 711 &tb_env->tb_offset, tb); 712 } 713 714 static void cpu_ppc_tb_stop (CPUPPCState *env) 715 { 716 ppc_tb_t *tb_env = env->tb_env; 717 uint64_t tb, atb, vmclk; 718 719 /* If the time base is already frozen, do nothing */ 720 if (tb_env->tb_freq != 0) { 721 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 722 /* Get the time base */ 723 tb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->tb_offset); 724 /* Get the alternate time base */ 725 atb = cpu_ppc_get_tb(tb_env, vmclk, tb_env->atb_offset); 726 /* Store the time base value (ie compute the current offset) */ 727 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 728 /* Store the alternate time base value (compute the current offset) */ 729 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 730 /* Set the time base frequency to zero */ 731 tb_env->tb_freq = 0; 732 /* Now, the time bases are frozen to tb_offset / atb_offset value */ 733 } 734 } 735 736 static void cpu_ppc_tb_start (CPUPPCState *env) 737 { 738 ppc_tb_t *tb_env = env->tb_env; 739 uint64_t tb, atb, vmclk; 740 741 /* If the time base is not frozen, do nothing */ 742 if (tb_env->tb_freq == 0) { 743 vmclk = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 744 /* Get the time base from tb_offset */ 745 tb = tb_env->tb_offset; 746 /* Get the alternate time base from atb_offset */ 747 atb = tb_env->atb_offset; 748 /* Restore the tb frequency from the decrementer frequency */ 749 tb_env->tb_freq = tb_env->decr_freq; 750 /* Store the time base value */ 751 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->tb_offset, tb); 752 /* Store the alternate time base value */ 753 cpu_ppc_store_tb(tb_env, vmclk, &tb_env->atb_offset, atb); 754 } 755 } 756 757 bool ppc_decr_clear_on_delivery(CPUPPCState *env) 758 { 759 ppc_tb_t *tb_env = env->tb_env; 760 int flags = PPC_DECR_UNDERFLOW_TRIGGERED | PPC_DECR_UNDERFLOW_LEVEL; 761 return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); 762 } 763 764 static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) 765 { 766 ppc_tb_t *tb_env = env->tb_env; 767 int64_t decr, diff; 768 769 diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 770 if (diff >= 0) { 771 decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 772 } else if (tb_env->flags & PPC_TIMER_BOOKE) { 773 decr = 0; 774 } else { 775 decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); 776 } 777 LOG_TB("%s: %016" PRIx64 "\n", __func__, decr); 778 779 return decr; 780 } 781 782 target_ulong cpu_ppc_load_decr(CPUPPCState *env) 783 { 784 ppc_tb_t *tb_env = env->tb_env; 785 uint64_t decr; 786 787 if (kvm_enabled()) { 788 return env->spr[SPR_DECR]; 789 } 790 791 decr = _cpu_ppc_load_decr(env, tb_env->decr_next); 792 793 /* 794 * If large decrementer is enabled then the decrementer is signed extened 795 * to 64 bits, otherwise it is a 32 bit value. 796 */ 797 if (env->spr[SPR_LPCR] & LPCR_LD) { 798 return decr; 799 } 800 return (uint32_t) decr; 801 } 802 803 target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) 804 { 805 PowerPCCPU *cpu = env_archcpu(env); 806 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 807 ppc_tb_t *tb_env = env->tb_env; 808 uint64_t hdecr; 809 810 hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next); 811 812 /* 813 * If we have a large decrementer (POWER9 or later) then hdecr is sign 814 * extended to 64 bits, otherwise it is 32 bits. 815 */ 816 if (pcc->lrg_decr_bits > 32) { 817 return hdecr; 818 } 819 return (uint32_t) hdecr; 820 } 821 822 uint64_t cpu_ppc_load_purr (CPUPPCState *env) 823 { 824 ppc_tb_t *tb_env = env->tb_env; 825 826 return cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 827 tb_env->purr_offset); 828 } 829 830 /* When decrementer expires, 831 * all we need to do is generate or queue a CPU exception 832 */ 833 static inline void cpu_ppc_decr_excp(PowerPCCPU *cpu) 834 { 835 /* Raise it */ 836 LOG_TB("raise decrementer exception\n"); 837 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 1); 838 } 839 840 static inline void cpu_ppc_decr_lower(PowerPCCPU *cpu) 841 { 842 ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); 843 } 844 845 static inline void cpu_ppc_hdecr_excp(PowerPCCPU *cpu) 846 { 847 CPUPPCState *env = &cpu->env; 848 849 /* Raise it */ 850 LOG_TB("raise hv decrementer exception\n"); 851 852 /* The architecture specifies that we don't deliver HDEC 853 * interrupts in a PM state. Not only they don't cause a 854 * wakeup but they also get effectively discarded. 855 */ 856 if (!env->resume_as_sreset) { 857 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 1); 858 } 859 } 860 861 static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) 862 { 863 ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); 864 } 865 866 static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, 867 QEMUTimer *timer, 868 void (*raise_excp)(void *), 869 void (*lower_excp)(PowerPCCPU *), 870 target_ulong decr, target_ulong value, 871 int nr_bits) 872 { 873 CPUPPCState *env = &cpu->env; 874 ppc_tb_t *tb_env = env->tb_env; 875 uint64_t now, next; 876 bool negative; 877 878 /* Truncate value to decr_width and sign extend for simplicity */ 879 value &= ((1ULL << nr_bits) - 1); 880 negative = !!(value & (1ULL << (nr_bits - 1))); 881 if (negative) { 882 value |= (0xFFFFFFFFULL << nr_bits); 883 } 884 885 LOG_TB("%s: " TARGET_FMT_lx " => " TARGET_FMT_lx "\n", __func__, 886 decr, value); 887 888 if (kvm_enabled()) { 889 /* KVM handles decrementer exceptions, we don't need our own timer */ 890 return; 891 } 892 893 /* 894 * Going from 2 -> 1, 1 -> 0 or 0 -> -1 is the event to generate a DEC 895 * interrupt. 896 * 897 * If we get a really small DEC value, we can assume that by the time we 898 * handled it we should inject an interrupt already. 899 * 900 * On MSB level based DEC implementations the MSB always means the interrupt 901 * is pending, so raise it on those. 902 * 903 * On MSB edge based DEC implementations the MSB going from 0 -> 1 triggers 904 * an edge interrupt, so raise it here too. 905 */ 906 if ((value < 3) || 907 ((tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL) && negative) || 908 ((tb_env->flags & PPC_DECR_UNDERFLOW_TRIGGERED) && negative 909 && !(decr & (1ULL << (nr_bits - 1))))) { 910 (*raise_excp)(cpu); 911 return; 912 } 913 914 /* On MSB level based systems a 0 for the MSB stops interrupt delivery */ 915 if (!negative && (tb_env->flags & PPC_DECR_UNDERFLOW_LEVEL)) { 916 (*lower_excp)(cpu); 917 } 918 919 /* Calculate the next timer event */ 920 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 921 next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 922 *nextp = next; 923 924 /* Adjust timer */ 925 timer_mod(timer, next); 926 } 927 928 static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, 929 target_ulong value, int nr_bits) 930 { 931 ppc_tb_t *tb_env = cpu->env.tb_env; 932 933 __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, 934 tb_env->decr_timer->cb, &cpu_ppc_decr_lower, decr, 935 value, nr_bits); 936 } 937 938 void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) 939 { 940 PowerPCCPU *cpu = env_archcpu(env); 941 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 942 int nr_bits = 32; 943 944 if (env->spr[SPR_LPCR] & LPCR_LD) { 945 nr_bits = pcc->lrg_decr_bits; 946 } 947 948 _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits); 949 } 950 951 static void cpu_ppc_decr_cb(void *opaque) 952 { 953 PowerPCCPU *cpu = opaque; 954 955 cpu_ppc_decr_excp(cpu); 956 } 957 958 static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr, 959 target_ulong value, int nr_bits) 960 { 961 ppc_tb_t *tb_env = cpu->env.tb_env; 962 963 if (tb_env->hdecr_timer != NULL) { 964 __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, 965 tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, 966 hdecr, value, nr_bits); 967 } 968 } 969 970 void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) 971 { 972 PowerPCCPU *cpu = env_archcpu(env); 973 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); 974 975 _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, 976 pcc->lrg_decr_bits); 977 } 978 979 static void cpu_ppc_hdecr_cb(void *opaque) 980 { 981 PowerPCCPU *cpu = opaque; 982 983 cpu_ppc_hdecr_excp(cpu); 984 } 985 986 void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) 987 { 988 ppc_tb_t *tb_env = env->tb_env; 989 990 cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 991 &tb_env->purr_offset, value); 992 } 993 994 static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) 995 { 996 CPUPPCState *env = opaque; 997 PowerPCCPU *cpu = env_archcpu(env); 998 ppc_tb_t *tb_env = env->tb_env; 999 1000 tb_env->tb_freq = freq; 1001 tb_env->decr_freq = freq; 1002 /* There is a bug in Linux 2.4 kernels: 1003 * if a decrementer exception is pending when it enables msr_ee at startup, 1004 * it's not ready to handle it... 1005 */ 1006 _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 1007 _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); 1008 cpu_ppc_store_purr(env, 0x0000000000000000ULL); 1009 } 1010 1011 static void timebase_save(PPCTimebase *tb) 1012 { 1013 uint64_t ticks = cpu_get_host_ticks(); 1014 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1015 1016 if (!first_ppc_cpu->env.tb_env) { 1017 error_report("No timebase object"); 1018 return; 1019 } 1020 1021 /* not used anymore, we keep it for compatibility */ 1022 tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); 1023 /* 1024 * tb_offset is only expected to be changed by QEMU so 1025 * there is no need to update it from KVM here 1026 */ 1027 tb->guest_timebase = ticks + first_ppc_cpu->env.tb_env->tb_offset; 1028 1029 tb->runstate_paused = runstate_check(RUN_STATE_PAUSED); 1030 } 1031 1032 static void timebase_load(PPCTimebase *tb) 1033 { 1034 CPUState *cpu; 1035 PowerPCCPU *first_ppc_cpu = POWERPC_CPU(first_cpu); 1036 int64_t tb_off_adj, tb_off; 1037 unsigned long freq; 1038 1039 if (!first_ppc_cpu->env.tb_env) { 1040 error_report("No timebase object"); 1041 return; 1042 } 1043 1044 freq = first_ppc_cpu->env.tb_env->tb_freq; 1045 1046 tb_off_adj = tb->guest_timebase - cpu_get_host_ticks(); 1047 1048 tb_off = first_ppc_cpu->env.tb_env->tb_offset; 1049 trace_ppc_tb_adjust(tb_off, tb_off_adj, tb_off_adj - tb_off, 1050 (tb_off_adj - tb_off) / freq); 1051 1052 /* Set new offset to all CPUs */ 1053 CPU_FOREACH(cpu) { 1054 PowerPCCPU *pcpu = POWERPC_CPU(cpu); 1055 pcpu->env.tb_env->tb_offset = tb_off_adj; 1056 kvmppc_set_reg_tb_offset(pcpu, pcpu->env.tb_env->tb_offset); 1057 } 1058 } 1059 1060 void cpu_ppc_clock_vm_state_change(void *opaque, int running, 1061 RunState state) 1062 { 1063 PPCTimebase *tb = opaque; 1064 1065 if (running) { 1066 timebase_load(tb); 1067 } else { 1068 timebase_save(tb); 1069 } 1070 } 1071 1072 /* 1073 * When migrating a running guest, read the clock just 1074 * before migration, so that the guest clock counts 1075 * during the events between: 1076 * 1077 * * vm_stop() 1078 * * 1079 * * pre_save() 1080 * 1081 * This reduces clock difference on migration from 5s 1082 * to 0.1s (when max_downtime == 5s), because sending the 1083 * final pages of memory (which happens between vm_stop() 1084 * and pre_save()) takes max_downtime. 1085 */ 1086 static int timebase_pre_save(void *opaque) 1087 { 1088 PPCTimebase *tb = opaque; 1089 1090 /* guest_timebase won't be overridden in case of paused guest */ 1091 if (!tb->runstate_paused) { 1092 timebase_save(tb); 1093 } 1094 1095 return 0; 1096 } 1097 1098 const VMStateDescription vmstate_ppc_timebase = { 1099 .name = "timebase", 1100 .version_id = 1, 1101 .minimum_version_id = 1, 1102 .minimum_version_id_old = 1, 1103 .pre_save = timebase_pre_save, 1104 .fields = (VMStateField []) { 1105 VMSTATE_UINT64(guest_timebase, PPCTimebase), 1106 VMSTATE_INT64(time_of_the_day_ns, PPCTimebase), 1107 VMSTATE_END_OF_LIST() 1108 }, 1109 }; 1110 1111 /* Set up (once) timebase frequency (in Hz) */ 1112 clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) 1113 { 1114 PowerPCCPU *cpu = env_archcpu(env); 1115 ppc_tb_t *tb_env; 1116 1117 tb_env = g_malloc0(sizeof(ppc_tb_t)); 1118 env->tb_env = tb_env; 1119 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1120 if (is_book3s_arch2x(env)) { 1121 /* All Book3S 64bit CPUs implement level based DEC logic */ 1122 tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; 1123 } 1124 /* Create new timer */ 1125 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); 1126 if (env->has_hv_mode) { 1127 tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, 1128 cpu); 1129 } else { 1130 tb_env->hdecr_timer = NULL; 1131 } 1132 cpu_ppc_set_tb_clk(env, freq); 1133 1134 return &cpu_ppc_set_tb_clk; 1135 } 1136 1137 /* Specific helpers for POWER & PowerPC 601 RTC */ 1138 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value) 1139 { 1140 _cpu_ppc_store_tbu(env, value); 1141 } 1142 1143 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env) 1144 { 1145 return _cpu_ppc_load_tbu(env); 1146 } 1147 1148 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value) 1149 { 1150 cpu_ppc_store_tbl(env, value & 0x3FFFFF80); 1151 } 1152 1153 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env) 1154 { 1155 return cpu_ppc_load_tbl(env) & 0x3FFFFF80; 1156 } 1157 1158 /*****************************************************************************/ 1159 /* PowerPC 40x timers */ 1160 1161 /* PIT, FIT & WDT */ 1162 typedef struct ppc40x_timer_t ppc40x_timer_t; 1163 struct ppc40x_timer_t { 1164 uint64_t pit_reload; /* PIT auto-reload value */ 1165 uint64_t fit_next; /* Tick for next FIT interrupt */ 1166 QEMUTimer *fit_timer; 1167 uint64_t wdt_next; /* Tick for next WDT interrupt */ 1168 QEMUTimer *wdt_timer; 1169 1170 /* 405 have the PIT, 440 have a DECR. */ 1171 unsigned int decr_excp; 1172 }; 1173 1174 /* Fixed interval timer */ 1175 static void cpu_4xx_fit_cb (void *opaque) 1176 { 1177 PowerPCCPU *cpu; 1178 CPUPPCState *env; 1179 ppc_tb_t *tb_env; 1180 ppc40x_timer_t *ppc40x_timer; 1181 uint64_t now, next; 1182 1183 env = opaque; 1184 cpu = env_archcpu(env); 1185 tb_env = env->tb_env; 1186 ppc40x_timer = tb_env->opaque; 1187 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1188 switch ((env->spr[SPR_40x_TCR] >> 24) & 0x3) { 1189 case 0: 1190 next = 1 << 9; 1191 break; 1192 case 1: 1193 next = 1 << 13; 1194 break; 1195 case 2: 1196 next = 1 << 17; 1197 break; 1198 case 3: 1199 next = 1 << 21; 1200 break; 1201 default: 1202 /* Cannot occur, but makes gcc happy */ 1203 return; 1204 } 1205 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq); 1206 if (next == now) 1207 next++; 1208 timer_mod(ppc40x_timer->fit_timer, next); 1209 env->spr[SPR_40x_TSR] |= 1 << 26; 1210 if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { 1211 ppc_set_irq(cpu, PPC_INTERRUPT_FIT, 1); 1212 } 1213 LOG_TB("%s: ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1214 (int)((env->spr[SPR_40x_TCR] >> 23) & 0x1), 1215 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1216 } 1217 1218 /* Programmable interval timer */ 1219 static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) 1220 { 1221 ppc40x_timer_t *ppc40x_timer; 1222 uint64_t now, next; 1223 1224 ppc40x_timer = tb_env->opaque; 1225 if (ppc40x_timer->pit_reload <= 1 || 1226 !((env->spr[SPR_40x_TCR] >> 26) & 0x1) || 1227 (is_excp && !((env->spr[SPR_40x_TCR] >> 22) & 0x1))) { 1228 /* Stop PIT */ 1229 LOG_TB("%s: stop PIT\n", __func__); 1230 timer_del(tb_env->decr_timer); 1231 } else { 1232 LOG_TB("%s: start PIT %016" PRIx64 "\n", 1233 __func__, ppc40x_timer->pit_reload); 1234 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1235 next = now + muldiv64(ppc40x_timer->pit_reload, 1236 NANOSECONDS_PER_SECOND, tb_env->decr_freq); 1237 if (is_excp) 1238 next += tb_env->decr_next - now; 1239 if (next == now) 1240 next++; 1241 timer_mod(tb_env->decr_timer, next); 1242 tb_env->decr_next = next; 1243 } 1244 } 1245 1246 static void cpu_4xx_pit_cb (void *opaque) 1247 { 1248 PowerPCCPU *cpu; 1249 CPUPPCState *env; 1250 ppc_tb_t *tb_env; 1251 ppc40x_timer_t *ppc40x_timer; 1252 1253 env = opaque; 1254 cpu = env_archcpu(env); 1255 tb_env = env->tb_env; 1256 ppc40x_timer = tb_env->opaque; 1257 env->spr[SPR_40x_TSR] |= 1 << 27; 1258 if ((env->spr[SPR_40x_TCR] >> 26) & 0x1) { 1259 ppc_set_irq(cpu, ppc40x_timer->decr_excp, 1); 1260 } 1261 start_stop_pit(env, tb_env, 1); 1262 LOG_TB("%s: ar %d ir %d TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx " " 1263 "%016" PRIx64 "\n", __func__, 1264 (int)((env->spr[SPR_40x_TCR] >> 22) & 0x1), 1265 (int)((env->spr[SPR_40x_TCR] >> 26) & 0x1), 1266 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR], 1267 ppc40x_timer->pit_reload); 1268 } 1269 1270 /* Watchdog timer */ 1271 static void cpu_4xx_wdt_cb (void *opaque) 1272 { 1273 PowerPCCPU *cpu; 1274 CPUPPCState *env; 1275 ppc_tb_t *tb_env; 1276 ppc40x_timer_t *ppc40x_timer; 1277 uint64_t now, next; 1278 1279 env = opaque; 1280 cpu = env_archcpu(env); 1281 tb_env = env->tb_env; 1282 ppc40x_timer = tb_env->opaque; 1283 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1284 switch ((env->spr[SPR_40x_TCR] >> 30) & 0x3) { 1285 case 0: 1286 next = 1 << 17; 1287 break; 1288 case 1: 1289 next = 1 << 21; 1290 break; 1291 case 2: 1292 next = 1 << 25; 1293 break; 1294 case 3: 1295 next = 1 << 29; 1296 break; 1297 default: 1298 /* Cannot occur, but makes gcc happy */ 1299 return; 1300 } 1301 next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq); 1302 if (next == now) 1303 next++; 1304 LOG_TB("%s: TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx "\n", __func__, 1305 env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); 1306 switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { 1307 case 0x0: 1308 case 0x1: 1309 timer_mod(ppc40x_timer->wdt_timer, next); 1310 ppc40x_timer->wdt_next = next; 1311 env->spr[SPR_40x_TSR] |= 1U << 31; 1312 break; 1313 case 0x2: 1314 timer_mod(ppc40x_timer->wdt_timer, next); 1315 ppc40x_timer->wdt_next = next; 1316 env->spr[SPR_40x_TSR] |= 1 << 30; 1317 if ((env->spr[SPR_40x_TCR] >> 27) & 0x1) { 1318 ppc_set_irq(cpu, PPC_INTERRUPT_WDT, 1); 1319 } 1320 break; 1321 case 0x3: 1322 env->spr[SPR_40x_TSR] &= ~0x30000000; 1323 env->spr[SPR_40x_TSR] |= env->spr[SPR_40x_TCR] & 0x30000000; 1324 switch ((env->spr[SPR_40x_TCR] >> 28) & 0x3) { 1325 case 0x0: 1326 /* No reset */ 1327 break; 1328 case 0x1: /* Core reset */ 1329 ppc40x_core_reset(cpu); 1330 break; 1331 case 0x2: /* Chip reset */ 1332 ppc40x_chip_reset(cpu); 1333 break; 1334 case 0x3: /* System reset */ 1335 ppc40x_system_reset(cpu); 1336 break; 1337 } 1338 } 1339 } 1340 1341 void store_40x_pit (CPUPPCState *env, target_ulong val) 1342 { 1343 ppc_tb_t *tb_env; 1344 ppc40x_timer_t *ppc40x_timer; 1345 1346 tb_env = env->tb_env; 1347 ppc40x_timer = tb_env->opaque; 1348 LOG_TB("%s val" TARGET_FMT_lx "\n", __func__, val); 1349 ppc40x_timer->pit_reload = val; 1350 start_stop_pit(env, tb_env, 0); 1351 } 1352 1353 target_ulong load_40x_pit (CPUPPCState *env) 1354 { 1355 return cpu_ppc_load_decr(env); 1356 } 1357 1358 static void ppc_40x_set_tb_clk (void *opaque, uint32_t freq) 1359 { 1360 CPUPPCState *env = opaque; 1361 ppc_tb_t *tb_env = env->tb_env; 1362 1363 LOG_TB("%s set new frequency to %" PRIu32 "\n", __func__, 1364 freq); 1365 tb_env->tb_freq = freq; 1366 tb_env->decr_freq = freq; 1367 /* XXX: we should also update all timers */ 1368 } 1369 1370 clk_setup_cb ppc_40x_timers_init (CPUPPCState *env, uint32_t freq, 1371 unsigned int decr_excp) 1372 { 1373 ppc_tb_t *tb_env; 1374 ppc40x_timer_t *ppc40x_timer; 1375 1376 tb_env = g_malloc0(sizeof(ppc_tb_t)); 1377 env->tb_env = tb_env; 1378 tb_env->flags = PPC_DECR_UNDERFLOW_TRIGGERED; 1379 ppc40x_timer = g_malloc0(sizeof(ppc40x_timer_t)); 1380 tb_env->tb_freq = freq; 1381 tb_env->decr_freq = freq; 1382 tb_env->opaque = ppc40x_timer; 1383 LOG_TB("%s freq %" PRIu32 "\n", __func__, freq); 1384 if (ppc40x_timer != NULL) { 1385 /* We use decr timer for PIT */ 1386 tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_pit_cb, env); 1387 ppc40x_timer->fit_timer = 1388 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_fit_cb, env); 1389 ppc40x_timer->wdt_timer = 1390 timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_4xx_wdt_cb, env); 1391 ppc40x_timer->decr_excp = decr_excp; 1392 } 1393 1394 return &ppc_40x_set_tb_clk; 1395 } 1396 1397 /*****************************************************************************/ 1398 /* Embedded PowerPC Device Control Registers */ 1399 typedef struct ppc_dcrn_t ppc_dcrn_t; 1400 struct ppc_dcrn_t { 1401 dcr_read_cb dcr_read; 1402 dcr_write_cb dcr_write; 1403 void *opaque; 1404 }; 1405 1406 /* XXX: on 460, DCR addresses are 32 bits wide, 1407 * using DCRIPR to get the 22 upper bits of the DCR address 1408 */ 1409 #define DCRN_NB 1024 1410 struct ppc_dcr_t { 1411 ppc_dcrn_t dcrn[DCRN_NB]; 1412 int (*read_error)(int dcrn); 1413 int (*write_error)(int dcrn); 1414 }; 1415 1416 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp) 1417 { 1418 ppc_dcrn_t *dcr; 1419 1420 if (dcrn < 0 || dcrn >= DCRN_NB) 1421 goto error; 1422 dcr = &dcr_env->dcrn[dcrn]; 1423 if (dcr->dcr_read == NULL) 1424 goto error; 1425 *valp = (*dcr->dcr_read)(dcr->opaque, dcrn); 1426 1427 return 0; 1428 1429 error: 1430 if (dcr_env->read_error != NULL) 1431 return (*dcr_env->read_error)(dcrn); 1432 1433 return -1; 1434 } 1435 1436 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val) 1437 { 1438 ppc_dcrn_t *dcr; 1439 1440 if (dcrn < 0 || dcrn >= DCRN_NB) 1441 goto error; 1442 dcr = &dcr_env->dcrn[dcrn]; 1443 if (dcr->dcr_write == NULL) 1444 goto error; 1445 (*dcr->dcr_write)(dcr->opaque, dcrn, val); 1446 1447 return 0; 1448 1449 error: 1450 if (dcr_env->write_error != NULL) 1451 return (*dcr_env->write_error)(dcrn); 1452 1453 return -1; 1454 } 1455 1456 int ppc_dcr_register (CPUPPCState *env, int dcrn, void *opaque, 1457 dcr_read_cb dcr_read, dcr_write_cb dcr_write) 1458 { 1459 ppc_dcr_t *dcr_env; 1460 ppc_dcrn_t *dcr; 1461 1462 dcr_env = env->dcr_env; 1463 if (dcr_env == NULL) 1464 return -1; 1465 if (dcrn < 0 || dcrn >= DCRN_NB) 1466 return -1; 1467 dcr = &dcr_env->dcrn[dcrn]; 1468 if (dcr->opaque != NULL || 1469 dcr->dcr_read != NULL || 1470 dcr->dcr_write != NULL) 1471 return -1; 1472 dcr->opaque = opaque; 1473 dcr->dcr_read = dcr_read; 1474 dcr->dcr_write = dcr_write; 1475 1476 return 0; 1477 } 1478 1479 int ppc_dcr_init (CPUPPCState *env, int (*read_error)(int dcrn), 1480 int (*write_error)(int dcrn)) 1481 { 1482 ppc_dcr_t *dcr_env; 1483 1484 dcr_env = g_malloc0(sizeof(ppc_dcr_t)); 1485 dcr_env->read_error = read_error; 1486 dcr_env->write_error = write_error; 1487 env->dcr_env = dcr_env; 1488 1489 return 0; 1490 } 1491 1492 /*****************************************************************************/ 1493 /* Debug port */ 1494 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val) 1495 { 1496 addr &= 0xF; 1497 switch (addr) { 1498 case 0: 1499 printf("%c", val); 1500 break; 1501 case 1: 1502 printf("\n"); 1503 fflush(stdout); 1504 break; 1505 case 2: 1506 printf("Set loglevel to %04" PRIx32 "\n", val); 1507 qemu_set_log(val | 0x100); 1508 break; 1509 } 1510 } 1511 1512 int ppc_cpu_pir(PowerPCCPU *cpu) 1513 { 1514 CPUPPCState *env = &cpu->env; 1515 return env->spr_cb[SPR_PIR].default_value; 1516 } 1517 1518 PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 1519 { 1520 CPUState *cs; 1521 1522 CPU_FOREACH(cs) { 1523 PowerPCCPU *cpu = POWERPC_CPU(cs); 1524 1525 if (ppc_cpu_pir(cpu) == pir) { 1526 return cpu; 1527 } 1528 } 1529 1530 return NULL; 1531 } 1532 1533 void ppc_irq_reset(PowerPCCPU *cpu) 1534 { 1535 CPUPPCState *env = &cpu->env; 1536 1537 env->irq_input_state = 0; 1538 kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0); 1539 } 1540