1 /* 2 * QEMU PowerPC PowerNV XSCOM bus 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "hw/hw.h" 21 #include "qemu/log.h" 22 #include "sysemu/hw_accel.h" 23 #include "target/ppc/cpu.h" 24 #include "hw/sysbus.h" 25 26 #include "hw/ppc/fdt.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_xscom.h" 29 30 #include <libfdt.h> 31 32 /* PRD registers */ 33 #define PRD_P8_IPOLL_REG_MASK 0x01020013 34 #define PRD_P8_IPOLL_REG_STATUS 0x01020014 35 #define PRD_P9_IPOLL_REG_MASK 0x000F0033 36 #define PRD_P9_IPOLL_REG_STATUS 0x000F0034 37 38 static void xscom_complete(CPUState *cs, uint64_t hmer_bits) 39 { 40 /* 41 * TODO: When the read/write comes from the monitor, NULL is 42 * passed for the cpu, and no CPU completion is generated. 43 */ 44 if (cs) { 45 PowerPCCPU *cpu = POWERPC_CPU(cs); 46 CPUPPCState *env = &cpu->env; 47 48 /* 49 * TODO: Need a CPU helper to set HMER, also handle generation 50 * of HMIs 51 */ 52 cpu_synchronize_state(cs); 53 env->spr[SPR_HMER] |= hmer_bits; 54 } 55 } 56 57 static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) 58 { 59 addr &= (PNV_XSCOM_SIZE - 1); 60 61 if (pnv_chip_is_power9(chip)) { 62 return addr >> 3; 63 } else { 64 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 65 } 66 } 67 68 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) 69 { 70 switch (pcba) { 71 case 0xf000f: 72 return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id; 73 case 0x18002: /* ECID2 */ 74 return 0; 75 76 case 0x1010c00: /* PIBAM FIR */ 77 case 0x1010c03: /* PIBAM FIR MASK */ 78 79 /* PRD registers */ 80 case PRD_P8_IPOLL_REG_MASK: 81 case PRD_P8_IPOLL_REG_STATUS: 82 case PRD_P9_IPOLL_REG_MASK: 83 case PRD_P9_IPOLL_REG_STATUS: 84 85 /* P9 xscom reset */ 86 case 0x0090018: /* Receive status reg */ 87 case 0x0090012: /* log register */ 88 case 0x0090013: /* error register */ 89 90 /* P8 xscom reset */ 91 case 0x2020007: /* ADU stuff, log register */ 92 case 0x2020009: /* ADU stuff, error register */ 93 case 0x202000f: /* ADU stuff, receive status register*/ 94 return 0; 95 case 0x2013f00: /* PBA stuff */ 96 case 0x2013f01: /* PBA stuff */ 97 case 0x2013f02: /* PBA stuff */ 98 case 0x2013f03: /* PBA stuff */ 99 case 0x2013f04: /* PBA stuff */ 100 case 0x2013f05: /* PBA stuff */ 101 case 0x2013f06: /* PBA stuff */ 102 case 0x2013f07: /* PBA stuff */ 103 return 0; 104 case 0x2013028: /* CAPP stuff */ 105 case 0x201302a: /* CAPP stuff */ 106 case 0x2013801: /* CAPP stuff */ 107 case 0x2013802: /* CAPP stuff */ 108 return 0; 109 default: 110 return -1; 111 } 112 } 113 114 static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val) 115 { 116 /* We ignore writes to these */ 117 switch (pcba) { 118 case 0xf000f: /* chip id is RO */ 119 case 0x1010c00: /* PIBAM FIR */ 120 case 0x1010c01: /* PIBAM FIR */ 121 case 0x1010c02: /* PIBAM FIR */ 122 case 0x1010c03: /* PIBAM FIR MASK */ 123 case 0x1010c04: /* PIBAM FIR MASK */ 124 case 0x1010c05: /* PIBAM FIR MASK */ 125 /* P9 xscom reset */ 126 case 0x0090018: /* Receive status reg */ 127 case 0x0090012: /* log register */ 128 case 0x0090013: /* error register */ 129 130 /* P8 xscom reset */ 131 case 0x2020007: /* ADU stuff, log register */ 132 case 0x2020009: /* ADU stuff, error register */ 133 case 0x202000f: /* ADU stuff, receive status register*/ 134 135 case 0x2013028: /* CAPP stuff */ 136 case 0x201302a: /* CAPP stuff */ 137 case 0x2013801: /* CAPP stuff */ 138 case 0x2013802: /* CAPP stuff */ 139 140 /* P8 PRD registers */ 141 case PRD_P8_IPOLL_REG_MASK: 142 case PRD_P8_IPOLL_REG_STATUS: 143 case PRD_P9_IPOLL_REG_MASK: 144 case PRD_P9_IPOLL_REG_STATUS: 145 return true; 146 default: 147 return false; 148 } 149 } 150 151 static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width) 152 { 153 PnvChip *chip = opaque; 154 uint32_t pcba = pnv_xscom_pcba(chip, addr); 155 uint64_t val = 0; 156 MemTxResult result; 157 158 /* Handle some SCOMs here before dispatch */ 159 val = xscom_read_default(chip, pcba); 160 if (val != -1) { 161 goto complete; 162 } 163 164 val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3, 165 MEMTXATTRS_UNSPECIFIED, &result); 166 if (result != MEMTX_OK) { 167 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%" 168 HWADDR_PRIx " pcba=0x%08x\n", addr, pcba); 169 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); 170 return 0; 171 } 172 173 complete: 174 xscom_complete(current_cpu, HMER_XSCOM_DONE); 175 return val; 176 } 177 178 static void xscom_write(void *opaque, hwaddr addr, uint64_t val, 179 unsigned width) 180 { 181 PnvChip *chip = opaque; 182 uint32_t pcba = pnv_xscom_pcba(chip, addr); 183 MemTxResult result; 184 185 /* Handle some SCOMs here before dispatch */ 186 if (xscom_write_default(chip, pcba, val)) { 187 goto complete; 188 } 189 190 address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val, 191 MEMTXATTRS_UNSPECIFIED, &result); 192 if (result != MEMTX_OK) { 193 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%" 194 HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n", 195 addr, pcba, val); 196 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); 197 return; 198 } 199 200 complete: 201 xscom_complete(current_cpu, HMER_XSCOM_DONE); 202 } 203 204 const MemoryRegionOps pnv_xscom_ops = { 205 .read = xscom_read, 206 .write = xscom_write, 207 .valid.min_access_size = 8, 208 .valid.max_access_size = 8, 209 .impl.min_access_size = 8, 210 .impl.max_access_size = 8, 211 .endianness = DEVICE_BIG_ENDIAN, 212 }; 213 214 void pnv_xscom_realize(PnvChip *chip, Error **errp) 215 { 216 SysBusDevice *sbd = SYS_BUS_DEVICE(chip); 217 char *name; 218 219 name = g_strdup_printf("xscom-%x", chip->chip_id); 220 memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops, 221 chip, name, PNV_XSCOM_SIZE); 222 sysbus_init_mmio(sbd, &chip->xscom_mmio); 223 224 memory_region_init(&chip->xscom, OBJECT(chip), name, PNV_XSCOM_SIZE); 225 address_space_init(&chip->xscom_as, &chip->xscom, name); 226 g_free(name); 227 } 228 229 static const TypeInfo pnv_xscom_interface_info = { 230 .name = TYPE_PNV_XSCOM_INTERFACE, 231 .parent = TYPE_INTERFACE, 232 .class_size = sizeof(PnvXScomInterfaceClass), 233 }; 234 235 static void pnv_xscom_register_types(void) 236 { 237 type_register_static(&pnv_xscom_interface_info); 238 } 239 240 type_init(pnv_xscom_register_types) 241 242 typedef struct ForeachPopulateArgs { 243 void *fdt; 244 int xscom_offset; 245 } ForeachPopulateArgs; 246 247 static int xscom_dt_child(Object *child, void *opaque) 248 { 249 if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) { 250 ForeachPopulateArgs *args = opaque; 251 PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child); 252 PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd); 253 254 if (xc->dt_xscom) { 255 _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset))); 256 } 257 } 258 return 0; 259 } 260 261 static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; 262 static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; 263 264 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) 265 { 266 uint64_t reg[] = { cpu_to_be64(PNV_XSCOM_BASE(chip)), 267 cpu_to_be64(PNV_XSCOM_SIZE) }; 268 int xscom_offset; 269 ForeachPopulateArgs args; 270 char *name; 271 272 name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0])); 273 xscom_offset = fdt_add_subnode(fdt, root_offset, name); 274 _FDT(xscom_offset); 275 g_free(name); 276 _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id))); 277 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1))); 278 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); 279 _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); 280 281 if (pnv_chip_is_power9(chip)) { 282 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, 283 sizeof(compat_p9)))); 284 } else { 285 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8, 286 sizeof(compat_p8)))); 287 } 288 289 _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0))); 290 291 args.fdt = fdt; 292 args.xscom_offset = xscom_offset; 293 294 object_child_foreach(OBJECT(chip), xscom_dt_child, &args); 295 return 0; 296 } 297 298 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr) 299 { 300 memory_region_add_subregion(&chip->xscom, offset << 3, mr); 301 } 302 303 void pnv_xscom_region_init(MemoryRegion *mr, 304 struct Object *owner, 305 const MemoryRegionOps *ops, 306 void *opaque, 307 const char *name, 308 uint64_t size) 309 { 310 memory_region_init_io(mr, owner, ops, opaque, name, size << 3); 311 } 312