1 /* 2 * QEMU PowerPC PowerNV XSCOM bus 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "hw/hw.h" 21 #include "qemu/log.h" 22 #include "sysemu/hw_accel.h" 23 #include "target/ppc/cpu.h" 24 #include "hw/sysbus.h" 25 26 #include "hw/ppc/fdt.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_xscom.h" 29 30 #include <libfdt.h> 31 32 static void xscom_complete(CPUState *cs, uint64_t hmer_bits) 33 { 34 /* 35 * TODO: When the read/write comes from the monitor, NULL is 36 * passed for the cpu, and no CPU completion is generated. 37 */ 38 if (cs) { 39 PowerPCCPU *cpu = POWERPC_CPU(cs); 40 CPUPPCState *env = &cpu->env; 41 42 /* 43 * TODO: Need a CPU helper to set HMER, also handle generation 44 * of HMIs 45 */ 46 cpu_synchronize_state(cs); 47 env->spr[SPR_HMER] |= hmer_bits; 48 } 49 } 50 51 static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) 52 { 53 addr &= (PNV_XSCOM_SIZE - 1); 54 55 if (pnv_chip_is_power9(chip)) { 56 return addr >> 3; 57 } else { 58 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 59 } 60 } 61 62 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) 63 { 64 switch (pcba) { 65 case 0xf000f: 66 return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id; 67 case 0x1010c00: /* PIBAM FIR */ 68 case 0x1010c03: /* PIBAM FIR MASK */ 69 case 0x2020007: /* ADU stuff */ 70 case 0x2020009: /* ADU stuff */ 71 case 0x202000f: /* ADU stuff */ 72 return 0; 73 case 0x2013f00: /* PBA stuff */ 74 case 0x2013f01: /* PBA stuff */ 75 case 0x2013f02: /* PBA stuff */ 76 case 0x2013f03: /* PBA stuff */ 77 case 0x2013f04: /* PBA stuff */ 78 case 0x2013f05: /* PBA stuff */ 79 case 0x2013f06: /* PBA stuff */ 80 case 0x2013f07: /* PBA stuff */ 81 return 0; 82 case 0x2013028: /* CAPP stuff */ 83 case 0x201302a: /* CAPP stuff */ 84 case 0x2013801: /* CAPP stuff */ 85 case 0x2013802: /* CAPP stuff */ 86 return 0; 87 default: 88 return -1; 89 } 90 } 91 92 static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val) 93 { 94 /* We ignore writes to these */ 95 switch (pcba) { 96 case 0xf000f: /* chip id is RO */ 97 case 0x1010c00: /* PIBAM FIR */ 98 case 0x1010c01: /* PIBAM FIR */ 99 case 0x1010c02: /* PIBAM FIR */ 100 case 0x1010c03: /* PIBAM FIR MASK */ 101 case 0x1010c04: /* PIBAM FIR MASK */ 102 case 0x1010c05: /* PIBAM FIR MASK */ 103 case 0x2020007: /* ADU stuff */ 104 case 0x2020009: /* ADU stuff */ 105 case 0x202000f: /* ADU stuff */ 106 return true; 107 default: 108 return false; 109 } 110 } 111 112 static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width) 113 { 114 PnvChip *chip = opaque; 115 uint32_t pcba = pnv_xscom_pcba(chip, addr); 116 uint64_t val = 0; 117 MemTxResult result; 118 119 /* Handle some SCOMs here before dispatch */ 120 val = xscom_read_default(chip, pcba); 121 if (val != -1) { 122 goto complete; 123 } 124 125 val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3, 126 MEMTXATTRS_UNSPECIFIED, &result); 127 if (result != MEMTX_OK) { 128 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%" 129 HWADDR_PRIx " pcba=0x%08x\n", addr, pcba); 130 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); 131 return 0; 132 } 133 134 complete: 135 xscom_complete(current_cpu, HMER_XSCOM_DONE); 136 return val; 137 } 138 139 static void xscom_write(void *opaque, hwaddr addr, uint64_t val, 140 unsigned width) 141 { 142 PnvChip *chip = opaque; 143 uint32_t pcba = pnv_xscom_pcba(chip, addr); 144 MemTxResult result; 145 146 /* Handle some SCOMs here before dispatch */ 147 if (xscom_write_default(chip, pcba, val)) { 148 goto complete; 149 } 150 151 address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val, 152 MEMTXATTRS_UNSPECIFIED, &result); 153 if (result != MEMTX_OK) { 154 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%" 155 HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n", 156 addr, pcba, val); 157 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); 158 return; 159 } 160 161 complete: 162 xscom_complete(current_cpu, HMER_XSCOM_DONE); 163 } 164 165 const MemoryRegionOps pnv_xscom_ops = { 166 .read = xscom_read, 167 .write = xscom_write, 168 .valid.min_access_size = 8, 169 .valid.max_access_size = 8, 170 .impl.min_access_size = 8, 171 .impl.max_access_size = 8, 172 .endianness = DEVICE_BIG_ENDIAN, 173 }; 174 175 void pnv_xscom_realize(PnvChip *chip, Error **errp) 176 { 177 SysBusDevice *sbd = SYS_BUS_DEVICE(chip); 178 char *name; 179 180 name = g_strdup_printf("xscom-%x", chip->chip_id); 181 memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops, 182 chip, name, PNV_XSCOM_SIZE); 183 sysbus_init_mmio(sbd, &chip->xscom_mmio); 184 185 memory_region_init(&chip->xscom, OBJECT(chip), name, PNV_XSCOM_SIZE); 186 address_space_init(&chip->xscom_as, &chip->xscom, name); 187 g_free(name); 188 } 189 190 static const TypeInfo pnv_xscom_interface_info = { 191 .name = TYPE_PNV_XSCOM_INTERFACE, 192 .parent = TYPE_INTERFACE, 193 .class_size = sizeof(PnvXScomInterfaceClass), 194 }; 195 196 static void pnv_xscom_register_types(void) 197 { 198 type_register_static(&pnv_xscom_interface_info); 199 } 200 201 type_init(pnv_xscom_register_types) 202 203 typedef struct ForeachPopulateArgs { 204 void *fdt; 205 int xscom_offset; 206 } ForeachPopulateArgs; 207 208 static int xscom_dt_child(Object *child, void *opaque) 209 { 210 if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) { 211 ForeachPopulateArgs *args = opaque; 212 PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child); 213 PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd); 214 215 if (xc->dt_xscom) { 216 _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset))); 217 } 218 } 219 return 0; 220 } 221 222 static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; 223 static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; 224 225 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) 226 { 227 uint64_t reg[] = { cpu_to_be64(PNV_XSCOM_BASE(chip)), 228 cpu_to_be64(PNV_XSCOM_SIZE) }; 229 int xscom_offset; 230 ForeachPopulateArgs args; 231 char *name; 232 233 name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0])); 234 xscom_offset = fdt_add_subnode(fdt, root_offset, name); 235 _FDT(xscom_offset); 236 g_free(name); 237 _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id))); 238 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1))); 239 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); 240 _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); 241 242 if (pnv_chip_is_power9(chip)) { 243 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, 244 sizeof(compat_p9)))); 245 } else { 246 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8, 247 sizeof(compat_p8)))); 248 } 249 250 _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0))); 251 252 args.fdt = fdt; 253 args.xscom_offset = xscom_offset; 254 255 object_child_foreach(OBJECT(chip), xscom_dt_child, &args); 256 return 0; 257 } 258 259 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr) 260 { 261 memory_region_add_subregion(&chip->xscom, offset << 3, mr); 262 } 263 264 void pnv_xscom_region_init(MemoryRegion *mr, 265 struct Object *owner, 266 const MemoryRegionOps *ops, 267 void *opaque, 268 const char *name, 269 uint64_t size) 270 { 271 memory_region_init_io(mr, owner, ops, opaque, name, size << 3); 272 } 273