1 /* 2 * QEMU PowerPC PowerNV XSCOM bus 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "qapi/error.h" 21 #include "hw/hw.h" 22 #include "qemu/log.h" 23 #include "sysemu/hw_accel.h" 24 #include "target/ppc/cpu.h" 25 #include "hw/sysbus.h" 26 27 #include "hw/ppc/fdt.h" 28 #include "hw/ppc/pnv.h" 29 #include "hw/ppc/pnv_xscom.h" 30 31 #include <libfdt.h> 32 33 static void xscom_complete(CPUState *cs, uint64_t hmer_bits) 34 { 35 /* 36 * TODO: When the read/write comes from the monitor, NULL is 37 * passed for the cpu, and no CPU completion is generated. 38 */ 39 if (cs) { 40 PowerPCCPU *cpu = POWERPC_CPU(cs); 41 CPUPPCState *env = &cpu->env; 42 43 /* 44 * TODO: Need a CPU helper to set HMER, also handle generation 45 * of HMIs 46 */ 47 cpu_synchronize_state(cs); 48 env->spr[SPR_HMER] |= hmer_bits; 49 } 50 } 51 52 static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) 53 { 54 addr &= (PNV_XSCOM_SIZE - 1); 55 56 if (pnv_chip_is_power9(chip)) { 57 return addr >> 3; 58 } else { 59 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 60 } 61 } 62 63 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) 64 { 65 switch (pcba) { 66 case 0xf000f: 67 return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id; 68 case 0x1010c00: /* PIBAM FIR */ 69 case 0x1010c03: /* PIBAM FIR MASK */ 70 case 0x2020007: /* ADU stuff */ 71 case 0x2020009: /* ADU stuff */ 72 case 0x202000f: /* ADU stuff */ 73 return 0; 74 case 0x2013f00: /* PBA stuff */ 75 case 0x2013f01: /* PBA stuff */ 76 case 0x2013f02: /* PBA stuff */ 77 case 0x2013f03: /* PBA stuff */ 78 case 0x2013f04: /* PBA stuff */ 79 case 0x2013f05: /* PBA stuff */ 80 case 0x2013f06: /* PBA stuff */ 81 case 0x2013f07: /* PBA stuff */ 82 return 0; 83 case 0x2013028: /* CAPP stuff */ 84 case 0x201302a: /* CAPP stuff */ 85 case 0x2013801: /* CAPP stuff */ 86 case 0x2013802: /* CAPP stuff */ 87 return 0; 88 default: 89 return -1; 90 } 91 } 92 93 static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val) 94 { 95 /* We ignore writes to these */ 96 switch (pcba) { 97 case 0xf000f: /* chip id is RO */ 98 case 0x1010c00: /* PIBAM FIR */ 99 case 0x1010c01: /* PIBAM FIR */ 100 case 0x1010c02: /* PIBAM FIR */ 101 case 0x1010c03: /* PIBAM FIR MASK */ 102 case 0x1010c04: /* PIBAM FIR MASK */ 103 case 0x1010c05: /* PIBAM FIR MASK */ 104 case 0x2020007: /* ADU stuff */ 105 case 0x2020009: /* ADU stuff */ 106 case 0x202000f: /* ADU stuff */ 107 return true; 108 default: 109 return false; 110 } 111 } 112 113 static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width) 114 { 115 PnvChip *chip = opaque; 116 uint32_t pcba = pnv_xscom_pcba(chip, addr); 117 uint64_t val = 0; 118 MemTxResult result; 119 120 /* Handle some SCOMs here before dispatch */ 121 val = xscom_read_default(chip, pcba); 122 if (val != -1) { 123 goto complete; 124 } 125 126 val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3, 127 MEMTXATTRS_UNSPECIFIED, &result); 128 if (result != MEMTX_OK) { 129 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%" 130 HWADDR_PRIx " pcba=0x%08x\n", addr, pcba); 131 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); 132 return 0; 133 } 134 135 complete: 136 xscom_complete(current_cpu, HMER_XSCOM_DONE); 137 return val; 138 } 139 140 static void xscom_write(void *opaque, hwaddr addr, uint64_t val, 141 unsigned width) 142 { 143 PnvChip *chip = opaque; 144 uint32_t pcba = pnv_xscom_pcba(chip, addr); 145 MemTxResult result; 146 147 /* Handle some SCOMs here before dispatch */ 148 if (xscom_write_default(chip, pcba, val)) { 149 goto complete; 150 } 151 152 address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val, 153 MEMTXATTRS_UNSPECIFIED, &result); 154 if (result != MEMTX_OK) { 155 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%" 156 HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n", 157 addr, pcba, val); 158 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); 159 return; 160 } 161 162 complete: 163 xscom_complete(current_cpu, HMER_XSCOM_DONE); 164 } 165 166 const MemoryRegionOps pnv_xscom_ops = { 167 .read = xscom_read, 168 .write = xscom_write, 169 .valid.min_access_size = 8, 170 .valid.max_access_size = 8, 171 .impl.min_access_size = 8, 172 .impl.max_access_size = 8, 173 .endianness = DEVICE_BIG_ENDIAN, 174 }; 175 176 void pnv_xscom_realize(PnvChip *chip, Error **errp) 177 { 178 SysBusDevice *sbd = SYS_BUS_DEVICE(chip); 179 char *name; 180 181 name = g_strdup_printf("xscom-%x", chip->chip_id); 182 memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops, 183 chip, name, PNV_XSCOM_SIZE); 184 sysbus_init_mmio(sbd, &chip->xscom_mmio); 185 186 memory_region_init(&chip->xscom, OBJECT(chip), name, PNV_XSCOM_SIZE); 187 address_space_init(&chip->xscom_as, &chip->xscom, name); 188 g_free(name); 189 } 190 191 static const TypeInfo pnv_xscom_interface_info = { 192 .name = TYPE_PNV_XSCOM_INTERFACE, 193 .parent = TYPE_INTERFACE, 194 .class_size = sizeof(PnvXScomInterfaceClass), 195 }; 196 197 static void pnv_xscom_register_types(void) 198 { 199 type_register_static(&pnv_xscom_interface_info); 200 } 201 202 type_init(pnv_xscom_register_types) 203 204 typedef struct ForeachPopulateArgs { 205 void *fdt; 206 int xscom_offset; 207 } ForeachPopulateArgs; 208 209 static int xscom_dt_child(Object *child, void *opaque) 210 { 211 if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) { 212 ForeachPopulateArgs *args = opaque; 213 PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child); 214 PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd); 215 216 if (xc->dt_xscom) { 217 _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset))); 218 } 219 } 220 return 0; 221 } 222 223 static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; 224 static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; 225 226 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) 227 { 228 uint64_t reg[] = { cpu_to_be64(PNV_XSCOM_BASE(chip)), 229 cpu_to_be64(PNV_XSCOM_SIZE) }; 230 int xscom_offset; 231 ForeachPopulateArgs args; 232 char *name; 233 234 name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0])); 235 xscom_offset = fdt_add_subnode(fdt, root_offset, name); 236 _FDT(xscom_offset); 237 g_free(name); 238 _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id))); 239 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1))); 240 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); 241 _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); 242 243 if (pnv_chip_is_power9(chip)) { 244 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, 245 sizeof(compat_p9)))); 246 } else { 247 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8, 248 sizeof(compat_p8)))); 249 } 250 251 _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0))); 252 253 args.fdt = fdt; 254 args.xscom_offset = xscom_offset; 255 256 object_child_foreach(OBJECT(chip), xscom_dt_child, &args); 257 return 0; 258 } 259 260 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr) 261 { 262 memory_region_add_subregion(&chip->xscom, offset << 3, mr); 263 } 264 265 void pnv_xscom_region_init(MemoryRegion *mr, 266 struct Object *owner, 267 const MemoryRegionOps *ops, 268 void *opaque, 269 const char *name, 270 uint64_t size) 271 { 272 memory_region_init_io(mr, owner, ops, opaque, name, size << 3); 273 } 274