1 /* 2 * QEMU PowerPC PowerNV XSCOM bus 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/log.h" 22 #include "qemu/module.h" 23 #include "sysemu/hw_accel.h" 24 #include "target/ppc/cpu.h" 25 #include "hw/sysbus.h" 26 27 #include "hw/ppc/fdt.h" 28 #include "hw/ppc/pnv.h" 29 #include "hw/ppc/pnv_xscom.h" 30 31 #include <libfdt.h> 32 33 /* PRD registers */ 34 #define PRD_P8_IPOLL_REG_MASK 0x01020013 35 #define PRD_P8_IPOLL_REG_STATUS 0x01020014 36 #define PRD_P9_IPOLL_REG_MASK 0x000F0033 37 #define PRD_P9_IPOLL_REG_STATUS 0x000F0034 38 39 /* PBA BARs */ 40 #define P8_PBA_BAR0 0x2013f00 41 #define P8_PBA_BAR2 0x2013f02 42 #define P8_PBA_BARMASK0 0x2013f04 43 #define P8_PBA_BARMASK2 0x2013f06 44 #define P9_PBA_BAR0 0x5012b00 45 #define P9_PBA_BAR2 0x5012b02 46 #define P9_PBA_BARMASK0 0x5012b04 47 #define P9_PBA_BARMASK2 0x5012b06 48 49 static void xscom_complete(CPUState *cs, uint64_t hmer_bits) 50 { 51 /* 52 * TODO: When the read/write comes from the monitor, NULL is 53 * passed for the cpu, and no CPU completion is generated. 54 */ 55 if (cs) { 56 PowerPCCPU *cpu = POWERPC_CPU(cs); 57 CPUPPCState *env = &cpu->env; 58 59 /* 60 * TODO: Need a CPU helper to set HMER, also handle generation 61 * of HMIs 62 */ 63 cpu_synchronize_state(cs); 64 env->spr[SPR_HMER] |= hmer_bits; 65 } 66 } 67 68 static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) 69 { 70 addr &= (PNV_XSCOM_SIZE - 1); 71 72 switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { 73 case PNV_CHIP_POWER8E: 74 case PNV_CHIP_POWER8: 75 case PNV_CHIP_POWER8NVL: 76 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 77 case PNV_CHIP_POWER9: 78 case PNV_CHIP_POWER10: 79 return addr >> 3; 80 default: 81 g_assert_not_reached(); 82 } 83 } 84 85 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) 86 { 87 switch (pcba) { 88 case 0xf000f: 89 return PNV_CHIP_GET_CLASS(chip)->chip_cfam_id; 90 case 0x18002: /* ECID2 */ 91 return 0; 92 93 case P9_PBA_BAR0: 94 return PNV9_HOMER_BASE(chip); 95 case P8_PBA_BAR0: 96 return PNV_HOMER_BASE(chip); 97 98 case P9_PBA_BARMASK0: /* P9 homer region size */ 99 return PNV9_HOMER_SIZE; 100 case P8_PBA_BARMASK0: /* P8 homer region size */ 101 return PNV_HOMER_SIZE; 102 103 case P9_PBA_BAR2: /* P9 occ common area */ 104 return PNV9_OCC_COMMON_AREA(chip); 105 case P8_PBA_BAR2: /* P8 occ common area */ 106 return PNV_OCC_COMMON_AREA(chip); 107 108 case P9_PBA_BARMASK2: /* P9 occ common area size */ 109 return PNV9_OCC_COMMON_AREA_SIZE; 110 case P8_PBA_BARMASK2: /* P8 occ common area size */ 111 return PNV_OCC_COMMON_AREA_SIZE; 112 113 case 0x1010c00: /* PIBAM FIR */ 114 case 0x1010c03: /* PIBAM FIR MASK */ 115 116 /* PRD registers */ 117 case PRD_P8_IPOLL_REG_MASK: 118 case PRD_P8_IPOLL_REG_STATUS: 119 case PRD_P9_IPOLL_REG_MASK: 120 case PRD_P9_IPOLL_REG_STATUS: 121 122 /* P9 xscom reset */ 123 case 0x0090018: /* Receive status reg */ 124 case 0x0090012: /* log register */ 125 case 0x0090013: /* error register */ 126 127 /* P8 xscom reset */ 128 case 0x2020007: /* ADU stuff, log register */ 129 case 0x2020009: /* ADU stuff, error register */ 130 case 0x202000f: /* ADU stuff, receive status register*/ 131 return 0; 132 case 0x2013f01: /* PBA stuff */ 133 case 0x2013f03: /* PBA stuff */ 134 case 0x2013f05: /* PBA stuff */ 135 case 0x2013f07: /* PBA stuff */ 136 return 0; 137 case 0x2013028: /* CAPP stuff */ 138 case 0x201302a: /* CAPP stuff */ 139 case 0x2013801: /* CAPP stuff */ 140 case 0x2013802: /* CAPP stuff */ 141 142 /* P9 CAPP regs */ 143 case 0x2010841: 144 case 0x2010842: 145 case 0x201082a: 146 case 0x2010828: 147 case 0x4010841: 148 case 0x4010842: 149 case 0x401082a: 150 case 0x4010828: 151 return 0; 152 default: 153 return -1; 154 } 155 } 156 157 static bool xscom_write_default(PnvChip *chip, uint32_t pcba, uint64_t val) 158 { 159 /* We ignore writes to these */ 160 switch (pcba) { 161 case 0xf000f: /* chip id is RO */ 162 case 0x1010c00: /* PIBAM FIR */ 163 case 0x1010c01: /* PIBAM FIR */ 164 case 0x1010c02: /* PIBAM FIR */ 165 case 0x1010c03: /* PIBAM FIR MASK */ 166 case 0x1010c04: /* PIBAM FIR MASK */ 167 case 0x1010c05: /* PIBAM FIR MASK */ 168 /* P9 xscom reset */ 169 case 0x0090018: /* Receive status reg */ 170 case 0x0090012: /* log register */ 171 case 0x0090013: /* error register */ 172 173 /* P8 xscom reset */ 174 case 0x2020007: /* ADU stuff, log register */ 175 case 0x2020009: /* ADU stuff, error register */ 176 case 0x202000f: /* ADU stuff, receive status register*/ 177 178 case 0x2013028: /* CAPP stuff */ 179 case 0x201302a: /* CAPP stuff */ 180 case 0x2013801: /* CAPP stuff */ 181 case 0x2013802: /* CAPP stuff */ 182 183 /* P9 CAPP regs */ 184 case 0x2010841: 185 case 0x2010842: 186 case 0x201082a: 187 case 0x2010828: 188 case 0x4010841: 189 case 0x4010842: 190 case 0x401082a: 191 case 0x4010828: 192 193 /* P8 PRD registers */ 194 case PRD_P8_IPOLL_REG_MASK: 195 case PRD_P8_IPOLL_REG_STATUS: 196 case PRD_P9_IPOLL_REG_MASK: 197 case PRD_P9_IPOLL_REG_STATUS: 198 return true; 199 default: 200 return false; 201 } 202 } 203 204 static uint64_t xscom_read(void *opaque, hwaddr addr, unsigned width) 205 { 206 PnvChip *chip = opaque; 207 uint32_t pcba = pnv_xscom_pcba(chip, addr); 208 uint64_t val = 0; 209 MemTxResult result; 210 211 /* Handle some SCOMs here before dispatch */ 212 val = xscom_read_default(chip, pcba); 213 if (val != -1) { 214 goto complete; 215 } 216 217 val = address_space_ldq(&chip->xscom_as, (uint64_t) pcba << 3, 218 MEMTXATTRS_UNSPECIFIED, &result); 219 if (result != MEMTX_OK) { 220 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM read failed at @0x%" 221 HWADDR_PRIx " pcba=0x%08x\n", addr, pcba); 222 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); 223 return 0; 224 } 225 226 complete: 227 xscom_complete(current_cpu, HMER_XSCOM_DONE); 228 return val; 229 } 230 231 static void xscom_write(void *opaque, hwaddr addr, uint64_t val, 232 unsigned width) 233 { 234 PnvChip *chip = opaque; 235 uint32_t pcba = pnv_xscom_pcba(chip, addr); 236 MemTxResult result; 237 238 /* Handle some SCOMs here before dispatch */ 239 if (xscom_write_default(chip, pcba, val)) { 240 goto complete; 241 } 242 243 address_space_stq(&chip->xscom_as, (uint64_t) pcba << 3, val, 244 MEMTXATTRS_UNSPECIFIED, &result); 245 if (result != MEMTX_OK) { 246 qemu_log_mask(LOG_GUEST_ERROR, "XSCOM write failed at @0x%" 247 HWADDR_PRIx " pcba=0x%08x data=0x%" PRIx64 "\n", 248 addr, pcba, val); 249 xscom_complete(current_cpu, HMER_XSCOM_FAIL | HMER_XSCOM_DONE); 250 return; 251 } 252 253 complete: 254 xscom_complete(current_cpu, HMER_XSCOM_DONE); 255 } 256 257 const MemoryRegionOps pnv_xscom_ops = { 258 .read = xscom_read, 259 .write = xscom_write, 260 .valid.min_access_size = 8, 261 .valid.max_access_size = 8, 262 .impl.min_access_size = 8, 263 .impl.max_access_size = 8, 264 .endianness = DEVICE_BIG_ENDIAN, 265 }; 266 267 void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp) 268 { 269 SysBusDevice *sbd = SYS_BUS_DEVICE(chip); 270 char *name; 271 272 name = g_strdup_printf("xscom-%x", chip->chip_id); 273 memory_region_init_io(&chip->xscom_mmio, OBJECT(chip), &pnv_xscom_ops, 274 chip, name, size); 275 sysbus_init_mmio(sbd, &chip->xscom_mmio); 276 277 memory_region_init(&chip->xscom, OBJECT(chip), name, size); 278 address_space_init(&chip->xscom_as, &chip->xscom, name); 279 g_free(name); 280 } 281 282 static const TypeInfo pnv_xscom_interface_info = { 283 .name = TYPE_PNV_XSCOM_INTERFACE, 284 .parent = TYPE_INTERFACE, 285 .class_size = sizeof(PnvXScomInterfaceClass), 286 }; 287 288 static void pnv_xscom_register_types(void) 289 { 290 type_register_static(&pnv_xscom_interface_info); 291 } 292 293 type_init(pnv_xscom_register_types) 294 295 typedef struct ForeachPopulateArgs { 296 void *fdt; 297 int xscom_offset; 298 } ForeachPopulateArgs; 299 300 static int xscom_dt_child(Object *child, void *opaque) 301 { 302 if (object_dynamic_cast(child, TYPE_PNV_XSCOM_INTERFACE)) { 303 ForeachPopulateArgs *args = opaque; 304 PnvXScomInterface *xd = PNV_XSCOM_INTERFACE(child); 305 PnvXScomInterfaceClass *xc = PNV_XSCOM_INTERFACE_GET_CLASS(xd); 306 307 if (xc->dt_xscom) { 308 _FDT((xc->dt_xscom(xd, args->fdt, args->xscom_offset))); 309 } 310 } 311 return 0; 312 } 313 314 static const char compat_p8[] = "ibm,power8-xscom\0ibm,xscom"; 315 static const char compat_p9[] = "ibm,power9-xscom\0ibm,xscom"; 316 static const char compat_p10[] = "ibm,power10-xscom\0ibm,xscom"; 317 318 int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) 319 { 320 uint64_t reg[2]; 321 int xscom_offset; 322 ForeachPopulateArgs args; 323 char *name; 324 325 if (pnv_chip_is_power10(chip)) { 326 reg[0] = cpu_to_be64(PNV10_XSCOM_BASE(chip)); 327 reg[1] = cpu_to_be64(PNV10_XSCOM_SIZE); 328 } else if (pnv_chip_is_power9(chip)) { 329 reg[0] = cpu_to_be64(PNV9_XSCOM_BASE(chip)); 330 reg[1] = cpu_to_be64(PNV9_XSCOM_SIZE); 331 } else { 332 reg[0] = cpu_to_be64(PNV_XSCOM_BASE(chip)); 333 reg[1] = cpu_to_be64(PNV_XSCOM_SIZE); 334 } 335 336 name = g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0])); 337 xscom_offset = fdt_add_subnode(fdt, root_offset, name); 338 _FDT(xscom_offset); 339 g_free(name); 340 _FDT((fdt_setprop_cell(fdt, xscom_offset, "ibm,chip-id", chip->chip_id))); 341 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1))); 342 _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); 343 _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); 344 345 if (pnv_chip_is_power10(chip)) { 346 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10, 347 sizeof(compat_p10)))); 348 } else if (pnv_chip_is_power9(chip)) { 349 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, 350 sizeof(compat_p9)))); 351 } else { 352 _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8, 353 sizeof(compat_p8)))); 354 } 355 356 _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0))); 357 358 args.fdt = fdt; 359 args.xscom_offset = xscom_offset; 360 361 object_child_foreach(OBJECT(chip), xscom_dt_child, &args); 362 return 0; 363 } 364 365 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr) 366 { 367 memory_region_add_subregion(&chip->xscom, offset << 3, mr); 368 } 369 370 void pnv_xscom_region_init(MemoryRegion *mr, 371 struct Object *owner, 372 const MemoryRegionOps *ops, 373 void *opaque, 374 const char *name, 375 uint64_t size) 376 { 377 memory_region_init_io(mr, owner, ops, opaque, name, size << 3); 378 } 379