1 /* 2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/irq.h" 22 #include "target/ppc/cpu.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "sysemu/reset.h" 26 #include "qapi/error.h" 27 #include "monitor/monitor.h" 28 29 30 #include "hw/ppc/fdt.h" 31 #include "hw/ppc/pnv.h" 32 #include "hw/ppc/pnv_xscom.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/ppc/pnv_psi.h" 35 36 #include <libfdt.h> 37 38 #define PSIHB_XSCOM_FIR_RW 0x00 39 #define PSIHB_XSCOM_FIR_AND 0x01 40 #define PSIHB_XSCOM_FIR_OR 0x02 41 #define PSIHB_XSCOM_FIRMASK_RW 0x03 42 #define PSIHB_XSCOM_FIRMASK_AND 0x04 43 #define PSIHB_XSCOM_FIRMASK_OR 0x05 44 #define PSIHB_XSCOM_FIRACT0 0x06 45 #define PSIHB_XSCOM_FIRACT1 0x07 46 47 /* Host Bridge Base Address Register */ 48 #define PSIHB_XSCOM_BAR 0x0a 49 #define PSIHB_BAR_EN 0x0000000000000001ull 50 51 /* FSP Base Address Register */ 52 #define PSIHB_XSCOM_FSPBAR 0x0b 53 54 /* PSI Host Bridge Control/Status Register */ 55 #define PSIHB_XSCOM_CR 0x0e 56 #define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull 57 #define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull 58 #define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull 59 #define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull 60 #define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull 61 #define PSIHB_CR_FSP_RESET 0x0200000000000000ull 62 #define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull 63 #define PSIHB_CR_PSI_IRQ 0x0000800000000000ull 64 #define PSIHB_CR_FSP_IRQ 0x0000400000000000ull 65 #define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull 66 #define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull 67 /* and more ... */ 68 69 /* PSIHB Status / Error Mask Register */ 70 #define PSIHB_XSCOM_SEMR 0x0f 71 72 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */ 73 #define PSIHB_XSCOM_XIVR_FSP 0x10 74 #define PSIHB_XIVR_SERVER_SH 40 75 #define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH) 76 #define PSIHB_XIVR_PRIO_SH 32 77 #define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH) 78 #define PSIHB_XIVR_SRC_SH 29 79 #define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH) 80 #define PSIHB_XIVR_PENDING 0x01000000ull 81 82 /* PSI Host Bridge Set Control/ Status Register */ 83 #define PSIHB_XSCOM_SCR 0x12 84 85 /* PSI Host Bridge Clear Control/ Status Register */ 86 #define PSIHB_XSCOM_CCR 0x13 87 88 /* DMA Upper Address Register */ 89 #define PSIHB_XSCOM_DMA_UPADD 0x14 90 91 /* Interrupt Status */ 92 #define PSIHB_XSCOM_IRQ_STAT 0x15 93 #define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull 94 #define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull 95 #define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull 96 #define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull 97 #define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull 98 99 /* remaining XIVR */ 100 #define PSIHB_XSCOM_XIVR_OCC 0x16 101 #define PSIHB_XSCOM_XIVR_FSI 0x17 102 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18 103 #define PSIHB_XSCOM_XIVR_LOCERR 0x19 104 #define PSIHB_XSCOM_XIVR_EXT 0x1a 105 106 /* Interrupt Requester Source Compare Register */ 107 #define PSIHB_XSCOM_IRSN 0x1b 108 #define PSIHB_IRSN_COMP_SH 45 109 #define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH) 110 #define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull 111 #define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull 112 #define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull 113 #define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull 114 #define PSIHB_IRSN_COMPMASK_SH 13 115 #define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH) 116 117 #define PSIHB_BAR_MASK 0x0003fffffff00000ull 118 #define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull 119 120 #define PSIHB9_BAR_MASK 0x00fffffffff00000ull 121 #define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull 122 123 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) 124 125 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) 126 { 127 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi); 128 MemoryRegion *sysmem = get_system_memory(); 129 uint64_t old = psi->regs[PSIHB_XSCOM_BAR]; 130 131 psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN); 132 133 /* Update MR, always remove it first */ 134 if (old & PSIHB_BAR_EN) { 135 memory_region_del_subregion(sysmem, &psi->regs_mr); 136 } 137 138 /* Then add it back if needed */ 139 if (bar & PSIHB_BAR_EN) { 140 uint64_t addr = bar & ppc->bar_mask; 141 memory_region_add_subregion(sysmem, addr, &psi->regs_mr); 142 } 143 } 144 145 static void pnv_psi_update_fsp_mr(PnvPsi *psi) 146 { 147 /* TODO: Update FSP MR if/when we support FSP BAR */ 148 } 149 150 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr) 151 { 152 uint64_t old = psi->regs[PSIHB_XSCOM_CR]; 153 154 psi->regs[PSIHB_XSCOM_CR] = cr; 155 156 /* Check some bit changes */ 157 if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) { 158 pnv_psi_update_fsp_mr(psi); 159 } 160 } 161 162 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val) 163 { 164 ICSState *ics = &PNV8_PSI(psi)->ics; 165 166 /* In this model we ignore the up/down enable bits for now 167 * as SW doesn't use them (other than setting them at boot). 168 * We ignore IRQ_MUX, its meaning isn't clear and we don't use 169 * it and finally we ignore reset (XXX fix that ?) 170 */ 171 psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK | 172 PSIHB_IRSN_IRQ_MUX | 173 PSIHB_IRSN_IRQ_RESET | 174 PSIHB_IRSN_DOWNSTREAM_EN | 175 PSIHB_IRSN_UPSTREAM_EN); 176 177 /* We ignore the compare mask as well, our ICS emulation is too 178 * simplistic to make any use if it, and we extract the offset 179 * from the compare value 180 */ 181 ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH; 182 } 183 184 /* 185 * FSP and PSI interrupts are muxed under the same number. 186 */ 187 static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = { 188 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP, 189 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC, 190 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI, 191 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C, 192 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR, 193 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT, 194 }; 195 196 static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = { 197 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR, 198 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT, 199 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT, 200 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT, 201 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT, 202 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT, 203 }; 204 205 static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = { 206 [PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ, 207 [PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC, 208 [PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI, 209 [PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C, 210 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR, 211 [PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT, 212 }; 213 214 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state) 215 { 216 PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state); 217 } 218 219 static void __pnv_psi_irq_set(void *opaque, int irq, int state) 220 { 221 PnvPsi *psi = (PnvPsi *) opaque; 222 PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state); 223 } 224 225 static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state) 226 { 227 uint32_t xivr_reg; 228 uint32_t stat_reg; 229 uint32_t src; 230 bool masked; 231 232 if (irq > PSIHB_IRQ_EXTERNAL) { 233 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq); 234 return; 235 } 236 237 xivr_reg = xivr_regs[irq]; 238 stat_reg = stat_regs[irq]; 239 240 src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 241 if (state) { 242 psi->regs[stat_reg] |= stat_bits[irq]; 243 /* TODO: optimization, check mask here. That means 244 * re-evaluating when unmasking 245 */ 246 qemu_irq_raise(psi->qirqs[src]); 247 } else { 248 psi->regs[stat_reg] &= ~stat_bits[irq]; 249 250 /* FSP and PSI are muxed so don't lower if either is still set */ 251 if (stat_reg != PSIHB_XSCOM_CR || 252 !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) { 253 qemu_irq_lower(psi->qirqs[src]); 254 } else { 255 state = true; 256 } 257 } 258 259 /* Note about the emulation of the pending bit: This isn't 260 * entirely correct. The pending bit should be cleared when the 261 * EOI has been received. However, we don't have callbacks on EOI 262 * (especially not under KVM) so no way to emulate that properly, 263 * so instead we just set that bit as the logical "output" of the 264 * XIVR (ie pending & !masked) 265 * 266 * CLG: We could define a new ICS object with a custom eoi() 267 * handler to clear the pending bit. But I am not sure this would 268 * be useful for the software anyhow. 269 */ 270 masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK; 271 if (state && !masked) { 272 psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING; 273 } else { 274 psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING; 275 } 276 } 277 278 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val) 279 { 280 ICSState *ics = &PNV8_PSI(psi)->ics; 281 uint16_t server; 282 uint8_t prio; 283 uint8_t src; 284 285 psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) | 286 (val & (PSIHB_XIVR_SERVER_MSK | 287 PSIHB_XIVR_PRIO_MSK | 288 PSIHB_XIVR_SRC_MSK)); 289 val = psi->regs[reg]; 290 server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH; 291 prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH; 292 src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 293 294 if (src >= PSI_NUM_INTERRUPTS) { 295 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src); 296 return; 297 } 298 299 /* Remove pending bit if the IRQ is masked */ 300 if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) { 301 psi->regs[reg] &= ~PSIHB_XIVR_PENDING; 302 } 303 304 /* The low order 2 bits are the link pointer (Type II interrupts). 305 * Shift back to get a valid IRQ server. 306 */ 307 server >>= 2; 308 309 /* Now because of source remapping, weird things can happen 310 * if you change the source number dynamically, our simple ICS 311 * doesn't deal with remapping. So we just poke a different 312 * ICS entry based on what source number was written. This will 313 * do for now but a more accurate implementation would instead 314 * use a fixed server/prio and a remapper of the generated irq. 315 */ 316 ics_write_xive(ics, src, server, prio, prio); 317 } 318 319 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio) 320 { 321 uint64_t val = 0xffffffffffffffffull; 322 323 switch (offset) { 324 case PSIHB_XSCOM_FIR_RW: 325 case PSIHB_XSCOM_FIRACT0: 326 case PSIHB_XSCOM_FIRACT1: 327 case PSIHB_XSCOM_BAR: 328 case PSIHB_XSCOM_FSPBAR: 329 case PSIHB_XSCOM_CR: 330 case PSIHB_XSCOM_XIVR_FSP: 331 case PSIHB_XSCOM_XIVR_OCC: 332 case PSIHB_XSCOM_XIVR_FSI: 333 case PSIHB_XSCOM_XIVR_LPCI2C: 334 case PSIHB_XSCOM_XIVR_LOCERR: 335 case PSIHB_XSCOM_XIVR_EXT: 336 case PSIHB_XSCOM_IRQ_STAT: 337 case PSIHB_XSCOM_SEMR: 338 case PSIHB_XSCOM_DMA_UPADD: 339 case PSIHB_XSCOM_IRSN: 340 val = psi->regs[offset]; 341 break; 342 default: 343 qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset); 344 } 345 return val; 346 } 347 348 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val, 349 bool mmio) 350 { 351 switch (offset) { 352 case PSIHB_XSCOM_FIR_RW: 353 case PSIHB_XSCOM_FIRACT0: 354 case PSIHB_XSCOM_FIRACT1: 355 case PSIHB_XSCOM_SEMR: 356 case PSIHB_XSCOM_DMA_UPADD: 357 psi->regs[offset] = val; 358 break; 359 case PSIHB_XSCOM_FIR_OR: 360 psi->regs[PSIHB_XSCOM_FIR_RW] |= val; 361 break; 362 case PSIHB_XSCOM_FIR_AND: 363 psi->regs[PSIHB_XSCOM_FIR_RW] &= val; 364 break; 365 case PSIHB_XSCOM_BAR: 366 /* Only XSCOM can write this one */ 367 if (!mmio) { 368 pnv_psi_set_bar(psi, val); 369 } else { 370 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n"); 371 } 372 break; 373 case PSIHB_XSCOM_FSPBAR: 374 psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK; 375 pnv_psi_update_fsp_mr(psi); 376 break; 377 case PSIHB_XSCOM_CR: 378 pnv_psi_set_cr(psi, val); 379 break; 380 case PSIHB_XSCOM_SCR: 381 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val); 382 break; 383 case PSIHB_XSCOM_CCR: 384 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val); 385 break; 386 case PSIHB_XSCOM_XIVR_FSP: 387 case PSIHB_XSCOM_XIVR_OCC: 388 case PSIHB_XSCOM_XIVR_FSI: 389 case PSIHB_XSCOM_XIVR_LPCI2C: 390 case PSIHB_XSCOM_XIVR_LOCERR: 391 case PSIHB_XSCOM_XIVR_EXT: 392 pnv_psi_set_xivr(psi, offset, val); 393 break; 394 case PSIHB_XSCOM_IRQ_STAT: 395 /* Read only */ 396 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n"); 397 break; 398 case PSIHB_XSCOM_IRSN: 399 pnv_psi_set_irsn(psi, val); 400 break; 401 default: 402 qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset); 403 } 404 } 405 406 /* 407 * The values of the registers when accessed through the MMIO region 408 * follow the relation : xscom = (mmio + 0x50) >> 3 409 */ 410 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size) 411 { 412 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); 413 } 414 415 static void pnv_psi_mmio_write(void *opaque, hwaddr addr, 416 uint64_t val, unsigned size) 417 { 418 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); 419 } 420 421 static const MemoryRegionOps psi_mmio_ops = { 422 .read = pnv_psi_mmio_read, 423 .write = pnv_psi_mmio_write, 424 .endianness = DEVICE_BIG_ENDIAN, 425 .valid = { 426 .min_access_size = 8, 427 .max_access_size = 8, 428 }, 429 .impl = { 430 .min_access_size = 8, 431 .max_access_size = 8, 432 }, 433 }; 434 435 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size) 436 { 437 return pnv_psi_reg_read(opaque, addr >> 3, false); 438 } 439 440 static void pnv_psi_xscom_write(void *opaque, hwaddr addr, 441 uint64_t val, unsigned size) 442 { 443 pnv_psi_reg_write(opaque, addr >> 3, val, false); 444 } 445 446 static const MemoryRegionOps pnv_psi_xscom_ops = { 447 .read = pnv_psi_xscom_read, 448 .write = pnv_psi_xscom_write, 449 .endianness = DEVICE_BIG_ENDIAN, 450 .valid = { 451 .min_access_size = 8, 452 .max_access_size = 8, 453 }, 454 .impl = { 455 .min_access_size = 8, 456 .max_access_size = 8, 457 } 458 }; 459 460 static void pnv_psi_reset(DeviceState *dev) 461 { 462 PnvPsi *psi = PNV_PSI(dev); 463 464 memset(psi->regs, 0x0, sizeof(psi->regs)); 465 466 psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN; 467 } 468 469 static void pnv_psi_reset_handler(void *dev) 470 { 471 device_cold_reset(DEVICE(dev)); 472 } 473 474 static void pnv_psi_realize(DeviceState *dev, Error **errp) 475 { 476 PnvPsi *psi = PNV_PSI(dev); 477 478 /* Default BAR for MMIO region */ 479 pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); 480 481 qemu_register_reset(pnv_psi_reset_handler, dev); 482 } 483 484 static void pnv_psi_power8_instance_init(Object *obj) 485 { 486 Pnv8Psi *psi8 = PNV8_PSI(obj); 487 488 object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS); 489 object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics), 490 ICS_PROP_XICS); 491 } 492 493 static const uint8_t irq_to_xivr[] = { 494 PSIHB_XSCOM_XIVR_FSP, 495 PSIHB_XSCOM_XIVR_OCC, 496 PSIHB_XSCOM_XIVR_FSI, 497 PSIHB_XSCOM_XIVR_LPCI2C, 498 PSIHB_XSCOM_XIVR_LOCERR, 499 PSIHB_XSCOM_XIVR_EXT, 500 }; 501 502 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) 503 { 504 PnvPsi *psi = PNV_PSI(dev); 505 ICSState *ics = &PNV8_PSI(psi)->ics; 506 unsigned int i; 507 508 /* Create PSI interrupt control source */ 509 if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS, 510 errp)) { 511 return; 512 } 513 if (!qdev_realize(DEVICE(ics), NULL, errp)) { 514 return; 515 } 516 517 for (i = 0; i < ics->nr_irqs; i++) { 518 ics_set_irq_type(ics, i, true); 519 } 520 521 qdev_init_gpio_in(dev, __pnv_psi_irq_set, ics->nr_irqs); 522 523 psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); 524 525 /* XSCOM region for PSI registers */ 526 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops, 527 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE); 528 529 /* Initialize MMIO region */ 530 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, 531 "psihb", PNV_PSIHB_SIZE); 532 533 /* Default sources in XIVR */ 534 for (i = 0; i < PSI_NUM_INTERRUPTS; i++) { 535 uint8_t xivr = irq_to_xivr[i]; 536 psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK | 537 ((uint64_t) i << PSIHB_XIVR_SRC_SH); 538 } 539 540 pnv_psi_realize(dev, errp); 541 } 542 543 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) 544 { 545 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev); 546 char *name; 547 int offset; 548 uint32_t reg[] = { 549 cpu_to_be32(ppc->xscom_pcba), 550 cpu_to_be32(ppc->xscom_size) 551 }; 552 553 name = g_strdup_printf("psihb@%x", ppc->xscom_pcba); 554 offset = fdt_add_subnode(fdt, xscom_offset, name); 555 _FDT(offset); 556 g_free(name); 557 558 _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); 559 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); 560 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); 561 _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat, 562 ppc->compat_size)); 563 return 0; 564 } 565 566 static Property pnv_psi_properties[] = { 567 DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0), 568 DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0), 569 DEFINE_PROP_END_OF_LIST(), 570 }; 571 572 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) 573 { 574 DeviceClass *dc = DEVICE_CLASS(klass); 575 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 576 static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x"; 577 578 dc->desc = "PowerNV PSI Controller POWER8"; 579 dc->realize = pnv_psi_power8_realize; 580 581 ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE; 582 ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE; 583 ppc->bar_mask = PSIHB_BAR_MASK; 584 ppc->irq_set = pnv_psi_power8_irq_set; 585 ppc->compat = compat; 586 ppc->compat_size = sizeof(compat); 587 } 588 589 static const TypeInfo pnv_psi_power8_info = { 590 .name = TYPE_PNV8_PSI, 591 .parent = TYPE_PNV_PSI, 592 .instance_size = sizeof(Pnv8Psi), 593 .instance_init = pnv_psi_power8_instance_init, 594 .class_init = pnv_psi_power8_class_init, 595 }; 596 597 598 /* Common registers */ 599 600 #define PSIHB9_CR 0x20 601 #define PSIHB9_SEMR 0x28 602 603 /* P9 registers */ 604 605 #define PSIHB9_INTERRUPT_CONTROL 0x58 606 #define PSIHB9_IRQ_METHOD PPC_BIT(0) 607 #define PSIHB9_IRQ_RESET PPC_BIT(1) 608 #define PSIHB9_ESB_CI_BASE 0x60 609 #define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47) 610 #define PSIHB9_ESB_CI_VALID PPC_BIT(63) 611 #define PSIHB9_ESB_NOTIF_ADDR 0x68 612 #define PSIHB9_ESB_NOTIF_ADDR_MASK PPC_BITMASK(8, 60) 613 #define PSIHB9_ESB_NOTIF_VALID PPC_BIT(63) 614 #define PSIHB9_IVT_OFFSET 0x70 615 #define PSIHB9_IVT_OFF_SHIFT 32 616 617 #define PSIHB9_IRQ_LEVEL 0x78 /* assertion */ 618 #define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0) 619 #define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1) 620 #define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2) 621 #define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3) 622 #define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4) 623 #define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5) 624 #define PSIHB9_IRQ_LEVEL_TPM PPC_BIT(6) 625 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ1 PPC_BIT(7) 626 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ2 PPC_BIT(8) 627 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ3 PPC_BIT(9) 628 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ4 PPC_BIT(10) 629 #define PSIHB9_IRQ_LEVEL_SBE_I2C PPC_BIT(11) 630 #define PSIHB9_IRQ_LEVEL_DIO PPC_BIT(12) 631 #define PSIHB9_IRQ_LEVEL_PSU PPC_BIT(13) 632 #define PSIHB9_IRQ_LEVEL_I2C_C PPC_BIT(14) 633 #define PSIHB9_IRQ_LEVEL_I2C_D PPC_BIT(15) 634 #define PSIHB9_IRQ_LEVEL_I2C_E PPC_BIT(16) 635 #define PSIHB9_IRQ_LEVEL_SBE PPC_BIT(19) 636 637 #define PSIHB9_IRQ_STAT 0x80 /* P bit */ 638 #define PSIHB9_IRQ_STAT_PSI PPC_BIT(0) 639 #define PSIHB9_IRQ_STAT_OCC PPC_BIT(1) 640 #define PSIHB9_IRQ_STAT_FSI PPC_BIT(2) 641 #define PSIHB9_IRQ_STAT_LPCHC PPC_BIT(3) 642 #define PSIHB9_IRQ_STAT_LOCAL_ERR PPC_BIT(4) 643 #define PSIHB9_IRQ_STAT_GLOBAL_ERR PPC_BIT(5) 644 #define PSIHB9_IRQ_STAT_TPM PPC_BIT(6) 645 #define PSIHB9_IRQ_STAT_LPC_SIRQ1 PPC_BIT(7) 646 #define PSIHB9_IRQ_STAT_LPC_SIRQ2 PPC_BIT(8) 647 #define PSIHB9_IRQ_STAT_LPC_SIRQ3 PPC_BIT(9) 648 #define PSIHB9_IRQ_STAT_LPC_SIRQ4 PPC_BIT(10) 649 #define PSIHB9_IRQ_STAT_SBE_I2C PPC_BIT(11) 650 #define PSIHB9_IRQ_STAT_DIO PPC_BIT(12) 651 #define PSIHB9_IRQ_STAT_PSU PPC_BIT(13) 652 653 /* P10 register extensions */ 654 655 #define PSIHB10_CR PSIHB9_CR 656 #define PSIHB10_CR_STORE_EOI PPC_BIT(12) 657 658 #define PSIHB10_ESB_CI_BASE PSIHB9_ESB_CI_BASE 659 #define PSIHB10_ESB_CI_64K PPC_BIT(1) 660 661 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno, bool pq_checked) 662 { 663 PnvPsi *psi = PNV_PSI(xf); 664 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; 665 bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID; 666 uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID; 667 668 uint32_t offset = 669 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); 670 uint64_t data = offset | srcno; 671 MemTxResult result; 672 673 if (pq_checked) { 674 data |= XIVE_TRIGGER_PQ; 675 } 676 677 if (!valid) { 678 return; 679 } 680 681 address_space_stq_be(&address_space_memory, notify_addr, data, 682 MEMTXATTRS_UNSPECIFIED, &result); 683 if (result != MEMTX_OK) { 684 qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%" 685 HWADDR_PRIx "\n", __func__, notif_port); 686 return; 687 } 688 } 689 690 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size) 691 { 692 PnvPsi *psi = PNV_PSI(opaque); 693 uint32_t reg = PSIHB_REG(addr); 694 uint64_t val = -1; 695 696 switch (addr) { 697 case PSIHB9_CR: 698 case PSIHB9_SEMR: 699 /* FSP stuff */ 700 case PSIHB9_INTERRUPT_CONTROL: 701 case PSIHB9_ESB_CI_BASE: 702 case PSIHB9_ESB_NOTIF_ADDR: 703 case PSIHB9_IVT_OFFSET: 704 val = psi->regs[reg]; 705 break; 706 default: 707 qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr); 708 } 709 710 return val; 711 } 712 713 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, 714 uint64_t val, unsigned size) 715 { 716 PnvPsi *psi = PNV_PSI(opaque); 717 Pnv9Psi *psi9 = PNV9_PSI(psi); 718 uint32_t reg = PSIHB_REG(addr); 719 MemoryRegion *sysmem = get_system_memory(); 720 721 switch (addr) { 722 case PSIHB9_CR: 723 if (val & PSIHB10_CR_STORE_EOI) { 724 psi9->source.esb_flags |= XIVE_SRC_STORE_EOI; 725 } else { 726 psi9->source.esb_flags &= ~XIVE_SRC_STORE_EOI; 727 } 728 break; 729 730 case PSIHB9_SEMR: 731 /* FSP stuff */ 732 break; 733 case PSIHB9_INTERRUPT_CONTROL: 734 if (val & PSIHB9_IRQ_RESET) { 735 device_cold_reset(DEVICE(&psi9->source)); 736 } 737 psi->regs[reg] = val; 738 break; 739 740 case PSIHB9_ESB_CI_BASE: 741 if (val & PSIHB10_ESB_CI_64K) { 742 psi9->source.esb_shift = XIVE_ESB_64K; 743 } else { 744 psi9->source.esb_shift = XIVE_ESB_4K; 745 } 746 if (!(val & PSIHB9_ESB_CI_VALID)) { 747 if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) { 748 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio); 749 } 750 } else { 751 if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) { 752 hwaddr addr = val & ~(PSIHB9_ESB_CI_VALID | PSIHB10_ESB_CI_64K); 753 memory_region_add_subregion(sysmem, addr, 754 &psi9->source.esb_mmio); 755 } 756 } 757 psi->regs[reg] = val; 758 break; 759 760 case PSIHB9_ESB_NOTIF_ADDR: 761 psi->regs[reg] = val; 762 break; 763 case PSIHB9_IVT_OFFSET: 764 psi->regs[reg] = val; 765 break; 766 default: 767 qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr); 768 } 769 } 770 771 static const MemoryRegionOps pnv_psi_p9_mmio_ops = { 772 .read = pnv_psi_p9_mmio_read, 773 .write = pnv_psi_p9_mmio_write, 774 .endianness = DEVICE_BIG_ENDIAN, 775 .valid = { 776 .min_access_size = 8, 777 .max_access_size = 8, 778 }, 779 .impl = { 780 .min_access_size = 8, 781 .max_access_size = 8, 782 }, 783 }; 784 785 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size) 786 { 787 /* No read are expected */ 788 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr); 789 return -1; 790 } 791 792 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr, 793 uint64_t val, unsigned size) 794 { 795 PnvPsi *psi = PNV_PSI(opaque); 796 797 /* XSCOM is only used to set the PSIHB MMIO region */ 798 switch (addr >> 3) { 799 case PSIHB_XSCOM_BAR: 800 pnv_psi_set_bar(psi, val); 801 break; 802 default: 803 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n", 804 addr); 805 } 806 } 807 808 static const MemoryRegionOps pnv_psi_p9_xscom_ops = { 809 .read = pnv_psi_p9_xscom_read, 810 .write = pnv_psi_p9_xscom_write, 811 .endianness = DEVICE_BIG_ENDIAN, 812 .valid = { 813 .min_access_size = 8, 814 .max_access_size = 8, 815 }, 816 .impl = { 817 .min_access_size = 8, 818 .max_access_size = 8, 819 } 820 }; 821 822 static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state) 823 { 824 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; 825 826 if (irq > PSIHB9_NUM_IRQS) { 827 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq); 828 return; 829 } 830 831 if (irq_method & PSIHB9_IRQ_METHOD) { 832 qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n"); 833 return; 834 } 835 836 /* Update LSI levels */ 837 if (state) { 838 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); 839 } else { 840 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); 841 } 842 843 qemu_set_irq(psi->qirqs[irq], state); 844 } 845 846 static void pnv_psi_power9_reset(DeviceState *dev) 847 { 848 Pnv9Psi *psi = PNV9_PSI(dev); 849 850 pnv_psi_reset(dev); 851 852 if (memory_region_is_mapped(&psi->source.esb_mmio)) { 853 memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio); 854 } 855 } 856 857 static void pnv_psi_power9_instance_init(Object *obj) 858 { 859 Pnv9Psi *psi = PNV9_PSI(obj); 860 861 object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE); 862 object_property_add_alias(obj, "shift", OBJECT(&psi->source), "shift"); 863 } 864 865 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) 866 { 867 PnvPsi *psi = PNV_PSI(dev); 868 XiveSource *xsrc = &PNV9_PSI(psi)->source; 869 int i; 870 871 object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS, 872 &error_fatal); 873 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort); 874 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { 875 return; 876 } 877 878 for (i = 0; i < xsrc->nr_irqs; i++) { 879 xive_source_irq_set_lsi(xsrc, i); 880 } 881 882 psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); 883 884 qdev_init_gpio_in(dev, __pnv_psi_irq_set, xsrc->nr_irqs); 885 886 /* XSCOM region for PSI registers */ 887 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops, 888 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE); 889 890 /* MMIO region for PSI registers */ 891 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi, 892 "psihb", PNV9_PSIHB_SIZE); 893 894 pnv_psi_realize(dev, errp); 895 } 896 897 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) 898 { 899 DeviceClass *dc = DEVICE_CLASS(klass); 900 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 901 XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); 902 static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x"; 903 904 dc->desc = "PowerNV PSI Controller POWER9"; 905 dc->realize = pnv_psi_power9_realize; 906 dc->reset = pnv_psi_power9_reset; 907 908 ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; 909 ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; 910 ppc->bar_mask = PSIHB9_BAR_MASK; 911 ppc->irq_set = pnv_psi_power9_irq_set; 912 ppc->compat = compat; 913 ppc->compat_size = sizeof(compat); 914 915 xfc->notify = pnv_psi_notify; 916 } 917 918 static const TypeInfo pnv_psi_power9_info = { 919 .name = TYPE_PNV9_PSI, 920 .parent = TYPE_PNV_PSI, 921 .instance_size = sizeof(Pnv9Psi), 922 .instance_init = pnv_psi_power9_instance_init, 923 .class_init = pnv_psi_power9_class_init, 924 .interfaces = (InterfaceInfo[]) { 925 { TYPE_XIVE_NOTIFIER }, 926 { }, 927 }, 928 }; 929 930 static void pnv_psi_power10_class_init(ObjectClass *klass, void *data) 931 { 932 DeviceClass *dc = DEVICE_CLASS(klass); 933 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 934 static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x"; 935 936 dc->desc = "PowerNV PSI Controller POWER10"; 937 938 ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE; 939 ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE; 940 ppc->compat = compat; 941 ppc->compat_size = sizeof(compat); 942 } 943 944 static const TypeInfo pnv_psi_power10_info = { 945 .name = TYPE_PNV10_PSI, 946 .parent = TYPE_PNV9_PSI, 947 .class_init = pnv_psi_power10_class_init, 948 }; 949 950 static void pnv_psi_class_init(ObjectClass *klass, void *data) 951 { 952 DeviceClass *dc = DEVICE_CLASS(klass); 953 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 954 955 xdc->dt_xscom = pnv_psi_dt_xscom; 956 957 dc->desc = "PowerNV PSI Controller"; 958 device_class_set_props(dc, pnv_psi_properties); 959 dc->reset = pnv_psi_reset; 960 dc->user_creatable = false; 961 } 962 963 static const TypeInfo pnv_psi_info = { 964 .name = TYPE_PNV_PSI, 965 .parent = TYPE_DEVICE, 966 .instance_size = sizeof(PnvPsi), 967 .class_init = pnv_psi_class_init, 968 .class_size = sizeof(PnvPsiClass), 969 .abstract = true, 970 .interfaces = (InterfaceInfo[]) { 971 { TYPE_PNV_XSCOM_INTERFACE }, 972 { } 973 } 974 }; 975 976 static void pnv_psi_register_types(void) 977 { 978 type_register_static(&pnv_psi_info); 979 type_register_static(&pnv_psi_power8_info); 980 type_register_static(&pnv_psi_power9_info); 981 type_register_static(&pnv_psi_power10_info); 982 } 983 984 type_init(pnv_psi_register_types); 985 986 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon) 987 { 988 PnvPsi *psi = PNV_PSI(psi9); 989 990 uint32_t offset = 991 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); 992 993 monitor_printf(mon, "PSIHB Source %08x .. %08x\n", 994 offset, offset + psi9->source.nr_irqs - 1); 995 xive_source_pic_print_info(&psi9->source, offset, mon); 996 } 997