xref: /openbmc/qemu/hw/ppc/pnv_psi.c (revision 9d49bcf6)
1 /*
2  * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
3  *
4  * Copyright (c) 2015-2017, IBM Corporation.
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2.1 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "hw/irq.h"
22 #include "target/ppc/cpu.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 #include "sysemu/reset.h"
26 #include "qapi/error.h"
27 #include "monitor/monitor.h"
28 
29 
30 #include "hw/ppc/fdt.h"
31 #include "hw/ppc/pnv.h"
32 #include "hw/ppc/pnv_xscom.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/ppc/pnv_psi.h"
35 
36 #include <libfdt.h>
37 
38 #define PSIHB_XSCOM_FIR_RW      0x00
39 #define PSIHB_XSCOM_FIR_AND     0x01
40 #define PSIHB_XSCOM_FIR_OR      0x02
41 #define PSIHB_XSCOM_FIRMASK_RW  0x03
42 #define PSIHB_XSCOM_FIRMASK_AND 0x04
43 #define PSIHB_XSCOM_FIRMASK_OR  0x05
44 #define PSIHB_XSCOM_FIRACT0     0x06
45 #define PSIHB_XSCOM_FIRACT1     0x07
46 
47 /* Host Bridge Base Address Register */
48 #define PSIHB_XSCOM_BAR         0x0a
49 #define   PSIHB_BAR_EN                  0x0000000000000001ull
50 
51 /* FSP Base Address Register */
52 #define PSIHB_XSCOM_FSPBAR      0x0b
53 
54 /* PSI Host Bridge Control/Status Register */
55 #define PSIHB_XSCOM_CR          0x0e
56 #define   PSIHB_CR_FSP_CMD_ENABLE       0x8000000000000000ull
57 #define   PSIHB_CR_FSP_MMIO_ENABLE      0x4000000000000000ull
58 #define   PSIHB_CR_FSP_IRQ_ENABLE       0x1000000000000000ull
59 #define   PSIHB_CR_FSP_ERR_RSP_ENABLE   0x0800000000000000ull
60 #define   PSIHB_CR_PSI_LINK_ENABLE      0x0400000000000000ull
61 #define   PSIHB_CR_FSP_RESET            0x0200000000000000ull
62 #define   PSIHB_CR_PSIHB_RESET          0x0100000000000000ull
63 #define   PSIHB_CR_PSI_IRQ              0x0000800000000000ull
64 #define   PSIHB_CR_FSP_IRQ              0x0000400000000000ull
65 #define   PSIHB_CR_FSP_LINK_ACTIVE      0x0000200000000000ull
66 #define   PSIHB_CR_IRQ_CMD_EXPECT       0x0000010000000000ull
67           /* and more ... */
68 
69 /* PSIHB Status / Error Mask Register */
70 #define PSIHB_XSCOM_SEMR        0x0f
71 
72 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
73 #define PSIHB_XSCOM_XIVR_FSP    0x10
74 #define   PSIHB_XIVR_SERVER_SH          40
75 #define   PSIHB_XIVR_SERVER_MSK         (0xffffull << PSIHB_XIVR_SERVER_SH)
76 #define   PSIHB_XIVR_PRIO_SH            32
77 #define   PSIHB_XIVR_PRIO_MSK           (0xffull << PSIHB_XIVR_PRIO_SH)
78 #define   PSIHB_XIVR_SRC_SH             29
79 #define   PSIHB_XIVR_SRC_MSK            (0x7ull << PSIHB_XIVR_SRC_SH)
80 #define   PSIHB_XIVR_PENDING            0x01000000ull
81 
82 /* PSI Host Bridge Set Control/ Status Register */
83 #define PSIHB_XSCOM_SCR         0x12
84 
85 /* PSI Host Bridge Clear Control/ Status Register */
86 #define PSIHB_XSCOM_CCR         0x13
87 
88 /* DMA Upper Address Register */
89 #define PSIHB_XSCOM_DMA_UPADD   0x14
90 
91 /* Interrupt Status */
92 #define PSIHB_XSCOM_IRQ_STAT    0x15
93 #define   PSIHB_IRQ_STAT_OCC            0x0000001000000000ull
94 #define   PSIHB_IRQ_STAT_FSI            0x0000000800000000ull
95 #define   PSIHB_IRQ_STAT_LPCI2C         0x0000000400000000ull
96 #define   PSIHB_IRQ_STAT_LOCERR         0x0000000200000000ull
97 #define   PSIHB_IRQ_STAT_EXT            0x0000000100000000ull
98 
99 /* remaining XIVR */
100 #define PSIHB_XSCOM_XIVR_OCC    0x16
101 #define PSIHB_XSCOM_XIVR_FSI    0x17
102 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18
103 #define PSIHB_XSCOM_XIVR_LOCERR 0x19
104 #define PSIHB_XSCOM_XIVR_EXT    0x1a
105 
106 /* Interrupt Requester Source Compare Register */
107 #define PSIHB_XSCOM_IRSN        0x1b
108 #define   PSIHB_IRSN_COMP_SH            45
109 #define   PSIHB_IRSN_COMP_MSK           (0x7ffffull << PSIHB_IRSN_COMP_SH)
110 #define   PSIHB_IRSN_IRQ_MUX            0x0000000800000000ull
111 #define   PSIHB_IRSN_IRQ_RESET          0x0000000400000000ull
112 #define   PSIHB_IRSN_DOWNSTREAM_EN      0x0000000200000000ull
113 #define   PSIHB_IRSN_UPSTREAM_EN        0x0000000100000000ull
114 #define   PSIHB_IRSN_COMPMASK_SH        13
115 #define   PSIHB_IRSN_COMPMASK_MSK       (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
116 
117 #define PSIHB_BAR_MASK                  0x0003fffffff00000ull
118 #define PSIHB_FSPBAR_MASK               0x0003ffff00000000ull
119 
120 #define PSIHB9_BAR_MASK                 0x00fffffffff00000ull
121 #define PSIHB9_FSPBAR_MASK              0x00ffffff00000000ull
122 
123 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
124 
125 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
126 {
127     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
128     MemoryRegion *sysmem = get_system_memory();
129     uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
130 
131     psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
132 
133     /* Update MR, always remove it first */
134     if (old & PSIHB_BAR_EN) {
135         memory_region_del_subregion(sysmem, &psi->regs_mr);
136     }
137 
138     /* Then add it back if needed */
139     if (bar & PSIHB_BAR_EN) {
140         uint64_t addr = bar & ppc->bar_mask;
141         memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
142     }
143 }
144 
145 static void pnv_psi_update_fsp_mr(PnvPsi *psi)
146 {
147     /* TODO: Update FSP MR if/when we support FSP BAR */
148 }
149 
150 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
151 {
152     uint64_t old = psi->regs[PSIHB_XSCOM_CR];
153 
154     psi->regs[PSIHB_XSCOM_CR] = cr;
155 
156     /* Check some bit changes */
157     if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
158         pnv_psi_update_fsp_mr(psi);
159     }
160 }
161 
162 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
163 {
164     ICSState *ics = &PNV8_PSI(psi)->ics;
165 
166     /* In this model we ignore the up/down enable bits for now
167      * as SW doesn't use them (other than setting them at boot).
168      * We ignore IRQ_MUX, its meaning isn't clear and we don't use
169      * it and finally we ignore reset (XXX fix that ?)
170      */
171     psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
172                                          PSIHB_IRSN_IRQ_MUX |
173                                          PSIHB_IRSN_IRQ_RESET |
174                                          PSIHB_IRSN_DOWNSTREAM_EN |
175                                          PSIHB_IRSN_UPSTREAM_EN);
176 
177     /* We ignore the compare mask as well, our ICS emulation is too
178      * simplistic to make any use if it, and we extract the offset
179      * from the compare value
180      */
181     ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
182 }
183 
184 /*
185  * FSP and PSI interrupts are muxed under the same number.
186  */
187 static const uint32_t xivr_regs[] = {
188     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_XIVR_FSP,
189     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_XIVR_FSP,
190     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_XIVR_OCC,
191     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_XIVR_FSI,
192     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_XIVR_LPCI2C,
193     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
194     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_XIVR_EXT,
195 };
196 
197 static const uint32_t stat_regs[] = {
198     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_CR,
199     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_CR,
200     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_IRQ_STAT,
201     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_IRQ_STAT,
202     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_IRQ_STAT,
203     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
204     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_IRQ_STAT,
205 };
206 
207 static const uint64_t stat_bits[] = {
208     [PSIHB_IRQ_PSI]       = PSIHB_CR_PSI_IRQ,
209     [PSIHB_IRQ_FSP]       = PSIHB_CR_FSP_IRQ,
210     [PSIHB_IRQ_OCC]       = PSIHB_IRQ_STAT_OCC,
211     [PSIHB_IRQ_FSI]       = PSIHB_IRQ_STAT_FSI,
212     [PSIHB_IRQ_LPC_I2C]   = PSIHB_IRQ_STAT_LPCI2C,
213     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
214     [PSIHB_IRQ_EXTERNAL]  = PSIHB_IRQ_STAT_EXT,
215 };
216 
217 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
218 {
219     PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
220 }
221 
222 static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
223 {
224     uint32_t xivr_reg;
225     uint32_t stat_reg;
226     uint32_t src;
227     bool masked;
228 
229     if (irq > PSIHB_IRQ_EXTERNAL) {
230         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
231         return;
232     }
233 
234     xivr_reg = xivr_regs[irq];
235     stat_reg = stat_regs[irq];
236 
237     src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
238     if (state) {
239         psi->regs[stat_reg] |= stat_bits[irq];
240         /* TODO: optimization, check mask here. That means
241          * re-evaluating when unmasking
242          */
243         qemu_irq_raise(psi->qirqs[src]);
244     } else {
245         psi->regs[stat_reg] &= ~stat_bits[irq];
246 
247         /* FSP and PSI are muxed so don't lower if either is still set */
248         if (stat_reg != PSIHB_XSCOM_CR ||
249             !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
250             qemu_irq_lower(psi->qirqs[src]);
251         } else {
252             state = true;
253         }
254     }
255 
256     /* Note about the emulation of the pending bit: This isn't
257      * entirely correct. The pending bit should be cleared when the
258      * EOI has been received. However, we don't have callbacks on EOI
259      * (especially not under KVM) so no way to emulate that properly,
260      * so instead we just set that bit as the logical "output" of the
261      * XIVR (ie pending & !masked)
262      *
263      * CLG: We could define a new ICS object with a custom eoi()
264      * handler to clear the pending bit. But I am not sure this would
265      * be useful for the software anyhow.
266      */
267     masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
268     if (state && !masked) {
269         psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
270     } else {
271         psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
272     }
273 }
274 
275 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
276 {
277     ICSState *ics = &PNV8_PSI(psi)->ics;
278     uint16_t server;
279     uint8_t prio;
280     uint8_t src;
281 
282     psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
283             (val & (PSIHB_XIVR_SERVER_MSK |
284                     PSIHB_XIVR_PRIO_MSK |
285                     PSIHB_XIVR_SRC_MSK));
286     val = psi->regs[reg];
287     server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
288     prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
289     src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
290 
291     if (src >= PSI_NUM_INTERRUPTS) {
292         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
293         return;
294     }
295 
296     /* Remove pending bit if the IRQ is masked */
297     if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
298         psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
299     }
300 
301     /* The low order 2 bits are the link pointer (Type II interrupts).
302      * Shift back to get a valid IRQ server.
303      */
304     server >>= 2;
305 
306     /* Now because of source remapping, weird things can happen
307      * if you change the source number dynamically, our simple ICS
308      * doesn't deal with remapping. So we just poke a different
309      * ICS entry based on what source number was written. This will
310      * do for now but a more accurate implementation would instead
311      * use a fixed server/prio and a remapper of the generated irq.
312      */
313     ics_write_xive(ics, src, server, prio, prio);
314 }
315 
316 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
317 {
318     uint64_t val = 0xffffffffffffffffull;
319 
320     switch (offset) {
321     case PSIHB_XSCOM_FIR_RW:
322     case PSIHB_XSCOM_FIRACT0:
323     case PSIHB_XSCOM_FIRACT1:
324     case PSIHB_XSCOM_BAR:
325     case PSIHB_XSCOM_FSPBAR:
326     case PSIHB_XSCOM_CR:
327     case PSIHB_XSCOM_XIVR_FSP:
328     case PSIHB_XSCOM_XIVR_OCC:
329     case PSIHB_XSCOM_XIVR_FSI:
330     case PSIHB_XSCOM_XIVR_LPCI2C:
331     case PSIHB_XSCOM_XIVR_LOCERR:
332     case PSIHB_XSCOM_XIVR_EXT:
333     case PSIHB_XSCOM_IRQ_STAT:
334     case PSIHB_XSCOM_SEMR:
335     case PSIHB_XSCOM_DMA_UPADD:
336     case PSIHB_XSCOM_IRSN:
337         val = psi->regs[offset];
338         break;
339     default:
340         qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
341     }
342     return val;
343 }
344 
345 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
346                               bool mmio)
347 {
348     switch (offset) {
349     case PSIHB_XSCOM_FIR_RW:
350     case PSIHB_XSCOM_FIRACT0:
351     case PSIHB_XSCOM_FIRACT1:
352     case PSIHB_XSCOM_SEMR:
353     case PSIHB_XSCOM_DMA_UPADD:
354         psi->regs[offset] = val;
355         break;
356     case PSIHB_XSCOM_FIR_OR:
357         psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
358         break;
359     case PSIHB_XSCOM_FIR_AND:
360         psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
361         break;
362     case PSIHB_XSCOM_BAR:
363         /* Only XSCOM can write this one */
364         if (!mmio) {
365             pnv_psi_set_bar(psi, val);
366         } else {
367             qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
368         }
369         break;
370     case PSIHB_XSCOM_FSPBAR:
371         psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
372         pnv_psi_update_fsp_mr(psi);
373         break;
374     case PSIHB_XSCOM_CR:
375         pnv_psi_set_cr(psi, val);
376         break;
377     case PSIHB_XSCOM_SCR:
378         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
379         break;
380     case PSIHB_XSCOM_CCR:
381         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
382         break;
383     case PSIHB_XSCOM_XIVR_FSP:
384     case PSIHB_XSCOM_XIVR_OCC:
385     case PSIHB_XSCOM_XIVR_FSI:
386     case PSIHB_XSCOM_XIVR_LPCI2C:
387     case PSIHB_XSCOM_XIVR_LOCERR:
388     case PSIHB_XSCOM_XIVR_EXT:
389         pnv_psi_set_xivr(psi, offset, val);
390         break;
391     case PSIHB_XSCOM_IRQ_STAT:
392         /* Read only */
393         qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
394         break;
395     case PSIHB_XSCOM_IRSN:
396         pnv_psi_set_irsn(psi, val);
397         break;
398     default:
399         qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
400     }
401 }
402 
403 /*
404  * The values of the registers when accessed through the MMIO region
405  * follow the relation : xscom = (mmio + 0x50) >> 3
406  */
407 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
408 {
409     return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
410 }
411 
412 static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
413                               uint64_t val, unsigned size)
414 {
415     pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
416 }
417 
418 static const MemoryRegionOps psi_mmio_ops = {
419     .read = pnv_psi_mmio_read,
420     .write = pnv_psi_mmio_write,
421     .endianness = DEVICE_BIG_ENDIAN,
422     .valid = {
423         .min_access_size = 8,
424         .max_access_size = 8,
425     },
426     .impl = {
427         .min_access_size = 8,
428         .max_access_size = 8,
429     },
430 };
431 
432 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
433 {
434     return pnv_psi_reg_read(opaque, addr >> 3, false);
435 }
436 
437 static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
438                                 uint64_t val, unsigned size)
439 {
440     pnv_psi_reg_write(opaque, addr >> 3, val, false);
441 }
442 
443 static const MemoryRegionOps pnv_psi_xscom_ops = {
444     .read = pnv_psi_xscom_read,
445     .write = pnv_psi_xscom_write,
446     .endianness = DEVICE_BIG_ENDIAN,
447     .valid = {
448         .min_access_size = 8,
449         .max_access_size = 8,
450     },
451     .impl = {
452         .min_access_size = 8,
453         .max_access_size = 8,
454     }
455 };
456 
457 static void pnv_psi_reset(DeviceState *dev)
458 {
459     PnvPsi *psi = PNV_PSI(dev);
460 
461     memset(psi->regs, 0x0, sizeof(psi->regs));
462 
463     psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
464 }
465 
466 static void pnv_psi_reset_handler(void *dev)
467 {
468     device_cold_reset(DEVICE(dev));
469 }
470 
471 static void pnv_psi_realize(DeviceState *dev, Error **errp)
472 {
473     PnvPsi *psi = PNV_PSI(dev);
474 
475     /* Default BAR for MMIO region */
476     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
477 
478     qemu_register_reset(pnv_psi_reset_handler, dev);
479 }
480 
481 static void pnv_psi_power8_instance_init(Object *obj)
482 {
483     Pnv8Psi *psi8 = PNV8_PSI(obj);
484 
485     object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS);
486     object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics),
487                               ICS_PROP_XICS);
488 }
489 
490 static const uint8_t irq_to_xivr[] = {
491     PSIHB_XSCOM_XIVR_FSP,
492     PSIHB_XSCOM_XIVR_OCC,
493     PSIHB_XSCOM_XIVR_FSI,
494     PSIHB_XSCOM_XIVR_LPCI2C,
495     PSIHB_XSCOM_XIVR_LOCERR,
496     PSIHB_XSCOM_XIVR_EXT,
497 };
498 
499 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
500 {
501     PnvPsi *psi = PNV_PSI(dev);
502     ICSState *ics = &PNV8_PSI(psi)->ics;
503     unsigned int i;
504 
505     /* Create PSI interrupt control source */
506     if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS,
507                                  errp)) {
508         return;
509     }
510     if (!qdev_realize(DEVICE(ics), NULL, errp)) {
511         return;
512     }
513 
514     for (i = 0; i < ics->nr_irqs; i++) {
515         ics_set_irq_type(ics, i, true);
516     }
517 
518     psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
519 
520     /* XSCOM region for PSI registers */
521     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
522                 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
523 
524     /* Initialize MMIO region */
525     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
526                           "psihb", PNV_PSIHB_SIZE);
527 
528     /* Default sources in XIVR */
529     for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
530         uint8_t xivr = irq_to_xivr[i];
531         psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
532             ((uint64_t) i << PSIHB_XIVR_SRC_SH);
533     }
534 
535     pnv_psi_realize(dev, errp);
536 }
537 
538 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
539 {
540     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
541     char *name;
542     int offset;
543     uint32_t reg[] = {
544         cpu_to_be32(ppc->xscom_pcba),
545         cpu_to_be32(ppc->xscom_size)
546     };
547 
548     name = g_strdup_printf("psihb@%x", ppc->xscom_pcba);
549     offset = fdt_add_subnode(fdt, xscom_offset, name);
550     _FDT(offset);
551     g_free(name);
552 
553     _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
554     _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
555     _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
556     _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat,
557                      ppc->compat_size));
558     return 0;
559 }
560 
561 static Property pnv_psi_properties[] = {
562     DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
563     DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
564     DEFINE_PROP_END_OF_LIST(),
565 };
566 
567 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
568 {
569     DeviceClass *dc = DEVICE_CLASS(klass);
570     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
571     static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
572 
573     dc->desc    = "PowerNV PSI Controller POWER8";
574     dc->realize = pnv_psi_power8_realize;
575 
576     ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
577     ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
578     ppc->bar_mask   = PSIHB_BAR_MASK;
579     ppc->irq_set    = pnv_psi_power8_irq_set;
580     ppc->compat     = compat;
581     ppc->compat_size = sizeof(compat);
582 }
583 
584 static const TypeInfo pnv_psi_power8_info = {
585     .name          = TYPE_PNV8_PSI,
586     .parent        = TYPE_PNV_PSI,
587     .instance_size = sizeof(Pnv8Psi),
588     .instance_init = pnv_psi_power8_instance_init,
589     .class_init    = pnv_psi_power8_class_init,
590 };
591 
592 
593 /* Common registers */
594 
595 #define PSIHB9_CR                       0x20
596 #define PSIHB9_SEMR                     0x28
597 
598 /* P9 registers */
599 
600 #define PSIHB9_INTERRUPT_CONTROL        0x58
601 #define   PSIHB9_IRQ_METHOD             PPC_BIT(0)
602 #define   PSIHB9_IRQ_RESET              PPC_BIT(1)
603 #define PSIHB9_ESB_CI_BASE              0x60
604 #define   PSIHB9_ESB_CI_64K             PPC_BIT(1)
605 #define   PSIHB9_ESB_CI_ADDR_MASK       PPC_BITMASK(8, 47)
606 #define   PSIHB9_ESB_CI_VALID           PPC_BIT(63)
607 #define PSIHB9_ESB_NOTIF_ADDR           0x68
608 #define   PSIHB9_ESB_NOTIF_ADDR_MASK    PPC_BITMASK(8, 60)
609 #define   PSIHB9_ESB_NOTIF_VALID        PPC_BIT(63)
610 #define PSIHB9_IVT_OFFSET               0x70
611 #define   PSIHB9_IVT_OFF_SHIFT          32
612 
613 #define PSIHB9_IRQ_LEVEL                0x78 /* assertion */
614 #define   PSIHB9_IRQ_LEVEL_PSI          PPC_BIT(0)
615 #define   PSIHB9_IRQ_LEVEL_OCC          PPC_BIT(1)
616 #define   PSIHB9_IRQ_LEVEL_FSI          PPC_BIT(2)
617 #define   PSIHB9_IRQ_LEVEL_LPCHC        PPC_BIT(3)
618 #define   PSIHB9_IRQ_LEVEL_LOCAL_ERR    PPC_BIT(4)
619 #define   PSIHB9_IRQ_LEVEL_GLOBAL_ERR   PPC_BIT(5)
620 #define   PSIHB9_IRQ_LEVEL_TPM          PPC_BIT(6)
621 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ1    PPC_BIT(7)
622 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ2    PPC_BIT(8)
623 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ3    PPC_BIT(9)
624 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ4    PPC_BIT(10)
625 #define   PSIHB9_IRQ_LEVEL_SBE_I2C      PPC_BIT(11)
626 #define   PSIHB9_IRQ_LEVEL_DIO          PPC_BIT(12)
627 #define   PSIHB9_IRQ_LEVEL_PSU          PPC_BIT(13)
628 #define   PSIHB9_IRQ_LEVEL_I2C_C        PPC_BIT(14)
629 #define   PSIHB9_IRQ_LEVEL_I2C_D        PPC_BIT(15)
630 #define   PSIHB9_IRQ_LEVEL_I2C_E        PPC_BIT(16)
631 #define   PSIHB9_IRQ_LEVEL_SBE          PPC_BIT(19)
632 
633 #define PSIHB9_IRQ_STAT                 0x80 /* P bit */
634 #define   PSIHB9_IRQ_STAT_PSI           PPC_BIT(0)
635 #define   PSIHB9_IRQ_STAT_OCC           PPC_BIT(1)
636 #define   PSIHB9_IRQ_STAT_FSI           PPC_BIT(2)
637 #define   PSIHB9_IRQ_STAT_LPCHC         PPC_BIT(3)
638 #define   PSIHB9_IRQ_STAT_LOCAL_ERR     PPC_BIT(4)
639 #define   PSIHB9_IRQ_STAT_GLOBAL_ERR    PPC_BIT(5)
640 #define   PSIHB9_IRQ_STAT_TPM           PPC_BIT(6)
641 #define   PSIHB9_IRQ_STAT_LPC_SIRQ1     PPC_BIT(7)
642 #define   PSIHB9_IRQ_STAT_LPC_SIRQ2     PPC_BIT(8)
643 #define   PSIHB9_IRQ_STAT_LPC_SIRQ3     PPC_BIT(9)
644 #define   PSIHB9_IRQ_STAT_LPC_SIRQ4     PPC_BIT(10)
645 #define   PSIHB9_IRQ_STAT_SBE_I2C       PPC_BIT(11)
646 #define   PSIHB9_IRQ_STAT_DIO           PPC_BIT(12)
647 #define   PSIHB9_IRQ_STAT_PSU           PPC_BIT(13)
648 
649 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
650 {
651     PnvPsi *psi = PNV_PSI(xf);
652     uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
653     bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID;
654     uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID;
655 
656     uint32_t offset =
657         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
658     uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
659     MemTxResult result;
660 
661     if (!valid) {
662         return;
663     }
664 
665     address_space_stq_be(&address_space_memory, notify_addr, data,
666                          MEMTXATTRS_UNSPECIFIED, &result);
667     if (result != MEMTX_OK) {
668         qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%"
669                       HWADDR_PRIx "\n", __func__, notif_port);
670         return;
671     }
672 }
673 
674 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size)
675 {
676     PnvPsi *psi = PNV_PSI(opaque);
677     uint32_t reg = PSIHB_REG(addr);
678     uint64_t val = -1;
679 
680     switch (addr) {
681     case PSIHB9_CR:
682     case PSIHB9_SEMR:
683         /* FSP stuff */
684     case PSIHB9_INTERRUPT_CONTROL:
685     case PSIHB9_ESB_CI_BASE:
686     case PSIHB9_ESB_NOTIF_ADDR:
687     case PSIHB9_IVT_OFFSET:
688         val = psi->regs[reg];
689         break;
690     default:
691         qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr);
692     }
693 
694     return val;
695 }
696 
697 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
698                                   uint64_t val, unsigned size)
699 {
700     PnvPsi *psi = PNV_PSI(opaque);
701     Pnv9Psi *psi9 = PNV9_PSI(psi);
702     uint32_t reg = PSIHB_REG(addr);
703     MemoryRegion *sysmem = get_system_memory();
704 
705     switch (addr) {
706     case PSIHB9_CR:
707     case PSIHB9_SEMR:
708         /* FSP stuff */
709         break;
710     case PSIHB9_INTERRUPT_CONTROL:
711         if (val & PSIHB9_IRQ_RESET) {
712             device_cold_reset(DEVICE(&psi9->source));
713         }
714         psi->regs[reg] = val;
715         break;
716 
717     case PSIHB9_ESB_CI_BASE:
718         if (!(val & PSIHB9_ESB_CI_VALID)) {
719             if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
720                 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
721             }
722         } else {
723             if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
724                 memory_region_add_subregion(sysmem,
725                                         val & ~PSIHB9_ESB_CI_VALID,
726                                         &psi9->source.esb_mmio);
727             }
728         }
729         psi->regs[reg] = val;
730         break;
731 
732     case PSIHB9_ESB_NOTIF_ADDR:
733         psi->regs[reg] = val;
734         break;
735     case PSIHB9_IVT_OFFSET:
736         psi->regs[reg] = val;
737         break;
738     default:
739         qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr);
740     }
741 }
742 
743 static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
744     .read = pnv_psi_p9_mmio_read,
745     .write = pnv_psi_p9_mmio_write,
746     .endianness = DEVICE_BIG_ENDIAN,
747     .valid = {
748         .min_access_size = 8,
749         .max_access_size = 8,
750     },
751     .impl = {
752         .min_access_size = 8,
753         .max_access_size = 8,
754     },
755 };
756 
757 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
758 {
759     /* No read are expected */
760     qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr);
761     return -1;
762 }
763 
764 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
765                                 uint64_t val, unsigned size)
766 {
767     PnvPsi *psi = PNV_PSI(opaque);
768 
769     /* XSCOM is only used to set the PSIHB MMIO region */
770     switch (addr >> 3) {
771     case PSIHB_XSCOM_BAR:
772         pnv_psi_set_bar(psi, val);
773         break;
774     default:
775         qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n",
776                       addr);
777     }
778 }
779 
780 static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
781     .read = pnv_psi_p9_xscom_read,
782     .write = pnv_psi_p9_xscom_write,
783     .endianness = DEVICE_BIG_ENDIAN,
784     .valid = {
785         .min_access_size = 8,
786         .max_access_size = 8,
787     },
788     .impl = {
789         .min_access_size = 8,
790         .max_access_size = 8,
791     }
792 };
793 
794 static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
795 {
796     uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
797 
798     if (irq > PSIHB9_NUM_IRQS) {
799         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
800         return;
801     }
802 
803     if (irq_method & PSIHB9_IRQ_METHOD) {
804         qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
805         return;
806     }
807 
808     /* Update LSI levels */
809     if (state) {
810         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
811     } else {
812         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
813     }
814 
815     qemu_set_irq(psi->qirqs[irq], state);
816 }
817 
818 static void pnv_psi_power9_reset(DeviceState *dev)
819 {
820     Pnv9Psi *psi = PNV9_PSI(dev);
821 
822     pnv_psi_reset(dev);
823 
824     if (memory_region_is_mapped(&psi->source.esb_mmio)) {
825         memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
826     }
827 }
828 
829 static void pnv_psi_power9_instance_init(Object *obj)
830 {
831     Pnv9Psi *psi = PNV9_PSI(obj);
832 
833     object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE);
834 }
835 
836 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
837 {
838     PnvPsi *psi = PNV_PSI(dev);
839     XiveSource *xsrc = &PNV9_PSI(psi)->source;
840     int i;
841 
842     /* This is the only device with 4k ESB pages */
843     object_property_set_int(OBJECT(xsrc), "shift", XIVE_ESB_4K, &error_fatal);
844     object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS,
845                             &error_fatal);
846     object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort);
847     if (!qdev_realize(DEVICE(xsrc), NULL, errp)) {
848         return;
849     }
850 
851     for (i = 0; i < xsrc->nr_irqs; i++) {
852         xive_source_irq_set_lsi(xsrc, i);
853     }
854 
855     psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
856 
857     /* XSCOM region for PSI registers */
858     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
859                 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
860 
861     /* MMIO region for PSI registers */
862     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi,
863                           "psihb", PNV9_PSIHB_SIZE);
864 
865     pnv_psi_realize(dev, errp);
866 }
867 
868 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
869 {
870     DeviceClass *dc = DEVICE_CLASS(klass);
871     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
872     XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
873     static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x";
874 
875     dc->desc    = "PowerNV PSI Controller POWER9";
876     dc->realize = pnv_psi_power9_realize;
877     dc->reset   = pnv_psi_power9_reset;
878 
879     ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
880     ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
881     ppc->bar_mask   = PSIHB9_BAR_MASK;
882     ppc->irq_set    = pnv_psi_power9_irq_set;
883     ppc->compat     = compat;
884     ppc->compat_size = sizeof(compat);
885 
886     xfc->notify      = pnv_psi_notify;
887 }
888 
889 static const TypeInfo pnv_psi_power9_info = {
890     .name          = TYPE_PNV9_PSI,
891     .parent        = TYPE_PNV_PSI,
892     .instance_size = sizeof(Pnv9Psi),
893     .instance_init = pnv_psi_power9_instance_init,
894     .class_init    = pnv_psi_power9_class_init,
895     .interfaces = (InterfaceInfo[]) {
896             { TYPE_XIVE_NOTIFIER },
897             { },
898     },
899 };
900 
901 static void pnv_psi_power10_class_init(ObjectClass *klass, void *data)
902 {
903     DeviceClass *dc = DEVICE_CLASS(klass);
904     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
905     static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x";
906 
907     dc->desc    = "PowerNV PSI Controller POWER10";
908 
909     ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE;
910     ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE;
911     ppc->compat     = compat;
912     ppc->compat_size = sizeof(compat);
913 }
914 
915 static const TypeInfo pnv_psi_power10_info = {
916     .name          = TYPE_PNV10_PSI,
917     .parent        = TYPE_PNV9_PSI,
918     .class_init    = pnv_psi_power10_class_init,
919 };
920 
921 static void pnv_psi_class_init(ObjectClass *klass, void *data)
922 {
923     DeviceClass *dc = DEVICE_CLASS(klass);
924     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
925 
926     xdc->dt_xscom = pnv_psi_dt_xscom;
927 
928     dc->desc = "PowerNV PSI Controller";
929     device_class_set_props(dc, pnv_psi_properties);
930     dc->reset = pnv_psi_reset;
931     dc->user_creatable = false;
932 }
933 
934 static const TypeInfo pnv_psi_info = {
935     .name          = TYPE_PNV_PSI,
936     .parent        = TYPE_DEVICE,
937     .instance_size = sizeof(PnvPsi),
938     .class_init    = pnv_psi_class_init,
939     .class_size    = sizeof(PnvPsiClass),
940     .abstract      = true,
941     .interfaces    = (InterfaceInfo[]) {
942         { TYPE_PNV_XSCOM_INTERFACE },
943         { }
944     }
945 };
946 
947 static void pnv_psi_register_types(void)
948 {
949     type_register_static(&pnv_psi_info);
950     type_register_static(&pnv_psi_power8_info);
951     type_register_static(&pnv_psi_power9_info);
952     type_register_static(&pnv_psi_power10_info);
953 }
954 
955 type_init(pnv_psi_register_types);
956 
957 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon)
958 {
959     PnvPsi *psi = PNV_PSI(psi9);
960 
961     uint32_t offset =
962         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
963 
964     monitor_printf(mon, "PSIHB Source %08x .. %08x\n",
965                   offset, offset + psi9->source.nr_irqs - 1);
966     xive_source_pic_print_info(&psi9->source, offset, mon);
967 }
968