1 /* 2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/address-spaces.h" 22 #include "hw/irq.h" 23 #include "target/ppc/cpu.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "sysemu/reset.h" 27 #include "qapi/error.h" 28 #include "monitor/monitor.h" 29 30 31 #include "hw/ppc/fdt.h" 32 #include "hw/ppc/pnv.h" 33 #include "hw/ppc/pnv_xscom.h" 34 #include "hw/qdev-properties.h" 35 #include "hw/ppc/pnv_psi.h" 36 37 #include <libfdt.h> 38 39 #define PSIHB_XSCOM_FIR_RW 0x00 40 #define PSIHB_XSCOM_FIR_AND 0x01 41 #define PSIHB_XSCOM_FIR_OR 0x02 42 #define PSIHB_XSCOM_FIRMASK_RW 0x03 43 #define PSIHB_XSCOM_FIRMASK_AND 0x04 44 #define PSIHB_XSCOM_FIRMASK_OR 0x05 45 #define PSIHB_XSCOM_FIRACT0 0x06 46 #define PSIHB_XSCOM_FIRACT1 0x07 47 48 /* Host Bridge Base Address Register */ 49 #define PSIHB_XSCOM_BAR 0x0a 50 #define PSIHB_BAR_EN 0x0000000000000001ull 51 52 /* FSP Base Address Register */ 53 #define PSIHB_XSCOM_FSPBAR 0x0b 54 55 /* PSI Host Bridge Control/Status Register */ 56 #define PSIHB_XSCOM_CR 0x0e 57 #define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull 58 #define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull 59 #define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull 60 #define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull 61 #define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull 62 #define PSIHB_CR_FSP_RESET 0x0200000000000000ull 63 #define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull 64 #define PSIHB_CR_PSI_IRQ 0x0000800000000000ull 65 #define PSIHB_CR_FSP_IRQ 0x0000400000000000ull 66 #define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull 67 #define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull 68 /* and more ... */ 69 70 /* PSIHB Status / Error Mask Register */ 71 #define PSIHB_XSCOM_SEMR 0x0f 72 73 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */ 74 #define PSIHB_XSCOM_XIVR_FSP 0x10 75 #define PSIHB_XIVR_SERVER_SH 40 76 #define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH) 77 #define PSIHB_XIVR_PRIO_SH 32 78 #define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH) 79 #define PSIHB_XIVR_SRC_SH 29 80 #define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH) 81 #define PSIHB_XIVR_PENDING 0x01000000ull 82 83 /* PSI Host Bridge Set Control/ Status Register */ 84 #define PSIHB_XSCOM_SCR 0x12 85 86 /* PSI Host Bridge Clear Control/ Status Register */ 87 #define PSIHB_XSCOM_CCR 0x13 88 89 /* DMA Upper Address Register */ 90 #define PSIHB_XSCOM_DMA_UPADD 0x14 91 92 /* Interrupt Status */ 93 #define PSIHB_XSCOM_IRQ_STAT 0x15 94 #define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull 95 #define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull 96 #define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull 97 #define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull 98 #define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull 99 100 /* remaining XIVR */ 101 #define PSIHB_XSCOM_XIVR_OCC 0x16 102 #define PSIHB_XSCOM_XIVR_FSI 0x17 103 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18 104 #define PSIHB_XSCOM_XIVR_LOCERR 0x19 105 #define PSIHB_XSCOM_XIVR_EXT 0x1a 106 107 /* Interrupt Requester Source Compare Register */ 108 #define PSIHB_XSCOM_IRSN 0x1b 109 #define PSIHB_IRSN_COMP_SH 45 110 #define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH) 111 #define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull 112 #define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull 113 #define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull 114 #define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull 115 #define PSIHB_IRSN_COMPMASK_SH 13 116 #define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH) 117 118 #define PSIHB_BAR_MASK 0x0003fffffff00000ull 119 #define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull 120 121 #define PSIHB9_BAR_MASK 0x00fffffffff00000ull 122 #define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull 123 124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) 125 126 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) 127 { 128 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi); 129 MemoryRegion *sysmem = get_system_memory(); 130 uint64_t old = psi->regs[PSIHB_XSCOM_BAR]; 131 132 psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN); 133 134 /* Update MR, always remove it first */ 135 if (old & PSIHB_BAR_EN) { 136 memory_region_del_subregion(sysmem, &psi->regs_mr); 137 } 138 139 /* Then add it back if needed */ 140 if (bar & PSIHB_BAR_EN) { 141 uint64_t addr = bar & ppc->bar_mask; 142 memory_region_add_subregion(sysmem, addr, &psi->regs_mr); 143 } 144 } 145 146 static void pnv_psi_update_fsp_mr(PnvPsi *psi) 147 { 148 /* TODO: Update FSP MR if/when we support FSP BAR */ 149 } 150 151 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr) 152 { 153 uint64_t old = psi->regs[PSIHB_XSCOM_CR]; 154 155 psi->regs[PSIHB_XSCOM_CR] = cr; 156 157 /* Check some bit changes */ 158 if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) { 159 pnv_psi_update_fsp_mr(psi); 160 } 161 } 162 163 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val) 164 { 165 ICSState *ics = &PNV8_PSI(psi)->ics; 166 167 /* In this model we ignore the up/down enable bits for now 168 * as SW doesn't use them (other than setting them at boot). 169 * We ignore IRQ_MUX, its meaning isn't clear and we don't use 170 * it and finally we ignore reset (XXX fix that ?) 171 */ 172 psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK | 173 PSIHB_IRSN_IRQ_MUX | 174 PSIHB_IRSN_IRQ_RESET | 175 PSIHB_IRSN_DOWNSTREAM_EN | 176 PSIHB_IRSN_UPSTREAM_EN); 177 178 /* We ignore the compare mask as well, our ICS emulation is too 179 * simplistic to make any use if it, and we extract the offset 180 * from the compare value 181 */ 182 ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH; 183 } 184 185 /* 186 * FSP and PSI interrupts are muxed under the same number. 187 */ 188 static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = { 189 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP, 190 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC, 191 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI, 192 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C, 193 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR, 194 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT, 195 }; 196 197 static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = { 198 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR, 199 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT, 200 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT, 201 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT, 202 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT, 203 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT, 204 }; 205 206 static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = { 207 [PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ, 208 [PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC, 209 [PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI, 210 [PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C, 211 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR, 212 [PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT, 213 }; 214 215 static void pnv_psi_power8_set_irq(void *opaque, int irq, int state) 216 { 217 PnvPsi *psi = opaque; 218 uint32_t xivr_reg; 219 uint32_t stat_reg; 220 uint32_t src; 221 bool masked; 222 223 xivr_reg = xivr_regs[irq]; 224 stat_reg = stat_regs[irq]; 225 226 src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 227 if (state) { 228 psi->regs[stat_reg] |= stat_bits[irq]; 229 /* TODO: optimization, check mask here. That means 230 * re-evaluating when unmasking 231 */ 232 qemu_irq_raise(psi->qirqs[src]); 233 } else { 234 psi->regs[stat_reg] &= ~stat_bits[irq]; 235 236 /* FSP and PSI are muxed so don't lower if either is still set */ 237 if (stat_reg != PSIHB_XSCOM_CR || 238 !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) { 239 qemu_irq_lower(psi->qirqs[src]); 240 } else { 241 state = true; 242 } 243 } 244 245 /* Note about the emulation of the pending bit: This isn't 246 * entirely correct. The pending bit should be cleared when the 247 * EOI has been received. However, we don't have callbacks on EOI 248 * (especially not under KVM) so no way to emulate that properly, 249 * so instead we just set that bit as the logical "output" of the 250 * XIVR (ie pending & !masked) 251 * 252 * CLG: We could define a new ICS object with a custom eoi() 253 * handler to clear the pending bit. But I am not sure this would 254 * be useful for the software anyhow. 255 */ 256 masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK; 257 if (state && !masked) { 258 psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING; 259 } else { 260 psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING; 261 } 262 } 263 264 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val) 265 { 266 ICSState *ics = &PNV8_PSI(psi)->ics; 267 uint16_t server; 268 uint8_t prio; 269 uint8_t src; 270 271 psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) | 272 (val & (PSIHB_XIVR_SERVER_MSK | 273 PSIHB_XIVR_PRIO_MSK | 274 PSIHB_XIVR_SRC_MSK)); 275 val = psi->regs[reg]; 276 server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH; 277 prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH; 278 src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 279 280 if (src >= PSI_NUM_INTERRUPTS) { 281 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src); 282 return; 283 } 284 285 /* Remove pending bit if the IRQ is masked */ 286 if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) { 287 psi->regs[reg] &= ~PSIHB_XIVR_PENDING; 288 } 289 290 /* The low order 2 bits are the link pointer (Type II interrupts). 291 * Shift back to get a valid IRQ server. 292 */ 293 server >>= 2; 294 295 /* Now because of source remapping, weird things can happen 296 * if you change the source number dynamically, our simple ICS 297 * doesn't deal with remapping. So we just poke a different 298 * ICS entry based on what source number was written. This will 299 * do for now but a more accurate implementation would instead 300 * use a fixed server/prio and a remapper of the generated irq. 301 */ 302 ics_write_xive(ics, src, server, prio, prio); 303 } 304 305 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio) 306 { 307 uint64_t val = 0xffffffffffffffffull; 308 309 switch (offset) { 310 case PSIHB_XSCOM_FIR_RW: 311 case PSIHB_XSCOM_FIRACT0: 312 case PSIHB_XSCOM_FIRACT1: 313 case PSIHB_XSCOM_BAR: 314 case PSIHB_XSCOM_FSPBAR: 315 case PSIHB_XSCOM_CR: 316 case PSIHB_XSCOM_XIVR_FSP: 317 case PSIHB_XSCOM_XIVR_OCC: 318 case PSIHB_XSCOM_XIVR_FSI: 319 case PSIHB_XSCOM_XIVR_LPCI2C: 320 case PSIHB_XSCOM_XIVR_LOCERR: 321 case PSIHB_XSCOM_XIVR_EXT: 322 case PSIHB_XSCOM_IRQ_STAT: 323 case PSIHB_XSCOM_SEMR: 324 case PSIHB_XSCOM_DMA_UPADD: 325 case PSIHB_XSCOM_IRSN: 326 val = psi->regs[offset]; 327 break; 328 default: 329 qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset); 330 } 331 return val; 332 } 333 334 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val, 335 bool mmio) 336 { 337 switch (offset) { 338 case PSIHB_XSCOM_FIR_RW: 339 case PSIHB_XSCOM_FIRACT0: 340 case PSIHB_XSCOM_FIRACT1: 341 case PSIHB_XSCOM_SEMR: 342 case PSIHB_XSCOM_DMA_UPADD: 343 psi->regs[offset] = val; 344 break; 345 case PSIHB_XSCOM_FIR_OR: 346 psi->regs[PSIHB_XSCOM_FIR_RW] |= val; 347 break; 348 case PSIHB_XSCOM_FIR_AND: 349 psi->regs[PSIHB_XSCOM_FIR_RW] &= val; 350 break; 351 case PSIHB_XSCOM_BAR: 352 /* Only XSCOM can write this one */ 353 if (!mmio) { 354 pnv_psi_set_bar(psi, val); 355 } else { 356 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n"); 357 } 358 break; 359 case PSIHB_XSCOM_FSPBAR: 360 psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK; 361 pnv_psi_update_fsp_mr(psi); 362 break; 363 case PSIHB_XSCOM_CR: 364 pnv_psi_set_cr(psi, val); 365 break; 366 case PSIHB_XSCOM_SCR: 367 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val); 368 break; 369 case PSIHB_XSCOM_CCR: 370 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val); 371 break; 372 case PSIHB_XSCOM_XIVR_FSP: 373 case PSIHB_XSCOM_XIVR_OCC: 374 case PSIHB_XSCOM_XIVR_FSI: 375 case PSIHB_XSCOM_XIVR_LPCI2C: 376 case PSIHB_XSCOM_XIVR_LOCERR: 377 case PSIHB_XSCOM_XIVR_EXT: 378 pnv_psi_set_xivr(psi, offset, val); 379 break; 380 case PSIHB_XSCOM_IRQ_STAT: 381 /* Read only */ 382 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n"); 383 break; 384 case PSIHB_XSCOM_IRSN: 385 pnv_psi_set_irsn(psi, val); 386 break; 387 default: 388 qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset); 389 } 390 } 391 392 /* 393 * The values of the registers when accessed through the MMIO region 394 * follow the relation : xscom = (mmio + 0x50) >> 3 395 */ 396 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size) 397 { 398 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); 399 } 400 401 static void pnv_psi_mmio_write(void *opaque, hwaddr addr, 402 uint64_t val, unsigned size) 403 { 404 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); 405 } 406 407 static const MemoryRegionOps psi_mmio_ops = { 408 .read = pnv_psi_mmio_read, 409 .write = pnv_psi_mmio_write, 410 .endianness = DEVICE_BIG_ENDIAN, 411 .valid = { 412 .min_access_size = 8, 413 .max_access_size = 8, 414 }, 415 .impl = { 416 .min_access_size = 8, 417 .max_access_size = 8, 418 }, 419 }; 420 421 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size) 422 { 423 return pnv_psi_reg_read(opaque, addr >> 3, false); 424 } 425 426 static void pnv_psi_xscom_write(void *opaque, hwaddr addr, 427 uint64_t val, unsigned size) 428 { 429 pnv_psi_reg_write(opaque, addr >> 3, val, false); 430 } 431 432 static const MemoryRegionOps pnv_psi_xscom_ops = { 433 .read = pnv_psi_xscom_read, 434 .write = pnv_psi_xscom_write, 435 .endianness = DEVICE_BIG_ENDIAN, 436 .valid = { 437 .min_access_size = 8, 438 .max_access_size = 8, 439 }, 440 .impl = { 441 .min_access_size = 8, 442 .max_access_size = 8, 443 } 444 }; 445 446 static void pnv_psi_reset(DeviceState *dev) 447 { 448 PnvPsi *psi = PNV_PSI(dev); 449 450 memset(psi->regs, 0x0, sizeof(psi->regs)); 451 452 psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN; 453 } 454 455 static void pnv_psi_reset_handler(void *dev) 456 { 457 device_cold_reset(DEVICE(dev)); 458 } 459 460 static void pnv_psi_realize(DeviceState *dev, Error **errp) 461 { 462 PnvPsi *psi = PNV_PSI(dev); 463 464 /* Default BAR for MMIO region */ 465 pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); 466 467 qemu_register_reset(pnv_psi_reset_handler, dev); 468 } 469 470 static void pnv_psi_power8_instance_init(Object *obj) 471 { 472 Pnv8Psi *psi8 = PNV8_PSI(obj); 473 474 object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS); 475 object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics), 476 ICS_PROP_XICS); 477 } 478 479 static const uint8_t irq_to_xivr[] = { 480 PSIHB_XSCOM_XIVR_FSP, 481 PSIHB_XSCOM_XIVR_OCC, 482 PSIHB_XSCOM_XIVR_FSI, 483 PSIHB_XSCOM_XIVR_LPCI2C, 484 PSIHB_XSCOM_XIVR_LOCERR, 485 PSIHB_XSCOM_XIVR_EXT, 486 }; 487 488 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) 489 { 490 PnvPsi *psi = PNV_PSI(dev); 491 ICSState *ics = &PNV8_PSI(psi)->ics; 492 unsigned int i; 493 494 /* Create PSI interrupt control source */ 495 if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS, 496 errp)) { 497 return; 498 } 499 if (!qdev_realize(DEVICE(ics), NULL, errp)) { 500 return; 501 } 502 503 for (i = 0; i < ics->nr_irqs; i++) { 504 ics_set_irq_type(ics, i, true); 505 } 506 507 qdev_init_gpio_in(dev, pnv_psi_power8_set_irq, ics->nr_irqs); 508 509 psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); 510 511 /* XSCOM region for PSI registers */ 512 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops, 513 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE); 514 515 /* Initialize MMIO region */ 516 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, 517 "psihb", PNV_PSIHB_SIZE); 518 519 /* Default sources in XIVR */ 520 for (i = 0; i < PSI_NUM_INTERRUPTS; i++) { 521 uint8_t xivr = irq_to_xivr[i]; 522 psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK | 523 ((uint64_t) i << PSIHB_XIVR_SRC_SH); 524 } 525 526 pnv_psi_realize(dev, errp); 527 } 528 529 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) 530 { 531 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev); 532 char *name; 533 int offset; 534 uint32_t reg[] = { 535 cpu_to_be32(ppc->xscom_pcba), 536 cpu_to_be32(ppc->xscom_size) 537 }; 538 539 name = g_strdup_printf("psihb@%x", ppc->xscom_pcba); 540 offset = fdt_add_subnode(fdt, xscom_offset, name); 541 _FDT(offset); 542 g_free(name); 543 544 _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); 545 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); 546 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); 547 _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat, 548 ppc->compat_size)); 549 return 0; 550 } 551 552 static Property pnv_psi_properties[] = { 553 DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0), 554 DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0), 555 DEFINE_PROP_END_OF_LIST(), 556 }; 557 558 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) 559 { 560 DeviceClass *dc = DEVICE_CLASS(klass); 561 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 562 static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x"; 563 564 dc->desc = "PowerNV PSI Controller POWER8"; 565 dc->realize = pnv_psi_power8_realize; 566 567 ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE; 568 ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE; 569 ppc->bar_mask = PSIHB_BAR_MASK; 570 ppc->compat = compat; 571 ppc->compat_size = sizeof(compat); 572 } 573 574 static const TypeInfo pnv_psi_power8_info = { 575 .name = TYPE_PNV8_PSI, 576 .parent = TYPE_PNV_PSI, 577 .instance_size = sizeof(Pnv8Psi), 578 .instance_init = pnv_psi_power8_instance_init, 579 .class_init = pnv_psi_power8_class_init, 580 }; 581 582 583 /* Common registers */ 584 585 #define PSIHB9_CR 0x20 586 #define PSIHB9_SEMR 0x28 587 588 /* P9 registers */ 589 590 #define PSIHB9_INTERRUPT_CONTROL 0x58 591 #define PSIHB9_IRQ_METHOD PPC_BIT(0) 592 #define PSIHB9_IRQ_RESET PPC_BIT(1) 593 #define PSIHB9_ESB_CI_BASE 0x60 594 #define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47) 595 #define PSIHB9_ESB_CI_VALID PPC_BIT(63) 596 #define PSIHB9_ESB_NOTIF_ADDR 0x68 597 #define PSIHB9_ESB_NOTIF_ADDR_MASK PPC_BITMASK(8, 60) 598 #define PSIHB9_ESB_NOTIF_VALID PPC_BIT(63) 599 #define PSIHB9_IVT_OFFSET 0x70 600 #define PSIHB9_IVT_OFF_SHIFT 32 601 602 #define PSIHB9_IRQ_LEVEL 0x78 /* assertion */ 603 #define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0) 604 #define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1) 605 #define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2) 606 #define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3) 607 #define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4) 608 #define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5) 609 #define PSIHB9_IRQ_LEVEL_TPM PPC_BIT(6) 610 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ1 PPC_BIT(7) 611 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ2 PPC_BIT(8) 612 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ3 PPC_BIT(9) 613 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ4 PPC_BIT(10) 614 #define PSIHB9_IRQ_LEVEL_SBE_I2C PPC_BIT(11) 615 #define PSIHB9_IRQ_LEVEL_DIO PPC_BIT(12) 616 #define PSIHB9_IRQ_LEVEL_PSU PPC_BIT(13) 617 #define PSIHB9_IRQ_LEVEL_I2C_C PPC_BIT(14) 618 #define PSIHB9_IRQ_LEVEL_I2C_D PPC_BIT(15) 619 #define PSIHB9_IRQ_LEVEL_I2C_E PPC_BIT(16) 620 #define PSIHB9_IRQ_LEVEL_SBE PPC_BIT(19) 621 622 #define PSIHB9_IRQ_STAT 0x80 /* P bit */ 623 #define PSIHB9_IRQ_STAT_PSI PPC_BIT(0) 624 #define PSIHB9_IRQ_STAT_OCC PPC_BIT(1) 625 #define PSIHB9_IRQ_STAT_FSI PPC_BIT(2) 626 #define PSIHB9_IRQ_STAT_LPCHC PPC_BIT(3) 627 #define PSIHB9_IRQ_STAT_LOCAL_ERR PPC_BIT(4) 628 #define PSIHB9_IRQ_STAT_GLOBAL_ERR PPC_BIT(5) 629 #define PSIHB9_IRQ_STAT_TPM PPC_BIT(6) 630 #define PSIHB9_IRQ_STAT_LPC_SIRQ1 PPC_BIT(7) 631 #define PSIHB9_IRQ_STAT_LPC_SIRQ2 PPC_BIT(8) 632 #define PSIHB9_IRQ_STAT_LPC_SIRQ3 PPC_BIT(9) 633 #define PSIHB9_IRQ_STAT_LPC_SIRQ4 PPC_BIT(10) 634 #define PSIHB9_IRQ_STAT_SBE_I2C PPC_BIT(11) 635 #define PSIHB9_IRQ_STAT_DIO PPC_BIT(12) 636 #define PSIHB9_IRQ_STAT_PSU PPC_BIT(13) 637 638 /* P10 register extensions */ 639 640 #define PSIHB10_CR PSIHB9_CR 641 #define PSIHB10_CR_STORE_EOI PPC_BIT(12) 642 643 #define PSIHB10_ESB_CI_BASE PSIHB9_ESB_CI_BASE 644 #define PSIHB10_ESB_CI_64K PPC_BIT(1) 645 646 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno, bool pq_checked) 647 { 648 PnvPsi *psi = PNV_PSI(xf); 649 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; 650 bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID; 651 uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID; 652 653 uint32_t offset = 654 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); 655 uint64_t data = offset | srcno; 656 MemTxResult result; 657 658 if (pq_checked) { 659 data |= XIVE_TRIGGER_PQ; 660 } 661 662 if (!valid) { 663 return; 664 } 665 666 address_space_stq_be(&address_space_memory, notify_addr, data, 667 MEMTXATTRS_UNSPECIFIED, &result); 668 if (result != MEMTX_OK) { 669 qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%" 670 HWADDR_PRIx "\n", __func__, notif_port); 671 return; 672 } 673 } 674 675 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size) 676 { 677 PnvPsi *psi = PNV_PSI(opaque); 678 uint32_t reg = PSIHB_REG(addr); 679 uint64_t val = -1; 680 681 switch (addr) { 682 case PSIHB9_CR: 683 case PSIHB9_SEMR: 684 /* FSP stuff */ 685 case PSIHB9_INTERRUPT_CONTROL: 686 case PSIHB9_ESB_CI_BASE: 687 case PSIHB9_ESB_NOTIF_ADDR: 688 case PSIHB9_IVT_OFFSET: 689 val = psi->regs[reg]; 690 break; 691 default: 692 qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr); 693 } 694 695 return val; 696 } 697 698 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, 699 uint64_t val, unsigned size) 700 { 701 PnvPsi *psi = PNV_PSI(opaque); 702 Pnv9Psi *psi9 = PNV9_PSI(psi); 703 uint32_t reg = PSIHB_REG(addr); 704 MemoryRegion *sysmem = get_system_memory(); 705 706 switch (addr) { 707 case PSIHB9_CR: 708 if (val & PSIHB10_CR_STORE_EOI) { 709 psi9->source.esb_flags |= XIVE_SRC_STORE_EOI; 710 } else { 711 psi9->source.esb_flags &= ~XIVE_SRC_STORE_EOI; 712 } 713 break; 714 715 case PSIHB9_SEMR: 716 /* FSP stuff */ 717 break; 718 case PSIHB9_INTERRUPT_CONTROL: 719 if (val & PSIHB9_IRQ_RESET) { 720 device_cold_reset(DEVICE(&psi9->source)); 721 } 722 psi->regs[reg] = val; 723 break; 724 725 case PSIHB9_ESB_CI_BASE: 726 if (val & PSIHB10_ESB_CI_64K) { 727 psi9->source.esb_shift = XIVE_ESB_64K; 728 } else { 729 psi9->source.esb_shift = XIVE_ESB_4K; 730 } 731 if (!(val & PSIHB9_ESB_CI_VALID)) { 732 if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) { 733 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio); 734 } 735 } else { 736 if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) { 737 hwaddr addr = val & ~(PSIHB9_ESB_CI_VALID | PSIHB10_ESB_CI_64K); 738 memory_region_add_subregion(sysmem, addr, 739 &psi9->source.esb_mmio); 740 } 741 } 742 psi->regs[reg] = val; 743 break; 744 745 case PSIHB9_ESB_NOTIF_ADDR: 746 psi->regs[reg] = val; 747 break; 748 case PSIHB9_IVT_OFFSET: 749 psi->regs[reg] = val; 750 break; 751 default: 752 qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr); 753 } 754 } 755 756 static const MemoryRegionOps pnv_psi_p9_mmio_ops = { 757 .read = pnv_psi_p9_mmio_read, 758 .write = pnv_psi_p9_mmio_write, 759 .endianness = DEVICE_BIG_ENDIAN, 760 .valid = { 761 .min_access_size = 8, 762 .max_access_size = 8, 763 }, 764 .impl = { 765 .min_access_size = 8, 766 .max_access_size = 8, 767 }, 768 }; 769 770 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size) 771 { 772 /* No read are expected */ 773 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr); 774 return -1; 775 } 776 777 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr, 778 uint64_t val, unsigned size) 779 { 780 PnvPsi *psi = PNV_PSI(opaque); 781 782 /* XSCOM is only used to set the PSIHB MMIO region */ 783 switch (addr >> 3) { 784 case PSIHB_XSCOM_BAR: 785 pnv_psi_set_bar(psi, val); 786 break; 787 default: 788 qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n", 789 addr); 790 } 791 } 792 793 static const MemoryRegionOps pnv_psi_p9_xscom_ops = { 794 .read = pnv_psi_p9_xscom_read, 795 .write = pnv_psi_p9_xscom_write, 796 .endianness = DEVICE_BIG_ENDIAN, 797 .valid = { 798 .min_access_size = 8, 799 .max_access_size = 8, 800 }, 801 .impl = { 802 .min_access_size = 8, 803 .max_access_size = 8, 804 } 805 }; 806 807 static void pnv_psi_power9_set_irq(void *opaque, int irq, int state) 808 { 809 PnvPsi *psi = opaque; 810 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; 811 812 if (irq_method & PSIHB9_IRQ_METHOD) { 813 qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n"); 814 return; 815 } 816 817 /* Update LSI levels */ 818 if (state) { 819 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); 820 } else { 821 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); 822 } 823 824 qemu_set_irq(psi->qirqs[irq], state); 825 } 826 827 static void pnv_psi_power9_reset(DeviceState *dev) 828 { 829 Pnv9Psi *psi = PNV9_PSI(dev); 830 831 pnv_psi_reset(dev); 832 833 if (memory_region_is_mapped(&psi->source.esb_mmio)) { 834 memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio); 835 } 836 } 837 838 static void pnv_psi_power9_instance_init(Object *obj) 839 { 840 Pnv9Psi *psi = PNV9_PSI(obj); 841 842 object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE); 843 object_property_add_alias(obj, "shift", OBJECT(&psi->source), "shift"); 844 } 845 846 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) 847 { 848 PnvPsi *psi = PNV_PSI(dev); 849 XiveSource *xsrc = &PNV9_PSI(psi)->source; 850 int i; 851 852 object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS, 853 &error_fatal); 854 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort); 855 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { 856 return; 857 } 858 859 for (i = 0; i < xsrc->nr_irqs; i++) { 860 xive_source_irq_set_lsi(xsrc, i); 861 } 862 863 psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); 864 865 qdev_init_gpio_in(dev, pnv_psi_power9_set_irq, xsrc->nr_irqs); 866 867 /* XSCOM region for PSI registers */ 868 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops, 869 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE); 870 871 /* MMIO region for PSI registers */ 872 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi, 873 "psihb", PNV9_PSIHB_SIZE); 874 875 pnv_psi_realize(dev, errp); 876 } 877 878 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) 879 { 880 DeviceClass *dc = DEVICE_CLASS(klass); 881 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 882 XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); 883 static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x"; 884 885 dc->desc = "PowerNV PSI Controller POWER9"; 886 dc->realize = pnv_psi_power9_realize; 887 dc->reset = pnv_psi_power9_reset; 888 889 ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; 890 ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; 891 ppc->bar_mask = PSIHB9_BAR_MASK; 892 ppc->compat = compat; 893 ppc->compat_size = sizeof(compat); 894 895 xfc->notify = pnv_psi_notify; 896 } 897 898 static const TypeInfo pnv_psi_power9_info = { 899 .name = TYPE_PNV9_PSI, 900 .parent = TYPE_PNV_PSI, 901 .instance_size = sizeof(Pnv9Psi), 902 .instance_init = pnv_psi_power9_instance_init, 903 .class_init = pnv_psi_power9_class_init, 904 .interfaces = (InterfaceInfo[]) { 905 { TYPE_XIVE_NOTIFIER }, 906 { }, 907 }, 908 }; 909 910 static void pnv_psi_power10_class_init(ObjectClass *klass, void *data) 911 { 912 DeviceClass *dc = DEVICE_CLASS(klass); 913 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 914 static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x"; 915 916 dc->desc = "PowerNV PSI Controller POWER10"; 917 918 ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE; 919 ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE; 920 ppc->compat = compat; 921 ppc->compat_size = sizeof(compat); 922 } 923 924 static const TypeInfo pnv_psi_power10_info = { 925 .name = TYPE_PNV10_PSI, 926 .parent = TYPE_PNV9_PSI, 927 .class_init = pnv_psi_power10_class_init, 928 }; 929 930 static void pnv_psi_class_init(ObjectClass *klass, void *data) 931 { 932 DeviceClass *dc = DEVICE_CLASS(klass); 933 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 934 935 xdc->dt_xscom = pnv_psi_dt_xscom; 936 937 dc->desc = "PowerNV PSI Controller"; 938 device_class_set_props(dc, pnv_psi_properties); 939 dc->reset = pnv_psi_reset; 940 dc->user_creatable = false; 941 } 942 943 static const TypeInfo pnv_psi_info = { 944 .name = TYPE_PNV_PSI, 945 .parent = TYPE_DEVICE, 946 .instance_size = sizeof(PnvPsi), 947 .class_init = pnv_psi_class_init, 948 .class_size = sizeof(PnvPsiClass), 949 .abstract = true, 950 .interfaces = (InterfaceInfo[]) { 951 { TYPE_PNV_XSCOM_INTERFACE }, 952 { } 953 } 954 }; 955 956 static void pnv_psi_register_types(void) 957 { 958 type_register_static(&pnv_psi_info); 959 type_register_static(&pnv_psi_power8_info); 960 type_register_static(&pnv_psi_power9_info); 961 type_register_static(&pnv_psi_power10_info); 962 } 963 964 type_init(pnv_psi_register_types); 965 966 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon) 967 { 968 PnvPsi *psi = PNV_PSI(psi9); 969 970 uint32_t offset = 971 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); 972 973 monitor_printf(mon, "PSIHB Source %08x .. %08x\n", 974 offset, offset + psi9->source.nr_irqs - 1); 975 xive_source_pic_print_info(&psi9->source, offset, mon); 976 } 977