1 /* 2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "exec/address-spaces.h" 22 #include "hw/irq.h" 23 #include "target/ppc/cpu.h" 24 #include "qemu/log.h" 25 #include "qemu/module.h" 26 #include "sysemu/reset.h" 27 #include "qapi/error.h" 28 29 30 #include "hw/ppc/fdt.h" 31 #include "hw/ppc/pnv.h" 32 #include "hw/ppc/pnv_xscom.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/ppc/pnv_psi.h" 35 36 #include <libfdt.h> 37 38 #define PSIHB_XSCOM_FIR_RW 0x00 39 #define PSIHB_XSCOM_FIR_AND 0x01 40 #define PSIHB_XSCOM_FIR_OR 0x02 41 #define PSIHB_XSCOM_FIRMASK_RW 0x03 42 #define PSIHB_XSCOM_FIRMASK_AND 0x04 43 #define PSIHB_XSCOM_FIRMASK_OR 0x05 44 #define PSIHB_XSCOM_FIRACT0 0x06 45 #define PSIHB_XSCOM_FIRACT1 0x07 46 47 /* Host Bridge Base Address Register */ 48 #define PSIHB_XSCOM_BAR 0x0a 49 #define PSIHB_BAR_EN 0x0000000000000001ull 50 51 /* FSP Base Address Register */ 52 #define PSIHB_XSCOM_FSPBAR 0x0b 53 54 /* PSI Host Bridge Control/Status Register */ 55 #define PSIHB_XSCOM_CR 0x0e 56 #define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull 57 #define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull 58 #define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull 59 #define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull 60 #define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull 61 #define PSIHB_CR_FSP_RESET 0x0200000000000000ull 62 #define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull 63 #define PSIHB_CR_PSI_IRQ 0x0000800000000000ull 64 #define PSIHB_CR_FSP_IRQ 0x0000400000000000ull 65 #define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull 66 #define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull 67 /* and more ... */ 68 69 /* PSIHB Status / Error Mask Register */ 70 #define PSIHB_XSCOM_SEMR 0x0f 71 72 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */ 73 #define PSIHB_XSCOM_XIVR_FSP 0x10 74 #define PSIHB_XIVR_SERVER_SH 40 75 #define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH) 76 #define PSIHB_XIVR_PRIO_SH 32 77 #define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH) 78 #define PSIHB_XIVR_SRC_SH 29 79 #define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH) 80 #define PSIHB_XIVR_PENDING 0x01000000ull 81 82 /* PSI Host Bridge Set Control/ Status Register */ 83 #define PSIHB_XSCOM_SCR 0x12 84 85 /* PSI Host Bridge Clear Control/ Status Register */ 86 #define PSIHB_XSCOM_CCR 0x13 87 88 /* DMA Upper Address Register */ 89 #define PSIHB_XSCOM_DMA_UPADD 0x14 90 91 /* Interrupt Status */ 92 #define PSIHB_XSCOM_IRQ_STAT 0x15 93 #define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull 94 #define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull 95 #define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull 96 #define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull 97 #define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull 98 99 /* remaining XIVR */ 100 #define PSIHB_XSCOM_XIVR_OCC 0x16 101 #define PSIHB_XSCOM_XIVR_FSI 0x17 102 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18 103 #define PSIHB_XSCOM_XIVR_LOCERR 0x19 104 #define PSIHB_XSCOM_XIVR_EXT 0x1a 105 106 /* Interrupt Requester Source Compare Register */ 107 #define PSIHB_XSCOM_IRSN 0x1b 108 #define PSIHB_IRSN_COMP_SH 45 109 #define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH) 110 #define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull 111 #define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull 112 #define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull 113 #define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull 114 #define PSIHB_IRSN_COMPMASK_SH 13 115 #define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH) 116 117 #define PSIHB_BAR_MASK 0x0003fffffff00000ull 118 #define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull 119 120 #define PSIHB9_BAR_MASK 0x00fffffffff00000ull 121 #define PSIHB9_FSPBAR_MASK 0x00ffffff00000000ull 122 123 /* mmio address to xscom address */ 124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR) 125 126 /* xscom address to mmio address */ 127 #define PSIHB_MMIO(reg) ((reg - PSIHB_XSCOM_BAR) << 3) 128 129 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) 130 { 131 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi); 132 MemoryRegion *sysmem = get_system_memory(); 133 uint64_t old = psi->regs[PSIHB_XSCOM_BAR]; 134 135 psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN); 136 137 /* Update MR, always remove it first */ 138 if (old & PSIHB_BAR_EN) { 139 memory_region_del_subregion(sysmem, &psi->regs_mr); 140 } 141 142 /* Then add it back if needed */ 143 if (bar & PSIHB_BAR_EN) { 144 uint64_t addr = bar & ppc->bar_mask; 145 memory_region_add_subregion(sysmem, addr, &psi->regs_mr); 146 } 147 } 148 149 static void pnv_psi_update_fsp_mr(PnvPsi *psi) 150 { 151 /* TODO: Update FSP MR if/when we support FSP BAR */ 152 } 153 154 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr) 155 { 156 uint64_t old = psi->regs[PSIHB_XSCOM_CR]; 157 158 psi->regs[PSIHB_XSCOM_CR] = cr; 159 160 /* Check some bit changes */ 161 if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) { 162 pnv_psi_update_fsp_mr(psi); 163 } 164 } 165 166 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val) 167 { 168 ICSState *ics = &PNV8_PSI(psi)->ics; 169 170 /* In this model we ignore the up/down enable bits for now 171 * as SW doesn't use them (other than setting them at boot). 172 * We ignore IRQ_MUX, its meaning isn't clear and we don't use 173 * it and finally we ignore reset (XXX fix that ?) 174 */ 175 psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK | 176 PSIHB_IRSN_IRQ_MUX | 177 PSIHB_IRSN_IRQ_RESET | 178 PSIHB_IRSN_DOWNSTREAM_EN | 179 PSIHB_IRSN_UPSTREAM_EN); 180 181 /* We ignore the compare mask as well, our ICS emulation is too 182 * simplistic to make any use if it, and we extract the offset 183 * from the compare value 184 */ 185 ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH; 186 } 187 188 /* 189 * FSP and PSI interrupts are muxed under the same number. 190 */ 191 static const uint32_t xivr_regs[PSI_NUM_INTERRUPTS] = { 192 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP, 193 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC, 194 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI, 195 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C, 196 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR, 197 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT, 198 }; 199 200 static const uint32_t stat_regs[PSI_NUM_INTERRUPTS] = { 201 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR, 202 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT, 203 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT, 204 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT, 205 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT, 206 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT, 207 }; 208 209 static const uint64_t stat_bits[PSI_NUM_INTERRUPTS] = { 210 [PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ, 211 [PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC, 212 [PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI, 213 [PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C, 214 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR, 215 [PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT, 216 }; 217 218 static void pnv_psi_power8_set_irq(void *opaque, int irq, int state) 219 { 220 PnvPsi *psi = opaque; 221 uint32_t xivr_reg; 222 uint32_t stat_reg; 223 uint32_t src; 224 bool masked; 225 226 xivr_reg = xivr_regs[irq]; 227 stat_reg = stat_regs[irq]; 228 229 src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 230 if (state) { 231 psi->regs[stat_reg] |= stat_bits[irq]; 232 /* TODO: optimization, check mask here. That means 233 * re-evaluating when unmasking 234 */ 235 qemu_irq_raise(psi->qirqs[src]); 236 } else { 237 psi->regs[stat_reg] &= ~stat_bits[irq]; 238 239 /* FSP and PSI are muxed so don't lower if either is still set */ 240 if (stat_reg != PSIHB_XSCOM_CR || 241 !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) { 242 qemu_irq_lower(psi->qirqs[src]); 243 } else { 244 state = true; 245 } 246 } 247 248 /* Note about the emulation of the pending bit: This isn't 249 * entirely correct. The pending bit should be cleared when the 250 * EOI has been received. However, we don't have callbacks on EOI 251 * (especially not under KVM) so no way to emulate that properly, 252 * so instead we just set that bit as the logical "output" of the 253 * XIVR (ie pending & !masked) 254 * 255 * CLG: We could define a new ICS object with a custom eoi() 256 * handler to clear the pending bit. But I am not sure this would 257 * be useful for the software anyhow. 258 */ 259 masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK; 260 if (state && !masked) { 261 psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING; 262 } else { 263 psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING; 264 } 265 } 266 267 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val) 268 { 269 ICSState *ics = &PNV8_PSI(psi)->ics; 270 uint16_t server; 271 uint8_t prio; 272 uint8_t src; 273 274 psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) | 275 (val & (PSIHB_XIVR_SERVER_MSK | 276 PSIHB_XIVR_PRIO_MSK | 277 PSIHB_XIVR_SRC_MSK)); 278 val = psi->regs[reg]; 279 server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH; 280 prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH; 281 src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 282 283 if (src >= PSI_NUM_INTERRUPTS) { 284 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src); 285 return; 286 } 287 288 /* Remove pending bit if the IRQ is masked */ 289 if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) { 290 psi->regs[reg] &= ~PSIHB_XIVR_PENDING; 291 } 292 293 /* The low order 2 bits are the link pointer (Type II interrupts). 294 * Shift back to get a valid IRQ server. 295 */ 296 server >>= 2; 297 298 /* Now because of source remapping, weird things can happen 299 * if you change the source number dynamically, our simple ICS 300 * doesn't deal with remapping. So we just poke a different 301 * ICS entry based on what source number was written. This will 302 * do for now but a more accurate implementation would instead 303 * use a fixed server/prio and a remapper of the generated irq. 304 */ 305 ics_write_xive(ics, src, server, prio, prio); 306 } 307 308 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio) 309 { 310 uint64_t val = 0xffffffffffffffffull; 311 312 switch (offset) { 313 case PSIHB_XSCOM_FIR_RW: 314 case PSIHB_XSCOM_FIRACT0: 315 case PSIHB_XSCOM_FIRACT1: 316 case PSIHB_XSCOM_BAR: 317 case PSIHB_XSCOM_FSPBAR: 318 case PSIHB_XSCOM_CR: 319 case PSIHB_XSCOM_XIVR_FSP: 320 case PSIHB_XSCOM_XIVR_OCC: 321 case PSIHB_XSCOM_XIVR_FSI: 322 case PSIHB_XSCOM_XIVR_LPCI2C: 323 case PSIHB_XSCOM_XIVR_LOCERR: 324 case PSIHB_XSCOM_XIVR_EXT: 325 case PSIHB_XSCOM_IRQ_STAT: 326 case PSIHB_XSCOM_SEMR: 327 case PSIHB_XSCOM_DMA_UPADD: 328 case PSIHB_XSCOM_IRSN: 329 val = psi->regs[offset]; 330 break; 331 default: 332 qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset); 333 } 334 return val; 335 } 336 337 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val, 338 bool mmio) 339 { 340 switch (offset) { 341 case PSIHB_XSCOM_FIR_RW: 342 case PSIHB_XSCOM_FIRACT0: 343 case PSIHB_XSCOM_FIRACT1: 344 case PSIHB_XSCOM_SEMR: 345 case PSIHB_XSCOM_DMA_UPADD: 346 psi->regs[offset] = val; 347 break; 348 case PSIHB_XSCOM_FIR_OR: 349 psi->regs[PSIHB_XSCOM_FIR_RW] |= val; 350 break; 351 case PSIHB_XSCOM_FIR_AND: 352 psi->regs[PSIHB_XSCOM_FIR_RW] &= val; 353 break; 354 case PSIHB_XSCOM_BAR: 355 /* Only XSCOM can write this one */ 356 if (!mmio) { 357 pnv_psi_set_bar(psi, val); 358 } else { 359 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n"); 360 } 361 break; 362 case PSIHB_XSCOM_FSPBAR: 363 psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK; 364 pnv_psi_update_fsp_mr(psi); 365 break; 366 case PSIHB_XSCOM_CR: 367 pnv_psi_set_cr(psi, val); 368 break; 369 case PSIHB_XSCOM_SCR: 370 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val); 371 break; 372 case PSIHB_XSCOM_CCR: 373 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val); 374 break; 375 case PSIHB_XSCOM_XIVR_FSP: 376 case PSIHB_XSCOM_XIVR_OCC: 377 case PSIHB_XSCOM_XIVR_FSI: 378 case PSIHB_XSCOM_XIVR_LPCI2C: 379 case PSIHB_XSCOM_XIVR_LOCERR: 380 case PSIHB_XSCOM_XIVR_EXT: 381 pnv_psi_set_xivr(psi, offset, val); 382 break; 383 case PSIHB_XSCOM_IRQ_STAT: 384 /* Read only */ 385 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n"); 386 break; 387 case PSIHB_XSCOM_IRSN: 388 pnv_psi_set_irsn(psi, val); 389 break; 390 default: 391 qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset); 392 } 393 } 394 395 /* 396 * The values of the registers when accessed through the MMIO region 397 * follow the relation : xscom = (mmio + 0x50) >> 3 398 */ 399 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size) 400 { 401 return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true); 402 } 403 404 static void pnv_psi_mmio_write(void *opaque, hwaddr addr, 405 uint64_t val, unsigned size) 406 { 407 pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true); 408 } 409 410 static const MemoryRegionOps psi_mmio_ops = { 411 .read = pnv_psi_mmio_read, 412 .write = pnv_psi_mmio_write, 413 .endianness = DEVICE_BIG_ENDIAN, 414 .valid = { 415 .min_access_size = 8, 416 .max_access_size = 8, 417 }, 418 .impl = { 419 .min_access_size = 8, 420 .max_access_size = 8, 421 }, 422 }; 423 424 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size) 425 { 426 return pnv_psi_reg_read(opaque, addr >> 3, false); 427 } 428 429 static void pnv_psi_xscom_write(void *opaque, hwaddr addr, 430 uint64_t val, unsigned size) 431 { 432 pnv_psi_reg_write(opaque, addr >> 3, val, false); 433 } 434 435 static const MemoryRegionOps pnv_psi_xscom_ops = { 436 .read = pnv_psi_xscom_read, 437 .write = pnv_psi_xscom_write, 438 .endianness = DEVICE_BIG_ENDIAN, 439 .valid = { 440 .min_access_size = 8, 441 .max_access_size = 8, 442 }, 443 .impl = { 444 .min_access_size = 8, 445 .max_access_size = 8, 446 } 447 }; 448 449 static void pnv_psi_reset(DeviceState *dev) 450 { 451 PnvPsi *psi = PNV_PSI(dev); 452 453 memset(psi->regs, 0x0, sizeof(psi->regs)); 454 455 psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN; 456 } 457 458 static void pnv_psi_reset_handler(void *dev) 459 { 460 device_cold_reset(DEVICE(dev)); 461 } 462 463 static void pnv_psi_realize(DeviceState *dev, Error **errp) 464 { 465 PnvPsi *psi = PNV_PSI(dev); 466 467 /* Default BAR for MMIO region */ 468 pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); 469 470 qemu_register_reset(pnv_psi_reset_handler, dev); 471 } 472 473 static void pnv_psi_power8_instance_init(Object *obj) 474 { 475 Pnv8Psi *psi8 = PNV8_PSI(obj); 476 477 object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS); 478 object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics), 479 ICS_PROP_XICS); 480 } 481 482 static const uint8_t irq_to_xivr[] = { 483 PSIHB_XSCOM_XIVR_FSP, 484 PSIHB_XSCOM_XIVR_OCC, 485 PSIHB_XSCOM_XIVR_FSI, 486 PSIHB_XSCOM_XIVR_LPCI2C, 487 PSIHB_XSCOM_XIVR_LOCERR, 488 PSIHB_XSCOM_XIVR_EXT, 489 }; 490 491 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) 492 { 493 PnvPsi *psi = PNV_PSI(dev); 494 ICSState *ics = &PNV8_PSI(psi)->ics; 495 unsigned int i; 496 497 /* Create PSI interrupt control source */ 498 if (!object_property_set_int(OBJECT(ics), "nr-irqs", PSI_NUM_INTERRUPTS, 499 errp)) { 500 return; 501 } 502 if (!qdev_realize(DEVICE(ics), NULL, errp)) { 503 return; 504 } 505 506 for (i = 0; i < ics->nr_irqs; i++) { 507 ics_set_irq_type(ics, i, true); 508 } 509 510 qdev_init_gpio_in(dev, pnv_psi_power8_set_irq, ics->nr_irqs); 511 512 psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs); 513 514 /* XSCOM region for PSI registers */ 515 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops, 516 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE); 517 518 /* Initialize MMIO region */ 519 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, 520 "psihb", PNV_PSIHB_SIZE); 521 522 /* Default sources in XIVR */ 523 for (i = 0; i < PSI_NUM_INTERRUPTS; i++) { 524 uint8_t xivr = irq_to_xivr[i]; 525 psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK | 526 ((uint64_t) i << PSIHB_XIVR_SRC_SH); 527 } 528 529 pnv_psi_realize(dev, errp); 530 } 531 532 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) 533 { 534 PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev); 535 char *name; 536 int offset; 537 uint32_t reg[] = { 538 cpu_to_be32(ppc->xscom_pcba), 539 cpu_to_be32(ppc->xscom_size) 540 }; 541 542 name = g_strdup_printf("psihb@%x", ppc->xscom_pcba); 543 offset = fdt_add_subnode(fdt, xscom_offset, name); 544 _FDT(offset); 545 g_free(name); 546 547 _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); 548 _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); 549 _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); 550 _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat, 551 ppc->compat_size)); 552 return 0; 553 } 554 555 static Property pnv_psi_properties[] = { 556 DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0), 557 DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0), 558 DEFINE_PROP_END_OF_LIST(), 559 }; 560 561 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) 562 { 563 DeviceClass *dc = DEVICE_CLASS(klass); 564 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 565 static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x"; 566 567 dc->desc = "PowerNV PSI Controller POWER8"; 568 dc->realize = pnv_psi_power8_realize; 569 570 ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE; 571 ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE; 572 ppc->bar_mask = PSIHB_BAR_MASK; 573 ppc->compat = compat; 574 ppc->compat_size = sizeof(compat); 575 } 576 577 static const TypeInfo pnv_psi_power8_info = { 578 .name = TYPE_PNV8_PSI, 579 .parent = TYPE_PNV_PSI, 580 .instance_size = sizeof(Pnv8Psi), 581 .instance_init = pnv_psi_power8_instance_init, 582 .class_init = pnv_psi_power8_class_init, 583 }; 584 585 586 /* Common registers */ 587 588 #define PSIHB9_CR 0x20 589 #define PSIHB9_SEMR 0x28 590 591 /* P9 registers */ 592 593 #define PSIHB9_INTERRUPT_CONTROL 0x58 594 #define PSIHB9_IRQ_METHOD PPC_BIT(0) 595 #define PSIHB9_IRQ_RESET PPC_BIT(1) 596 #define PSIHB9_ESB_CI_BASE 0x60 597 #define PSIHB9_ESB_CI_ADDR_MASK PPC_BITMASK(8, 47) 598 #define PSIHB9_ESB_CI_VALID PPC_BIT(63) 599 #define PSIHB9_ESB_NOTIF_ADDR 0x68 600 #define PSIHB9_ESB_NOTIF_ADDR_MASK PPC_BITMASK(8, 60) 601 #define PSIHB9_ESB_NOTIF_VALID PPC_BIT(63) 602 #define PSIHB9_IVT_OFFSET 0x70 603 #define PSIHB9_IVT_OFF_SHIFT 32 604 605 #define PSIHB9_IRQ_LEVEL 0x78 /* assertion */ 606 #define PSIHB9_IRQ_LEVEL_PSI PPC_BIT(0) 607 #define PSIHB9_IRQ_LEVEL_OCC PPC_BIT(1) 608 #define PSIHB9_IRQ_LEVEL_FSI PPC_BIT(2) 609 #define PSIHB9_IRQ_LEVEL_LPCHC PPC_BIT(3) 610 #define PSIHB9_IRQ_LEVEL_LOCAL_ERR PPC_BIT(4) 611 #define PSIHB9_IRQ_LEVEL_GLOBAL_ERR PPC_BIT(5) 612 #define PSIHB9_IRQ_LEVEL_TPM PPC_BIT(6) 613 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ1 PPC_BIT(7) 614 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ2 PPC_BIT(8) 615 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ3 PPC_BIT(9) 616 #define PSIHB9_IRQ_LEVEL_LPC_SIRQ4 PPC_BIT(10) 617 #define PSIHB9_IRQ_LEVEL_SBE_I2C PPC_BIT(11) 618 #define PSIHB9_IRQ_LEVEL_DIO PPC_BIT(12) 619 #define PSIHB9_IRQ_LEVEL_PSU PPC_BIT(13) 620 #define PSIHB9_IRQ_LEVEL_I2C_C PPC_BIT(14) 621 #define PSIHB9_IRQ_LEVEL_I2C_D PPC_BIT(15) 622 #define PSIHB9_IRQ_LEVEL_I2C_E PPC_BIT(16) 623 #define PSIHB9_IRQ_LEVEL_SBE PPC_BIT(19) 624 625 #define PSIHB9_IRQ_STAT 0x80 /* P bit */ 626 #define PSIHB9_IRQ_STAT_PSI PPC_BIT(0) 627 #define PSIHB9_IRQ_STAT_OCC PPC_BIT(1) 628 #define PSIHB9_IRQ_STAT_FSI PPC_BIT(2) 629 #define PSIHB9_IRQ_STAT_LPCHC PPC_BIT(3) 630 #define PSIHB9_IRQ_STAT_LOCAL_ERR PPC_BIT(4) 631 #define PSIHB9_IRQ_STAT_GLOBAL_ERR PPC_BIT(5) 632 #define PSIHB9_IRQ_STAT_TPM PPC_BIT(6) 633 #define PSIHB9_IRQ_STAT_LPC_SIRQ1 PPC_BIT(7) 634 #define PSIHB9_IRQ_STAT_LPC_SIRQ2 PPC_BIT(8) 635 #define PSIHB9_IRQ_STAT_LPC_SIRQ3 PPC_BIT(9) 636 #define PSIHB9_IRQ_STAT_LPC_SIRQ4 PPC_BIT(10) 637 #define PSIHB9_IRQ_STAT_SBE_I2C PPC_BIT(11) 638 #define PSIHB9_IRQ_STAT_DIO PPC_BIT(12) 639 #define PSIHB9_IRQ_STAT_PSU PPC_BIT(13) 640 641 /* P10 register extensions */ 642 643 #define PSIHB10_CR PSIHB9_CR 644 #define PSIHB10_CR_STORE_EOI PPC_BIT(12) 645 646 #define PSIHB10_ESB_CI_BASE PSIHB9_ESB_CI_BASE 647 #define PSIHB10_ESB_CI_64K PPC_BIT(1) 648 649 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno, bool pq_checked) 650 { 651 PnvPsi *psi = PNV_PSI(xf); 652 uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)]; 653 bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID; 654 uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID; 655 656 uint32_t offset = 657 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); 658 uint64_t data = offset | srcno; 659 MemTxResult result; 660 661 if (pq_checked) { 662 data |= XIVE_TRIGGER_PQ; 663 } 664 665 if (!valid) { 666 return; 667 } 668 669 address_space_stq_be(&address_space_memory, notify_addr, data, 670 MEMTXATTRS_UNSPECIFIED, &result); 671 if (result != MEMTX_OK) { 672 qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%" 673 HWADDR_PRIx "\n", __func__, notif_port); 674 return; 675 } 676 } 677 678 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size) 679 { 680 PnvPsi *psi = PNV_PSI(opaque); 681 uint32_t reg = PSIHB_REG(addr); 682 uint64_t val = -1; 683 684 switch (addr) { 685 case PSIHB9_CR: 686 case PSIHB9_SEMR: 687 /* FSP stuff */ 688 case PSIHB9_INTERRUPT_CONTROL: 689 case PSIHB9_ESB_CI_BASE: 690 case PSIHB9_ESB_NOTIF_ADDR: 691 case PSIHB9_IVT_OFFSET: 692 val = psi->regs[reg]; 693 break; 694 default: 695 qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr); 696 } 697 698 return val; 699 } 700 701 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr, 702 uint64_t val, unsigned size) 703 { 704 PnvPsi *psi = PNV_PSI(opaque); 705 Pnv9Psi *psi9 = PNV9_PSI(psi); 706 uint32_t reg = PSIHB_REG(addr); 707 MemoryRegion *sysmem = get_system_memory(); 708 709 switch (addr) { 710 case PSIHB9_CR: 711 if (val & PSIHB10_CR_STORE_EOI) { 712 psi9->source.esb_flags |= XIVE_SRC_STORE_EOI; 713 } else { 714 psi9->source.esb_flags &= ~XIVE_SRC_STORE_EOI; 715 } 716 break; 717 718 case PSIHB9_SEMR: 719 /* FSP stuff */ 720 break; 721 case PSIHB9_INTERRUPT_CONTROL: 722 if (val & PSIHB9_IRQ_RESET) { 723 device_cold_reset(DEVICE(&psi9->source)); 724 } 725 psi->regs[reg] = val; 726 break; 727 728 case PSIHB9_ESB_CI_BASE: 729 if (val & PSIHB10_ESB_CI_64K) { 730 psi9->source.esb_shift = XIVE_ESB_64K; 731 } else { 732 psi9->source.esb_shift = XIVE_ESB_4K; 733 } 734 if (!(val & PSIHB9_ESB_CI_VALID)) { 735 if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) { 736 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio); 737 } 738 } else { 739 if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) { 740 hwaddr esb_addr = 741 val & ~(PSIHB9_ESB_CI_VALID | PSIHB10_ESB_CI_64K); 742 memory_region_add_subregion(sysmem, esb_addr, 743 &psi9->source.esb_mmio); 744 } 745 } 746 psi->regs[reg] = val; 747 break; 748 749 case PSIHB9_ESB_NOTIF_ADDR: 750 psi->regs[reg] = val; 751 break; 752 case PSIHB9_IVT_OFFSET: 753 psi->regs[reg] = val; 754 break; 755 default: 756 qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr); 757 } 758 } 759 760 static const MemoryRegionOps pnv_psi_p9_mmio_ops = { 761 .read = pnv_psi_p9_mmio_read, 762 .write = pnv_psi_p9_mmio_write, 763 .endianness = DEVICE_BIG_ENDIAN, 764 .valid = { 765 .min_access_size = 8, 766 .max_access_size = 8, 767 }, 768 .impl = { 769 .min_access_size = 8, 770 .max_access_size = 8, 771 }, 772 }; 773 774 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size) 775 { 776 uint32_t reg = addr >> 3; 777 uint64_t val = -1; 778 779 if (reg < PSIHB_XSCOM_BAR) { 780 /* FIR, not modeled */ 781 qemu_log_mask(LOG_UNIMP, "PSI: xscom read at 0x%08x\n", reg); 782 } else { 783 val = pnv_psi_p9_mmio_read(opaque, PSIHB_MMIO(reg), size); 784 } 785 return val; 786 } 787 788 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr, 789 uint64_t val, unsigned size) 790 { 791 PnvPsi *psi = PNV_PSI(opaque); 792 uint32_t reg = addr >> 3; 793 794 if (reg < PSIHB_XSCOM_BAR) { 795 /* FIR, not modeled */ 796 qemu_log_mask(LOG_UNIMP, "PSI: xscom write at 0x%08x\n", reg); 797 } else if (reg == PSIHB_XSCOM_BAR) { 798 pnv_psi_set_bar(psi, val); 799 } else { 800 pnv_psi_p9_mmio_write(opaque, PSIHB_MMIO(reg), val, size); 801 } 802 } 803 804 static const MemoryRegionOps pnv_psi_p9_xscom_ops = { 805 .read = pnv_psi_p9_xscom_read, 806 .write = pnv_psi_p9_xscom_write, 807 .endianness = DEVICE_BIG_ENDIAN, 808 .valid = { 809 .min_access_size = 8, 810 .max_access_size = 8, 811 }, 812 .impl = { 813 .min_access_size = 8, 814 .max_access_size = 8, 815 } 816 }; 817 818 static void pnv_psi_power9_set_irq(void *opaque, int irq, int state) 819 { 820 PnvPsi *psi = opaque; 821 uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)]; 822 823 if (irq_method & PSIHB9_IRQ_METHOD) { 824 qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n"); 825 return; 826 } 827 828 /* Update LSI levels */ 829 if (state) { 830 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq); 831 } else { 832 psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq); 833 } 834 835 qemu_set_irq(psi->qirqs[irq], state); 836 } 837 838 static void pnv_psi_power9_reset(DeviceState *dev) 839 { 840 Pnv9Psi *psi = PNV9_PSI(dev); 841 842 pnv_psi_reset(dev); 843 844 if (memory_region_is_mapped(&psi->source.esb_mmio)) { 845 memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio); 846 } 847 } 848 849 static void pnv_psi_power9_instance_init(Object *obj) 850 { 851 Pnv9Psi *psi = PNV9_PSI(obj); 852 853 object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE); 854 object_property_add_alias(obj, "shift", OBJECT(&psi->source), "shift"); 855 } 856 857 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) 858 { 859 PnvPsi *psi = PNV_PSI(dev); 860 XiveSource *xsrc = &PNV9_PSI(psi)->source; 861 int i; 862 863 object_property_set_int(OBJECT(xsrc), "nr-irqs", PSIHB9_NUM_IRQS, 864 &error_fatal); 865 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(psi), &error_abort); 866 object_property_set_int(OBJECT(xsrc), "reset-pq", XIVE_ESB_RESET, 867 &error_abort); 868 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { 869 return; 870 } 871 872 for (i = 0; i < xsrc->nr_irqs; i++) { 873 xive_source_irq_set_lsi(xsrc, i); 874 } 875 876 psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); 877 878 qdev_init_gpio_in(dev, pnv_psi_power9_set_irq, xsrc->nr_irqs); 879 880 /* XSCOM region for PSI registers */ 881 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops, 882 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE); 883 884 /* MMIO region for PSI registers */ 885 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi, 886 "psihb", PNV9_PSIHB_SIZE); 887 888 pnv_psi_realize(dev, errp); 889 } 890 891 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) 892 { 893 DeviceClass *dc = DEVICE_CLASS(klass); 894 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 895 XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); 896 static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x"; 897 898 dc->desc = "PowerNV PSI Controller POWER9"; 899 dc->realize = pnv_psi_power9_realize; 900 device_class_set_legacy_reset(dc, pnv_psi_power9_reset); 901 902 ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; 903 ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; 904 ppc->bar_mask = PSIHB9_BAR_MASK; 905 ppc->compat = compat; 906 ppc->compat_size = sizeof(compat); 907 908 xfc->notify = pnv_psi_notify; 909 } 910 911 static const TypeInfo pnv_psi_power9_info = { 912 .name = TYPE_PNV9_PSI, 913 .parent = TYPE_PNV_PSI, 914 .instance_size = sizeof(Pnv9Psi), 915 .instance_init = pnv_psi_power9_instance_init, 916 .class_init = pnv_psi_power9_class_init, 917 .interfaces = (InterfaceInfo[]) { 918 { TYPE_XIVE_NOTIFIER }, 919 { }, 920 }, 921 }; 922 923 static void pnv_psi_power10_class_init(ObjectClass *klass, void *data) 924 { 925 DeviceClass *dc = DEVICE_CLASS(klass); 926 PnvPsiClass *ppc = PNV_PSI_CLASS(klass); 927 static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x"; 928 929 dc->desc = "PowerNV PSI Controller POWER10"; 930 931 ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE; 932 ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE; 933 ppc->compat = compat; 934 ppc->compat_size = sizeof(compat); 935 } 936 937 static const TypeInfo pnv_psi_power10_info = { 938 .name = TYPE_PNV10_PSI, 939 .parent = TYPE_PNV9_PSI, 940 .class_init = pnv_psi_power10_class_init, 941 }; 942 943 static void pnv_psi_class_init(ObjectClass *klass, void *data) 944 { 945 DeviceClass *dc = DEVICE_CLASS(klass); 946 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 947 948 xdc->dt_xscom = pnv_psi_dt_xscom; 949 950 dc->desc = "PowerNV PSI Controller"; 951 device_class_set_props(dc, pnv_psi_properties); 952 device_class_set_legacy_reset(dc, pnv_psi_reset); 953 dc->user_creatable = false; 954 } 955 956 static const TypeInfo pnv_psi_info = { 957 .name = TYPE_PNV_PSI, 958 .parent = TYPE_DEVICE, 959 .instance_size = sizeof(PnvPsi), 960 .class_init = pnv_psi_class_init, 961 .class_size = sizeof(PnvPsiClass), 962 .abstract = true, 963 .interfaces = (InterfaceInfo[]) { 964 { TYPE_PNV_XSCOM_INTERFACE }, 965 { } 966 } 967 }; 968 969 static void pnv_psi_register_types(void) 970 { 971 type_register_static(&pnv_psi_info); 972 type_register_static(&pnv_psi_power8_info); 973 type_register_static(&pnv_psi_power9_info); 974 type_register_static(&pnv_psi_power10_info); 975 } 976 977 type_init(pnv_psi_register_types); 978 979 void pnv_psi_pic_print_info(Pnv9Psi *psi9, GString *buf) 980 { 981 PnvPsi *psi = PNV_PSI(psi9); 982 983 uint32_t offset = 984 (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT); 985 986 g_string_append_printf(buf, "PSIHB Source %08x .. %08x\n", 987 offset, offset + psi9->source.nr_irqs - 1); 988 xive_source_pic_print_info(&psi9->source, offset, buf); 989 } 990