1 /* 2 * QEMU PowerPC PowerNV Processor Service Interface (PSI) model 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "hw/hw.h" 22 #include "target/ppc/cpu.h" 23 #include "qemu/log.h" 24 #include "qapi/error.h" 25 26 #include "exec/address-spaces.h" 27 28 #include "hw/ppc/fdt.h" 29 #include "hw/ppc/pnv.h" 30 #include "hw/ppc/pnv_xscom.h" 31 #include "hw/ppc/pnv_psi.h" 32 33 #include <libfdt.h> 34 35 #define PSIHB_XSCOM_FIR_RW 0x00 36 #define PSIHB_XSCOM_FIR_AND 0x01 37 #define PSIHB_XSCOM_FIR_OR 0x02 38 #define PSIHB_XSCOM_FIRMASK_RW 0x03 39 #define PSIHB_XSCOM_FIRMASK_AND 0x04 40 #define PSIHB_XSCOM_FIRMASK_OR 0x05 41 #define PSIHB_XSCOM_FIRACT0 0x06 42 #define PSIHB_XSCOM_FIRACT1 0x07 43 44 /* Host Bridge Base Address Register */ 45 #define PSIHB_XSCOM_BAR 0x0a 46 #define PSIHB_BAR_EN 0x0000000000000001ull 47 48 /* FSP Base Address Register */ 49 #define PSIHB_XSCOM_FSPBAR 0x0b 50 51 /* PSI Host Bridge Control/Status Register */ 52 #define PSIHB_XSCOM_CR 0x0e 53 #define PSIHB_CR_FSP_CMD_ENABLE 0x8000000000000000ull 54 #define PSIHB_CR_FSP_MMIO_ENABLE 0x4000000000000000ull 55 #define PSIHB_CR_FSP_IRQ_ENABLE 0x1000000000000000ull 56 #define PSIHB_CR_FSP_ERR_RSP_ENABLE 0x0800000000000000ull 57 #define PSIHB_CR_PSI_LINK_ENABLE 0x0400000000000000ull 58 #define PSIHB_CR_FSP_RESET 0x0200000000000000ull 59 #define PSIHB_CR_PSIHB_RESET 0x0100000000000000ull 60 #define PSIHB_CR_PSI_IRQ 0x0000800000000000ull 61 #define PSIHB_CR_FSP_IRQ 0x0000400000000000ull 62 #define PSIHB_CR_FSP_LINK_ACTIVE 0x0000200000000000ull 63 #define PSIHB_CR_IRQ_CMD_EXPECT 0x0000010000000000ull 64 /* and more ... */ 65 66 /* PSIHB Status / Error Mask Register */ 67 #define PSIHB_XSCOM_SEMR 0x0f 68 69 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */ 70 #define PSIHB_XSCOM_XIVR_FSP 0x10 71 #define PSIHB_XIVR_SERVER_SH 40 72 #define PSIHB_XIVR_SERVER_MSK (0xffffull << PSIHB_XIVR_SERVER_SH) 73 #define PSIHB_XIVR_PRIO_SH 32 74 #define PSIHB_XIVR_PRIO_MSK (0xffull << PSIHB_XIVR_PRIO_SH) 75 #define PSIHB_XIVR_SRC_SH 29 76 #define PSIHB_XIVR_SRC_MSK (0x7ull << PSIHB_XIVR_SRC_SH) 77 #define PSIHB_XIVR_PENDING 0x01000000ull 78 79 /* PSI Host Bridge Set Control/ Status Register */ 80 #define PSIHB_XSCOM_SCR 0x12 81 82 /* PSI Host Bridge Clear Control/ Status Register */ 83 #define PSIHB_XSCOM_CCR 0x13 84 85 /* DMA Upper Address Register */ 86 #define PSIHB_XSCOM_DMA_UPADD 0x14 87 88 /* Interrupt Status */ 89 #define PSIHB_XSCOM_IRQ_STAT 0x15 90 #define PSIHB_IRQ_STAT_OCC 0x0000001000000000ull 91 #define PSIHB_IRQ_STAT_FSI 0x0000000800000000ull 92 #define PSIHB_IRQ_STAT_LPCI2C 0x0000000400000000ull 93 #define PSIHB_IRQ_STAT_LOCERR 0x0000000200000000ull 94 #define PSIHB_IRQ_STAT_EXT 0x0000000100000000ull 95 96 /* remaining XIVR */ 97 #define PSIHB_XSCOM_XIVR_OCC 0x16 98 #define PSIHB_XSCOM_XIVR_FSI 0x17 99 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18 100 #define PSIHB_XSCOM_XIVR_LOCERR 0x19 101 #define PSIHB_XSCOM_XIVR_EXT 0x1a 102 103 /* Interrupt Requester Source Compare Register */ 104 #define PSIHB_XSCOM_IRSN 0x1b 105 #define PSIHB_IRSN_COMP_SH 45 106 #define PSIHB_IRSN_COMP_MSK (0x7ffffull << PSIHB_IRSN_COMP_SH) 107 #define PSIHB_IRSN_IRQ_MUX 0x0000000800000000ull 108 #define PSIHB_IRSN_IRQ_RESET 0x0000000400000000ull 109 #define PSIHB_IRSN_DOWNSTREAM_EN 0x0000000200000000ull 110 #define PSIHB_IRSN_UPSTREAM_EN 0x0000000100000000ull 111 #define PSIHB_IRSN_COMPMASK_SH 13 112 #define PSIHB_IRSN_COMPMASK_MSK (0x7ffffull << PSIHB_IRSN_COMPMASK_SH) 113 114 #define PSIHB_BAR_MASK 0x0003fffffff00000ull 115 #define PSIHB_FSPBAR_MASK 0x0003ffff00000000ull 116 117 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar) 118 { 119 MemoryRegion *sysmem = get_system_memory(); 120 uint64_t old = psi->regs[PSIHB_XSCOM_BAR]; 121 122 psi->regs[PSIHB_XSCOM_BAR] = bar & (PSIHB_BAR_MASK | PSIHB_BAR_EN); 123 124 /* Update MR, always remove it first */ 125 if (old & PSIHB_BAR_EN) { 126 memory_region_del_subregion(sysmem, &psi->regs_mr); 127 } 128 129 /* Then add it back if needed */ 130 if (bar & PSIHB_BAR_EN) { 131 uint64_t addr = bar & PSIHB_BAR_MASK; 132 memory_region_add_subregion(sysmem, addr, &psi->regs_mr); 133 } 134 } 135 136 static void pnv_psi_update_fsp_mr(PnvPsi *psi) 137 { 138 /* TODO: Update FSP MR if/when we support FSP BAR */ 139 } 140 141 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr) 142 { 143 uint64_t old = psi->regs[PSIHB_XSCOM_CR]; 144 145 psi->regs[PSIHB_XSCOM_CR] = cr; 146 147 /* Check some bit changes */ 148 if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) { 149 pnv_psi_update_fsp_mr(psi); 150 } 151 } 152 153 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val) 154 { 155 ICSState *ics = &psi->ics; 156 157 /* In this model we ignore the up/down enable bits for now 158 * as SW doesn't use them (other than setting them at boot). 159 * We ignore IRQ_MUX, its meaning isn't clear and we don't use 160 * it and finally we ignore reset (XXX fix that ?) 161 */ 162 psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK | 163 PSIHB_IRSN_IRQ_MUX | 164 PSIHB_IRSN_IRQ_RESET | 165 PSIHB_IRSN_DOWNSTREAM_EN | 166 PSIHB_IRSN_UPSTREAM_EN); 167 168 /* We ignore the compare mask as well, our ICS emulation is too 169 * simplistic to make any use if it, and we extract the offset 170 * from the compare value 171 */ 172 ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH; 173 } 174 175 /* 176 * FSP and PSI interrupts are muxed under the same number. 177 */ 178 static const uint32_t xivr_regs[] = { 179 [PSIHB_IRQ_PSI] = PSIHB_XSCOM_XIVR_FSP, 180 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_XIVR_FSP, 181 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_XIVR_OCC, 182 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_XIVR_FSI, 183 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_XIVR_LPCI2C, 184 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR, 185 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_XIVR_EXT, 186 }; 187 188 static const uint32_t stat_regs[] = { 189 [PSIHB_IRQ_PSI] = PSIHB_XSCOM_CR, 190 [PSIHB_IRQ_FSP] = PSIHB_XSCOM_CR, 191 [PSIHB_IRQ_OCC] = PSIHB_XSCOM_IRQ_STAT, 192 [PSIHB_IRQ_FSI] = PSIHB_XSCOM_IRQ_STAT, 193 [PSIHB_IRQ_LPC_I2C] = PSIHB_XSCOM_IRQ_STAT, 194 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT, 195 [PSIHB_IRQ_EXTERNAL] = PSIHB_XSCOM_IRQ_STAT, 196 }; 197 198 static const uint64_t stat_bits[] = { 199 [PSIHB_IRQ_PSI] = PSIHB_CR_PSI_IRQ, 200 [PSIHB_IRQ_FSP] = PSIHB_CR_FSP_IRQ, 201 [PSIHB_IRQ_OCC] = PSIHB_IRQ_STAT_OCC, 202 [PSIHB_IRQ_FSI] = PSIHB_IRQ_STAT_FSI, 203 [PSIHB_IRQ_LPC_I2C] = PSIHB_IRQ_STAT_LPCI2C, 204 [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR, 205 [PSIHB_IRQ_EXTERNAL] = PSIHB_IRQ_STAT_EXT, 206 }; 207 208 void pnv_psi_irq_set(PnvPsi *psi, PnvPsiIrq irq, bool state) 209 { 210 uint32_t xivr_reg; 211 uint32_t stat_reg; 212 uint32_t src; 213 bool masked; 214 215 if (irq > PSIHB_IRQ_EXTERNAL) { 216 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq); 217 return; 218 } 219 220 xivr_reg = xivr_regs[irq]; 221 stat_reg = stat_regs[irq]; 222 223 src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 224 if (state) { 225 psi->regs[stat_reg] |= stat_bits[irq]; 226 /* TODO: optimization, check mask here. That means 227 * re-evaluating when unmasking 228 */ 229 qemu_irq_raise(psi->qirqs[src]); 230 } else { 231 psi->regs[stat_reg] &= ~stat_bits[irq]; 232 233 /* FSP and PSI are muxed so don't lower if either is still set */ 234 if (stat_reg != PSIHB_XSCOM_CR || 235 !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) { 236 qemu_irq_lower(psi->qirqs[src]); 237 } else { 238 state = true; 239 } 240 } 241 242 /* Note about the emulation of the pending bit: This isn't 243 * entirely correct. The pending bit should be cleared when the 244 * EOI has been received. However, we don't have callbacks on EOI 245 * (especially not under KVM) so no way to emulate that properly, 246 * so instead we just set that bit as the logical "output" of the 247 * XIVR (ie pending & !masked) 248 * 249 * CLG: We could define a new ICS object with a custom eoi() 250 * handler to clear the pending bit. But I am not sure this would 251 * be useful for the software anyhow. 252 */ 253 masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK; 254 if (state && !masked) { 255 psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING; 256 } else { 257 psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING; 258 } 259 } 260 261 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val) 262 { 263 ICSState *ics = &psi->ics; 264 uint16_t server; 265 uint8_t prio; 266 uint8_t src; 267 268 psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) | 269 (val & (PSIHB_XIVR_SERVER_MSK | 270 PSIHB_XIVR_PRIO_MSK | 271 PSIHB_XIVR_SRC_MSK)); 272 val = psi->regs[reg]; 273 server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH; 274 prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH; 275 src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH; 276 277 if (src >= PSI_NUM_INTERRUPTS) { 278 qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src); 279 return; 280 } 281 282 /* Remove pending bit if the IRQ is masked */ 283 if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) { 284 psi->regs[reg] &= ~PSIHB_XIVR_PENDING; 285 } 286 287 /* The low order 2 bits are the link pointer (Type II interrupts). 288 * Shift back to get a valid IRQ server. 289 */ 290 server >>= 2; 291 292 /* Now because of source remapping, weird things can happen 293 * if you change the source number dynamically, our simple ICS 294 * doesn't deal with remapping. So we just poke a different 295 * ICS entry based on what source number was written. This will 296 * do for now but a more accurate implementation would instead 297 * use a fixed server/prio and a remapper of the generated irq. 298 */ 299 ics_simple_write_xive(ics, src, server, prio, prio); 300 } 301 302 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio) 303 { 304 uint64_t val = 0xffffffffffffffffull; 305 306 switch (offset) { 307 case PSIHB_XSCOM_FIR_RW: 308 case PSIHB_XSCOM_FIRACT0: 309 case PSIHB_XSCOM_FIRACT1: 310 case PSIHB_XSCOM_BAR: 311 case PSIHB_XSCOM_FSPBAR: 312 case PSIHB_XSCOM_CR: 313 case PSIHB_XSCOM_XIVR_FSP: 314 case PSIHB_XSCOM_XIVR_OCC: 315 case PSIHB_XSCOM_XIVR_FSI: 316 case PSIHB_XSCOM_XIVR_LPCI2C: 317 case PSIHB_XSCOM_XIVR_LOCERR: 318 case PSIHB_XSCOM_XIVR_EXT: 319 case PSIHB_XSCOM_IRQ_STAT: 320 case PSIHB_XSCOM_SEMR: 321 case PSIHB_XSCOM_DMA_UPADD: 322 case PSIHB_XSCOM_IRSN: 323 val = psi->regs[offset]; 324 break; 325 default: 326 qemu_log_mask(LOG_UNIMP, "PSI: read at Ox%" PRIx32 "\n", offset); 327 } 328 return val; 329 } 330 331 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val, 332 bool mmio) 333 { 334 switch (offset) { 335 case PSIHB_XSCOM_FIR_RW: 336 case PSIHB_XSCOM_FIRACT0: 337 case PSIHB_XSCOM_FIRACT1: 338 case PSIHB_XSCOM_SEMR: 339 case PSIHB_XSCOM_DMA_UPADD: 340 psi->regs[offset] = val; 341 break; 342 case PSIHB_XSCOM_FIR_OR: 343 psi->regs[PSIHB_XSCOM_FIR_RW] |= val; 344 break; 345 case PSIHB_XSCOM_FIR_AND: 346 psi->regs[PSIHB_XSCOM_FIR_RW] &= val; 347 break; 348 case PSIHB_XSCOM_BAR: 349 /* Only XSCOM can write this one */ 350 if (!mmio) { 351 pnv_psi_set_bar(psi, val); 352 } else { 353 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n"); 354 } 355 break; 356 case PSIHB_XSCOM_FSPBAR: 357 psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK; 358 pnv_psi_update_fsp_mr(psi); 359 break; 360 case PSIHB_XSCOM_CR: 361 pnv_psi_set_cr(psi, val); 362 break; 363 case PSIHB_XSCOM_SCR: 364 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val); 365 break; 366 case PSIHB_XSCOM_CCR: 367 pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val); 368 break; 369 case PSIHB_XSCOM_XIVR_FSP: 370 case PSIHB_XSCOM_XIVR_OCC: 371 case PSIHB_XSCOM_XIVR_FSI: 372 case PSIHB_XSCOM_XIVR_LPCI2C: 373 case PSIHB_XSCOM_XIVR_LOCERR: 374 case PSIHB_XSCOM_XIVR_EXT: 375 pnv_psi_set_xivr(psi, offset, val); 376 break; 377 case PSIHB_XSCOM_IRQ_STAT: 378 /* Read only */ 379 qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n"); 380 break; 381 case PSIHB_XSCOM_IRSN: 382 pnv_psi_set_irsn(psi, val); 383 break; 384 default: 385 qemu_log_mask(LOG_UNIMP, "PSI: write at Ox%" PRIx32 "\n", offset); 386 } 387 } 388 389 /* 390 * The values of the registers when accessed through the MMIO region 391 * follow the relation : xscom = (mmio + 0x50) >> 3 392 */ 393 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size) 394 { 395 return pnv_psi_reg_read(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, true); 396 } 397 398 static void pnv_psi_mmio_write(void *opaque, hwaddr addr, 399 uint64_t val, unsigned size) 400 { 401 pnv_psi_reg_write(opaque, (addr >> 3) + PSIHB_XSCOM_BAR, val, true); 402 } 403 404 static const MemoryRegionOps psi_mmio_ops = { 405 .read = pnv_psi_mmio_read, 406 .write = pnv_psi_mmio_write, 407 .endianness = DEVICE_BIG_ENDIAN, 408 .valid = { 409 .min_access_size = 8, 410 .max_access_size = 8, 411 }, 412 .impl = { 413 .min_access_size = 8, 414 .max_access_size = 8, 415 }, 416 }; 417 418 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size) 419 { 420 return pnv_psi_reg_read(opaque, addr >> 3, false); 421 } 422 423 static void pnv_psi_xscom_write(void *opaque, hwaddr addr, 424 uint64_t val, unsigned size) 425 { 426 pnv_psi_reg_write(opaque, addr >> 3, val, false); 427 } 428 429 static const MemoryRegionOps pnv_psi_xscom_ops = { 430 .read = pnv_psi_xscom_read, 431 .write = pnv_psi_xscom_write, 432 .endianness = DEVICE_BIG_ENDIAN, 433 .valid = { 434 .min_access_size = 8, 435 .max_access_size = 8, 436 }, 437 .impl = { 438 .min_access_size = 8, 439 .max_access_size = 8, 440 } 441 }; 442 443 static void pnv_psi_init(Object *obj) 444 { 445 PnvPsi *psi = PNV_PSI(obj); 446 447 object_initialize_child(obj, "ics-psi", &psi->ics, sizeof(psi->ics), 448 TYPE_ICS_SIMPLE, &error_abort, NULL); 449 } 450 451 static const uint8_t irq_to_xivr[] = { 452 PSIHB_XSCOM_XIVR_FSP, 453 PSIHB_XSCOM_XIVR_OCC, 454 PSIHB_XSCOM_XIVR_FSI, 455 PSIHB_XSCOM_XIVR_LPCI2C, 456 PSIHB_XSCOM_XIVR_LOCERR, 457 PSIHB_XSCOM_XIVR_EXT, 458 }; 459 460 static void pnv_psi_realize(DeviceState *dev, Error **errp) 461 { 462 PnvPsi *psi = PNV_PSI(dev); 463 ICSState *ics = &psi->ics; 464 Object *obj; 465 Error *err = NULL; 466 unsigned int i; 467 468 obj = object_property_get_link(OBJECT(dev), "xics", &err); 469 if (!obj) { 470 error_setg(errp, "%s: required link 'xics' not found: %s", 471 __func__, error_get_pretty(err)); 472 return; 473 } 474 475 /* Create PSI interrupt control source */ 476 object_property_add_const_link(OBJECT(ics), ICS_PROP_XICS, obj, 477 &error_abort); 478 object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err); 479 if (err) { 480 error_propagate(errp, err); 481 return; 482 } 483 object_property_set_bool(OBJECT(ics), true, "realized", &err); 484 if (err) { 485 error_propagate(errp, err); 486 return; 487 } 488 489 for (i = 0; i < ics->nr_irqs; i++) { 490 ics_set_irq_type(ics, i, true); 491 } 492 493 psi->qirqs = qemu_allocate_irqs(ics_simple_set_irq, ics, ics->nr_irqs); 494 495 /* XSCOM region for PSI registers */ 496 pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops, 497 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE); 498 499 /* Initialize MMIO region */ 500 memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, 501 "psihb", PNV_PSIHB_SIZE); 502 503 /* Default BAR for MMIO region */ 504 pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); 505 506 /* Default sources in XIVR */ 507 for (i = 0; i < PSI_NUM_INTERRUPTS; i++) { 508 uint8_t xivr = irq_to_xivr[i]; 509 psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK | 510 ((uint64_t) i << PSIHB_XIVR_SRC_SH); 511 } 512 } 513 514 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) 515 { 516 const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x"; 517 char *name; 518 int offset; 519 uint32_t lpc_pcba = PNV_XSCOM_PSIHB_BASE; 520 uint32_t reg[] = { 521 cpu_to_be32(lpc_pcba), 522 cpu_to_be32(PNV_XSCOM_PSIHB_SIZE) 523 }; 524 525 name = g_strdup_printf("psihb@%x", lpc_pcba); 526 offset = fdt_add_subnode(fdt, xscom_offset, name); 527 _FDT(offset); 528 g_free(name); 529 530 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 531 532 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); 533 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); 534 _FDT((fdt_setprop(fdt, offset, "compatible", compat, 535 sizeof(compat)))); 536 return 0; 537 } 538 539 static Property pnv_psi_properties[] = { 540 DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0), 541 DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0), 542 DEFINE_PROP_END_OF_LIST(), 543 }; 544 545 static void pnv_psi_class_init(ObjectClass *klass, void *data) 546 { 547 DeviceClass *dc = DEVICE_CLASS(klass); 548 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 549 550 xdc->dt_xscom = pnv_psi_dt_xscom; 551 552 dc->realize = pnv_psi_realize; 553 dc->props = pnv_psi_properties; 554 } 555 556 static const TypeInfo pnv_psi_info = { 557 .name = TYPE_PNV_PSI, 558 .parent = TYPE_SYS_BUS_DEVICE, 559 .instance_size = sizeof(PnvPsi), 560 .instance_init = pnv_psi_init, 561 .class_init = pnv_psi_class_init, 562 .interfaces = (InterfaceInfo[]) { 563 { TYPE_PNV_XSCOM_INTERFACE }, 564 { } 565 } 566 }; 567 568 static void pnv_psi_register_types(void) 569 { 570 type_register_static(&pnv_psi_info); 571 } 572 573 type_init(pnv_psi_register_types) 574