xref: /openbmc/qemu/hw/ppc/pnv_psi.c (revision 3c4b89c3)
1 /*
2  * QEMU PowerPC PowerNV Processor Service Interface (PSI) model
3  *
4  * Copyright (c) 2015-2017, IBM Corporation.
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "hw/irq.h"
22 #include "target/ppc/cpu.h"
23 #include "qemu/log.h"
24 #include "qemu/module.h"
25 #include "sysemu/reset.h"
26 #include "qapi/error.h"
27 #include "monitor/monitor.h"
28 
29 #include "exec/address-spaces.h"
30 
31 #include "hw/ppc/fdt.h"
32 #include "hw/ppc/pnv.h"
33 #include "hw/ppc/pnv_xscom.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/ppc/pnv_psi.h"
36 
37 #include <libfdt.h>
38 
39 #define PSIHB_XSCOM_FIR_RW      0x00
40 #define PSIHB_XSCOM_FIR_AND     0x01
41 #define PSIHB_XSCOM_FIR_OR      0x02
42 #define PSIHB_XSCOM_FIRMASK_RW  0x03
43 #define PSIHB_XSCOM_FIRMASK_AND 0x04
44 #define PSIHB_XSCOM_FIRMASK_OR  0x05
45 #define PSIHB_XSCOM_FIRACT0     0x06
46 #define PSIHB_XSCOM_FIRACT1     0x07
47 
48 /* Host Bridge Base Address Register */
49 #define PSIHB_XSCOM_BAR         0x0a
50 #define   PSIHB_BAR_EN                  0x0000000000000001ull
51 
52 /* FSP Base Address Register */
53 #define PSIHB_XSCOM_FSPBAR      0x0b
54 
55 /* PSI Host Bridge Control/Status Register */
56 #define PSIHB_XSCOM_CR          0x0e
57 #define   PSIHB_CR_FSP_CMD_ENABLE       0x8000000000000000ull
58 #define   PSIHB_CR_FSP_MMIO_ENABLE      0x4000000000000000ull
59 #define   PSIHB_CR_FSP_IRQ_ENABLE       0x1000000000000000ull
60 #define   PSIHB_CR_FSP_ERR_RSP_ENABLE   0x0800000000000000ull
61 #define   PSIHB_CR_PSI_LINK_ENABLE      0x0400000000000000ull
62 #define   PSIHB_CR_FSP_RESET            0x0200000000000000ull
63 #define   PSIHB_CR_PSIHB_RESET          0x0100000000000000ull
64 #define   PSIHB_CR_PSI_IRQ              0x0000800000000000ull
65 #define   PSIHB_CR_FSP_IRQ              0x0000400000000000ull
66 #define   PSIHB_CR_FSP_LINK_ACTIVE      0x0000200000000000ull
67 #define   PSIHB_CR_IRQ_CMD_EXPECT       0x0000010000000000ull
68           /* and more ... */
69 
70 /* PSIHB Status / Error Mask Register */
71 #define PSIHB_XSCOM_SEMR        0x0f
72 
73 /* XIVR, to signal interrupts to the CEC firmware. more XIVR below. */
74 #define PSIHB_XSCOM_XIVR_FSP    0x10
75 #define   PSIHB_XIVR_SERVER_SH          40
76 #define   PSIHB_XIVR_SERVER_MSK         (0xffffull << PSIHB_XIVR_SERVER_SH)
77 #define   PSIHB_XIVR_PRIO_SH            32
78 #define   PSIHB_XIVR_PRIO_MSK           (0xffull << PSIHB_XIVR_PRIO_SH)
79 #define   PSIHB_XIVR_SRC_SH             29
80 #define   PSIHB_XIVR_SRC_MSK            (0x7ull << PSIHB_XIVR_SRC_SH)
81 #define   PSIHB_XIVR_PENDING            0x01000000ull
82 
83 /* PSI Host Bridge Set Control/ Status Register */
84 #define PSIHB_XSCOM_SCR         0x12
85 
86 /* PSI Host Bridge Clear Control/ Status Register */
87 #define PSIHB_XSCOM_CCR         0x13
88 
89 /* DMA Upper Address Register */
90 #define PSIHB_XSCOM_DMA_UPADD   0x14
91 
92 /* Interrupt Status */
93 #define PSIHB_XSCOM_IRQ_STAT    0x15
94 #define   PSIHB_IRQ_STAT_OCC            0x0000001000000000ull
95 #define   PSIHB_IRQ_STAT_FSI            0x0000000800000000ull
96 #define   PSIHB_IRQ_STAT_LPCI2C         0x0000000400000000ull
97 #define   PSIHB_IRQ_STAT_LOCERR         0x0000000200000000ull
98 #define   PSIHB_IRQ_STAT_EXT            0x0000000100000000ull
99 
100 /* remaining XIVR */
101 #define PSIHB_XSCOM_XIVR_OCC    0x16
102 #define PSIHB_XSCOM_XIVR_FSI    0x17
103 #define PSIHB_XSCOM_XIVR_LPCI2C 0x18
104 #define PSIHB_XSCOM_XIVR_LOCERR 0x19
105 #define PSIHB_XSCOM_XIVR_EXT    0x1a
106 
107 /* Interrupt Requester Source Compare Register */
108 #define PSIHB_XSCOM_IRSN        0x1b
109 #define   PSIHB_IRSN_COMP_SH            45
110 #define   PSIHB_IRSN_COMP_MSK           (0x7ffffull << PSIHB_IRSN_COMP_SH)
111 #define   PSIHB_IRSN_IRQ_MUX            0x0000000800000000ull
112 #define   PSIHB_IRSN_IRQ_RESET          0x0000000400000000ull
113 #define   PSIHB_IRSN_DOWNSTREAM_EN      0x0000000200000000ull
114 #define   PSIHB_IRSN_UPSTREAM_EN        0x0000000100000000ull
115 #define   PSIHB_IRSN_COMPMASK_SH        13
116 #define   PSIHB_IRSN_COMPMASK_MSK       (0x7ffffull << PSIHB_IRSN_COMPMASK_SH)
117 
118 #define PSIHB_BAR_MASK                  0x0003fffffff00000ull
119 #define PSIHB_FSPBAR_MASK               0x0003ffff00000000ull
120 
121 #define PSIHB9_BAR_MASK                 0x00fffffffff00000ull
122 #define PSIHB9_FSPBAR_MASK              0x00ffffff00000000ull
123 
124 #define PSIHB_REG(addr) (((addr) >> 3) + PSIHB_XSCOM_BAR)
125 
126 static void pnv_psi_set_bar(PnvPsi *psi, uint64_t bar)
127 {
128     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(psi);
129     MemoryRegion *sysmem = get_system_memory();
130     uint64_t old = psi->regs[PSIHB_XSCOM_BAR];
131 
132     psi->regs[PSIHB_XSCOM_BAR] = bar & (ppc->bar_mask | PSIHB_BAR_EN);
133 
134     /* Update MR, always remove it first */
135     if (old & PSIHB_BAR_EN) {
136         memory_region_del_subregion(sysmem, &psi->regs_mr);
137     }
138 
139     /* Then add it back if needed */
140     if (bar & PSIHB_BAR_EN) {
141         uint64_t addr = bar & ppc->bar_mask;
142         memory_region_add_subregion(sysmem, addr, &psi->regs_mr);
143     }
144 }
145 
146 static void pnv_psi_update_fsp_mr(PnvPsi *psi)
147 {
148     /* TODO: Update FSP MR if/when we support FSP BAR */
149 }
150 
151 static void pnv_psi_set_cr(PnvPsi *psi, uint64_t cr)
152 {
153     uint64_t old = psi->regs[PSIHB_XSCOM_CR];
154 
155     psi->regs[PSIHB_XSCOM_CR] = cr;
156 
157     /* Check some bit changes */
158     if ((old ^ psi->regs[PSIHB_XSCOM_CR]) & PSIHB_CR_FSP_MMIO_ENABLE) {
159         pnv_psi_update_fsp_mr(psi);
160     }
161 }
162 
163 static void pnv_psi_set_irsn(PnvPsi *psi, uint64_t val)
164 {
165     ICSState *ics = &PNV8_PSI(psi)->ics;
166 
167     /* In this model we ignore the up/down enable bits for now
168      * as SW doesn't use them (other than setting them at boot).
169      * We ignore IRQ_MUX, its meaning isn't clear and we don't use
170      * it and finally we ignore reset (XXX fix that ?)
171      */
172     psi->regs[PSIHB_XSCOM_IRSN] = val & (PSIHB_IRSN_COMP_MSK |
173                                          PSIHB_IRSN_IRQ_MUX |
174                                          PSIHB_IRSN_IRQ_RESET |
175                                          PSIHB_IRSN_DOWNSTREAM_EN |
176                                          PSIHB_IRSN_UPSTREAM_EN);
177 
178     /* We ignore the compare mask as well, our ICS emulation is too
179      * simplistic to make any use if it, and we extract the offset
180      * from the compare value
181      */
182     ics->offset = (val & PSIHB_IRSN_COMP_MSK) >> PSIHB_IRSN_COMP_SH;
183 }
184 
185 /*
186  * FSP and PSI interrupts are muxed under the same number.
187  */
188 static const uint32_t xivr_regs[] = {
189     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_XIVR_FSP,
190     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_XIVR_FSP,
191     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_XIVR_OCC,
192     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_XIVR_FSI,
193     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_XIVR_LPCI2C,
194     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_XIVR_LOCERR,
195     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_XIVR_EXT,
196 };
197 
198 static const uint32_t stat_regs[] = {
199     [PSIHB_IRQ_PSI]       = PSIHB_XSCOM_CR,
200     [PSIHB_IRQ_FSP]       = PSIHB_XSCOM_CR,
201     [PSIHB_IRQ_OCC]       = PSIHB_XSCOM_IRQ_STAT,
202     [PSIHB_IRQ_FSI]       = PSIHB_XSCOM_IRQ_STAT,
203     [PSIHB_IRQ_LPC_I2C]   = PSIHB_XSCOM_IRQ_STAT,
204     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_XSCOM_IRQ_STAT,
205     [PSIHB_IRQ_EXTERNAL]  = PSIHB_XSCOM_IRQ_STAT,
206 };
207 
208 static const uint64_t stat_bits[] = {
209     [PSIHB_IRQ_PSI]       = PSIHB_CR_PSI_IRQ,
210     [PSIHB_IRQ_FSP]       = PSIHB_CR_FSP_IRQ,
211     [PSIHB_IRQ_OCC]       = PSIHB_IRQ_STAT_OCC,
212     [PSIHB_IRQ_FSI]       = PSIHB_IRQ_STAT_FSI,
213     [PSIHB_IRQ_LPC_I2C]   = PSIHB_IRQ_STAT_LPCI2C,
214     [PSIHB_IRQ_LOCAL_ERR] = PSIHB_IRQ_STAT_LOCERR,
215     [PSIHB_IRQ_EXTERNAL]  = PSIHB_IRQ_STAT_EXT,
216 };
217 
218 void pnv_psi_irq_set(PnvPsi *psi, int irq, bool state)
219 {
220     PNV_PSI_GET_CLASS(psi)->irq_set(psi, irq, state);
221 }
222 
223 static void pnv_psi_power8_irq_set(PnvPsi *psi, int irq, bool state)
224 {
225     uint32_t xivr_reg;
226     uint32_t stat_reg;
227     uint32_t src;
228     bool masked;
229 
230     if (irq > PSIHB_IRQ_EXTERNAL) {
231         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
232         return;
233     }
234 
235     xivr_reg = xivr_regs[irq];
236     stat_reg = stat_regs[irq];
237 
238     src = (psi->regs[xivr_reg] & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
239     if (state) {
240         psi->regs[stat_reg] |= stat_bits[irq];
241         /* TODO: optimization, check mask here. That means
242          * re-evaluating when unmasking
243          */
244         qemu_irq_raise(psi->qirqs[src]);
245     } else {
246         psi->regs[stat_reg] &= ~stat_bits[irq];
247 
248         /* FSP and PSI are muxed so don't lower if either is still set */
249         if (stat_reg != PSIHB_XSCOM_CR ||
250             !(psi->regs[stat_reg] & (PSIHB_CR_PSI_IRQ | PSIHB_CR_FSP_IRQ))) {
251             qemu_irq_lower(psi->qirqs[src]);
252         } else {
253             state = true;
254         }
255     }
256 
257     /* Note about the emulation of the pending bit: This isn't
258      * entirely correct. The pending bit should be cleared when the
259      * EOI has been received. However, we don't have callbacks on EOI
260      * (especially not under KVM) so no way to emulate that properly,
261      * so instead we just set that bit as the logical "output" of the
262      * XIVR (ie pending & !masked)
263      *
264      * CLG: We could define a new ICS object with a custom eoi()
265      * handler to clear the pending bit. But I am not sure this would
266      * be useful for the software anyhow.
267      */
268     masked = (psi->regs[xivr_reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK;
269     if (state && !masked) {
270         psi->regs[xivr_reg] |= PSIHB_XIVR_PENDING;
271     } else {
272         psi->regs[xivr_reg] &= ~PSIHB_XIVR_PENDING;
273     }
274 }
275 
276 static void pnv_psi_set_xivr(PnvPsi *psi, uint32_t reg, uint64_t val)
277 {
278     ICSState *ics = &PNV8_PSI(psi)->ics;
279     uint16_t server;
280     uint8_t prio;
281     uint8_t src;
282 
283     psi->regs[reg] = (psi->regs[reg] & PSIHB_XIVR_PENDING) |
284             (val & (PSIHB_XIVR_SERVER_MSK |
285                     PSIHB_XIVR_PRIO_MSK |
286                     PSIHB_XIVR_SRC_MSK));
287     val = psi->regs[reg];
288     server = (val & PSIHB_XIVR_SERVER_MSK) >> PSIHB_XIVR_SERVER_SH;
289     prio = (val & PSIHB_XIVR_PRIO_MSK) >> PSIHB_XIVR_PRIO_SH;
290     src = (val & PSIHB_XIVR_SRC_MSK) >> PSIHB_XIVR_SRC_SH;
291 
292     if (src >= PSI_NUM_INTERRUPTS) {
293         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", src);
294         return;
295     }
296 
297     /* Remove pending bit if the IRQ is masked */
298     if ((psi->regs[reg] & PSIHB_XIVR_PRIO_MSK) == PSIHB_XIVR_PRIO_MSK) {
299         psi->regs[reg] &= ~PSIHB_XIVR_PENDING;
300     }
301 
302     /* The low order 2 bits are the link pointer (Type II interrupts).
303      * Shift back to get a valid IRQ server.
304      */
305     server >>= 2;
306 
307     /* Now because of source remapping, weird things can happen
308      * if you change the source number dynamically, our simple ICS
309      * doesn't deal with remapping. So we just poke a different
310      * ICS entry based on what source number was written. This will
311      * do for now but a more accurate implementation would instead
312      * use a fixed server/prio and a remapper of the generated irq.
313      */
314     ics_write_xive(ics, src, server, prio, prio);
315 }
316 
317 static uint64_t pnv_psi_reg_read(PnvPsi *psi, uint32_t offset, bool mmio)
318 {
319     uint64_t val = 0xffffffffffffffffull;
320 
321     switch (offset) {
322     case PSIHB_XSCOM_FIR_RW:
323     case PSIHB_XSCOM_FIRACT0:
324     case PSIHB_XSCOM_FIRACT1:
325     case PSIHB_XSCOM_BAR:
326     case PSIHB_XSCOM_FSPBAR:
327     case PSIHB_XSCOM_CR:
328     case PSIHB_XSCOM_XIVR_FSP:
329     case PSIHB_XSCOM_XIVR_OCC:
330     case PSIHB_XSCOM_XIVR_FSI:
331     case PSIHB_XSCOM_XIVR_LPCI2C:
332     case PSIHB_XSCOM_XIVR_LOCERR:
333     case PSIHB_XSCOM_XIVR_EXT:
334     case PSIHB_XSCOM_IRQ_STAT:
335     case PSIHB_XSCOM_SEMR:
336     case PSIHB_XSCOM_DMA_UPADD:
337     case PSIHB_XSCOM_IRSN:
338         val = psi->regs[offset];
339         break;
340     default:
341         qemu_log_mask(LOG_UNIMP, "PSI: read at 0x%" PRIx32 "\n", offset);
342     }
343     return val;
344 }
345 
346 static void pnv_psi_reg_write(PnvPsi *psi, uint32_t offset, uint64_t val,
347                               bool mmio)
348 {
349     switch (offset) {
350     case PSIHB_XSCOM_FIR_RW:
351     case PSIHB_XSCOM_FIRACT0:
352     case PSIHB_XSCOM_FIRACT1:
353     case PSIHB_XSCOM_SEMR:
354     case PSIHB_XSCOM_DMA_UPADD:
355         psi->regs[offset] = val;
356         break;
357     case PSIHB_XSCOM_FIR_OR:
358         psi->regs[PSIHB_XSCOM_FIR_RW] |= val;
359         break;
360     case PSIHB_XSCOM_FIR_AND:
361         psi->regs[PSIHB_XSCOM_FIR_RW] &= val;
362         break;
363     case PSIHB_XSCOM_BAR:
364         /* Only XSCOM can write this one */
365         if (!mmio) {
366             pnv_psi_set_bar(psi, val);
367         } else {
368             qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of BAR\n");
369         }
370         break;
371     case PSIHB_XSCOM_FSPBAR:
372         psi->regs[PSIHB_XSCOM_FSPBAR] = val & PSIHB_FSPBAR_MASK;
373         pnv_psi_update_fsp_mr(psi);
374         break;
375     case PSIHB_XSCOM_CR:
376         pnv_psi_set_cr(psi, val);
377         break;
378     case PSIHB_XSCOM_SCR:
379         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] | val);
380         break;
381     case PSIHB_XSCOM_CCR:
382         pnv_psi_set_cr(psi, psi->regs[PSIHB_XSCOM_CR] & ~val);
383         break;
384     case PSIHB_XSCOM_XIVR_FSP:
385     case PSIHB_XSCOM_XIVR_OCC:
386     case PSIHB_XSCOM_XIVR_FSI:
387     case PSIHB_XSCOM_XIVR_LPCI2C:
388     case PSIHB_XSCOM_XIVR_LOCERR:
389     case PSIHB_XSCOM_XIVR_EXT:
390         pnv_psi_set_xivr(psi, offset, val);
391         break;
392     case PSIHB_XSCOM_IRQ_STAT:
393         /* Read only */
394         qemu_log_mask(LOG_GUEST_ERROR, "PSI: invalid write of IRQ_STAT\n");
395         break;
396     case PSIHB_XSCOM_IRSN:
397         pnv_psi_set_irsn(psi, val);
398         break;
399     default:
400         qemu_log_mask(LOG_UNIMP, "PSI: write at 0x%" PRIx32 "\n", offset);
401     }
402 }
403 
404 /*
405  * The values of the registers when accessed through the MMIO region
406  * follow the relation : xscom = (mmio + 0x50) >> 3
407  */
408 static uint64_t pnv_psi_mmio_read(void *opaque, hwaddr addr, unsigned size)
409 {
410     return pnv_psi_reg_read(opaque, PSIHB_REG(addr), true);
411 }
412 
413 static void pnv_psi_mmio_write(void *opaque, hwaddr addr,
414                               uint64_t val, unsigned size)
415 {
416     pnv_psi_reg_write(opaque, PSIHB_REG(addr), val, true);
417 }
418 
419 static const MemoryRegionOps psi_mmio_ops = {
420     .read = pnv_psi_mmio_read,
421     .write = pnv_psi_mmio_write,
422     .endianness = DEVICE_BIG_ENDIAN,
423     .valid = {
424         .min_access_size = 8,
425         .max_access_size = 8,
426     },
427     .impl = {
428         .min_access_size = 8,
429         .max_access_size = 8,
430     },
431 };
432 
433 static uint64_t pnv_psi_xscom_read(void *opaque, hwaddr addr, unsigned size)
434 {
435     return pnv_psi_reg_read(opaque, addr >> 3, false);
436 }
437 
438 static void pnv_psi_xscom_write(void *opaque, hwaddr addr,
439                                 uint64_t val, unsigned size)
440 {
441     pnv_psi_reg_write(opaque, addr >> 3, val, false);
442 }
443 
444 static const MemoryRegionOps pnv_psi_xscom_ops = {
445     .read = pnv_psi_xscom_read,
446     .write = pnv_psi_xscom_write,
447     .endianness = DEVICE_BIG_ENDIAN,
448     .valid = {
449         .min_access_size = 8,
450         .max_access_size = 8,
451     },
452     .impl = {
453         .min_access_size = 8,
454         .max_access_size = 8,
455     }
456 };
457 
458 static void pnv_psi_reset(DeviceState *dev)
459 {
460     PnvPsi *psi = PNV_PSI(dev);
461 
462     memset(psi->regs, 0x0, sizeof(psi->regs));
463 
464     psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN;
465 }
466 
467 static void pnv_psi_reset_handler(void *dev)
468 {
469     device_legacy_reset(DEVICE(dev));
470 }
471 
472 static void pnv_psi_realize(DeviceState *dev, Error **errp)
473 {
474     PnvPsi *psi = PNV_PSI(dev);
475 
476     /* Default BAR for MMIO region */
477     pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN);
478 
479     qemu_register_reset(pnv_psi_reset_handler, dev);
480 }
481 
482 static void pnv_psi_power8_instance_init(Object *obj)
483 {
484     Pnv8Psi *psi8 = PNV8_PSI(obj);
485 
486     object_initialize_child(obj, "ics-psi", &psi8->ics, TYPE_ICS);
487     object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics),
488                               ICS_PROP_XICS);
489 }
490 
491 static const uint8_t irq_to_xivr[] = {
492     PSIHB_XSCOM_XIVR_FSP,
493     PSIHB_XSCOM_XIVR_OCC,
494     PSIHB_XSCOM_XIVR_FSI,
495     PSIHB_XSCOM_XIVR_LPCI2C,
496     PSIHB_XSCOM_XIVR_LOCERR,
497     PSIHB_XSCOM_XIVR_EXT,
498 };
499 
500 static void pnv_psi_power8_realize(DeviceState *dev, Error **errp)
501 {
502     PnvPsi *psi = PNV_PSI(dev);
503     ICSState *ics = &PNV8_PSI(psi)->ics;
504     Error *err = NULL;
505     unsigned int i;
506 
507     /* Create PSI interrupt control source */
508     object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err);
509     if (err) {
510         error_propagate(errp, err);
511         return;
512     }
513     if (!qdev_realize(DEVICE(ics), NULL, &err)) {
514         error_propagate(errp, err);
515         return;
516     }
517 
518     for (i = 0; i < ics->nr_irqs; i++) {
519         ics_set_irq_type(ics, i, true);
520     }
521 
522     psi->qirqs = qemu_allocate_irqs(ics_set_irq, ics, ics->nr_irqs);
523 
524     /* XSCOM region for PSI registers */
525     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_xscom_ops,
526                 psi, "xscom-psi", PNV_XSCOM_PSIHB_SIZE);
527 
528     /* Initialize MMIO region */
529     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi,
530                           "psihb", PNV_PSIHB_SIZE);
531 
532     /* Default sources in XIVR */
533     for (i = 0; i < PSI_NUM_INTERRUPTS; i++) {
534         uint8_t xivr = irq_to_xivr[i];
535         psi->regs[xivr] = PSIHB_XIVR_PRIO_MSK |
536             ((uint64_t) i << PSIHB_XIVR_SRC_SH);
537     }
538 
539     pnv_psi_realize(dev, errp);
540 }
541 
542 static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset)
543 {
544     PnvPsiClass *ppc = PNV_PSI_GET_CLASS(dev);
545     char *name;
546     int offset;
547     uint32_t reg[] = {
548         cpu_to_be32(ppc->xscom_pcba),
549         cpu_to_be32(ppc->xscom_size)
550     };
551 
552     name = g_strdup_printf("psihb@%x", ppc->xscom_pcba);
553     offset = fdt_add_subnode(fdt, xscom_offset, name);
554     _FDT(offset);
555     g_free(name);
556 
557     _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)));
558     _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2));
559     _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1));
560     _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat,
561                      ppc->compat_size));
562     return 0;
563 }
564 
565 static Property pnv_psi_properties[] = {
566     DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0),
567     DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0),
568     DEFINE_PROP_END_OF_LIST(),
569 };
570 
571 static void pnv_psi_power8_class_init(ObjectClass *klass, void *data)
572 {
573     DeviceClass *dc = DEVICE_CLASS(klass);
574     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
575     static const char compat[] = "ibm,power8-psihb-x\0ibm,psihb-x";
576 
577     dc->desc    = "PowerNV PSI Controller POWER8";
578     dc->realize = pnv_psi_power8_realize;
579 
580     ppc->xscom_pcba = PNV_XSCOM_PSIHB_BASE;
581     ppc->xscom_size = PNV_XSCOM_PSIHB_SIZE;
582     ppc->bar_mask   = PSIHB_BAR_MASK;
583     ppc->irq_set    = pnv_psi_power8_irq_set;
584     ppc->compat     = compat;
585     ppc->compat_size = sizeof(compat);
586 }
587 
588 static const TypeInfo pnv_psi_power8_info = {
589     .name          = TYPE_PNV8_PSI,
590     .parent        = TYPE_PNV_PSI,
591     .instance_size = sizeof(Pnv8Psi),
592     .instance_init = pnv_psi_power8_instance_init,
593     .class_init    = pnv_psi_power8_class_init,
594 };
595 
596 
597 /* Common registers */
598 
599 #define PSIHB9_CR                       0x20
600 #define PSIHB9_SEMR                     0x28
601 
602 /* P9 registers */
603 
604 #define PSIHB9_INTERRUPT_CONTROL        0x58
605 #define   PSIHB9_IRQ_METHOD             PPC_BIT(0)
606 #define   PSIHB9_IRQ_RESET              PPC_BIT(1)
607 #define PSIHB9_ESB_CI_BASE              0x60
608 #define   PSIHB9_ESB_CI_64K             PPC_BIT(1)
609 #define   PSIHB9_ESB_CI_ADDR_MASK       PPC_BITMASK(8, 47)
610 #define   PSIHB9_ESB_CI_VALID           PPC_BIT(63)
611 #define PSIHB9_ESB_NOTIF_ADDR           0x68
612 #define   PSIHB9_ESB_NOTIF_ADDR_MASK    PPC_BITMASK(8, 60)
613 #define   PSIHB9_ESB_NOTIF_VALID        PPC_BIT(63)
614 #define PSIHB9_IVT_OFFSET               0x70
615 #define   PSIHB9_IVT_OFF_SHIFT          32
616 
617 #define PSIHB9_IRQ_LEVEL                0x78 /* assertion */
618 #define   PSIHB9_IRQ_LEVEL_PSI          PPC_BIT(0)
619 #define   PSIHB9_IRQ_LEVEL_OCC          PPC_BIT(1)
620 #define   PSIHB9_IRQ_LEVEL_FSI          PPC_BIT(2)
621 #define   PSIHB9_IRQ_LEVEL_LPCHC        PPC_BIT(3)
622 #define   PSIHB9_IRQ_LEVEL_LOCAL_ERR    PPC_BIT(4)
623 #define   PSIHB9_IRQ_LEVEL_GLOBAL_ERR   PPC_BIT(5)
624 #define   PSIHB9_IRQ_LEVEL_TPM          PPC_BIT(6)
625 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ1    PPC_BIT(7)
626 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ2    PPC_BIT(8)
627 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ3    PPC_BIT(9)
628 #define   PSIHB9_IRQ_LEVEL_LPC_SIRQ4    PPC_BIT(10)
629 #define   PSIHB9_IRQ_LEVEL_SBE_I2C      PPC_BIT(11)
630 #define   PSIHB9_IRQ_LEVEL_DIO          PPC_BIT(12)
631 #define   PSIHB9_IRQ_LEVEL_PSU          PPC_BIT(13)
632 #define   PSIHB9_IRQ_LEVEL_I2C_C        PPC_BIT(14)
633 #define   PSIHB9_IRQ_LEVEL_I2C_D        PPC_BIT(15)
634 #define   PSIHB9_IRQ_LEVEL_I2C_E        PPC_BIT(16)
635 #define   PSIHB9_IRQ_LEVEL_SBE          PPC_BIT(19)
636 
637 #define PSIHB9_IRQ_STAT                 0x80 /* P bit */
638 #define   PSIHB9_IRQ_STAT_PSI           PPC_BIT(0)
639 #define   PSIHB9_IRQ_STAT_OCC           PPC_BIT(1)
640 #define   PSIHB9_IRQ_STAT_FSI           PPC_BIT(2)
641 #define   PSIHB9_IRQ_STAT_LPCHC         PPC_BIT(3)
642 #define   PSIHB9_IRQ_STAT_LOCAL_ERR     PPC_BIT(4)
643 #define   PSIHB9_IRQ_STAT_GLOBAL_ERR    PPC_BIT(5)
644 #define   PSIHB9_IRQ_STAT_TPM           PPC_BIT(6)
645 #define   PSIHB9_IRQ_STAT_LPC_SIRQ1     PPC_BIT(7)
646 #define   PSIHB9_IRQ_STAT_LPC_SIRQ2     PPC_BIT(8)
647 #define   PSIHB9_IRQ_STAT_LPC_SIRQ3     PPC_BIT(9)
648 #define   PSIHB9_IRQ_STAT_LPC_SIRQ4     PPC_BIT(10)
649 #define   PSIHB9_IRQ_STAT_SBE_I2C       PPC_BIT(11)
650 #define   PSIHB9_IRQ_STAT_DIO           PPC_BIT(12)
651 #define   PSIHB9_IRQ_STAT_PSU           PPC_BIT(13)
652 
653 static void pnv_psi_notify(XiveNotifier *xf, uint32_t srcno)
654 {
655     PnvPsi *psi = PNV_PSI(xf);
656     uint64_t notif_port = psi->regs[PSIHB_REG(PSIHB9_ESB_NOTIF_ADDR)];
657     bool valid = notif_port & PSIHB9_ESB_NOTIF_VALID;
658     uint64_t notify_addr = notif_port & ~PSIHB9_ESB_NOTIF_VALID;
659 
660     uint32_t offset =
661         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
662     uint64_t data = XIVE_TRIGGER_PQ | offset | srcno;
663     MemTxResult result;
664 
665     if (!valid) {
666         return;
667     }
668 
669     address_space_stq_be(&address_space_memory, notify_addr, data,
670                          MEMTXATTRS_UNSPECIFIED, &result);
671     if (result != MEMTX_OK) {
672         qemu_log_mask(LOG_GUEST_ERROR, "%s: trigger failed @%"
673                       HWADDR_PRIx "\n", __func__, notif_port);
674         return;
675     }
676 }
677 
678 static uint64_t pnv_psi_p9_mmio_read(void *opaque, hwaddr addr, unsigned size)
679 {
680     PnvPsi *psi = PNV_PSI(opaque);
681     uint32_t reg = PSIHB_REG(addr);
682     uint64_t val = -1;
683 
684     switch (addr) {
685     case PSIHB9_CR:
686     case PSIHB9_SEMR:
687         /* FSP stuff */
688     case PSIHB9_INTERRUPT_CONTROL:
689     case PSIHB9_ESB_CI_BASE:
690     case PSIHB9_ESB_NOTIF_ADDR:
691     case PSIHB9_IVT_OFFSET:
692         val = psi->regs[reg];
693         break;
694     default:
695         qemu_log_mask(LOG_GUEST_ERROR, "PSI: read at 0x%" PRIx64 "\n", addr);
696     }
697 
698     return val;
699 }
700 
701 static void pnv_psi_p9_mmio_write(void *opaque, hwaddr addr,
702                                   uint64_t val, unsigned size)
703 {
704     PnvPsi *psi = PNV_PSI(opaque);
705     Pnv9Psi *psi9 = PNV9_PSI(psi);
706     uint32_t reg = PSIHB_REG(addr);
707     MemoryRegion *sysmem = get_system_memory();
708 
709     switch (addr) {
710     case PSIHB9_CR:
711     case PSIHB9_SEMR:
712         /* FSP stuff */
713         break;
714     case PSIHB9_INTERRUPT_CONTROL:
715         if (val & PSIHB9_IRQ_RESET) {
716             device_legacy_reset(DEVICE(&psi9->source));
717         }
718         psi->regs[reg] = val;
719         break;
720 
721     case PSIHB9_ESB_CI_BASE:
722         if (!(val & PSIHB9_ESB_CI_VALID)) {
723             if (psi->regs[reg] & PSIHB9_ESB_CI_VALID) {
724                 memory_region_del_subregion(sysmem, &psi9->source.esb_mmio);
725             }
726         } else {
727             if (!(psi->regs[reg] & PSIHB9_ESB_CI_VALID)) {
728                 memory_region_add_subregion(sysmem,
729                                         val & ~PSIHB9_ESB_CI_VALID,
730                                         &psi9->source.esb_mmio);
731             }
732         }
733         psi->regs[reg] = val;
734         break;
735 
736     case PSIHB9_ESB_NOTIF_ADDR:
737         psi->regs[reg] = val;
738         break;
739     case PSIHB9_IVT_OFFSET:
740         psi->regs[reg] = val;
741         break;
742     default:
743         qemu_log_mask(LOG_GUEST_ERROR, "PSI: write at 0x%" PRIx64 "\n", addr);
744     }
745 }
746 
747 static const MemoryRegionOps pnv_psi_p9_mmio_ops = {
748     .read = pnv_psi_p9_mmio_read,
749     .write = pnv_psi_p9_mmio_write,
750     .endianness = DEVICE_BIG_ENDIAN,
751     .valid = {
752         .min_access_size = 8,
753         .max_access_size = 8,
754     },
755     .impl = {
756         .min_access_size = 8,
757         .max_access_size = 8,
758     },
759 };
760 
761 static uint64_t pnv_psi_p9_xscom_read(void *opaque, hwaddr addr, unsigned size)
762 {
763     /* No read are expected */
764     qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom read at 0x%" PRIx64 "\n", addr);
765     return -1;
766 }
767 
768 static void pnv_psi_p9_xscom_write(void *opaque, hwaddr addr,
769                                 uint64_t val, unsigned size)
770 {
771     PnvPsi *psi = PNV_PSI(opaque);
772 
773     /* XSCOM is only used to set the PSIHB MMIO region */
774     switch (addr >> 3) {
775     case PSIHB_XSCOM_BAR:
776         pnv_psi_set_bar(psi, val);
777         break;
778     default:
779         qemu_log_mask(LOG_GUEST_ERROR, "PSI: xscom write at 0x%" PRIx64 "\n",
780                       addr);
781     }
782 }
783 
784 static const MemoryRegionOps pnv_psi_p9_xscom_ops = {
785     .read = pnv_psi_p9_xscom_read,
786     .write = pnv_psi_p9_xscom_write,
787     .endianness = DEVICE_BIG_ENDIAN,
788     .valid = {
789         .min_access_size = 8,
790         .max_access_size = 8,
791     },
792     .impl = {
793         .min_access_size = 8,
794         .max_access_size = 8,
795     }
796 };
797 
798 static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state)
799 {
800     uint64_t irq_method = psi->regs[PSIHB_REG(PSIHB9_INTERRUPT_CONTROL)];
801 
802     if (irq > PSIHB9_NUM_IRQS) {
803         qemu_log_mask(LOG_GUEST_ERROR, "PSI: Unsupported irq %d\n", irq);
804         return;
805     }
806 
807     if (irq_method & PSIHB9_IRQ_METHOD) {
808         qemu_log_mask(LOG_GUEST_ERROR, "PSI: LSI IRQ method no supported\n");
809         return;
810     }
811 
812     /* Update LSI levels */
813     if (state) {
814         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] |= PPC_BIT(irq);
815     } else {
816         psi->regs[PSIHB_REG(PSIHB9_IRQ_LEVEL)] &= ~PPC_BIT(irq);
817     }
818 
819     qemu_set_irq(psi->qirqs[irq], state);
820 }
821 
822 static void pnv_psi_power9_reset(DeviceState *dev)
823 {
824     Pnv9Psi *psi = PNV9_PSI(dev);
825 
826     pnv_psi_reset(dev);
827 
828     if (memory_region_is_mapped(&psi->source.esb_mmio)) {
829         memory_region_del_subregion(get_system_memory(), &psi->source.esb_mmio);
830     }
831 }
832 
833 static void pnv_psi_power9_instance_init(Object *obj)
834 {
835     Pnv9Psi *psi = PNV9_PSI(obj);
836 
837     object_initialize_child(obj, "source", &psi->source, TYPE_XIVE_SOURCE);
838 }
839 
840 static void pnv_psi_power9_realize(DeviceState *dev, Error **errp)
841 {
842     PnvPsi *psi = PNV_PSI(dev);
843     XiveSource *xsrc = &PNV9_PSI(psi)->source;
844     Error *local_err = NULL;
845     int i;
846 
847     /* This is the only device with 4k ESB pages */
848     object_property_set_int(OBJECT(xsrc), XIVE_ESB_4K, "shift",
849                             &error_fatal);
850     object_property_set_int(OBJECT(xsrc), PSIHB9_NUM_IRQS, "nr-irqs",
851                             &error_fatal);
852     object_property_set_link(OBJECT(xsrc), OBJECT(psi), "xive", &error_abort);
853     if (!qdev_realize(DEVICE(xsrc), NULL, &local_err)) {
854         error_propagate(errp, local_err);
855         return;
856     }
857 
858     for (i = 0; i < xsrc->nr_irqs; i++) {
859         xive_source_irq_set_lsi(xsrc, i);
860     }
861 
862     psi->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs);
863 
864     /* XSCOM region for PSI registers */
865     pnv_xscom_region_init(&psi->xscom_regs, OBJECT(dev), &pnv_psi_p9_xscom_ops,
866                 psi, "xscom-psi", PNV9_XSCOM_PSIHB_SIZE);
867 
868     /* MMIO region for PSI registers */
869     memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi,
870                           "psihb", PNV9_PSIHB_SIZE);
871 
872     pnv_psi_realize(dev, errp);
873 }
874 
875 static void pnv_psi_power9_class_init(ObjectClass *klass, void *data)
876 {
877     DeviceClass *dc = DEVICE_CLASS(klass);
878     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
879     XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass);
880     static const char compat[] = "ibm,power9-psihb-x\0ibm,psihb-x";
881 
882     dc->desc    = "PowerNV PSI Controller POWER9";
883     dc->realize = pnv_psi_power9_realize;
884     dc->reset   = pnv_psi_power9_reset;
885 
886     ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE;
887     ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE;
888     ppc->bar_mask   = PSIHB9_BAR_MASK;
889     ppc->irq_set    = pnv_psi_power9_irq_set;
890     ppc->compat     = compat;
891     ppc->compat_size = sizeof(compat);
892 
893     xfc->notify      = pnv_psi_notify;
894 }
895 
896 static const TypeInfo pnv_psi_power9_info = {
897     .name          = TYPE_PNV9_PSI,
898     .parent        = TYPE_PNV_PSI,
899     .instance_size = sizeof(Pnv9Psi),
900     .instance_init = pnv_psi_power9_instance_init,
901     .class_init    = pnv_psi_power9_class_init,
902     .interfaces = (InterfaceInfo[]) {
903             { TYPE_XIVE_NOTIFIER },
904             { },
905     },
906 };
907 
908 static void pnv_psi_power10_class_init(ObjectClass *klass, void *data)
909 {
910     DeviceClass *dc = DEVICE_CLASS(klass);
911     PnvPsiClass *ppc = PNV_PSI_CLASS(klass);
912     static const char compat[] = "ibm,power10-psihb-x\0ibm,psihb-x";
913 
914     dc->desc    = "PowerNV PSI Controller POWER10";
915 
916     ppc->xscom_pcba = PNV10_XSCOM_PSIHB_BASE;
917     ppc->xscom_size = PNV10_XSCOM_PSIHB_SIZE;
918     ppc->compat     = compat;
919     ppc->compat_size = sizeof(compat);
920 }
921 
922 static const TypeInfo pnv_psi_power10_info = {
923     .name          = TYPE_PNV10_PSI,
924     .parent        = TYPE_PNV9_PSI,
925     .class_init    = pnv_psi_power10_class_init,
926 };
927 
928 static void pnv_psi_class_init(ObjectClass *klass, void *data)
929 {
930     DeviceClass *dc = DEVICE_CLASS(klass);
931     PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass);
932 
933     xdc->dt_xscom = pnv_psi_dt_xscom;
934 
935     dc->desc = "PowerNV PSI Controller";
936     device_class_set_props(dc, pnv_psi_properties);
937     dc->reset = pnv_psi_reset;
938 }
939 
940 static const TypeInfo pnv_psi_info = {
941     .name          = TYPE_PNV_PSI,
942     .parent        = TYPE_DEVICE,
943     .instance_size = sizeof(PnvPsi),
944     .class_init    = pnv_psi_class_init,
945     .class_size    = sizeof(PnvPsiClass),
946     .abstract      = true,
947     .interfaces    = (InterfaceInfo[]) {
948         { TYPE_PNV_XSCOM_INTERFACE },
949         { }
950     }
951 };
952 
953 static void pnv_psi_register_types(void)
954 {
955     type_register_static(&pnv_psi_info);
956     type_register_static(&pnv_psi_power8_info);
957     type_register_static(&pnv_psi_power9_info);
958     type_register_static(&pnv_psi_power10_info);
959 }
960 
961 type_init(pnv_psi_register_types);
962 
963 void pnv_psi_pic_print_info(Pnv9Psi *psi9, Monitor *mon)
964 {
965     PnvPsi *psi = PNV_PSI(psi9);
966 
967     uint32_t offset =
968         (psi->regs[PSIHB_REG(PSIHB9_IVT_OFFSET)] >> PSIHB9_IVT_OFF_SHIFT);
969 
970     monitor_printf(mon, "PSIHB Source %08x .. %08x\n",
971                   offset, offset + psi9->source.nr_irqs - 1);
972     xive_source_pic_print_info(&psi9->source, offset, mon);
973 }
974