1 /* 2 * QEMU PowerPC PowerNV Emulation of a few OCC related registers 3 * 4 * Copyright (c) 2015-2017, IBM Corporation. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License, version 2, as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #include "qemu/osdep.h" 20 #include "target/ppc/cpu.h" 21 #include "qapi/error.h" 22 #include "qemu/log.h" 23 #include "qemu/module.h" 24 #include "hw/irq.h" 25 #include "hw/qdev-properties.h" 26 #include "hw/ppc/pnv.h" 27 #include "hw/ppc/pnv_chip.h" 28 #include "hw/ppc/pnv_xscom.h" 29 #include "hw/ppc/pnv_occ.h" 30 31 #define P8_HOMER_OPAL_DATA_OFFSET 0x1F8000 32 #define P9_HOMER_OPAL_DATA_OFFSET 0x0E2000 33 34 #define OCB_OCI_OCCMISC 0x4020 35 #define OCB_OCI_OCCMISC_AND 0x4021 36 #define OCB_OCI_OCCMISC_OR 0x4022 37 #define OCCMISC_PSI_IRQ PPC_BIT(0) 38 #define OCCMISC_IRQ_SHMEM PPC_BIT(3) 39 40 /* OCC sensors */ 41 #define OCC_SENSOR_DATA_BLOCK_OFFSET 0x0000 42 #define OCC_SENSOR_DATA_VALID 0x0001 43 #define OCC_SENSOR_DATA_VERSION 0x0002 44 #define OCC_SENSOR_DATA_READING_VERSION 0x0004 45 #define OCC_SENSOR_DATA_NR_SENSORS 0x0008 46 #define OCC_SENSOR_DATA_NAMES_OFFSET 0x0010 47 #define OCC_SENSOR_DATA_READING_PING_OFFSET 0x0014 48 #define OCC_SENSOR_DATA_READING_PONG_OFFSET 0x000c 49 #define OCC_SENSOR_DATA_NAME_LENGTH 0x000d 50 #define OCC_SENSOR_NAME_STRUCTURE_TYPE 0x0023 51 #define OCC_SENSOR_LOC_CORE 0x0022 52 #define OCC_SENSOR_LOC_GPU 0x0020 53 #define OCC_SENSOR_TYPE_POWER 0x0003 54 #define OCC_SENSOR_NAME 0x0005 55 #define HWMON_SENSORS_MASK 0x001e 56 57 static void pnv_occ_set_misc(PnvOCC *occ, uint64_t val) 58 { 59 val &= PPC_BITMASK(0, 18); /* Mask out unimplemented bits */ 60 61 occ->occmisc = val; 62 63 /* 64 * OCCMISC IRQ bit triggers the interrupt on a 0->1 edge, but not clear 65 * how that is handled in PSI so it is level-triggered here, which is not 66 * really correct (but skiboot is okay with it). 67 */ 68 qemu_set_irq(occ->psi_irq, !!(val & OCCMISC_PSI_IRQ)); 69 } 70 71 static void pnv_occ_raise_msg_irq(PnvOCC *occ) 72 { 73 pnv_occ_set_misc(occ, occ->occmisc | OCCMISC_PSI_IRQ | OCCMISC_IRQ_SHMEM); 74 } 75 76 static uint64_t pnv_occ_power8_xscom_read(void *opaque, hwaddr addr, 77 unsigned size) 78 { 79 PnvOCC *occ = PNV_OCC(opaque); 80 uint32_t offset = addr >> 3; 81 uint64_t val = 0; 82 83 switch (offset) { 84 case OCB_OCI_OCCMISC: 85 val = occ->occmisc; 86 break; 87 default: 88 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 89 HWADDR_PRIx "\n", addr >> 3); 90 } 91 return val; 92 } 93 94 static void pnv_occ_power8_xscom_write(void *opaque, hwaddr addr, 95 uint64_t val, unsigned size) 96 { 97 PnvOCC *occ = PNV_OCC(opaque); 98 uint32_t offset = addr >> 3; 99 100 switch (offset) { 101 case OCB_OCI_OCCMISC_AND: 102 pnv_occ_set_misc(occ, occ->occmisc & val); 103 break; 104 case OCB_OCI_OCCMISC_OR: 105 pnv_occ_set_misc(occ, occ->occmisc | val); 106 break; 107 case OCB_OCI_OCCMISC: 108 pnv_occ_set_misc(occ, val); 109 break; 110 default: 111 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 112 HWADDR_PRIx "\n", addr >> 3); 113 } 114 } 115 116 static uint64_t pnv_occ_common_area_read(void *opaque, hwaddr addr, 117 unsigned width) 118 { 119 switch (addr) { 120 /* 121 * occ-sensor sanity check that asserts the sensor 122 * header block 123 */ 124 case OCC_SENSOR_DATA_BLOCK_OFFSET: 125 case OCC_SENSOR_DATA_VALID: 126 case OCC_SENSOR_DATA_VERSION: 127 case OCC_SENSOR_DATA_READING_VERSION: 128 case OCC_SENSOR_DATA_NR_SENSORS: 129 case OCC_SENSOR_DATA_NAMES_OFFSET: 130 case OCC_SENSOR_DATA_READING_PING_OFFSET: 131 case OCC_SENSOR_DATA_READING_PONG_OFFSET: 132 case OCC_SENSOR_NAME_STRUCTURE_TYPE: 133 return 1; 134 case OCC_SENSOR_DATA_NAME_LENGTH: 135 return 0x30; 136 case OCC_SENSOR_LOC_CORE: 137 return 0x0040; 138 case OCC_SENSOR_TYPE_POWER: 139 return 0x0080; 140 case OCC_SENSOR_NAME: 141 return 0x1000; 142 case HWMON_SENSORS_MASK: 143 case OCC_SENSOR_LOC_GPU: 144 return 0x8e00; 145 } 146 return 0; 147 } 148 149 static void pnv_occ_common_area_write(void *opaque, hwaddr addr, 150 uint64_t val, unsigned width) 151 { 152 /* callback function defined to occ common area write */ 153 return; 154 } 155 156 static const MemoryRegionOps pnv_occ_power8_xscom_ops = { 157 .read = pnv_occ_power8_xscom_read, 158 .write = pnv_occ_power8_xscom_write, 159 .valid.min_access_size = 8, 160 .valid.max_access_size = 8, 161 .impl.min_access_size = 8, 162 .impl.max_access_size = 8, 163 .endianness = DEVICE_BIG_ENDIAN, 164 }; 165 166 const MemoryRegionOps pnv_occ_sram_ops = { 167 .read = pnv_occ_common_area_read, 168 .write = pnv_occ_common_area_write, 169 .valid.min_access_size = 1, 170 .valid.max_access_size = 8, 171 .impl.min_access_size = 1, 172 .impl.max_access_size = 8, 173 .endianness = DEVICE_BIG_ENDIAN, 174 }; 175 176 static void pnv_occ_power8_class_init(ObjectClass *klass, void *data) 177 { 178 PnvOCCClass *poc = PNV_OCC_CLASS(klass); 179 DeviceClass *dc = DEVICE_CLASS(klass); 180 181 dc->desc = "PowerNV OCC Controller (POWER8)"; 182 poc->opal_shared_memory_offset = P8_HOMER_OPAL_DATA_OFFSET; 183 poc->opal_shared_memory_version = 0x02; 184 poc->xscom_size = PNV_XSCOM_OCC_SIZE; 185 poc->xscom_ops = &pnv_occ_power8_xscom_ops; 186 } 187 188 static const TypeInfo pnv_occ_power8_type_info = { 189 .name = TYPE_PNV8_OCC, 190 .parent = TYPE_PNV_OCC, 191 .instance_size = sizeof(PnvOCC), 192 .class_init = pnv_occ_power8_class_init, 193 }; 194 195 #define P9_OCB_OCI_OCCMISC 0x6080 196 #define P9_OCB_OCI_OCCMISC_CLEAR 0x6081 197 #define P9_OCB_OCI_OCCMISC_OR 0x6082 198 199 200 static uint64_t pnv_occ_power9_xscom_read(void *opaque, hwaddr addr, 201 unsigned size) 202 { 203 PnvOCC *occ = PNV_OCC(opaque); 204 uint32_t offset = addr >> 3; 205 uint64_t val = 0; 206 207 switch (offset) { 208 case P9_OCB_OCI_OCCMISC: 209 val = occ->occmisc; 210 break; 211 default: 212 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 213 HWADDR_PRIx "\n", addr >> 3); 214 } 215 return val; 216 } 217 218 static void pnv_occ_power9_xscom_write(void *opaque, hwaddr addr, 219 uint64_t val, unsigned size) 220 { 221 PnvOCC *occ = PNV_OCC(opaque); 222 uint32_t offset = addr >> 3; 223 224 switch (offset) { 225 case P9_OCB_OCI_OCCMISC_CLEAR: 226 pnv_occ_set_misc(occ, 0); 227 break; 228 case P9_OCB_OCI_OCCMISC_OR: 229 pnv_occ_set_misc(occ, occ->occmisc | val); 230 break; 231 case P9_OCB_OCI_OCCMISC: 232 pnv_occ_set_misc(occ, val); 233 break; 234 default: 235 qemu_log_mask(LOG_UNIMP, "OCC Unimplemented register: Ox%" 236 HWADDR_PRIx "\n", addr >> 3); 237 } 238 } 239 240 static const MemoryRegionOps pnv_occ_power9_xscom_ops = { 241 .read = pnv_occ_power9_xscom_read, 242 .write = pnv_occ_power9_xscom_write, 243 .valid.min_access_size = 8, 244 .valid.max_access_size = 8, 245 .impl.min_access_size = 8, 246 .impl.max_access_size = 8, 247 .endianness = DEVICE_BIG_ENDIAN, 248 }; 249 250 static void pnv_occ_power9_class_init(ObjectClass *klass, void *data) 251 { 252 PnvOCCClass *poc = PNV_OCC_CLASS(klass); 253 DeviceClass *dc = DEVICE_CLASS(klass); 254 255 dc->desc = "PowerNV OCC Controller (POWER9)"; 256 poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET; 257 poc->opal_shared_memory_version = 0x90; 258 poc->xscom_size = PNV9_XSCOM_OCC_SIZE; 259 poc->xscom_ops = &pnv_occ_power9_xscom_ops; 260 assert(!dc->user_creatable); 261 } 262 263 static const TypeInfo pnv_occ_power9_type_info = { 264 .name = TYPE_PNV9_OCC, 265 .parent = TYPE_PNV_OCC, 266 .instance_size = sizeof(PnvOCC), 267 .class_init = pnv_occ_power9_class_init, 268 }; 269 270 static void pnv_occ_power10_class_init(ObjectClass *klass, void *data) 271 { 272 PnvOCCClass *poc = PNV_OCC_CLASS(klass); 273 DeviceClass *dc = DEVICE_CLASS(klass); 274 275 dc->desc = "PowerNV OCC Controller (POWER10)"; 276 poc->opal_shared_memory_offset = P9_HOMER_OPAL_DATA_OFFSET; 277 poc->opal_shared_memory_version = 0xA0; 278 poc->xscom_size = PNV9_XSCOM_OCC_SIZE; 279 poc->xscom_ops = &pnv_occ_power9_xscom_ops; 280 assert(!dc->user_creatable); 281 } 282 283 static const TypeInfo pnv_occ_power10_type_info = { 284 .name = TYPE_PNV10_OCC, 285 .parent = TYPE_PNV_OCC, 286 .class_init = pnv_occ_power10_class_init, 287 }; 288 289 static bool occ_init_homer_memory(PnvOCC *occ, Error **errp); 290 static bool occ_model_tick(PnvOCC *occ); 291 292 /* Relatively arbitrary */ 293 #define OCC_POLL_MS 100 294 295 static void occ_state_machine_timer(void *opaque) 296 { 297 PnvOCC *occ = opaque; 298 uint64_t next = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + OCC_POLL_MS; 299 300 if (occ_model_tick(occ)) { 301 timer_mod(&occ->state_machine_timer, next); 302 } 303 } 304 305 static void pnv_occ_realize(DeviceState *dev, Error **errp) 306 { 307 PnvOCC *occ = PNV_OCC(dev); 308 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 309 PnvHomer *homer = occ->homer; 310 311 assert(homer); 312 313 if (!occ_init_homer_memory(occ, errp)) { 314 return; 315 } 316 317 occ->occmisc = 0; 318 319 /* XScom region for OCC registers */ 320 pnv_xscom_region_init(&occ->xscom_regs, OBJECT(dev), poc->xscom_ops, 321 occ, "xscom-occ", poc->xscom_size); 322 323 /* OCC common area mmio region for OCC SRAM registers */ 324 memory_region_init_io(&occ->sram_regs, OBJECT(dev), &pnv_occ_sram_ops, 325 occ, "occ-common-area", 326 PNV_OCC_SENSOR_DATA_BLOCK_SIZE); 327 328 qdev_init_gpio_out(dev, &occ->psi_irq, 1); 329 330 timer_init_ms(&occ->state_machine_timer, QEMU_CLOCK_VIRTUAL, 331 occ_state_machine_timer, occ); 332 timer_mod(&occ->state_machine_timer, OCC_POLL_MS); 333 } 334 335 static const Property pnv_occ_properties[] = { 336 DEFINE_PROP_LINK("homer", PnvOCC, homer, TYPE_PNV_HOMER, PnvHomer *), 337 }; 338 339 static void pnv_occ_class_init(ObjectClass *klass, void *data) 340 { 341 DeviceClass *dc = DEVICE_CLASS(klass); 342 343 dc->realize = pnv_occ_realize; 344 device_class_set_props(dc, pnv_occ_properties); 345 dc->user_creatable = false; 346 } 347 348 static const TypeInfo pnv_occ_type_info = { 349 .name = TYPE_PNV_OCC, 350 .parent = TYPE_DEVICE, 351 .instance_size = sizeof(PnvOCC), 352 .class_init = pnv_occ_class_init, 353 .class_size = sizeof(PnvOCCClass), 354 .abstract = true, 355 }; 356 357 static void pnv_occ_register_types(void) 358 { 359 type_register_static(&pnv_occ_type_info); 360 type_register_static(&pnv_occ_power8_type_info); 361 type_register_static(&pnv_occ_power9_type_info); 362 type_register_static(&pnv_occ_power10_type_info); 363 } 364 365 type_init(pnv_occ_register_types); 366 367 /* From skiboot/hw/occ.c with tab to space conversion */ 368 /* OCC Communication Area for PStates */ 369 370 #define OPAL_DYNAMIC_DATA_OFFSET 0x0B80 371 /* relative to HOMER_OPAL_DATA_OFFSET */ 372 373 #define MAX_PSTATES 256 374 #define MAX_P8_CORES 12 375 #define MAX_P9_CORES 24 376 #define MAX_P10_CORES 32 377 378 #define MAX_OPAL_CMD_DATA_LENGTH 4090 379 #define MAX_OCC_RSP_DATA_LENGTH 8698 380 381 #define P8_PIR_CORE_MASK 0xFFF8 382 #define P9_PIR_QUAD_MASK 0xFFF0 383 #define P10_PIR_CHIP_MASK 0x0000 384 #define FREQ_MAX_IN_DOMAIN 0 385 #define FREQ_MOST_RECENTLY_SET 1 386 387 #define u8 uint8_t 388 #define s8 int8_t 389 #define u16 uint16_t 390 #define s16 int16_t 391 #define u32 uint32_t 392 #define s32 int32_t 393 #define u64 uint64_t 394 #define s64 int64_t 395 #define __be16 uint16_t 396 #define __be32 uint32_t 397 #define __packed QEMU_PACKED 398 399 /** 400 * OCC-OPAL Shared Memory Region 401 * 402 * Reference document : 403 * https://github.com/open-power/docs/blob/master/occ/OCC_OpenPwr_FW_Interfaces.pdf 404 * 405 * Supported layout versions: 406 * - 0x01, 0x02 : P8 407 * https://github.com/open-power/occ/blob/master_p8/src/occ/proc/proc_pstate.h 408 * 409 * - 0x90 : P9 410 * https://github.com/open-power/occ/blob/master/src/occ_405/proc/proc_pstate.h 411 * In 0x90 the data is separated into :- 412 * -- Static Data (struct occ_pstate_table): Data is written once by OCC 413 * -- Dynamic Data (struct occ_dynamic_data): Data is updated at runtime 414 * 415 * struct occ_pstate_table - Pstate table layout 416 * @valid: Indicates if data is valid 417 * @version: Layout version [Major/Minor] 418 * @v2.throttle: Reason for limiting the max pstate 419 * @v9.occ_role: OCC role (Master/Slave) 420 * @v#.pstate_min: Minimum pstate ever allowed 421 * @v#.pstate_nom: Nominal pstate 422 * @v#.pstate_turbo: Maximum turbo pstate 423 * @v#.pstate_ultra_turbo: Maximum ultra turbo pstate and the maximum 424 * pstate ever allowed 425 * @v#.pstates: Pstate-id and frequency list from Pmax to Pmin 426 * @v#.pstates.id: Pstate-id 427 * @v#.pstates.flags: Pstate-flag(reserved) 428 * @v2.pstates.vdd: Voltage Identifier 429 * @v2.pstates.vcs: Voltage Identifier 430 * @v#.pstates.freq_khz: Frequency in KHz 431 * @v#.core_max[1..N]: Max pstate with N active cores 432 * @spare/reserved/pad: Unused data 433 */ 434 struct occ_pstate_table { 435 u8 valid; 436 u8 version; 437 union __packed { 438 struct __packed { /* Version 0x01 and 0x02 */ 439 u8 throttle; 440 s8 pstate_min; 441 s8 pstate_nom; 442 s8 pstate_turbo; 443 s8 pstate_ultra_turbo; 444 u8 spare; 445 u64 reserved; 446 struct __packed { 447 s8 id; 448 u8 flags; 449 u8 vdd; 450 u8 vcs; 451 __be32 freq_khz; 452 } pstates[MAX_PSTATES]; 453 s8 core_max[MAX_P8_CORES]; 454 u8 pad[100]; 455 } v2; 456 struct __packed { /* Version 0x90 */ 457 u8 occ_role; 458 u8 pstate_min; 459 u8 pstate_nom; 460 u8 pstate_turbo; 461 u8 pstate_ultra_turbo; 462 u8 spare; 463 u64 reserved1; 464 u64 reserved2; 465 struct __packed { 466 u8 id; 467 u8 flags; 468 u16 reserved; 469 __be32 freq_khz; 470 } pstates[MAX_PSTATES]; 471 u8 core_max[MAX_P9_CORES]; 472 u8 pad[56]; 473 } v9; 474 struct __packed { /* Version 0xA0 */ 475 u8 occ_role; 476 u8 pstate_min; 477 u8 pstate_fixed_freq; 478 u8 pstate_base; 479 u8 pstate_ultra_turbo; 480 u8 pstate_fmax; 481 u8 minor; 482 u8 pstate_bottom_throttle; 483 u8 spare; 484 u8 spare1; 485 u32 reserved_32; 486 u64 reserved_64; 487 struct __packed { 488 u8 id; 489 u8 valid; 490 u16 reserved; 491 __be32 freq_khz; 492 } pstates[MAX_PSTATES]; 493 u8 core_max[MAX_P10_CORES]; 494 u8 pad[48]; 495 } v10; 496 }; 497 } __packed; 498 499 /** 500 * OPAL-OCC Command Response Interface 501 * 502 * OPAL-OCC Command Buffer 503 * 504 * --------------------------------------------------------------------- 505 * | OPAL | Cmd | OPAL | | Cmd Data | Cmd Data | OPAL | 506 * | Cmd | Request | OCC | Reserved | Length | Length | Cmd | 507 * | Flags | ID | Cmd | | (MSB) | (LSB) | Data... | 508 * --------------------------------------------------------------------- 509 * | ….OPAL Command Data up to max of Cmd Data Length 4090 bytes | 510 * | | 511 * --------------------------------------------------------------------- 512 * 513 * OPAL Command Flag 514 * 515 * ----------------------------------------------------------------- 516 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | 517 * | (msb) | | | | | | | (lsb) | 518 * ----------------------------------------------------------------- 519 * |Cmd | | | | | | | | 520 * |Ready | | | | | | | | 521 * ----------------------------------------------------------------- 522 * 523 * struct opal_command_buffer - Defines the layout of OPAL command buffer 524 * @flag: Provides general status of the command 525 * @request_id: Token to identify request 526 * @cmd: Command sent 527 * @data_size: Command data length 528 * @data: Command specific data 529 * @spare: Unused byte 530 */ 531 struct opal_command_buffer { 532 u8 flag; 533 u8 request_id; 534 u8 cmd; 535 u8 spare; 536 __be16 data_size; 537 u8 data[MAX_OPAL_CMD_DATA_LENGTH]; 538 } __packed; 539 540 /** 541 * OPAL-OCC Response Buffer 542 * 543 * --------------------------------------------------------------------- 544 * | OCC | Cmd | OPAL | Response | Rsp Data | Rsp Data | OPAL | 545 * | Rsp | Request | OCC | Status | Length | Length | Rsp | 546 * | Flags | ID | Cmd | | (MSB) | (LSB) | Data... | 547 * --------------------------------------------------------------------- 548 * | ….OPAL Response Data up to max of Rsp Data Length 8698 bytes | 549 * | | 550 * --------------------------------------------------------------------- 551 * 552 * OCC Response Flag 553 * 554 * ----------------------------------------------------------------- 555 * | Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | 556 * | (msb) | | | | | | | (lsb) | 557 * ----------------------------------------------------------------- 558 * | | | | | | |OCC in | Rsp | 559 * | | | | | | |progress|Ready | 560 * ----------------------------------------------------------------- 561 * 562 * struct occ_response_buffer - Defines the layout of OCC response buffer 563 * @flag: Provides general status of the response 564 * @request_id: Token to identify request 565 * @cmd: Command requested 566 * @status: Indicates success/failure status of 567 * the command 568 * @data_size: Response data length 569 * @data: Response specific data 570 */ 571 struct occ_response_buffer { 572 u8 flag; 573 u8 request_id; 574 u8 cmd; 575 u8 status; 576 __be16 data_size; 577 u8 data[MAX_OCC_RSP_DATA_LENGTH]; 578 } __packed; 579 580 /** 581 * OCC-OPAL Shared Memory Interface Dynamic Data Vx90 582 * 583 * struct occ_dynamic_data - Contains runtime attributes 584 * @occ_state: Current state of OCC 585 * @major_version: Major version number 586 * @minor_version: Minor version number (backwards compatible) 587 * Version 1 indicates GPU presence populated 588 * @gpus_present: Bitmask of GPUs present (on systems where GPU 589 * presence is detected through APSS) 590 * @cpu_throttle: Reason for limiting the max pstate 591 * @mem_throttle: Reason for throttling memory 592 * @quick_pwr_drop: Indicates if QPD is asserted 593 * @pwr_shifting_ratio: Indicates the current percentage of power to 594 * take away from the CPU vs GPU when shifting 595 * power to maintain a power cap. Value of 100 596 * means take all power from CPU. 597 * @pwr_cap_type: Indicates type of power cap in effect 598 * @hard_min_pwr_cap: Hard minimum system power cap in Watts. 599 * Guaranteed unless hardware failure 600 * @max_pwr_cap: Maximum allowed system power cap in Watts 601 * @cur_pwr_cap: Current system power cap 602 * @soft_min_pwr_cap: Soft powercap minimum. OCC may or may not be 603 * able to maintain this 604 * @spare/reserved: Unused data 605 * @cmd: Opal Command Buffer 606 * @rsp: OCC Response Buffer 607 */ 608 struct occ_dynamic_data { 609 u8 occ_state; 610 u8 major_version; 611 u8 minor_version; 612 u8 gpus_present; 613 union __packed { 614 struct __packed { /* Version 0x90 */ 615 u8 spare1; 616 } v9; 617 struct __packed { /* Version 0xA0 */ 618 u8 wof_enabled; 619 } v10; 620 }; 621 u8 cpu_throttle; 622 u8 mem_throttle; 623 u8 quick_pwr_drop; 624 u8 pwr_shifting_ratio; 625 u8 pwr_cap_type; 626 __be16 hard_min_pwr_cap; 627 __be16 max_pwr_cap; 628 __be16 cur_pwr_cap; 629 __be16 soft_min_pwr_cap; 630 u8 pad[110]; 631 struct opal_command_buffer cmd; 632 struct occ_response_buffer rsp; 633 } __packed; 634 635 enum occ_response_status { 636 OCC_RSP_SUCCESS = 0x00, 637 OCC_RSP_INVALID_COMMAND = 0x11, 638 OCC_RSP_INVALID_CMD_DATA_LENGTH = 0x12, 639 OCC_RSP_INVALID_DATA = 0x13, 640 OCC_RSP_INTERNAL_ERROR = 0x15, 641 }; 642 643 #define OCC_ROLE_SLAVE 0x00 644 #define OCC_ROLE_MASTER 0x01 645 646 #define OCC_FLAG_RSP_READY 0x01 647 #define OCC_FLAG_CMD_IN_PROGRESS 0x02 648 #define OPAL_FLAG_CMD_READY 0x80 649 650 #define PCAP_MAX_POWER_W 100 651 #define PCAP_SOFT_MIN_POWER_W 20 652 #define PCAP_HARD_MIN_POWER_W 10 653 654 static bool occ_write_static_data(PnvOCC *occ, 655 struct occ_pstate_table *static_data, 656 Error **errp) 657 { 658 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 659 PnvHomer *homer = occ->homer; 660 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; 661 MemTxResult ret; 662 663 ret = address_space_write(&address_space_memory, static_addr, 664 MEMTXATTRS_UNSPECIFIED, static_data, 665 sizeof(*static_data)); 666 if (ret != MEMTX_OK) { 667 error_setg(errp, "OCC: cannot write OCC-OPAL static data"); 668 return false; 669 } 670 671 return true; 672 } 673 674 static bool occ_read_dynamic_data(PnvOCC *occ, 675 struct occ_dynamic_data *dynamic_data, 676 Error **errp) 677 { 678 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 679 PnvHomer *homer = occ->homer; 680 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; 681 hwaddr dynamic_addr = static_addr + OPAL_DYNAMIC_DATA_OFFSET; 682 MemTxResult ret; 683 684 ret = address_space_read(&address_space_memory, dynamic_addr, 685 MEMTXATTRS_UNSPECIFIED, dynamic_data, 686 sizeof(*dynamic_data)); 687 if (ret != MEMTX_OK) { 688 error_setg(errp, "OCC: cannot read OCC-OPAL dynamic data"); 689 return false; 690 } 691 692 return true; 693 } 694 695 static bool occ_write_dynamic_data(PnvOCC *occ, 696 struct occ_dynamic_data *dynamic_data, 697 Error **errp) 698 { 699 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 700 PnvHomer *homer = occ->homer; 701 hwaddr static_addr = homer->base + poc->opal_shared_memory_offset; 702 hwaddr dynamic_addr = static_addr + OPAL_DYNAMIC_DATA_OFFSET; 703 MemTxResult ret; 704 705 ret = address_space_write(&address_space_memory, dynamic_addr, 706 MEMTXATTRS_UNSPECIFIED, dynamic_data, 707 sizeof(*dynamic_data)); 708 if (ret != MEMTX_OK) { 709 error_setg(errp, "OCC: cannot write OCC-OPAL dynamic data"); 710 return false; 711 } 712 713 return true; 714 } 715 716 static bool occ_opal_send_response(PnvOCC *occ, 717 struct occ_dynamic_data *dynamic_data, 718 enum occ_response_status status, 719 uint8_t *data, uint16_t datalen) 720 { 721 struct opal_command_buffer *cmd = &dynamic_data->cmd; 722 struct occ_response_buffer *rsp = &dynamic_data->rsp; 723 724 rsp->request_id = cmd->request_id; 725 rsp->cmd = cmd->cmd; 726 rsp->status = status; 727 rsp->data_size = cpu_to_be16(datalen); 728 if (datalen) { 729 memcpy(rsp->data, data, datalen); 730 } 731 if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) { 732 return false; 733 } 734 /* Would be a memory barrier here */ 735 rsp->flag = OCC_FLAG_RSP_READY; 736 cmd->flag = 0; 737 if (!occ_write_dynamic_data(occ, dynamic_data, NULL)) { 738 return false; 739 } 740 741 pnv_occ_raise_msg_irq(occ); 742 743 return true; 744 } 745 746 /* Returns error status */ 747 static bool occ_opal_process_command(PnvOCC *occ, 748 struct occ_dynamic_data *dynamic_data) 749 { 750 struct opal_command_buffer *cmd = &dynamic_data->cmd; 751 struct occ_response_buffer *rsp = &dynamic_data->rsp; 752 753 if (rsp->flag == 0) { 754 /* Spend one "tick" in the in-progress state */ 755 rsp->flag = OCC_FLAG_CMD_IN_PROGRESS; 756 return occ_write_dynamic_data(occ, dynamic_data, NULL); 757 } else if (rsp->flag != OCC_FLAG_CMD_IN_PROGRESS) { 758 return occ_opal_send_response(occ, dynamic_data, 759 OCC_RSP_INTERNAL_ERROR, 760 NULL, 0); 761 } 762 763 switch (cmd->cmd) { 764 case 0xD1: { /* SET_POWER_CAP */ 765 uint16_t data; 766 if (be16_to_cpu(cmd->data_size) != 2) { 767 return occ_opal_send_response(occ, dynamic_data, 768 OCC_RSP_INVALID_CMD_DATA_LENGTH, 769 (uint8_t *)&dynamic_data->cur_pwr_cap, 770 2); 771 } 772 data = be16_to_cpu(*(uint16_t *)cmd->data); 773 if (data == 0) { /* clear power cap */ 774 dynamic_data->pwr_cap_type = 0x00; /* none */ 775 data = PCAP_MAX_POWER_W; 776 } else { 777 dynamic_data->pwr_cap_type = 0x02; /* user set in-band */ 778 if (data < PCAP_HARD_MIN_POWER_W) { 779 data = PCAP_HARD_MIN_POWER_W; 780 } else if (data > PCAP_MAX_POWER_W) { 781 data = PCAP_MAX_POWER_W; 782 } 783 } 784 dynamic_data->cur_pwr_cap = cpu_to_be16(data); 785 return occ_opal_send_response(occ, dynamic_data, 786 OCC_RSP_SUCCESS, 787 (uint8_t *)&dynamic_data->cur_pwr_cap, 2); 788 } 789 790 default: 791 return occ_opal_send_response(occ, dynamic_data, 792 OCC_RSP_INVALID_COMMAND, 793 NULL, 0); 794 } 795 g_assert_not_reached(); 796 } 797 798 static bool occ_model_tick(PnvOCC *occ) 799 { 800 struct occ_dynamic_data dynamic_data; 801 802 if (!occ_read_dynamic_data(occ, &dynamic_data, NULL)) { 803 /* Can't move OCC state field to safe because we can't map it! */ 804 qemu_log("OCC: failed to read HOMER data, shutting down OCC\n"); 805 return false; 806 } 807 if (dynamic_data.cmd.flag == OPAL_FLAG_CMD_READY) { 808 if (!occ_opal_process_command(occ, &dynamic_data)) { 809 qemu_log("OCC: failed to write HOMER data, shutting down OCC\n"); 810 return false; 811 } 812 } 813 814 return true; 815 } 816 817 static bool occ_init_homer_memory(PnvOCC *occ, Error **errp) 818 { 819 PnvOCCClass *poc = PNV_OCC_GET_CLASS(occ); 820 PnvHomer *homer = occ->homer; 821 PnvChip *chip = homer->chip; 822 struct occ_pstate_table static_data; 823 struct occ_dynamic_data dynamic_data; 824 int i; 825 826 memset(&static_data, 0, sizeof(static_data)); 827 static_data.valid = 1; 828 static_data.version = poc->opal_shared_memory_version; 829 switch (poc->opal_shared_memory_version) { 830 case 0x02: 831 static_data.v2.throttle = 0; 832 static_data.v2.pstate_min = -2; 833 static_data.v2.pstate_nom = -1; 834 static_data.v2.pstate_turbo = -1; 835 static_data.v2.pstate_ultra_turbo = 0; 836 static_data.v2.pstates[0].id = 0; 837 static_data.v2.pstates[1].freq_khz = cpu_to_be32(4000000); 838 static_data.v2.pstates[1].id = -1; 839 static_data.v2.pstates[1].freq_khz = cpu_to_be32(3000000); 840 static_data.v2.pstates[2].id = -2; 841 static_data.v2.pstates[2].freq_khz = cpu_to_be32(2000000); 842 for (i = 0; i < chip->nr_cores; i++) { 843 static_data.v2.core_max[i] = 1; 844 } 845 break; 846 case 0x90: 847 if (chip->chip_id == 0) { 848 static_data.v9.occ_role = OCC_ROLE_MASTER; 849 } else { 850 static_data.v9.occ_role = OCC_ROLE_SLAVE; 851 } 852 static_data.v9.pstate_min = 2; 853 static_data.v9.pstate_nom = 1; 854 static_data.v9.pstate_turbo = 1; 855 static_data.v9.pstate_ultra_turbo = 0; 856 static_data.v9.pstates[0].id = 0; 857 static_data.v9.pstates[0].freq_khz = cpu_to_be32(4000000); 858 static_data.v9.pstates[1].id = 1; 859 static_data.v9.pstates[1].freq_khz = cpu_to_be32(3000000); 860 static_data.v9.pstates[2].id = 2; 861 static_data.v9.pstates[2].freq_khz = cpu_to_be32(2000000); 862 for (i = 0; i < chip->nr_cores; i++) { 863 static_data.v9.core_max[i] = 1; 864 } 865 break; 866 case 0xA0: 867 if (chip->chip_id == 0) { 868 static_data.v10.occ_role = OCC_ROLE_MASTER; 869 } else { 870 static_data.v10.occ_role = OCC_ROLE_SLAVE; 871 } 872 static_data.v10.pstate_min = 4; 873 static_data.v10.pstate_fixed_freq = 3; 874 static_data.v10.pstate_base = 2; 875 static_data.v10.pstate_ultra_turbo = 0; 876 static_data.v10.pstate_fmax = 1; 877 static_data.v10.minor = 0x01; 878 static_data.v10.pstates[0].valid = 1; 879 static_data.v10.pstates[0].id = 0; 880 static_data.v10.pstates[0].freq_khz = cpu_to_be32(4200000); 881 static_data.v10.pstates[1].valid = 1; 882 static_data.v10.pstates[1].id = 1; 883 static_data.v10.pstates[1].freq_khz = cpu_to_be32(4000000); 884 static_data.v10.pstates[2].valid = 1; 885 static_data.v10.pstates[2].id = 2; 886 static_data.v10.pstates[2].freq_khz = cpu_to_be32(3800000); 887 static_data.v10.pstates[3].valid = 1; 888 static_data.v10.pstates[3].id = 3; 889 static_data.v10.pstates[3].freq_khz = cpu_to_be32(3000000); 890 static_data.v10.pstates[4].valid = 1; 891 static_data.v10.pstates[4].id = 4; 892 static_data.v10.pstates[4].freq_khz = cpu_to_be32(2000000); 893 for (i = 0; i < chip->nr_cores; i++) { 894 static_data.v10.core_max[i] = 1; 895 } 896 break; 897 default: 898 g_assert_not_reached(); 899 } 900 if (!occ_write_static_data(occ, &static_data, errp)) { 901 return false; 902 } 903 904 memset(&dynamic_data, 0, sizeof(dynamic_data)); 905 dynamic_data.occ_state = 0x3; /* active */ 906 dynamic_data.major_version = 0x0; 907 dynamic_data.hard_min_pwr_cap = cpu_to_be16(PCAP_HARD_MIN_POWER_W); 908 dynamic_data.max_pwr_cap = cpu_to_be16(PCAP_MAX_POWER_W); 909 dynamic_data.cur_pwr_cap = cpu_to_be16(PCAP_MAX_POWER_W); 910 dynamic_data.soft_min_pwr_cap = cpu_to_be16(PCAP_SOFT_MIN_POWER_W); 911 switch (poc->opal_shared_memory_version) { 912 case 0xA0: 913 dynamic_data.minor_version = 0x1; 914 dynamic_data.v10.wof_enabled = 0x1; 915 break; 916 case 0x90: 917 dynamic_data.minor_version = 0x1; 918 break; 919 case 0x02: 920 dynamic_data.minor_version = 0x0; 921 break; 922 default: 923 g_assert_not_reached(); 924 } 925 if (!occ_write_dynamic_data(occ, &dynamic_data, errp)) { 926 return false; 927 } 928 929 return true; 930 } 931