1 /* 2 * QEMU PowerPC PowerNV LPC controller 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "target/ppc/cpu.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "hw/irq.h" 26 #include "hw/isa/isa.h" 27 #include "hw/qdev-properties.h" 28 #include "hw/ppc/pnv.h" 29 #include "hw/ppc/pnv_chip.h" 30 #include "hw/ppc/pnv_lpc.h" 31 #include "hw/ppc/pnv_xscom.h" 32 #include "hw/ppc/fdt.h" 33 34 #include <libfdt.h> 35 36 enum { 37 ECCB_CTL = 0, 38 ECCB_RESET = 1, 39 ECCB_STAT = 2, 40 ECCB_DATA = 3, 41 }; 42 43 /* OPB Master LS registers */ 44 #define OPB_MASTER_LS_ROUTE0 0x8 45 #define OPB_MASTER_LS_ROUTE1 0xC 46 #define OPB_MASTER_LS_IRQ_STAT 0x50 47 #define OPB_MASTER_IRQ_LPC 0x00000800 48 #define OPB_MASTER_LS_IRQ_MASK 0x54 49 #define OPB_MASTER_LS_IRQ_POL 0x58 50 #define OPB_MASTER_LS_IRQ_INPUT 0x5c 51 52 /* LPC HC registers */ 53 #define LPC_HC_FW_SEG_IDSEL 0x24 54 #define LPC_HC_FW_RD_ACC_SIZE 0x28 55 #define LPC_HC_FW_RD_1B 0x00000000 56 #define LPC_HC_FW_RD_2B 0x01000000 57 #define LPC_HC_FW_RD_4B 0x02000000 58 #define LPC_HC_FW_RD_16B 0x04000000 59 #define LPC_HC_FW_RD_128B 0x07000000 60 #define LPC_HC_IRQSER_CTRL 0x30 61 #define LPC_HC_IRQSER_EN 0x80000000 62 #define LPC_HC_IRQSER_QMODE 0x40000000 63 #define LPC_HC_IRQSER_START_MASK 0x03000000 64 #define LPC_HC_IRQSER_START_4CLK 0x00000000 65 #define LPC_HC_IRQSER_START_6CLK 0x01000000 66 #define LPC_HC_IRQSER_START_8CLK 0x02000000 67 #define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */ 68 #define LPC_HC_IRQSTAT 0x38 69 #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */ 70 #define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */ 71 #define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000 72 #define LPC_HC_IRQ_LRESET 0x00000400 73 #define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080 74 #define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040 75 #define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020 76 #define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010 77 #define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008 78 #define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004 79 #define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002 80 #define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001 81 #define LPC_HC_ERROR_ADDRESS 0x40 82 83 #define LPC_OPB_SIZE 0x100000000ull 84 85 #define ISA_IO_SIZE 0x00010000 86 #define ISA_MEM_SIZE 0x10000000 87 #define ISA_FW_SIZE 0x10000000 88 #define LPC_IO_OPB_ADDR 0xd0010000 89 #define LPC_IO_OPB_SIZE 0x00010000 90 #define LPC_MEM_OPB_ADDR 0xe0000000 91 #define LPC_MEM_OPB_SIZE 0x10000000 92 #define LPC_FW_OPB_ADDR 0xf0000000 93 #define LPC_FW_OPB_SIZE 0x10000000 94 95 #define LPC_OPB_REGS_OPB_ADDR 0xc0010000 96 #define LPC_OPB_REGS_OPB_SIZE 0x00000060 97 #define LPC_OPB_REGS_OPBA_ADDR 0xc0011000 98 #define LPC_OPB_REGS_OPBA_SIZE 0x00000008 99 #define LPC_HC_REGS_OPB_ADDR 0xc0012000 100 #define LPC_HC_REGS_OPB_SIZE 0x00000100 101 102 static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) 103 { 104 const char compat[] = "ibm,power8-lpc\0ibm,lpc"; 105 char *name; 106 int offset; 107 uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE; 108 uint32_t reg[] = { 109 cpu_to_be32(lpc_pcba), 110 cpu_to_be32(PNV_XSCOM_LPC_SIZE) 111 }; 112 113 name = g_strdup_printf("isa@%x", lpc_pcba); 114 offset = fdt_add_subnode(fdt, xscom_offset, name); 115 _FDT(offset); 116 g_free(name); 117 118 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 119 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); 120 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); 121 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 122 return 0; 123 } 124 125 /* POWER9 only */ 126 int pnv_dt_lpc(PnvChip *chip, void *fdt, int root_offset, uint64_t lpcm_addr, 127 uint64_t lpcm_size) 128 { 129 const char compat[] = "ibm,power9-lpcm-opb\0simple-bus"; 130 const char lpc_compat[] = "ibm,power9-lpc\0ibm,lpc"; 131 char *name; 132 int offset, lpcm_offset; 133 uint32_t opb_ranges[8] = { 0, 134 cpu_to_be32(lpcm_addr >> 32), 135 cpu_to_be32((uint32_t)lpcm_addr), 136 cpu_to_be32(lpcm_size / 2), 137 cpu_to_be32(lpcm_size / 2), 138 cpu_to_be32(lpcm_addr >> 32), 139 cpu_to_be32(lpcm_size / 2), 140 cpu_to_be32(lpcm_size / 2), 141 }; 142 uint32_t opb_reg[4] = { cpu_to_be32(lpcm_addr >> 32), 143 cpu_to_be32((uint32_t)lpcm_addr), 144 cpu_to_be32(lpcm_size >> 32), 145 cpu_to_be32((uint32_t)lpcm_size), 146 }; 147 uint32_t lpc_ranges[12] = { 0, 0, 148 cpu_to_be32(LPC_MEM_OPB_ADDR), 149 cpu_to_be32(LPC_MEM_OPB_SIZE), 150 cpu_to_be32(1), 0, 151 cpu_to_be32(LPC_IO_OPB_ADDR), 152 cpu_to_be32(LPC_IO_OPB_SIZE), 153 cpu_to_be32(3), 0, 154 cpu_to_be32(LPC_FW_OPB_ADDR), 155 cpu_to_be32(LPC_FW_OPB_SIZE), 156 }; 157 uint32_t reg[2]; 158 159 /* 160 * OPB bus 161 */ 162 name = g_strdup_printf("lpcm-opb@%"PRIx64, lpcm_addr); 163 lpcm_offset = fdt_add_subnode(fdt, root_offset, name); 164 _FDT(lpcm_offset); 165 g_free(name); 166 167 _FDT((fdt_setprop(fdt, lpcm_offset, "reg", opb_reg, sizeof(opb_reg)))); 168 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#address-cells", 1))); 169 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "#size-cells", 1))); 170 _FDT((fdt_setprop(fdt, lpcm_offset, "compatible", compat, sizeof(compat)))); 171 _FDT((fdt_setprop_cell(fdt, lpcm_offset, "ibm,chip-id", chip->chip_id))); 172 _FDT((fdt_setprop(fdt, lpcm_offset, "ranges", opb_ranges, 173 sizeof(opb_ranges)))); 174 175 /* 176 * OPB Master registers 177 */ 178 name = g_strdup_printf("opb-master@%x", LPC_OPB_REGS_OPB_ADDR); 179 offset = fdt_add_subnode(fdt, lpcm_offset, name); 180 _FDT(offset); 181 g_free(name); 182 183 reg[0] = cpu_to_be32(LPC_OPB_REGS_OPB_ADDR); 184 reg[1] = cpu_to_be32(LPC_OPB_REGS_OPB_SIZE); 185 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 186 _FDT((fdt_setprop_string(fdt, offset, "compatible", 187 "ibm,power9-lpcm-opb-master"))); 188 189 /* 190 * OPB arbitrer registers 191 */ 192 name = g_strdup_printf("opb-arbitrer@%x", LPC_OPB_REGS_OPBA_ADDR); 193 offset = fdt_add_subnode(fdt, lpcm_offset, name); 194 _FDT(offset); 195 g_free(name); 196 197 reg[0] = cpu_to_be32(LPC_OPB_REGS_OPBA_ADDR); 198 reg[1] = cpu_to_be32(LPC_OPB_REGS_OPBA_SIZE); 199 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 200 _FDT((fdt_setprop_string(fdt, offset, "compatible", 201 "ibm,power9-lpcm-opb-arbiter"))); 202 203 /* 204 * LPC Host Controller registers 205 */ 206 name = g_strdup_printf("lpc-controller@%x", LPC_HC_REGS_OPB_ADDR); 207 offset = fdt_add_subnode(fdt, lpcm_offset, name); 208 _FDT(offset); 209 g_free(name); 210 211 reg[0] = cpu_to_be32(LPC_HC_REGS_OPB_ADDR); 212 reg[1] = cpu_to_be32(LPC_HC_REGS_OPB_SIZE); 213 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 214 _FDT((fdt_setprop_string(fdt, offset, "compatible", 215 "ibm,power9-lpc-controller"))); 216 217 name = g_strdup_printf("lpc@0"); 218 offset = fdt_add_subnode(fdt, lpcm_offset, name); 219 _FDT(offset); 220 g_free(name); 221 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); 222 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); 223 _FDT((fdt_setprop(fdt, offset, "compatible", lpc_compat, 224 sizeof(lpc_compat)))); 225 _FDT((fdt_setprop(fdt, offset, "ranges", lpc_ranges, 226 sizeof(lpc_ranges)))); 227 228 return 0; 229 } 230 231 /* 232 * These read/write handlers of the OPB address space should be common 233 * with the P9 LPC Controller which uses direct MMIOs. 234 * 235 * TODO: rework to use address_space_stq() and address_space_ldq() 236 * instead. 237 */ 238 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 239 int sz) 240 { 241 /* XXX Handle access size limits and FW read caching here */ 242 return !address_space_read(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 243 data, sz); 244 } 245 246 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 247 int sz) 248 { 249 /* XXX Handle access size limits here */ 250 return !address_space_write(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 251 data, sz); 252 } 253 254 #define ECCB_CTL_READ PPC_BIT(15) 255 #define ECCB_CTL_SZ_LSH (63 - 7) 256 #define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7) 257 #define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63) 258 259 #define ECCB_STAT_OP_DONE PPC_BIT(52) 260 #define ECCB_STAT_OP_ERR PPC_BIT(52) 261 #define ECCB_STAT_RD_DATA_LSH (63 - 37) 262 #define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH) 263 264 static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd) 265 { 266 /* XXX Check for magic bits at the top, addr size etc... */ 267 unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH; 268 uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK; 269 uint8_t data[8]; 270 bool success; 271 272 if (sz > sizeof(data)) { 273 qemu_log_mask(LOG_GUEST_ERROR, 274 "ECCB: invalid operation at @0x%08x size %d\n", opb_addr, sz); 275 return; 276 } 277 278 if (cmd & ECCB_CTL_READ) { 279 success = opb_read(lpc, opb_addr, data, sz); 280 if (success) { 281 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | 282 (((uint64_t)data[0]) << 24 | 283 ((uint64_t)data[1]) << 16 | 284 ((uint64_t)data[2]) << 8 | 285 ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH; 286 } else { 287 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | 288 (0xffffffffull << ECCB_STAT_RD_DATA_LSH); 289 } 290 } else { 291 data[0] = lpc->eccb_data_reg >> 24; 292 data[1] = lpc->eccb_data_reg >> 16; 293 data[2] = lpc->eccb_data_reg >> 8; 294 data[3] = lpc->eccb_data_reg; 295 296 success = opb_write(lpc, opb_addr, data, sz); 297 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE; 298 } 299 /* XXX Which error bit (if any) to signal OPB error ? */ 300 } 301 302 static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size) 303 { 304 PnvLpcController *lpc = PNV_LPC(opaque); 305 uint32_t offset = addr >> 3; 306 uint64_t val = 0; 307 308 switch (offset & 3) { 309 case ECCB_CTL: 310 case ECCB_RESET: 311 val = 0; 312 break; 313 case ECCB_STAT: 314 val = lpc->eccb_stat_reg; 315 lpc->eccb_stat_reg = 0; 316 break; 317 case ECCB_DATA: 318 val = ((uint64_t)lpc->eccb_data_reg) << 32; 319 break; 320 } 321 return val; 322 } 323 324 static void pnv_lpc_xscom_write(void *opaque, hwaddr addr, 325 uint64_t val, unsigned size) 326 { 327 PnvLpcController *lpc = PNV_LPC(opaque); 328 uint32_t offset = addr >> 3; 329 330 switch (offset & 3) { 331 case ECCB_CTL: 332 pnv_lpc_do_eccb(lpc, val); 333 break; 334 case ECCB_RESET: 335 /* XXXX */ 336 break; 337 case ECCB_STAT: 338 break; 339 case ECCB_DATA: 340 lpc->eccb_data_reg = val >> 32; 341 break; 342 } 343 } 344 345 static const MemoryRegionOps pnv_lpc_xscom_ops = { 346 .read = pnv_lpc_xscom_read, 347 .write = pnv_lpc_xscom_write, 348 .valid.min_access_size = 8, 349 .valid.max_access_size = 8, 350 .impl.min_access_size = 8, 351 .impl.max_access_size = 8, 352 .endianness = DEVICE_BIG_ENDIAN, 353 }; 354 355 static uint64_t pnv_lpc_mmio_read(void *opaque, hwaddr addr, unsigned size) 356 { 357 PnvLpcController *lpc = PNV_LPC(opaque); 358 uint64_t val = 0; 359 uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK; 360 MemTxResult result; 361 362 switch (size) { 363 case 4: 364 val = address_space_ldl(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED, 365 &result); 366 break; 367 case 1: 368 val = address_space_ldub(&lpc->opb_as, opb_addr, MEMTXATTRS_UNSPECIFIED, 369 &result); 370 break; 371 default: 372 qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%" 373 HWADDR_PRIx " invalid size %d\n", addr, size); 374 return 0; 375 } 376 377 if (result != MEMTX_OK) { 378 qemu_log_mask(LOG_GUEST_ERROR, "OPB read failed at @0x%" 379 HWADDR_PRIx "\n", addr); 380 } 381 382 return val; 383 } 384 385 static void pnv_lpc_mmio_write(void *opaque, hwaddr addr, 386 uint64_t val, unsigned size) 387 { 388 PnvLpcController *lpc = PNV_LPC(opaque); 389 uint32_t opb_addr = addr & ECCB_CTL_ADDR_MASK; 390 MemTxResult result; 391 392 switch (size) { 393 case 4: 394 address_space_stl(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED, 395 &result); 396 break; 397 case 1: 398 address_space_stb(&lpc->opb_as, opb_addr, val, MEMTXATTRS_UNSPECIFIED, 399 &result); 400 break; 401 default: 402 qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%" 403 HWADDR_PRIx " invalid size %d\n", addr, size); 404 return; 405 } 406 407 if (result != MEMTX_OK) { 408 qemu_log_mask(LOG_GUEST_ERROR, "OPB write failed at @0x%" 409 HWADDR_PRIx "\n", addr); 410 } 411 } 412 413 static const MemoryRegionOps pnv_lpc_mmio_ops = { 414 .read = pnv_lpc_mmio_read, 415 .write = pnv_lpc_mmio_write, 416 .impl = { 417 .min_access_size = 1, 418 .max_access_size = 4, 419 }, 420 .endianness = DEVICE_BIG_ENDIAN, 421 }; 422 423 static void pnv_lpc_eval_irqs(PnvLpcController *lpc) 424 { 425 bool lpc_to_opb_irq = false; 426 427 /* Update LPC controller to OPB line */ 428 if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { 429 uint32_t irqs; 430 431 irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; 432 lpc_to_opb_irq = (irqs != 0); 433 } 434 435 /* We don't honor the polarity register, it's pointless and unused 436 * anyway 437 */ 438 if (lpc_to_opb_irq) { 439 lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC; 440 } else { 441 lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC; 442 } 443 444 /* Update OPB internal latch */ 445 lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask; 446 447 /* Reflect the interrupt */ 448 qemu_set_irq(lpc->psi_irq, lpc->opb_irq_stat != 0); 449 } 450 451 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) 452 { 453 PnvLpcController *lpc = opaque; 454 uint64_t val = 0xfffffffffffffffful; 455 456 switch (addr) { 457 case LPC_HC_FW_SEG_IDSEL: 458 val = lpc->lpc_hc_fw_seg_idsel; 459 break; 460 case LPC_HC_FW_RD_ACC_SIZE: 461 val = lpc->lpc_hc_fw_rd_acc_size; 462 break; 463 case LPC_HC_IRQSER_CTRL: 464 val = lpc->lpc_hc_irqser_ctrl; 465 break; 466 case LPC_HC_IRQMASK: 467 val = lpc->lpc_hc_irqmask; 468 break; 469 case LPC_HC_IRQSTAT: 470 val = lpc->lpc_hc_irqstat; 471 break; 472 case LPC_HC_ERROR_ADDRESS: 473 val = lpc->lpc_hc_error_addr; 474 break; 475 default: 476 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%" 477 HWADDR_PRIx "\n", addr); 478 } 479 return val; 480 } 481 482 static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val, 483 unsigned size) 484 { 485 PnvLpcController *lpc = opaque; 486 487 /* XXX Filter out reserved bits */ 488 489 switch (addr) { 490 case LPC_HC_FW_SEG_IDSEL: 491 /* XXX Actually figure out how that works as this impact 492 * memory regions/aliases 493 */ 494 lpc->lpc_hc_fw_seg_idsel = val; 495 break; 496 case LPC_HC_FW_RD_ACC_SIZE: 497 lpc->lpc_hc_fw_rd_acc_size = val; 498 break; 499 case LPC_HC_IRQSER_CTRL: 500 lpc->lpc_hc_irqser_ctrl = val; 501 pnv_lpc_eval_irqs(lpc); 502 break; 503 case LPC_HC_IRQMASK: 504 lpc->lpc_hc_irqmask = val; 505 pnv_lpc_eval_irqs(lpc); 506 break; 507 case LPC_HC_IRQSTAT: 508 lpc->lpc_hc_irqstat &= ~val; 509 pnv_lpc_eval_irqs(lpc); 510 break; 511 case LPC_HC_ERROR_ADDRESS: 512 break; 513 default: 514 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: 0x%" 515 HWADDR_PRIx "\n", addr); 516 } 517 } 518 519 static const MemoryRegionOps lpc_hc_ops = { 520 .read = lpc_hc_read, 521 .write = lpc_hc_write, 522 .endianness = DEVICE_BIG_ENDIAN, 523 .valid = { 524 .min_access_size = 4, 525 .max_access_size = 4, 526 }, 527 .impl = { 528 .min_access_size = 4, 529 .max_access_size = 4, 530 }, 531 }; 532 533 static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size) 534 { 535 PnvLpcController *lpc = opaque; 536 uint64_t val = 0xfffffffffffffffful; 537 538 switch (addr) { 539 case OPB_MASTER_LS_ROUTE0: /* TODO */ 540 val = lpc->opb_irq_route0; 541 break; 542 case OPB_MASTER_LS_ROUTE1: /* TODO */ 543 val = lpc->opb_irq_route1; 544 break; 545 case OPB_MASTER_LS_IRQ_STAT: 546 val = lpc->opb_irq_stat; 547 break; 548 case OPB_MASTER_LS_IRQ_MASK: 549 val = lpc->opb_irq_mask; 550 break; 551 case OPB_MASTER_LS_IRQ_POL: 552 val = lpc->opb_irq_pol; 553 break; 554 case OPB_MASTER_LS_IRQ_INPUT: 555 val = lpc->opb_irq_input; 556 break; 557 default: 558 qemu_log_mask(LOG_UNIMP, "OPBM: read on unimplemented register: 0x%" 559 HWADDR_PRIx "\n", addr); 560 } 561 562 return val; 563 } 564 565 static void opb_master_write(void *opaque, hwaddr addr, 566 uint64_t val, unsigned size) 567 { 568 PnvLpcController *lpc = opaque; 569 570 switch (addr) { 571 case OPB_MASTER_LS_ROUTE0: /* TODO */ 572 lpc->opb_irq_route0 = val; 573 break; 574 case OPB_MASTER_LS_ROUTE1: /* TODO */ 575 lpc->opb_irq_route1 = val; 576 break; 577 case OPB_MASTER_LS_IRQ_STAT: 578 lpc->opb_irq_stat &= ~val; 579 pnv_lpc_eval_irqs(lpc); 580 break; 581 case OPB_MASTER_LS_IRQ_MASK: 582 lpc->opb_irq_mask = val; 583 pnv_lpc_eval_irqs(lpc); 584 break; 585 case OPB_MASTER_LS_IRQ_POL: 586 lpc->opb_irq_pol = val; 587 pnv_lpc_eval_irqs(lpc); 588 break; 589 case OPB_MASTER_LS_IRQ_INPUT: 590 /* Read only */ 591 break; 592 default: 593 qemu_log_mask(LOG_UNIMP, "OPBM: write on unimplemented register: 0x%" 594 HWADDR_PRIx " val=0x%08"PRIx64"\n", addr, val); 595 } 596 } 597 598 static const MemoryRegionOps opb_master_ops = { 599 .read = opb_master_read, 600 .write = opb_master_write, 601 .endianness = DEVICE_BIG_ENDIAN, 602 .valid = { 603 .min_access_size = 4, 604 .max_access_size = 4, 605 }, 606 .impl = { 607 .min_access_size = 4, 608 .max_access_size = 4, 609 }, 610 }; 611 612 static void pnv_lpc_power8_realize(DeviceState *dev, Error **errp) 613 { 614 PnvLpcController *lpc = PNV_LPC(dev); 615 PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev); 616 Error *local_err = NULL; 617 618 plc->parent_realize(dev, &local_err); 619 if (local_err) { 620 error_propagate(errp, local_err); 621 return; 622 } 623 624 /* P8 uses a XSCOM region for LPC registers */ 625 pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(lpc), 626 &pnv_lpc_xscom_ops, lpc, "xscom-lpc", 627 PNV_XSCOM_LPC_SIZE); 628 } 629 630 static void pnv_lpc_power8_class_init(ObjectClass *klass, void *data) 631 { 632 DeviceClass *dc = DEVICE_CLASS(klass); 633 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 634 PnvLpcClass *plc = PNV_LPC_CLASS(klass); 635 636 dc->desc = "PowerNV LPC Controller POWER8"; 637 638 xdc->dt_xscom = pnv_lpc_dt_xscom; 639 640 device_class_set_parent_realize(dc, pnv_lpc_power8_realize, 641 &plc->parent_realize); 642 } 643 644 static const TypeInfo pnv_lpc_power8_info = { 645 .name = TYPE_PNV8_LPC, 646 .parent = TYPE_PNV_LPC, 647 .class_init = pnv_lpc_power8_class_init, 648 .interfaces = (InterfaceInfo[]) { 649 { TYPE_PNV_XSCOM_INTERFACE }, 650 { } 651 } 652 }; 653 654 static void pnv_lpc_power9_realize(DeviceState *dev, Error **errp) 655 { 656 PnvLpcController *lpc = PNV_LPC(dev); 657 PnvLpcClass *plc = PNV_LPC_GET_CLASS(dev); 658 Error *local_err = NULL; 659 660 plc->parent_realize(dev, &local_err); 661 if (local_err) { 662 error_propagate(errp, local_err); 663 return; 664 } 665 666 /* P9 uses a MMIO region */ 667 memory_region_init_io(&lpc->xscom_regs, OBJECT(lpc), &pnv_lpc_mmio_ops, 668 lpc, "lpcm", PNV9_LPCM_SIZE); 669 } 670 671 static void pnv_lpc_power9_class_init(ObjectClass *klass, void *data) 672 { 673 DeviceClass *dc = DEVICE_CLASS(klass); 674 PnvLpcClass *plc = PNV_LPC_CLASS(klass); 675 676 dc->desc = "PowerNV LPC Controller POWER9"; 677 678 device_class_set_parent_realize(dc, pnv_lpc_power9_realize, 679 &plc->parent_realize); 680 } 681 682 static const TypeInfo pnv_lpc_power9_info = { 683 .name = TYPE_PNV9_LPC, 684 .parent = TYPE_PNV_LPC, 685 .class_init = pnv_lpc_power9_class_init, 686 }; 687 688 static void pnv_lpc_power10_class_init(ObjectClass *klass, void *data) 689 { 690 DeviceClass *dc = DEVICE_CLASS(klass); 691 692 dc->desc = "PowerNV LPC Controller POWER10"; 693 } 694 695 static const TypeInfo pnv_lpc_power10_info = { 696 .name = TYPE_PNV10_LPC, 697 .parent = TYPE_PNV9_LPC, 698 .class_init = pnv_lpc_power10_class_init, 699 }; 700 701 static void pnv_lpc_realize(DeviceState *dev, Error **errp) 702 { 703 PnvLpcController *lpc = PNV_LPC(dev); 704 705 /* Reg inits */ 706 lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; 707 708 /* Create address space and backing MR for the OPB bus */ 709 memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull); 710 address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb"); 711 712 /* Create ISA IO and Mem space regions which are the root of 713 * the ISA bus (ie, ISA address spaces). We don't create a 714 * separate one for FW which we alias to memory. 715 */ 716 memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE); 717 memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE); 718 memory_region_init(&lpc->isa_fw, OBJECT(dev), "isa-fw", ISA_FW_SIZE); 719 720 /* Create windows from the OPB space to the ISA space */ 721 memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io", 722 &lpc->isa_io, 0, LPC_IO_OPB_SIZE); 723 memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR, 724 &lpc->opb_isa_io); 725 memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem", 726 &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE); 727 memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR, 728 &lpc->opb_isa_mem); 729 memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw", 730 &lpc->isa_fw, 0, LPC_FW_OPB_SIZE); 731 memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR, 732 &lpc->opb_isa_fw); 733 734 /* Create MMIO regions for LPC HC and OPB registers */ 735 memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops, 736 lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE); 737 lpc->opb_master_regs.disable_reentrancy_guard = true; 738 memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR, 739 &lpc->opb_master_regs); 740 memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc, 741 "lpc-hc", LPC_HC_REGS_OPB_SIZE); 742 /* xscom writes to lpc-hc. As such mark lpc-hc re-entrancy safe */ 743 lpc->lpc_hc_regs.disable_reentrancy_guard = true; 744 memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR, 745 &lpc->lpc_hc_regs); 746 747 qdev_init_gpio_out(DEVICE(dev), &lpc->psi_irq, 1); 748 } 749 750 static void pnv_lpc_class_init(ObjectClass *klass, void *data) 751 { 752 DeviceClass *dc = DEVICE_CLASS(klass); 753 754 dc->realize = pnv_lpc_realize; 755 dc->desc = "PowerNV LPC Controller"; 756 dc->user_creatable = false; 757 } 758 759 static const TypeInfo pnv_lpc_info = { 760 .name = TYPE_PNV_LPC, 761 .parent = TYPE_DEVICE, 762 .instance_size = sizeof(PnvLpcController), 763 .class_init = pnv_lpc_class_init, 764 .class_size = sizeof(PnvLpcClass), 765 .abstract = true, 766 }; 767 768 static void pnv_lpc_register_types(void) 769 { 770 type_register_static(&pnv_lpc_info); 771 type_register_static(&pnv_lpc_power8_info); 772 type_register_static(&pnv_lpc_power9_info); 773 type_register_static(&pnv_lpc_power10_info); 774 } 775 776 type_init(pnv_lpc_register_types) 777 778 /* If we don't use the built-in LPC interrupt deserializer, we need 779 * to provide a set of qirqs for the ISA bus or things will go bad. 780 * 781 * Most machines using pre-Naples chips (without said deserializer) 782 * have a CPLD that will collect the SerIRQ and shoot them as a 783 * single level interrupt to the P8 chip. So let's setup a hook 784 * for doing just that. 785 */ 786 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) 787 { 788 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 789 uint32_t old_state = pnv->cpld_irqstate; 790 PnvLpcController *lpc = PNV_LPC(opaque); 791 792 if (level) { 793 pnv->cpld_irqstate |= 1u << n; 794 } else { 795 pnv->cpld_irqstate &= ~(1u << n); 796 } 797 798 if (pnv->cpld_irqstate != old_state) { 799 qemu_set_irq(lpc->psi_irq, pnv->cpld_irqstate != 0); 800 } 801 } 802 803 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) 804 { 805 PnvLpcController *lpc = PNV_LPC(opaque); 806 807 /* The Naples HW latches the 1 levels, clearing is done by SW */ 808 if (level) { 809 lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n; 810 pnv_lpc_eval_irqs(lpc); 811 } 812 } 813 814 ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp) 815 { 816 Error *local_err = NULL; 817 ISABus *isa_bus; 818 qemu_irq *irqs; 819 qemu_irq_handler handler; 820 821 /* let isa_bus_new() create its own bridge on SysBus otherwise 822 * devices specified on the command line won't find the bus and 823 * will fail to create. 824 */ 825 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err); 826 if (local_err) { 827 error_propagate(errp, local_err); 828 return NULL; 829 } 830 831 /* Not all variants have a working serial irq decoder. If not, 832 * handling of LPC interrupts becomes a platform issue (some 833 * platforms have a CPLD to do it). 834 */ 835 if (use_cpld) { 836 handler = pnv_lpc_isa_irq_handler_cpld; 837 } else { 838 handler = pnv_lpc_isa_irq_handler; 839 } 840 841 irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS); 842 843 isa_bus_register_input_irqs(isa_bus, irqs); 844 845 return isa_bus; 846 } 847