1 /* 2 * QEMU PowerPC PowerNV LPC controller 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/sysemu.h" 22 #include "target/ppc/cpu.h" 23 #include "qapi/error.h" 24 #include "qemu/log.h" 25 26 #include "hw/ppc/pnv.h" 27 #include "hw/ppc/pnv_lpc.h" 28 #include "hw/ppc/pnv_xscom.h" 29 #include "hw/ppc/fdt.h" 30 31 #include <libfdt.h> 32 33 enum { 34 ECCB_CTL = 0, 35 ECCB_RESET = 1, 36 ECCB_STAT = 2, 37 ECCB_DATA = 3, 38 }; 39 40 /* OPB Master LS registers */ 41 #define OPB_MASTER_LS_IRQ_STAT 0x50 42 #define OPB_MASTER_IRQ_LPC 0x00000800 43 #define OPB_MASTER_LS_IRQ_MASK 0x54 44 #define OPB_MASTER_LS_IRQ_POL 0x58 45 #define OPB_MASTER_LS_IRQ_INPUT 0x5c 46 47 /* LPC HC registers */ 48 #define LPC_HC_FW_SEG_IDSEL 0x24 49 #define LPC_HC_FW_RD_ACC_SIZE 0x28 50 #define LPC_HC_FW_RD_1B 0x00000000 51 #define LPC_HC_FW_RD_2B 0x01000000 52 #define LPC_HC_FW_RD_4B 0x02000000 53 #define LPC_HC_FW_RD_16B 0x04000000 54 #define LPC_HC_FW_RD_128B 0x07000000 55 #define LPC_HC_IRQSER_CTRL 0x30 56 #define LPC_HC_IRQSER_EN 0x80000000 57 #define LPC_HC_IRQSER_QMODE 0x40000000 58 #define LPC_HC_IRQSER_START_MASK 0x03000000 59 #define LPC_HC_IRQSER_START_4CLK 0x00000000 60 #define LPC_HC_IRQSER_START_6CLK 0x01000000 61 #define LPC_HC_IRQSER_START_8CLK 0x02000000 62 #define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */ 63 #define LPC_HC_IRQSTAT 0x38 64 #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */ 65 #define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */ 66 #define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000 67 #define LPC_HC_IRQ_LRESET 0x00000400 68 #define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080 69 #define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040 70 #define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020 71 #define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010 72 #define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008 73 #define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004 74 #define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002 75 #define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001 76 #define LPC_HC_ERROR_ADDRESS 0x40 77 78 #define LPC_OPB_SIZE 0x100000000ull 79 80 #define ISA_IO_SIZE 0x00010000 81 #define ISA_MEM_SIZE 0x10000000 82 #define LPC_IO_OPB_ADDR 0xd0010000 83 #define LPC_IO_OPB_SIZE 0x00010000 84 #define LPC_MEM_OPB_ADDR 0xe0010000 85 #define LPC_MEM_OPB_SIZE 0x10000000 86 #define LPC_FW_OPB_ADDR 0xf0000000 87 #define LPC_FW_OPB_SIZE 0x10000000 88 89 #define LPC_OPB_REGS_OPB_ADDR 0xc0010000 90 #define LPC_OPB_REGS_OPB_SIZE 0x00002000 91 #define LPC_HC_REGS_OPB_ADDR 0xc0012000 92 #define LPC_HC_REGS_OPB_SIZE 0x00001000 93 94 95 static int pnv_lpc_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) 96 { 97 const char compat[] = "ibm,power8-lpc\0ibm,lpc"; 98 char *name; 99 int offset; 100 uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE; 101 uint32_t reg[] = { 102 cpu_to_be32(lpc_pcba), 103 cpu_to_be32(PNV_XSCOM_LPC_SIZE) 104 }; 105 106 name = g_strdup_printf("isa@%x", lpc_pcba); 107 offset = fdt_add_subnode(fdt, xscom_offset, name); 108 _FDT(offset); 109 g_free(name); 110 111 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 112 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); 113 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); 114 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 115 return 0; 116 } 117 118 /* 119 * These read/write handlers of the OPB address space should be common 120 * with the P9 LPC Controller which uses direct MMIOs. 121 * 122 * TODO: rework to use address_space_stq() and address_space_ldq() 123 * instead. 124 */ 125 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 126 int sz) 127 { 128 /* XXX Handle access size limits and FW read caching here */ 129 return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 130 data, sz, false); 131 } 132 133 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 134 int sz) 135 { 136 /* XXX Handle access size limits here */ 137 return !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 138 data, sz, true); 139 } 140 141 #define ECCB_CTL_READ PPC_BIT(15) 142 #define ECCB_CTL_SZ_LSH (63 - 7) 143 #define ECCB_CTL_SZ_MASK PPC_BITMASK(4, 7) 144 #define ECCB_CTL_ADDR_MASK PPC_BITMASK(32, 63) 145 146 #define ECCB_STAT_OP_DONE PPC_BIT(52) 147 #define ECCB_STAT_OP_ERR PPC_BIT(52) 148 #define ECCB_STAT_RD_DATA_LSH (63 - 37) 149 #define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH) 150 151 static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd) 152 { 153 /* XXX Check for magic bits at the top, addr size etc... */ 154 unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH; 155 uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK; 156 uint8_t data[4]; 157 bool success; 158 159 if (cmd & ECCB_CTL_READ) { 160 success = opb_read(lpc, opb_addr, data, sz); 161 if (success) { 162 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | 163 (((uint64_t)data[0]) << 24 | 164 ((uint64_t)data[1]) << 16 | 165 ((uint64_t)data[2]) << 8 | 166 ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH; 167 } else { 168 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | 169 (0xffffffffull << ECCB_STAT_RD_DATA_LSH); 170 } 171 } else { 172 data[0] = lpc->eccb_data_reg >> 24; 173 data[1] = lpc->eccb_data_reg >> 16; 174 data[2] = lpc->eccb_data_reg >> 8; 175 data[3] = lpc->eccb_data_reg; 176 177 success = opb_write(lpc, opb_addr, data, sz); 178 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE; 179 } 180 /* XXX Which error bit (if any) to signal OPB error ? */ 181 } 182 183 static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size) 184 { 185 PnvLpcController *lpc = PNV_LPC(opaque); 186 uint32_t offset = addr >> 3; 187 uint64_t val = 0; 188 189 switch (offset & 3) { 190 case ECCB_CTL: 191 case ECCB_RESET: 192 val = 0; 193 break; 194 case ECCB_STAT: 195 val = lpc->eccb_stat_reg; 196 lpc->eccb_stat_reg = 0; 197 break; 198 case ECCB_DATA: 199 val = ((uint64_t)lpc->eccb_data_reg) << 32; 200 break; 201 } 202 return val; 203 } 204 205 static void pnv_lpc_xscom_write(void *opaque, hwaddr addr, 206 uint64_t val, unsigned size) 207 { 208 PnvLpcController *lpc = PNV_LPC(opaque); 209 uint32_t offset = addr >> 3; 210 211 switch (offset & 3) { 212 case ECCB_CTL: 213 pnv_lpc_do_eccb(lpc, val); 214 break; 215 case ECCB_RESET: 216 /* XXXX */ 217 break; 218 case ECCB_STAT: 219 break; 220 case ECCB_DATA: 221 lpc->eccb_data_reg = val >> 32; 222 break; 223 } 224 } 225 226 static const MemoryRegionOps pnv_lpc_xscom_ops = { 227 .read = pnv_lpc_xscom_read, 228 .write = pnv_lpc_xscom_write, 229 .valid.min_access_size = 8, 230 .valid.max_access_size = 8, 231 .impl.min_access_size = 8, 232 .impl.max_access_size = 8, 233 .endianness = DEVICE_BIG_ENDIAN, 234 }; 235 236 static void pnv_lpc_eval_irqs(PnvLpcController *lpc) 237 { 238 bool lpc_to_opb_irq = false; 239 240 /* Update LPC controller to OPB line */ 241 if (lpc->lpc_hc_irqser_ctrl & LPC_HC_IRQSER_EN) { 242 uint32_t irqs; 243 244 irqs = lpc->lpc_hc_irqstat & lpc->lpc_hc_irqmask; 245 lpc_to_opb_irq = (irqs != 0); 246 } 247 248 /* We don't honor the polarity register, it's pointless and unused 249 * anyway 250 */ 251 if (lpc_to_opb_irq) { 252 lpc->opb_irq_input |= OPB_MASTER_IRQ_LPC; 253 } else { 254 lpc->opb_irq_input &= ~OPB_MASTER_IRQ_LPC; 255 } 256 257 /* Update OPB internal latch */ 258 lpc->opb_irq_stat |= lpc->opb_irq_input & lpc->opb_irq_mask; 259 260 /* Reflect the interrupt */ 261 pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_LPC_I2C, lpc->opb_irq_stat != 0); 262 } 263 264 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) 265 { 266 PnvLpcController *lpc = opaque; 267 uint64_t val = 0xfffffffffffffffful; 268 269 switch (addr) { 270 case LPC_HC_FW_SEG_IDSEL: 271 val = lpc->lpc_hc_fw_seg_idsel; 272 break; 273 case LPC_HC_FW_RD_ACC_SIZE: 274 val = lpc->lpc_hc_fw_rd_acc_size; 275 break; 276 case LPC_HC_IRQSER_CTRL: 277 val = lpc->lpc_hc_irqser_ctrl; 278 break; 279 case LPC_HC_IRQMASK: 280 val = lpc->lpc_hc_irqmask; 281 break; 282 case LPC_HC_IRQSTAT: 283 val = lpc->lpc_hc_irqstat; 284 break; 285 case LPC_HC_ERROR_ADDRESS: 286 val = lpc->lpc_hc_error_addr; 287 break; 288 default: 289 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%" 290 HWADDR_PRIx "\n", addr); 291 } 292 return val; 293 } 294 295 static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val, 296 unsigned size) 297 { 298 PnvLpcController *lpc = opaque; 299 300 /* XXX Filter out reserved bits */ 301 302 switch (addr) { 303 case LPC_HC_FW_SEG_IDSEL: 304 /* XXX Actually figure out how that works as this impact 305 * memory regions/aliases 306 */ 307 lpc->lpc_hc_fw_seg_idsel = val; 308 break; 309 case LPC_HC_FW_RD_ACC_SIZE: 310 lpc->lpc_hc_fw_rd_acc_size = val; 311 break; 312 case LPC_HC_IRQSER_CTRL: 313 lpc->lpc_hc_irqser_ctrl = val; 314 pnv_lpc_eval_irqs(lpc); 315 break; 316 case LPC_HC_IRQMASK: 317 lpc->lpc_hc_irqmask = val; 318 pnv_lpc_eval_irqs(lpc); 319 break; 320 case LPC_HC_IRQSTAT: 321 lpc->lpc_hc_irqstat &= ~val; 322 pnv_lpc_eval_irqs(lpc); 323 break; 324 case LPC_HC_ERROR_ADDRESS: 325 break; 326 default: 327 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%" 328 HWADDR_PRIx "\n", addr); 329 } 330 } 331 332 static const MemoryRegionOps lpc_hc_ops = { 333 .read = lpc_hc_read, 334 .write = lpc_hc_write, 335 .endianness = DEVICE_BIG_ENDIAN, 336 .valid = { 337 .min_access_size = 4, 338 .max_access_size = 4, 339 }, 340 .impl = { 341 .min_access_size = 4, 342 .max_access_size = 4, 343 }, 344 }; 345 346 static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size) 347 { 348 PnvLpcController *lpc = opaque; 349 uint64_t val = 0xfffffffffffffffful; 350 351 switch (addr) { 352 case OPB_MASTER_LS_IRQ_STAT: 353 val = lpc->opb_irq_stat; 354 break; 355 case OPB_MASTER_LS_IRQ_MASK: 356 val = lpc->opb_irq_mask; 357 break; 358 case OPB_MASTER_LS_IRQ_POL: 359 val = lpc->opb_irq_pol; 360 break; 361 case OPB_MASTER_LS_IRQ_INPUT: 362 val = lpc->opb_irq_input; 363 break; 364 default: 365 qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%" 366 HWADDR_PRIx "\n", addr); 367 } 368 369 return val; 370 } 371 372 static void opb_master_write(void *opaque, hwaddr addr, 373 uint64_t val, unsigned size) 374 { 375 PnvLpcController *lpc = opaque; 376 377 switch (addr) { 378 case OPB_MASTER_LS_IRQ_STAT: 379 lpc->opb_irq_stat &= ~val; 380 pnv_lpc_eval_irqs(lpc); 381 break; 382 case OPB_MASTER_LS_IRQ_MASK: 383 lpc->opb_irq_mask = val; 384 pnv_lpc_eval_irqs(lpc); 385 break; 386 case OPB_MASTER_LS_IRQ_POL: 387 lpc->opb_irq_pol = val; 388 pnv_lpc_eval_irqs(lpc); 389 break; 390 case OPB_MASTER_LS_IRQ_INPUT: 391 /* Read only */ 392 break; 393 default: 394 qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%" 395 HWADDR_PRIx "\n", addr); 396 } 397 } 398 399 static const MemoryRegionOps opb_master_ops = { 400 .read = opb_master_read, 401 .write = opb_master_write, 402 .endianness = DEVICE_BIG_ENDIAN, 403 .valid = { 404 .min_access_size = 4, 405 .max_access_size = 4, 406 }, 407 .impl = { 408 .min_access_size = 4, 409 .max_access_size = 4, 410 }, 411 }; 412 413 static void pnv_lpc_realize(DeviceState *dev, Error **errp) 414 { 415 PnvLpcController *lpc = PNV_LPC(dev); 416 Object *obj; 417 Error *error = NULL; 418 419 /* Reg inits */ 420 lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; 421 422 /* Create address space and backing MR for the OPB bus */ 423 memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull); 424 address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb"); 425 426 /* Create ISA IO and Mem space regions which are the root of 427 * the ISA bus (ie, ISA address spaces). We don't create a 428 * separate one for FW which we alias to memory. 429 */ 430 memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE); 431 memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE); 432 433 /* Create windows from the OPB space to the ISA space */ 434 memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io", 435 &lpc->isa_io, 0, LPC_IO_OPB_SIZE); 436 memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR, 437 &lpc->opb_isa_io); 438 memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem", 439 &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE); 440 memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR, 441 &lpc->opb_isa_mem); 442 memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw", 443 &lpc->isa_mem, 0, LPC_FW_OPB_SIZE); 444 memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR, 445 &lpc->opb_isa_fw); 446 447 /* Create MMIO regions for LPC HC and OPB registers */ 448 memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops, 449 lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE); 450 memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR, 451 &lpc->opb_master_regs); 452 memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc, 453 "lpc-hc", LPC_HC_REGS_OPB_SIZE); 454 memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR, 455 &lpc->lpc_hc_regs); 456 457 /* XScom region for LPC registers */ 458 pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), 459 &pnv_lpc_xscom_ops, lpc, "xscom-lpc", 460 PNV_XSCOM_LPC_SIZE); 461 462 /* get PSI object from chip */ 463 obj = object_property_get_link(OBJECT(dev), "psi", &error); 464 if (!obj) { 465 error_setg(errp, "%s: required link 'psi' not found: %s", 466 __func__, error_get_pretty(error)); 467 return; 468 } 469 lpc->psi = PNV_PSI(obj); 470 } 471 472 static void pnv_lpc_class_init(ObjectClass *klass, void *data) 473 { 474 DeviceClass *dc = DEVICE_CLASS(klass); 475 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 476 477 xdc->dt_xscom = pnv_lpc_dt_xscom; 478 479 dc->realize = pnv_lpc_realize; 480 } 481 482 static const TypeInfo pnv_lpc_info = { 483 .name = TYPE_PNV_LPC, 484 .parent = TYPE_DEVICE, 485 .instance_size = sizeof(PnvLpcController), 486 .class_init = pnv_lpc_class_init, 487 .interfaces = (InterfaceInfo[]) { 488 { TYPE_PNV_XSCOM_INTERFACE }, 489 { } 490 } 491 }; 492 493 static void pnv_lpc_register_types(void) 494 { 495 type_register_static(&pnv_lpc_info); 496 } 497 498 type_init(pnv_lpc_register_types) 499 500 /* If we don't use the built-in LPC interrupt deserializer, we need 501 * to provide a set of qirqs for the ISA bus or things will go bad. 502 * 503 * Most machines using pre-Naples chips (without said deserializer) 504 * have a CPLD that will collect the SerIRQ and shoot them as a 505 * single level interrupt to the P8 chip. So let's setup a hook 506 * for doing just that. 507 */ 508 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) 509 { 510 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 511 uint32_t old_state = pnv->cpld_irqstate; 512 PnvLpcController *lpc = PNV_LPC(opaque); 513 514 if (level) { 515 pnv->cpld_irqstate |= 1u << n; 516 } else { 517 pnv->cpld_irqstate &= ~(1u << n); 518 } 519 520 if (pnv->cpld_irqstate != old_state) { 521 pnv_psi_irq_set(lpc->psi, PSIHB_IRQ_EXTERNAL, pnv->cpld_irqstate != 0); 522 } 523 } 524 525 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) 526 { 527 PnvLpcController *lpc = PNV_LPC(opaque); 528 529 /* The Naples HW latches the 1 levels, clearing is done by SW */ 530 if (level) { 531 lpc->lpc_hc_irqstat |= LPC_HC_IRQ_SERIRQ0 >> n; 532 pnv_lpc_eval_irqs(lpc); 533 } 534 } 535 536 qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type, 537 int nirqs) 538 { 539 /* Not all variants have a working serial irq decoder. If not, 540 * handling of LPC interrupts becomes a platform issue (some 541 * platforms have a CPLD to do it). 542 */ 543 if (chip_type == PNV_CHIP_POWER8NVL) { 544 return qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, nirqs); 545 } else { 546 return qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, lpc, nirqs); 547 } 548 } 549