1 /* 2 * QEMU PowerPC PowerNV LPC controller 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/sysemu.h" 22 #include "target-ppc/cpu.h" 23 #include "qapi/error.h" 24 #include "qemu/log.h" 25 26 #include "hw/ppc/pnv_lpc.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/fdt.h" 29 30 #include <libfdt.h> 31 32 enum { 33 ECCB_CTL = 0, 34 ECCB_RESET = 1, 35 ECCB_STAT = 2, 36 ECCB_DATA = 3, 37 }; 38 39 /* OPB Master LS registers */ 40 #define OPB_MASTER_LS_IRQ_STAT 0x50 41 #define OPB_MASTER_IRQ_LPC 0x00000800 42 #define OPB_MASTER_LS_IRQ_MASK 0x54 43 #define OPB_MASTER_LS_IRQ_POL 0x58 44 #define OPB_MASTER_LS_IRQ_INPUT 0x5c 45 46 /* LPC HC registers */ 47 #define LPC_HC_FW_SEG_IDSEL 0x24 48 #define LPC_HC_FW_RD_ACC_SIZE 0x28 49 #define LPC_HC_FW_RD_1B 0x00000000 50 #define LPC_HC_FW_RD_2B 0x01000000 51 #define LPC_HC_FW_RD_4B 0x02000000 52 #define LPC_HC_FW_RD_16B 0x04000000 53 #define LPC_HC_FW_RD_128B 0x07000000 54 #define LPC_HC_IRQSER_CTRL 0x30 55 #define LPC_HC_IRQSER_EN 0x80000000 56 #define LPC_HC_IRQSER_QMODE 0x40000000 57 #define LPC_HC_IRQSER_START_MASK 0x03000000 58 #define LPC_HC_IRQSER_START_4CLK 0x00000000 59 #define LPC_HC_IRQSER_START_6CLK 0x01000000 60 #define LPC_HC_IRQSER_START_8CLK 0x02000000 61 #define LPC_HC_IRQMASK 0x34 /* same bit defs as LPC_HC_IRQSTAT */ 62 #define LPC_HC_IRQSTAT 0x38 63 #define LPC_HC_IRQ_SERIRQ0 0x80000000 /* all bits down to ... */ 64 #define LPC_HC_IRQ_SERIRQ16 0x00008000 /* IRQ16=IOCHK#, IRQ2=SMI# */ 65 #define LPC_HC_IRQ_SERIRQ_ALL 0xffff8000 66 #define LPC_HC_IRQ_LRESET 0x00000400 67 #define LPC_HC_IRQ_SYNC_ABNORM_ERR 0x00000080 68 #define LPC_HC_IRQ_SYNC_NORESP_ERR 0x00000040 69 #define LPC_HC_IRQ_SYNC_NORM_ERR 0x00000020 70 #define LPC_HC_IRQ_SYNC_TIMEOUT_ERR 0x00000010 71 #define LPC_HC_IRQ_SYNC_TARG_TAR_ERR 0x00000008 72 #define LPC_HC_IRQ_SYNC_BM_TAR_ERR 0x00000004 73 #define LPC_HC_IRQ_SYNC_BM0_REQ 0x00000002 74 #define LPC_HC_IRQ_SYNC_BM1_REQ 0x00000001 75 #define LPC_HC_ERROR_ADDRESS 0x40 76 77 #define LPC_OPB_SIZE 0x100000000ull 78 79 #define ISA_IO_SIZE 0x00010000 80 #define ISA_MEM_SIZE 0x10000000 81 #define LPC_IO_OPB_ADDR 0xd0010000 82 #define LPC_IO_OPB_SIZE 0x00010000 83 #define LPC_MEM_OPB_ADDR 0xe0010000 84 #define LPC_MEM_OPB_SIZE 0x10000000 85 #define LPC_FW_OPB_ADDR 0xf0000000 86 #define LPC_FW_OPB_SIZE 0x10000000 87 88 #define LPC_OPB_REGS_OPB_ADDR 0xc0010000 89 #define LPC_OPB_REGS_OPB_SIZE 0x00002000 90 #define LPC_HC_REGS_OPB_ADDR 0xc0012000 91 #define LPC_HC_REGS_OPB_SIZE 0x00001000 92 93 94 /* 95 * TODO: the "primary" cell should only be added on chip 0. This is 96 * how skiboot chooses the default LPC controller on multichip 97 * systems. 98 * 99 * It would be easly done if we can change the populate() interface to 100 * replace the PnvXScomInterface parameter by a PnvChip one 101 */ 102 static int pnv_lpc_populate(PnvXScomInterface *dev, void *fdt, int xscom_offset) 103 { 104 const char compat[] = "ibm,power8-lpc\0ibm,lpc"; 105 char *name; 106 int offset; 107 uint32_t lpc_pcba = PNV_XSCOM_LPC_BASE; 108 uint32_t reg[] = { 109 cpu_to_be32(lpc_pcba), 110 cpu_to_be32(PNV_XSCOM_LPC_SIZE) 111 }; 112 113 name = g_strdup_printf("isa@%x", lpc_pcba); 114 offset = fdt_add_subnode(fdt, xscom_offset, name); 115 _FDT(offset); 116 g_free(name); 117 118 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 119 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 2))); 120 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 1))); 121 _FDT((fdt_setprop(fdt, offset, "primary", NULL, 0))); 122 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 123 return 0; 124 } 125 126 /* 127 * These read/write handlers of the OPB address space should be common 128 * with the P9 LPC Controller which uses direct MMIOs. 129 * 130 * TODO: rework to use address_space_stq() and address_space_ldq() 131 * instead. 132 */ 133 static bool opb_read(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 134 int sz) 135 { 136 bool success; 137 138 /* XXX Handle access size limits and FW read caching here */ 139 success = !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 140 data, sz, false); 141 142 return success; 143 } 144 145 static bool opb_write(PnvLpcController *lpc, uint32_t addr, uint8_t *data, 146 int sz) 147 { 148 bool success; 149 150 /* XXX Handle access size limits here */ 151 success = !address_space_rw(&lpc->opb_as, addr, MEMTXATTRS_UNSPECIFIED, 152 data, sz, true); 153 154 return success; 155 } 156 157 #define ECCB_CTL_READ (1ull << (63 - 15)) 158 #define ECCB_CTL_SZ_LSH (63 - 7) 159 #define ECCB_CTL_SZ_MASK (0xfull << ECCB_CTL_SZ_LSH) 160 #define ECCB_CTL_ADDR_MASK 0xffffffffu; 161 162 #define ECCB_STAT_OP_DONE (1ull << (63 - 52)) 163 #define ECCB_STAT_OP_ERR (1ull << (63 - 52)) 164 #define ECCB_STAT_RD_DATA_LSH (63 - 37) 165 #define ECCB_STAT_RD_DATA_MASK (0xffffffff << ECCB_STAT_RD_DATA_LSH) 166 167 static void pnv_lpc_do_eccb(PnvLpcController *lpc, uint64_t cmd) 168 { 169 /* XXX Check for magic bits at the top, addr size etc... */ 170 unsigned int sz = (cmd & ECCB_CTL_SZ_MASK) >> ECCB_CTL_SZ_LSH; 171 uint32_t opb_addr = cmd & ECCB_CTL_ADDR_MASK; 172 uint8_t data[4]; 173 bool success; 174 175 if (cmd & ECCB_CTL_READ) { 176 success = opb_read(lpc, opb_addr, data, sz); 177 if (success) { 178 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | 179 (((uint64_t)data[0]) << 24 | 180 ((uint64_t)data[1]) << 16 | 181 ((uint64_t)data[2]) << 8 | 182 ((uint64_t)data[3])) << ECCB_STAT_RD_DATA_LSH; 183 } else { 184 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE | 185 (0xffffffffull << ECCB_STAT_RD_DATA_LSH); 186 } 187 } else { 188 data[0] = lpc->eccb_data_reg >> 24; 189 data[1] = lpc->eccb_data_reg >> 16; 190 data[2] = lpc->eccb_data_reg >> 8; 191 data[3] = lpc->eccb_data_reg; 192 193 success = opb_write(lpc, opb_addr, data, sz); 194 lpc->eccb_stat_reg = ECCB_STAT_OP_DONE; 195 } 196 /* XXX Which error bit (if any) to signal OPB error ? */ 197 } 198 199 static uint64_t pnv_lpc_xscom_read(void *opaque, hwaddr addr, unsigned size) 200 { 201 PnvLpcController *lpc = PNV_LPC(opaque); 202 uint32_t offset = addr >> 3; 203 uint64_t val = 0; 204 205 switch (offset & 3) { 206 case ECCB_CTL: 207 case ECCB_RESET: 208 val = 0; 209 break; 210 case ECCB_STAT: 211 val = lpc->eccb_stat_reg; 212 lpc->eccb_stat_reg = 0; 213 break; 214 case ECCB_DATA: 215 val = ((uint64_t)lpc->eccb_data_reg) << 32; 216 break; 217 } 218 return val; 219 } 220 221 static void pnv_lpc_xscom_write(void *opaque, hwaddr addr, 222 uint64_t val, unsigned size) 223 { 224 PnvLpcController *lpc = PNV_LPC(opaque); 225 uint32_t offset = addr >> 3; 226 227 switch (offset & 3) { 228 case ECCB_CTL: 229 pnv_lpc_do_eccb(lpc, val); 230 break; 231 case ECCB_RESET: 232 /* XXXX */ 233 break; 234 case ECCB_STAT: 235 break; 236 case ECCB_DATA: 237 lpc->eccb_data_reg = val >> 32; 238 break; 239 } 240 } 241 242 static const MemoryRegionOps pnv_lpc_xscom_ops = { 243 .read = pnv_lpc_xscom_read, 244 .write = pnv_lpc_xscom_write, 245 .valid.min_access_size = 8, 246 .valid.max_access_size = 8, 247 .impl.min_access_size = 8, 248 .impl.max_access_size = 8, 249 .endianness = DEVICE_BIG_ENDIAN, 250 }; 251 252 static uint64_t lpc_hc_read(void *opaque, hwaddr addr, unsigned size) 253 { 254 PnvLpcController *lpc = opaque; 255 uint64_t val = 0xfffffffffffffffful; 256 257 switch (addr) { 258 case LPC_HC_FW_SEG_IDSEL: 259 val = lpc->lpc_hc_fw_seg_idsel; 260 break; 261 case LPC_HC_FW_RD_ACC_SIZE: 262 val = lpc->lpc_hc_fw_rd_acc_size; 263 break; 264 case LPC_HC_IRQSER_CTRL: 265 val = lpc->lpc_hc_irqser_ctrl; 266 break; 267 case LPC_HC_IRQMASK: 268 val = lpc->lpc_hc_irqmask; 269 break; 270 case LPC_HC_IRQSTAT: 271 val = lpc->lpc_hc_irqstat; 272 break; 273 case LPC_HC_ERROR_ADDRESS: 274 val = lpc->lpc_hc_error_addr; 275 break; 276 default: 277 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%" 278 HWADDR_PRIx "\n", addr); 279 } 280 return val; 281 } 282 283 static void lpc_hc_write(void *opaque, hwaddr addr, uint64_t val, 284 unsigned size) 285 { 286 PnvLpcController *lpc = opaque; 287 288 /* XXX Filter out reserved bits */ 289 290 switch (addr) { 291 case LPC_HC_FW_SEG_IDSEL: 292 /* XXX Actually figure out how that works as this impact 293 * memory regions/aliases 294 */ 295 lpc->lpc_hc_fw_seg_idsel = val; 296 break; 297 case LPC_HC_FW_RD_ACC_SIZE: 298 lpc->lpc_hc_fw_rd_acc_size = val; 299 break; 300 case LPC_HC_IRQSER_CTRL: 301 lpc->lpc_hc_irqser_ctrl = val; 302 break; 303 case LPC_HC_IRQMASK: 304 lpc->lpc_hc_irqmask = val; 305 break; 306 case LPC_HC_IRQSTAT: 307 lpc->lpc_hc_irqstat &= ~val; 308 break; 309 case LPC_HC_ERROR_ADDRESS: 310 break; 311 default: 312 qemu_log_mask(LOG_UNIMP, "LPC HC Unimplemented register: Ox%" 313 HWADDR_PRIx "\n", addr); 314 } 315 } 316 317 static const MemoryRegionOps lpc_hc_ops = { 318 .read = lpc_hc_read, 319 .write = lpc_hc_write, 320 .endianness = DEVICE_BIG_ENDIAN, 321 .valid = { 322 .min_access_size = 4, 323 .max_access_size = 4, 324 }, 325 .impl = { 326 .min_access_size = 4, 327 .max_access_size = 4, 328 }, 329 }; 330 331 static uint64_t opb_master_read(void *opaque, hwaddr addr, unsigned size) 332 { 333 PnvLpcController *lpc = opaque; 334 uint64_t val = 0xfffffffffffffffful; 335 336 switch (addr) { 337 case OPB_MASTER_LS_IRQ_STAT: 338 val = lpc->opb_irq_stat; 339 break; 340 case OPB_MASTER_LS_IRQ_MASK: 341 val = lpc->opb_irq_mask; 342 break; 343 case OPB_MASTER_LS_IRQ_POL: 344 val = lpc->opb_irq_pol; 345 break; 346 case OPB_MASTER_LS_IRQ_INPUT: 347 val = lpc->opb_irq_input; 348 break; 349 default: 350 qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%" 351 HWADDR_PRIx "\n", addr); 352 } 353 354 return val; 355 } 356 357 static void opb_master_write(void *opaque, hwaddr addr, 358 uint64_t val, unsigned size) 359 { 360 PnvLpcController *lpc = opaque; 361 362 switch (addr) { 363 case OPB_MASTER_LS_IRQ_STAT: 364 lpc->opb_irq_stat &= ~val; 365 break; 366 case OPB_MASTER_LS_IRQ_MASK: 367 /* XXX Filter out reserved bits */ 368 lpc->opb_irq_mask = val; 369 break; 370 case OPB_MASTER_LS_IRQ_POL: 371 /* XXX Filter out reserved bits */ 372 lpc->opb_irq_pol = val; 373 break; 374 case OPB_MASTER_LS_IRQ_INPUT: 375 /* Read only */ 376 break; 377 default: 378 qemu_log_mask(LOG_UNIMP, "OPB MASTER Unimplemented register: Ox%" 379 HWADDR_PRIx "\n", addr); 380 } 381 } 382 383 static const MemoryRegionOps opb_master_ops = { 384 .read = opb_master_read, 385 .write = opb_master_write, 386 .endianness = DEVICE_BIG_ENDIAN, 387 .valid = { 388 .min_access_size = 4, 389 .max_access_size = 4, 390 }, 391 .impl = { 392 .min_access_size = 4, 393 .max_access_size = 4, 394 }, 395 }; 396 397 static void pnv_lpc_realize(DeviceState *dev, Error **errp) 398 { 399 PnvLpcController *lpc = PNV_LPC(dev); 400 401 /* Reg inits */ 402 lpc->lpc_hc_fw_rd_acc_size = LPC_HC_FW_RD_4B; 403 404 /* Create address space and backing MR for the OPB bus */ 405 memory_region_init(&lpc->opb_mr, OBJECT(dev), "lpc-opb", 0x100000000ull); 406 address_space_init(&lpc->opb_as, &lpc->opb_mr, "lpc-opb"); 407 408 /* Create ISA IO and Mem space regions which are the root of 409 * the ISA bus (ie, ISA address spaces). We don't create a 410 * separate one for FW which we alias to memory. 411 */ 412 memory_region_init(&lpc->isa_io, OBJECT(dev), "isa-io", ISA_IO_SIZE); 413 memory_region_init(&lpc->isa_mem, OBJECT(dev), "isa-mem", ISA_MEM_SIZE); 414 415 /* Create windows from the OPB space to the ISA space */ 416 memory_region_init_alias(&lpc->opb_isa_io, OBJECT(dev), "lpc-isa-io", 417 &lpc->isa_io, 0, LPC_IO_OPB_SIZE); 418 memory_region_add_subregion(&lpc->opb_mr, LPC_IO_OPB_ADDR, 419 &lpc->opb_isa_io); 420 memory_region_init_alias(&lpc->opb_isa_mem, OBJECT(dev), "lpc-isa-mem", 421 &lpc->isa_mem, 0, LPC_MEM_OPB_SIZE); 422 memory_region_add_subregion(&lpc->opb_mr, LPC_MEM_OPB_ADDR, 423 &lpc->opb_isa_mem); 424 memory_region_init_alias(&lpc->opb_isa_fw, OBJECT(dev), "lpc-isa-fw", 425 &lpc->isa_mem, 0, LPC_FW_OPB_SIZE); 426 memory_region_add_subregion(&lpc->opb_mr, LPC_FW_OPB_ADDR, 427 &lpc->opb_isa_fw); 428 429 /* Create MMIO regions for LPC HC and OPB registers */ 430 memory_region_init_io(&lpc->opb_master_regs, OBJECT(dev), &opb_master_ops, 431 lpc, "lpc-opb-master", LPC_OPB_REGS_OPB_SIZE); 432 memory_region_add_subregion(&lpc->opb_mr, LPC_OPB_REGS_OPB_ADDR, 433 &lpc->opb_master_regs); 434 memory_region_init_io(&lpc->lpc_hc_regs, OBJECT(dev), &lpc_hc_ops, lpc, 435 "lpc-hc", LPC_HC_REGS_OPB_SIZE); 436 memory_region_add_subregion(&lpc->opb_mr, LPC_HC_REGS_OPB_ADDR, 437 &lpc->lpc_hc_regs); 438 439 /* XScom region for LPC registers */ 440 pnv_xscom_region_init(&lpc->xscom_regs, OBJECT(dev), 441 &pnv_lpc_xscom_ops, lpc, "xscom-lpc", 442 PNV_XSCOM_LPC_SIZE); 443 } 444 445 static void pnv_lpc_class_init(ObjectClass *klass, void *data) 446 { 447 DeviceClass *dc = DEVICE_CLASS(klass); 448 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 449 450 xdc->populate = pnv_lpc_populate; 451 452 dc->realize = pnv_lpc_realize; 453 } 454 455 static const TypeInfo pnv_lpc_info = { 456 .name = TYPE_PNV_LPC, 457 .parent = TYPE_DEVICE, 458 .instance_size = sizeof(PnvLpcController), 459 .class_init = pnv_lpc_class_init, 460 .interfaces = (InterfaceInfo[]) { 461 { TYPE_PNV_XSCOM_INTERFACE }, 462 { } 463 } 464 }; 465 466 static void pnv_lpc_register_types(void) 467 { 468 type_register_static(&pnv_lpc_info); 469 } 470 471 type_init(pnv_lpc_register_types) 472