1 /* 2 * QEMU PowerPC PowerNV Processor I2C model 3 * 4 * Copyright (c) 2019-2023, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/module.h" 11 #include "qemu/log.h" 12 #include "sysemu/reset.h" 13 14 #include "hw/irq.h" 15 #include "hw/qdev-properties.h" 16 17 #include "hw/ppc/pnv.h" 18 #include "hw/ppc/pnv_chip.h" 19 #include "hw/ppc/pnv_i2c.h" 20 #include "hw/ppc/pnv_xscom.h" 21 #include "hw/ppc/fdt.h" 22 23 #include <libfdt.h> 24 25 /* I2C FIFO register */ 26 #define I2C_FIFO_REG 0x4 27 #define I2C_FIFO PPC_BITMASK(0, 7) 28 29 /* I2C command register */ 30 #define I2C_CMD_REG 0x5 31 #define I2C_CMD_WITH_START PPC_BIT(0) 32 #define I2C_CMD_WITH_ADDR PPC_BIT(1) 33 #define I2C_CMD_READ_CONT PPC_BIT(2) 34 #define I2C_CMD_WITH_STOP PPC_BIT(3) 35 #define I2C_CMD_INTR_STEERING PPC_BITMASK(6, 7) /* P9 */ 36 #define I2C_CMD_INTR_STEER_HOST 1 37 #define I2C_CMD_INTR_STEER_OCC 2 38 #define I2C_CMD_DEV_ADDR PPC_BITMASK(8, 14) 39 #define I2C_CMD_READ_NOT_WRITE PPC_BIT(15) 40 #define I2C_CMD_LEN_BYTES PPC_BITMASK(16, 31) 41 #define I2C_MAX_TFR_LEN 0xfff0ull 42 43 /* I2C mode register */ 44 #define I2C_MODE_REG 0x6 45 #define I2C_MODE_BIT_RATE_DIV PPC_BITMASK(0, 15) 46 #define I2C_MODE_PORT_NUM PPC_BITMASK(16, 21) 47 #define I2C_MODE_ENHANCED PPC_BIT(28) 48 #define I2C_MODE_DIAGNOSTIC PPC_BIT(29) 49 #define I2C_MODE_PACING_ALLOW PPC_BIT(30) 50 #define I2C_MODE_WRAP PPC_BIT(31) 51 52 /* I2C watermark register */ 53 #define I2C_WATERMARK_REG 0x7 54 #define I2C_WATERMARK_HIGH PPC_BITMASK(16, 19) 55 #define I2C_WATERMARK_LOW PPC_BITMASK(24, 27) 56 57 /* 58 * I2C interrupt mask and condition registers 59 * 60 * NB: The function of 0x9 and 0xa changes depending on whether you're reading 61 * or writing to them. When read they return the interrupt condition bits 62 * and on writes they update the interrupt mask register. 63 * 64 * The bit definitions are the same for all the interrupt registers. 65 */ 66 #define I2C_INTR_MASK_REG 0x8 67 68 #define I2C_INTR_RAW_COND_REG 0x9 /* read */ 69 #define I2C_INTR_MASK_OR_REG 0x9 /* write*/ 70 71 #define I2C_INTR_COND_REG 0xa /* read */ 72 #define I2C_INTR_MASK_AND_REG 0xa /* write */ 73 74 #define I2C_INTR_ALL PPC_BITMASK(16, 31) 75 #define I2C_INTR_INVALID_CMD PPC_BIT(16) 76 #define I2C_INTR_LBUS_PARITY_ERR PPC_BIT(17) 77 #define I2C_INTR_BKEND_OVERRUN_ERR PPC_BIT(18) 78 #define I2C_INTR_BKEND_ACCESS_ERR PPC_BIT(19) 79 #define I2C_INTR_ARBT_LOST_ERR PPC_BIT(20) 80 #define I2C_INTR_NACK_RCVD_ERR PPC_BIT(21) 81 #define I2C_INTR_DATA_REQ PPC_BIT(22) 82 #define I2C_INTR_CMD_COMP PPC_BIT(23) 83 #define I2C_INTR_STOP_ERR PPC_BIT(24) 84 #define I2C_INTR_I2C_BUSY PPC_BIT(25) 85 #define I2C_INTR_NOT_I2C_BUSY PPC_BIT(26) 86 #define I2C_INTR_SCL_EQ_1 PPC_BIT(28) 87 #define I2C_INTR_SCL_EQ_0 PPC_BIT(29) 88 #define I2C_INTR_SDA_EQ_1 PPC_BIT(30) 89 #define I2C_INTR_SDA_EQ_0 PPC_BIT(31) 90 91 /* I2C status register */ 92 #define I2C_RESET_I2C_REG 0xb /* write */ 93 #define I2C_RESET_ERRORS 0xc 94 #define I2C_STAT_REG 0xb /* read */ 95 #define I2C_STAT_INVALID_CMD PPC_BIT(0) 96 #define I2C_STAT_LBUS_PARITY_ERR PPC_BIT(1) 97 #define I2C_STAT_BKEND_OVERRUN_ERR PPC_BIT(2) 98 #define I2C_STAT_BKEND_ACCESS_ERR PPC_BIT(3) 99 #define I2C_STAT_ARBT_LOST_ERR PPC_BIT(4) 100 #define I2C_STAT_NACK_RCVD_ERR PPC_BIT(5) 101 #define I2C_STAT_DATA_REQ PPC_BIT(6) 102 #define I2C_STAT_CMD_COMP PPC_BIT(7) 103 #define I2C_STAT_STOP_ERR PPC_BIT(8) 104 #define I2C_STAT_UPPER_THRS PPC_BITMASK(9, 15) 105 #define I2C_STAT_ANY_I2C_INTR PPC_BIT(16) 106 #define I2C_STAT_PORT_HISTORY_BUSY PPC_BIT(19) 107 #define I2C_STAT_SCL_INPUT_LEVEL PPC_BIT(20) 108 #define I2C_STAT_SDA_INPUT_LEVEL PPC_BIT(21) 109 #define I2C_STAT_PORT_BUSY PPC_BIT(22) 110 #define I2C_STAT_INTERFACE_BUSY PPC_BIT(23) 111 #define I2C_STAT_FIFO_ENTRY_COUNT PPC_BITMASK(24, 31) 112 113 #define I2C_STAT_ANY_ERR (I2C_STAT_INVALID_CMD | I2C_STAT_LBUS_PARITY_ERR | \ 114 I2C_STAT_BKEND_OVERRUN_ERR | \ 115 I2C_STAT_BKEND_ACCESS_ERR | I2C_STAT_ARBT_LOST_ERR | \ 116 I2C_STAT_NACK_RCVD_ERR | I2C_STAT_STOP_ERR) 117 118 119 #define I2C_INTR_ACTIVE \ 120 ((I2C_STAT_ANY_ERR >> 16) | I2C_INTR_CMD_COMP | I2C_INTR_DATA_REQ) 121 122 /* Pseudo-status used for timeouts */ 123 #define I2C_STAT_PSEUDO_TIMEOUT PPC_BIT(63) 124 125 /* I2C extended status register */ 126 #define I2C_EXTD_STAT_REG 0xc 127 #define I2C_EXTD_STAT_FIFO_SIZE PPC_BITMASK(0, 7) 128 #define I2C_EXTD_STAT_MSM_CURSTATE PPC_BITMASK(11, 15) 129 #define I2C_EXTD_STAT_SCL_IN_SYNC PPC_BIT(16) 130 #define I2C_EXTD_STAT_SDA_IN_SYNC PPC_BIT(17) 131 #define I2C_EXTD_STAT_S_SCL PPC_BIT(18) 132 #define I2C_EXTD_STAT_S_SDA PPC_BIT(19) 133 #define I2C_EXTD_STAT_M_SCL PPC_BIT(20) 134 #define I2C_EXTD_STAT_M_SDA PPC_BIT(21) 135 #define I2C_EXTD_STAT_HIGH_WATER PPC_BIT(22) 136 #define I2C_EXTD_STAT_LOW_WATER PPC_BIT(23) 137 #define I2C_EXTD_STAT_I2C_BUSY PPC_BIT(24) 138 #define I2C_EXTD_STAT_SELF_BUSY PPC_BIT(25) 139 #define I2C_EXTD_STAT_I2C_VERSION PPC_BITMASK(27, 31) 140 141 /* I2C residual front end/back end length */ 142 #define I2C_RESIDUAL_LEN_REG 0xd 143 #define I2C_RESIDUAL_FRONT_END PPC_BITMASK(0, 15) 144 #define I2C_RESIDUAL_BACK_END PPC_BITMASK(16, 31) 145 146 /* Port busy register */ 147 #define I2C_PORT_BUSY_REG 0xe 148 #define I2C_SET_S_SCL_REG 0xd 149 #define I2C_RESET_S_SCL_REG 0xf 150 #define I2C_SET_S_SDA_REG 0x10 151 #define I2C_RESET_S_SDA_REG 0x11 152 153 #define PNV_I2C_FIFO_SIZE 8 154 155 static I2CBus *pnv_i2c_get_bus(PnvI2C *i2c) 156 { 157 uint8_t port = GETFIELD(I2C_MODE_PORT_NUM, i2c->regs[I2C_MODE_REG]); 158 159 if (port >= i2c->num_busses) { 160 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid bus number %d/%d\n", port, 161 i2c->num_busses); 162 return NULL; 163 } 164 return i2c->busses[port]; 165 } 166 167 static void pnv_i2c_update_irq(PnvI2C *i2c) 168 { 169 I2CBus *bus = pnv_i2c_get_bus(i2c); 170 bool recv = !!(i2c->regs[I2C_CMD_REG] & I2C_CMD_READ_NOT_WRITE); 171 uint16_t front_end = GETFIELD(I2C_RESIDUAL_FRONT_END, 172 i2c->regs[I2C_RESIDUAL_LEN_REG]); 173 uint16_t back_end = GETFIELD(I2C_RESIDUAL_BACK_END, 174 i2c->regs[I2C_RESIDUAL_LEN_REG]); 175 uint8_t fifo_count = GETFIELD(I2C_STAT_FIFO_ENTRY_COUNT, 176 i2c->regs[I2C_STAT_REG]); 177 uint8_t fifo_free = PNV_I2C_FIFO_SIZE - fifo_count; 178 179 if (!bus) { 180 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); 181 return; 182 } 183 184 if (i2c_bus_busy(bus)) { 185 i2c->regs[I2C_STAT_REG] &= ~I2C_STAT_DATA_REQ; 186 187 if (recv) { 188 if (fifo_count >= 189 GETFIELD(I2C_WATERMARK_HIGH, i2c->regs[I2C_WATERMARK_REG])) { 190 i2c->regs[I2C_EXTD_STAT_REG] |= I2C_EXTD_STAT_HIGH_WATER; 191 } else { 192 i2c->regs[I2C_EXTD_STAT_REG] &= ~I2C_EXTD_STAT_HIGH_WATER; 193 } 194 195 if (((i2c->regs[I2C_EXTD_STAT_REG] & I2C_EXTD_STAT_HIGH_WATER) && 196 fifo_count != 0) || front_end == 0) { 197 i2c->regs[I2C_STAT_REG] |= I2C_STAT_DATA_REQ; 198 } 199 } else { 200 if (fifo_count <= 201 GETFIELD(I2C_WATERMARK_LOW, i2c->regs[I2C_WATERMARK_REG])) { 202 i2c->regs[I2C_EXTD_STAT_REG] |= I2C_EXTD_STAT_LOW_WATER; 203 } else { 204 i2c->regs[I2C_EXTD_STAT_REG] &= ~I2C_EXTD_STAT_LOW_WATER; 205 } 206 207 if (back_end > 0 && 208 (fifo_free >= back_end || 209 (i2c->regs[I2C_EXTD_STAT_REG] & I2C_EXTD_STAT_LOW_WATER))) { 210 i2c->regs[I2C_STAT_REG] |= I2C_STAT_DATA_REQ; 211 } 212 } 213 214 if (back_end == 0 && front_end == 0) { 215 i2c->regs[I2C_STAT_REG] &= ~I2C_STAT_DATA_REQ; 216 i2c->regs[I2C_STAT_REG] |= I2C_STAT_CMD_COMP; 217 218 if (i2c->regs[I2C_CMD_REG] & I2C_CMD_WITH_STOP) { 219 i2c_end_transfer(bus); 220 i2c->regs[I2C_EXTD_STAT_REG] &= 221 ~(I2C_EXTD_STAT_I2C_BUSY | I2C_EXTD_STAT_SELF_BUSY); 222 } 223 } else { 224 i2c->regs[I2C_STAT_REG] &= ~I2C_STAT_CMD_COMP; 225 } 226 } 227 228 /* 229 * Status and interrupt registers have nearly the same layout. 230 */ 231 i2c->regs[I2C_INTR_RAW_COND_REG] = i2c->regs[I2C_STAT_REG] >> 16; 232 i2c->regs[I2C_INTR_COND_REG] = 233 i2c->regs[I2C_INTR_RAW_COND_REG] & i2c->regs[I2C_INTR_MASK_REG]; 234 235 qemu_set_irq(i2c->psi_irq, i2c->regs[I2C_INTR_COND_REG] != 0); 236 } 237 238 static void pnv_i2c_fifo_update_count(PnvI2C *i2c) 239 { 240 uint64_t stat = i2c->regs[I2C_STAT_REG]; 241 242 i2c->regs[I2C_STAT_REG] = SETFIELD(I2C_STAT_FIFO_ENTRY_COUNT, stat, 243 fifo8_num_used(&i2c->fifo)); 244 } 245 246 static void pnv_i2c_frontend_update(PnvI2C *i2c) 247 { 248 uint64_t residual_end = i2c->regs[I2C_RESIDUAL_LEN_REG]; 249 uint16_t front_end = GETFIELD(I2C_RESIDUAL_FRONT_END, residual_end); 250 251 i2c->regs[I2C_RESIDUAL_LEN_REG] = 252 SETFIELD(I2C_RESIDUAL_FRONT_END, residual_end, front_end - 1); 253 } 254 255 static void pnv_i2c_fifo_flush(PnvI2C *i2c) 256 { 257 I2CBus *bus = pnv_i2c_get_bus(i2c); 258 uint8_t data; 259 int ret; 260 261 if (!bus) { 262 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); 263 return; 264 } 265 if (!i2c_bus_busy(bus)) { 266 return; 267 } 268 269 if (i2c->regs[I2C_CMD_REG] & I2C_CMD_READ_NOT_WRITE) { 270 if (fifo8_is_full(&i2c->fifo)) { 271 return; 272 } 273 274 data = i2c_recv(bus); 275 fifo8_push(&i2c->fifo, data); 276 } else { 277 if (fifo8_is_empty(&i2c->fifo)) { 278 return; 279 } 280 281 data = fifo8_pop(&i2c->fifo); 282 ret = i2c_send(bus, data); 283 if (ret) { 284 i2c->regs[I2C_STAT_REG] |= I2C_STAT_NACK_RCVD_ERR; 285 i2c_end_transfer(bus); 286 } 287 } 288 289 pnv_i2c_fifo_update_count(i2c); 290 pnv_i2c_frontend_update(i2c); 291 } 292 293 static void pnv_i2c_handle_cmd(PnvI2C *i2c, uint64_t val) 294 { 295 I2CBus *bus = pnv_i2c_get_bus(i2c); 296 uint8_t addr = GETFIELD(I2C_CMD_DEV_ADDR, val); 297 int recv = !!(val & I2C_CMD_READ_NOT_WRITE); 298 uint32_t len_bytes = GETFIELD(I2C_CMD_LEN_BYTES, val); 299 300 if (!(val & I2C_CMD_WITH_START) && !(val & I2C_CMD_WITH_ADDR) && 301 !(val & I2C_CMD_WITH_STOP) && !len_bytes) { 302 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD; 303 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid command 0x%"PRIx64"\n", 304 val); 305 return; 306 } 307 308 if (!(i2c->regs[I2C_STAT_REG] & I2C_STAT_CMD_COMP)) { 309 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD; 310 qemu_log_mask(LOG_GUEST_ERROR, "I2C: command in progress\n"); 311 return; 312 } 313 314 if (!bus) { 315 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); 316 return; 317 } 318 319 i2c->regs[I2C_RESIDUAL_LEN_REG] = 320 SETFIELD(I2C_RESIDUAL_FRONT_END, 0ull, len_bytes) | 321 SETFIELD(I2C_RESIDUAL_BACK_END, 0ull, len_bytes); 322 323 if (val & I2C_CMD_WITH_START) { 324 if (i2c_start_transfer(bus, addr, recv)) { 325 i2c->regs[I2C_STAT_REG] |= I2C_STAT_NACK_RCVD_ERR; 326 } else { 327 i2c->regs[I2C_EXTD_STAT_REG] |= 328 (I2C_EXTD_STAT_I2C_BUSY | I2C_EXTD_STAT_SELF_BUSY); 329 pnv_i2c_fifo_flush(i2c); 330 } 331 } 332 } 333 334 static void pnv_i2c_backend_update(PnvI2C *i2c) 335 { 336 uint64_t residual_end = i2c->regs[I2C_RESIDUAL_LEN_REG]; 337 uint16_t back_end = GETFIELD(I2C_RESIDUAL_BACK_END, residual_end); 338 339 if (!back_end) { 340 i2c->regs[I2C_STAT_REG] |= I2C_STAT_BKEND_ACCESS_ERR; 341 return; 342 } 343 344 i2c->regs[I2C_RESIDUAL_LEN_REG] = 345 SETFIELD(I2C_RESIDUAL_BACK_END, residual_end, back_end - 1); 346 } 347 348 static void pnv_i2c_fifo_in(PnvI2C *i2c) 349 { 350 uint8_t data = GETFIELD(I2C_FIFO, i2c->regs[I2C_FIFO_REG]); 351 I2CBus *bus = pnv_i2c_get_bus(i2c); 352 353 if (!bus) { 354 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); 355 return; 356 } 357 358 if (!i2c_bus_busy(bus)) { 359 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD; 360 qemu_log_mask(LOG_GUEST_ERROR, "I2C: no command in progress\n"); 361 return; 362 } 363 364 if (i2c->regs[I2C_CMD_REG] & I2C_CMD_READ_NOT_WRITE) { 365 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD; 366 qemu_log_mask(LOG_GUEST_ERROR, "I2C: read command in progress\n"); 367 return; 368 } 369 370 if (fifo8_is_full(&i2c->fifo)) { 371 if (!(i2c->regs[I2C_MODE_REG] & I2C_MODE_PACING_ALLOW)) { 372 i2c->regs[I2C_STAT_REG] |= I2C_STAT_BKEND_OVERRUN_ERR; 373 } 374 return; 375 } 376 377 fifo8_push(&i2c->fifo, data); 378 pnv_i2c_fifo_update_count(i2c); 379 pnv_i2c_backend_update(i2c); 380 pnv_i2c_fifo_flush(i2c); 381 } 382 383 static void pnv_i2c_fifo_out(PnvI2C *i2c) 384 { 385 uint8_t data; 386 I2CBus *bus = pnv_i2c_get_bus(i2c); 387 388 if (!bus) { 389 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); 390 return; 391 } 392 393 if (!i2c_bus_busy(bus)) { 394 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD; 395 qemu_log_mask(LOG_GUEST_ERROR, "I2C: no command in progress\n"); 396 return; 397 } 398 399 if (!(i2c->regs[I2C_CMD_REG] & I2C_CMD_READ_NOT_WRITE)) { 400 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD; 401 qemu_log_mask(LOG_GUEST_ERROR, "I2C: write command in progress\n"); 402 return; 403 } 404 405 if (fifo8_is_empty(&i2c->fifo)) { 406 if (!(i2c->regs[I2C_MODE_REG] & I2C_MODE_PACING_ALLOW)) { 407 i2c->regs[I2C_STAT_REG] |= I2C_STAT_BKEND_OVERRUN_ERR; 408 } 409 return; 410 } 411 412 data = fifo8_pop(&i2c->fifo); 413 414 i2c->regs[I2C_FIFO_REG] = SETFIELD(I2C_FIFO, 0ull, data); 415 pnv_i2c_fifo_update_count(i2c); 416 pnv_i2c_backend_update(i2c); 417 } 418 419 static uint64_t pnv_i2c_xscom_read(void *opaque, hwaddr addr, 420 unsigned size) 421 { 422 PnvI2C *i2c = PNV_I2C(opaque); 423 uint32_t offset = addr >> 3; 424 uint64_t val = -1; 425 int i; 426 427 switch (offset) { 428 case I2C_STAT_REG: 429 val = i2c->regs[offset]; 430 break; 431 432 case I2C_FIFO_REG: 433 pnv_i2c_fifo_out(i2c); 434 val = i2c->regs[offset]; 435 break; 436 437 case I2C_PORT_BUSY_REG: /* compute busy bit for each port */ 438 val = 0; 439 for (i = 0; i < i2c->num_busses; i++) { 440 val |= i2c_bus_busy(i2c->busses[i]) << i; 441 } 442 break; 443 444 case I2C_CMD_REG: 445 case I2C_MODE_REG: 446 case I2C_WATERMARK_REG: 447 case I2C_INTR_MASK_REG: 448 case I2C_INTR_RAW_COND_REG: 449 case I2C_INTR_COND_REG: 450 case I2C_EXTD_STAT_REG: 451 case I2C_RESIDUAL_LEN_REG: 452 val = i2c->regs[offset]; 453 break; 454 default: 455 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD; 456 qemu_log_mask(LOG_GUEST_ERROR, "I2C: read at register: 0x%" 457 HWADDR_PRIx "\n", addr >> 3); 458 } 459 460 pnv_i2c_update_irq(i2c); 461 462 return val; 463 } 464 465 static void pnv_i2c_xscom_write(void *opaque, hwaddr addr, 466 uint64_t val, unsigned size) 467 { 468 PnvI2C *i2c = PNV_I2C(opaque); 469 uint32_t offset = addr >> 3; 470 471 switch (offset) { 472 case I2C_MODE_REG: 473 { 474 i2c->regs[offset] = val; 475 I2CBus *bus = pnv_i2c_get_bus(i2c); 476 if (!bus) { 477 qemu_log_mask(LOG_GUEST_ERROR, "I2C: invalid port\n"); 478 return; 479 } 480 if (i2c_bus_busy(bus)) { 481 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD; 482 qemu_log_mask(LOG_GUEST_ERROR, "I2C: command in progress\n"); 483 } 484 } 485 break; 486 487 case I2C_CMD_REG: 488 i2c->regs[offset] = val; 489 pnv_i2c_handle_cmd(i2c, val); 490 break; 491 492 case I2C_FIFO_REG: 493 i2c->regs[offset] = val; 494 pnv_i2c_fifo_in(i2c); 495 break; 496 497 case I2C_WATERMARK_REG: 498 i2c->regs[offset] = val; 499 break; 500 501 case I2C_RESET_I2C_REG: 502 i2c->regs[I2C_MODE_REG] = 0; 503 i2c->regs[I2C_CMD_REG] = 0; 504 i2c->regs[I2C_WATERMARK_REG] = 0; 505 i2c->regs[I2C_INTR_MASK_REG] = 0; 506 i2c->regs[I2C_INTR_COND_REG] = 0; 507 i2c->regs[I2C_INTR_RAW_COND_REG] = 0; 508 i2c->regs[I2C_STAT_REG] = 0; 509 i2c->regs[I2C_RESIDUAL_LEN_REG] = 0; 510 i2c->regs[I2C_EXTD_STAT_REG] &= 511 (I2C_EXTD_STAT_FIFO_SIZE | I2C_EXTD_STAT_I2C_VERSION); 512 break; 513 514 case I2C_RESET_ERRORS: 515 i2c->regs[I2C_STAT_REG] &= ~I2C_STAT_ANY_ERR; 516 i2c->regs[I2C_RESIDUAL_LEN_REG] = 0; 517 i2c->regs[I2C_EXTD_STAT_REG] &= 518 (I2C_EXTD_STAT_FIFO_SIZE | I2C_EXTD_STAT_I2C_VERSION); 519 fifo8_reset(&i2c->fifo); 520 break; 521 522 case I2C_INTR_MASK_REG: 523 i2c->regs[offset] = val; 524 break; 525 526 case I2C_INTR_MASK_OR_REG: 527 i2c->regs[I2C_INTR_MASK_REG] |= val; 528 break; 529 530 case I2C_INTR_MASK_AND_REG: 531 i2c->regs[I2C_INTR_MASK_REG] &= val; 532 break; 533 534 case I2C_PORT_BUSY_REG: 535 case I2C_SET_S_SCL_REG: 536 case I2C_RESET_S_SCL_REG: 537 case I2C_SET_S_SDA_REG: 538 case I2C_RESET_S_SDA_REG: 539 i2c->regs[offset] = val; 540 break; 541 default: 542 i2c->regs[I2C_STAT_REG] |= I2C_STAT_INVALID_CMD; 543 qemu_log_mask(LOG_GUEST_ERROR, "I2C: write at register: 0x%" 544 HWADDR_PRIx " val=0x%"PRIx64"\n", addr >> 3, val); 545 } 546 547 pnv_i2c_update_irq(i2c); 548 } 549 550 static const MemoryRegionOps pnv_i2c_xscom_ops = { 551 .read = pnv_i2c_xscom_read, 552 .write = pnv_i2c_xscom_write, 553 .valid.min_access_size = 8, 554 .valid.max_access_size = 8, 555 .impl.min_access_size = 8, 556 .impl.max_access_size = 8, 557 .endianness = DEVICE_BIG_ENDIAN, 558 }; 559 560 static int pnv_i2c_bus_dt_xscom(PnvI2C *i2c, void *fdt, 561 int offset, int index) 562 { 563 int i2c_bus_offset; 564 const char i2c_compat[] = 565 "ibm,opal-i2c\0ibm,power8-i2c-port\0ibm,power9-i2c-port"; 566 g_autofree char *i2c_port_name = NULL; 567 g_autofree char *name = g_strdup_printf("i2c-bus@%x", index); 568 569 i2c_bus_offset = fdt_add_subnode(fdt, offset, name); 570 _FDT(i2c_bus_offset); 571 572 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "reg", index))); 573 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "#address-cells", 1))); 574 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "#size-cells", 0))); 575 _FDT(fdt_setprop(fdt, i2c_bus_offset, "compatible", i2c_compat, 576 sizeof(i2c_compat))); 577 _FDT((fdt_setprop_cell(fdt, i2c_bus_offset, "bus-frequency", 400000))); 578 579 i2c_port_name = g_strdup_printf("p8_%08x_e%dp%d", i2c->chip->chip_id, 580 i2c->engine, index); 581 _FDT(fdt_setprop_string(fdt, i2c_bus_offset, "ibm,port-name", 582 i2c_port_name)); 583 return 0; 584 } 585 586 #define XSCOM_BUS_FREQUENCY 466500000 587 #define I2C_CLOCK_FREQUENCY (XSCOM_BUS_FREQUENCY / 4) 588 589 static int pnv_i2c_dt_xscom(PnvXScomInterface *dev, void *fdt, 590 int offset) 591 { 592 PnvI2C *i2c = PNV_I2C(dev); 593 int i2c_offset; 594 const char i2c_compat[] = "ibm,power8-i2cm\0ibm,power9-i2cm"; 595 uint32_t i2c_pcba = PNV9_XSCOM_I2CM_BASE + 596 i2c->engine * PNV9_XSCOM_I2CM_SIZE; 597 uint32_t reg[2] = { 598 cpu_to_be32(i2c_pcba), 599 cpu_to_be32(PNV9_XSCOM_I2CM_SIZE) 600 }; 601 int i; 602 g_autofree char *name = g_strdup_printf("i2cm@%x", i2c_pcba); 603 604 i2c_offset = fdt_add_subnode(fdt, offset, name); 605 _FDT(i2c_offset); 606 607 _FDT(fdt_setprop(fdt, i2c_offset, "reg", reg, sizeof(reg))); 608 609 _FDT((fdt_setprop_cell(fdt, i2c_offset, "#address-cells", 1))); 610 _FDT((fdt_setprop_cell(fdt, i2c_offset, "#size-cells", 0))); 611 _FDT(fdt_setprop(fdt, i2c_offset, "compatible", i2c_compat, 612 sizeof(i2c_compat))); 613 _FDT((fdt_setprop_cell(fdt, i2c_offset, "chip-engine#", i2c->engine))); 614 _FDT((fdt_setprop_cell(fdt, i2c_offset, "clock-frequency", 615 I2C_CLOCK_FREQUENCY))); 616 617 for (i = 0; i < i2c->num_busses; i++) { 618 pnv_i2c_bus_dt_xscom(i2c, fdt, i2c_offset, i); 619 } 620 return 0; 621 } 622 623 static void pnv_i2c_reset(void *dev) 624 { 625 PnvI2C *i2c = PNV_I2C(dev); 626 627 memset(i2c->regs, 0, sizeof(i2c->regs)); 628 629 i2c->regs[I2C_STAT_REG] = I2C_STAT_CMD_COMP; 630 i2c->regs[I2C_EXTD_STAT_REG] = 631 SETFIELD(I2C_EXTD_STAT_FIFO_SIZE, 0ull, PNV_I2C_FIFO_SIZE) | 632 SETFIELD(I2C_EXTD_STAT_I2C_VERSION, 0ull, 23); /* last version */ 633 634 fifo8_reset(&i2c->fifo); 635 } 636 637 static void pnv_i2c_realize(DeviceState *dev, Error **errp) 638 { 639 PnvI2C *i2c = PNV_I2C(dev); 640 int i; 641 642 assert(i2c->chip); 643 644 pnv_xscom_region_init(&i2c->xscom_regs, OBJECT(i2c), &pnv_i2c_xscom_ops, 645 i2c, "xscom-i2c", PNV9_XSCOM_I2CM_SIZE); 646 647 i2c->busses = g_new(I2CBus *, i2c->num_busses); 648 for (i = 0; i < i2c->num_busses; i++) { 649 char name[32]; 650 651 snprintf(name, sizeof(name), TYPE_PNV_I2C ".%d", i); 652 i2c->busses[i] = i2c_init_bus(dev, name); 653 } 654 655 fifo8_create(&i2c->fifo, PNV_I2C_FIFO_SIZE); 656 657 qemu_register_reset(pnv_i2c_reset, dev); 658 659 qdev_init_gpio_out(DEVICE(dev), &i2c->psi_irq, 1); 660 } 661 662 static Property pnv_i2c_properties[] = { 663 DEFINE_PROP_LINK("chip", PnvI2C, chip, TYPE_PNV_CHIP, PnvChip *), 664 DEFINE_PROP_UINT32("engine", PnvI2C, engine, 1), 665 DEFINE_PROP_UINT32("num-busses", PnvI2C, num_busses, 1), 666 DEFINE_PROP_END_OF_LIST(), 667 }; 668 669 static void pnv_i2c_class_init(ObjectClass *klass, void *data) 670 { 671 DeviceClass *dc = DEVICE_CLASS(klass); 672 PnvXScomInterfaceClass *xscomc = PNV_XSCOM_INTERFACE_CLASS(klass); 673 674 xscomc->dt_xscom = pnv_i2c_dt_xscom; 675 676 dc->desc = "PowerNV I2C"; 677 dc->realize = pnv_i2c_realize; 678 device_class_set_props(dc, pnv_i2c_properties); 679 } 680 681 static const TypeInfo pnv_i2c_info = { 682 .name = TYPE_PNV_I2C, 683 .parent = TYPE_DEVICE, 684 .instance_size = sizeof(PnvI2C), 685 .class_init = pnv_i2c_class_init, 686 .interfaces = (InterfaceInfo[]) { 687 { TYPE_PNV_XSCOM_INTERFACE }, 688 { } 689 } 690 }; 691 692 static void pnv_i2c_register_types(void) 693 { 694 type_register_static(&pnv_i2c_info); 695 } 696 697 type_init(pnv_i2c_register_types); 698