1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2.1 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/reset.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "target/ppc/cpu.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_chip.h" 29 #include "hw/ppc/pnv_core.h" 30 #include "hw/ppc/pnv_xscom.h" 31 #include "hw/ppc/xics.h" 32 #include "hw/qdev-properties.h" 33 #include "helper_regs.h" 34 35 static const char *pnv_core_cpu_typename(PnvCore *pc) 36 { 37 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 39 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 40 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 41 g_free(s); 42 return cpu_type; 43 } 44 45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) 46 { 47 CPUState *cs = CPU(cpu); 48 CPUPPCState *env = &cpu->env; 49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 50 51 cpu_reset(cs); 52 53 /* 54 * the skiboot firmware elects a primary thread to initialize the 55 * system and it can be any. 56 */ 57 env->gpr[3] = PNV_FDT_ADDR; 58 env->nip = 0x10; 59 env->msr |= MSR_HVB; /* Hypervisor mode */ 60 env->spr[SPR_HRMOR] = pc->hrmor; 61 hreg_compute_hflags(env); 62 ppc_maybe_interrupt(env); 63 64 cpu_ppc_tb_reset(env); 65 66 pcc->intc_reset(pc->chip, cpu); 67 } 68 69 /* 70 * These values are read by the PowerNV HW monitors under Linux 71 */ 72 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 73 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 74 75 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 76 unsigned int width) 77 { 78 uint32_t offset = addr >> 3; 79 uint64_t val = 0; 80 81 /* The result should be 38 C */ 82 switch (offset) { 83 case PNV_XSCOM_EX_DTS_RESULT0: 84 val = 0x26f024f023f0000ull; 85 break; 86 case PNV_XSCOM_EX_DTS_RESULT1: 87 val = 0x24f000000000000ull; 88 break; 89 default: 90 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 91 offset); 92 } 93 94 return val; 95 } 96 97 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 98 unsigned int width) 99 { 100 uint32_t offset = addr >> 3; 101 102 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 103 offset); 104 } 105 106 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 107 .read = pnv_core_power8_xscom_read, 108 .write = pnv_core_power8_xscom_write, 109 .valid.min_access_size = 8, 110 .valid.max_access_size = 8, 111 .impl.min_access_size = 8, 112 .impl.max_access_size = 8, 113 .endianness = DEVICE_BIG_ENDIAN, 114 }; 115 116 117 /* 118 * POWER9 core controls 119 */ 120 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 121 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 122 123 #define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3 124 125 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 126 unsigned int width) 127 { 128 uint32_t offset = addr >> 3; 129 uint64_t val = 0; 130 131 /* The result should be 38 C */ 132 switch (offset) { 133 case PNV_XSCOM_EX_DTS_RESULT0: 134 val = 0x26f024f023f0000ull; 135 break; 136 case PNV_XSCOM_EX_DTS_RESULT1: 137 val = 0x24f000000000000ull; 138 break; 139 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 140 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 141 val = 0x0; 142 break; 143 case PNV9_XSCOM_EC_CORE_THREAD_STATE: 144 val = 0; 145 break; 146 default: 147 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 148 offset); 149 } 150 151 return val; 152 } 153 154 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 155 unsigned int width) 156 { 157 uint32_t offset = addr >> 3; 158 159 switch (offset) { 160 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 161 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 162 break; 163 default: 164 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 165 offset); 166 } 167 } 168 169 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 170 .read = pnv_core_power9_xscom_read, 171 .write = pnv_core_power9_xscom_write, 172 .valid.min_access_size = 8, 173 .valid.max_access_size = 8, 174 .impl.min_access_size = 8, 175 .impl.max_access_size = 8, 176 .endianness = DEVICE_BIG_ENDIAN, 177 }; 178 179 /* 180 * POWER10 core controls 181 */ 182 183 #define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412 184 185 static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr, 186 unsigned int width) 187 { 188 uint32_t offset = addr >> 3; 189 uint64_t val = 0; 190 191 switch (offset) { 192 case PNV10_XSCOM_EC_CORE_THREAD_STATE: 193 val = 0; 194 break; 195 default: 196 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 197 offset); 198 } 199 200 return val; 201 } 202 203 static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr, 204 uint64_t val, unsigned int width) 205 { 206 uint32_t offset = addr >> 3; 207 208 switch (offset) { 209 default: 210 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 211 offset); 212 } 213 } 214 215 static const MemoryRegionOps pnv_core_power10_xscom_ops = { 216 .read = pnv_core_power10_xscom_read, 217 .write = pnv_core_power10_xscom_write, 218 .valid.min_access_size = 8, 219 .valid.max_access_size = 8, 220 .impl.min_access_size = 8, 221 .impl.max_access_size = 8, 222 .endianness = DEVICE_BIG_ENDIAN, 223 }; 224 225 static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, 226 int thread_index) 227 { 228 CPUPPCState *env = &cpu->env; 229 int core_hwid; 230 ppc_spr_t *pir_spr = &env->spr_cb[SPR_PIR]; 231 ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR]; 232 uint32_t pir, tir; 233 Error *local_err = NULL; 234 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 235 236 if (!qdev_realize(DEVICE(cpu), NULL, errp)) { 237 return; 238 } 239 240 pcc->intc_create(pc->chip, cpu, &local_err); 241 if (local_err) { 242 error_propagate(errp, local_err); 243 return; 244 } 245 246 core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort); 247 248 pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir); 249 pir_spr->default_value = pir; 250 tir_spr->default_value = tir; 251 252 env->core_index = core_hwid; 253 254 /* Set time-base frequency to 512 MHz */ 255 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 256 } 257 258 static void pnv_core_reset(void *dev) 259 { 260 CPUCore *cc = CPU_CORE(dev); 261 PnvCore *pc = PNV_CORE(dev); 262 int i; 263 264 for (i = 0; i < cc->nr_threads; i++) { 265 pnv_core_cpu_reset(pc, pc->threads[i]); 266 } 267 } 268 269 static void pnv_core_realize(DeviceState *dev, Error **errp) 270 { 271 PnvCore *pc = PNV_CORE(OBJECT(dev)); 272 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 273 CPUCore *cc = CPU_CORE(OBJECT(dev)); 274 const char *typename = pnv_core_cpu_typename(pc); 275 Error *local_err = NULL; 276 void *obj; 277 int i, j; 278 char name[32]; 279 280 assert(pc->chip); 281 282 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 283 for (i = 0; i < cc->nr_threads; i++) { 284 PowerPCCPU *cpu; 285 PnvCPUState *pnv_cpu; 286 287 obj = object_new(typename); 288 cpu = POWERPC_CPU(obj); 289 290 pc->threads[i] = POWERPC_CPU(obj); 291 292 snprintf(name, sizeof(name), "thread[%d]", i); 293 object_property_add_child(OBJECT(pc), name, obj); 294 295 cpu->machine_data = g_new0(PnvCPUState, 1); 296 pnv_cpu = pnv_cpu_state(cpu); 297 pnv_cpu->pnv_core = pc; 298 299 object_unref(obj); 300 } 301 302 for (j = 0; j < cc->nr_threads; j++) { 303 pnv_core_cpu_realize(pc, pc->threads[j], &local_err, j); 304 if (local_err) { 305 goto err; 306 } 307 } 308 309 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 310 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 311 pc, name, pcc->xscom_size); 312 313 qemu_register_reset(pnv_core_reset, pc); 314 return; 315 316 err: 317 while (--i >= 0) { 318 obj = OBJECT(pc->threads[i]); 319 object_unparent(obj); 320 } 321 g_free(pc->threads); 322 error_propagate(errp, local_err); 323 } 324 325 static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu) 326 { 327 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 328 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 329 330 pcc->intc_destroy(pc->chip, cpu); 331 cpu_remove_sync(CPU(cpu)); 332 cpu->machine_data = NULL; 333 g_free(pnv_cpu); 334 object_unparent(OBJECT(cpu)); 335 } 336 337 static void pnv_core_unrealize(DeviceState *dev) 338 { 339 PnvCore *pc = PNV_CORE(dev); 340 CPUCore *cc = CPU_CORE(dev); 341 int i; 342 343 qemu_unregister_reset(pnv_core_reset, pc); 344 345 for (i = 0; i < cc->nr_threads; i++) { 346 pnv_core_cpu_unrealize(pc, pc->threads[i]); 347 } 348 g_free(pc->threads); 349 } 350 351 static Property pnv_core_properties[] = { 352 DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0), 353 DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), 354 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), 355 DEFINE_PROP_END_OF_LIST(), 356 }; 357 358 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 359 { 360 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 361 362 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 363 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 364 } 365 366 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 367 { 368 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 369 370 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 371 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 372 } 373 374 static void pnv_core_power10_class_init(ObjectClass *oc, void *data) 375 { 376 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 377 378 pcc->xscom_ops = &pnv_core_power10_xscom_ops; 379 pcc->xscom_size = PNV10_XSCOM_EC_SIZE; 380 } 381 382 static void pnv_core_class_init(ObjectClass *oc, void *data) 383 { 384 DeviceClass *dc = DEVICE_CLASS(oc); 385 386 dc->realize = pnv_core_realize; 387 dc->unrealize = pnv_core_unrealize; 388 device_class_set_props(dc, pnv_core_properties); 389 dc->user_creatable = false; 390 } 391 392 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 393 { \ 394 .parent = TYPE_PNV_CORE, \ 395 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 396 .class_init = pnv_core_##family##_class_init, \ 397 } 398 399 static const TypeInfo pnv_core_infos[] = { 400 { 401 .name = TYPE_PNV_CORE, 402 .parent = TYPE_CPU_CORE, 403 .instance_size = sizeof(PnvCore), 404 .class_size = sizeof(PnvCoreClass), 405 .class_init = pnv_core_class_init, 406 .abstract = true, 407 }, 408 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 409 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 410 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 411 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), 412 DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), 413 }; 414 415 DEFINE_TYPES(pnv_core_infos) 416 417 /* 418 * POWER9 Quads 419 */ 420 421 #define P9X_EX_NCU_SPEC_BAR 0x11010 422 423 static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr, 424 unsigned int width) 425 { 426 uint32_t offset = addr >> 3; 427 uint64_t val = -1; 428 429 switch (offset) { 430 case P9X_EX_NCU_SPEC_BAR: 431 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 432 val = 0; 433 break; 434 default: 435 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 436 offset); 437 } 438 439 return val; 440 } 441 442 static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 443 unsigned int width) 444 { 445 uint32_t offset = addr >> 3; 446 447 switch (offset) { 448 case P9X_EX_NCU_SPEC_BAR: 449 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 450 break; 451 default: 452 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 453 offset); 454 } 455 } 456 457 static const MemoryRegionOps pnv_quad_power9_xscom_ops = { 458 .read = pnv_quad_power9_xscom_read, 459 .write = pnv_quad_power9_xscom_write, 460 .valid.min_access_size = 8, 461 .valid.max_access_size = 8, 462 .impl.min_access_size = 8, 463 .impl.max_access_size = 8, 464 .endianness = DEVICE_BIG_ENDIAN, 465 }; 466 467 /* 468 * POWER10 Quads 469 */ 470 471 static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, 472 unsigned int width) 473 { 474 uint32_t offset = addr >> 3; 475 uint64_t val = -1; 476 477 switch (offset) { 478 default: 479 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 480 offset); 481 } 482 483 return val; 484 } 485 486 static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, 487 uint64_t val, unsigned int width) 488 { 489 uint32_t offset = addr >> 3; 490 491 switch (offset) { 492 default: 493 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 494 offset); 495 } 496 } 497 498 static const MemoryRegionOps pnv_quad_power10_xscom_ops = { 499 .read = pnv_quad_power10_xscom_read, 500 .write = pnv_quad_power10_xscom_write, 501 .valid.min_access_size = 8, 502 .valid.max_access_size = 8, 503 .impl.min_access_size = 8, 504 .impl.max_access_size = 8, 505 .endianness = DEVICE_BIG_ENDIAN, 506 }; 507 508 #define P10_QME_SPWU_HYP 0x83c 509 #define P10_QME_SSH_HYP 0x82c 510 511 static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr, 512 unsigned int width) 513 { 514 uint32_t offset = addr >> 3; 515 uint64_t val = -1; 516 517 /* 518 * Forth nibble selects the core within a quad, mask it to process read 519 * for any core. 520 */ 521 switch (offset & ~0xf000) { 522 case P10_QME_SPWU_HYP: 523 case P10_QME_SSH_HYP: 524 return 0; 525 default: 526 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 527 offset); 528 } 529 530 return val; 531 } 532 533 static void pnv_qme_power10_xscom_write(void *opaque, hwaddr addr, 534 uint64_t val, unsigned int width) 535 { 536 uint32_t offset = addr >> 3; 537 538 switch (offset) { 539 default: 540 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 541 offset); 542 } 543 } 544 545 static const MemoryRegionOps pnv_qme_power10_xscom_ops = { 546 .read = pnv_qme_power10_xscom_read, 547 .write = pnv_qme_power10_xscom_write, 548 .valid.min_access_size = 8, 549 .valid.max_access_size = 8, 550 .impl.min_access_size = 8, 551 .impl.max_access_size = 8, 552 .endianness = DEVICE_BIG_ENDIAN, 553 }; 554 555 static void pnv_quad_power9_realize(DeviceState *dev, Error **errp) 556 { 557 PnvQuad *eq = PNV_QUAD(dev); 558 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 559 char name[32]; 560 561 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 562 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 563 pqc->xscom_ops, 564 eq, name, 565 pqc->xscom_size); 566 } 567 568 static void pnv_quad_power10_realize(DeviceState *dev, Error **errp) 569 { 570 PnvQuad *eq = PNV_QUAD(dev); 571 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 572 char name[32]; 573 574 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 575 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 576 pqc->xscom_ops, 577 eq, name, 578 pqc->xscom_size); 579 580 snprintf(name, sizeof(name), "xscom-qme.%d", eq->quad_id); 581 pnv_xscom_region_init(&eq->xscom_qme_regs, OBJECT(dev), 582 pqc->xscom_qme_ops, 583 eq, name, 584 pqc->xscom_qme_size); 585 } 586 587 static Property pnv_quad_properties[] = { 588 DEFINE_PROP_UINT32("quad-id", PnvQuad, quad_id, 0), 589 DEFINE_PROP_END_OF_LIST(), 590 }; 591 592 static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) 593 { 594 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 595 DeviceClass *dc = DEVICE_CLASS(oc); 596 597 dc->realize = pnv_quad_power9_realize; 598 599 pqc->xscom_ops = &pnv_quad_power9_xscom_ops; 600 pqc->xscom_size = PNV9_XSCOM_EQ_SIZE; 601 } 602 603 static void pnv_quad_power10_class_init(ObjectClass *oc, void *data) 604 { 605 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 606 DeviceClass *dc = DEVICE_CLASS(oc); 607 608 dc->realize = pnv_quad_power10_realize; 609 610 pqc->xscom_ops = &pnv_quad_power10_xscom_ops; 611 pqc->xscom_size = PNV10_XSCOM_EQ_SIZE; 612 613 pqc->xscom_qme_ops = &pnv_qme_power10_xscom_ops; 614 pqc->xscom_qme_size = PNV10_XSCOM_QME_SIZE; 615 } 616 617 static void pnv_quad_class_init(ObjectClass *oc, void *data) 618 { 619 DeviceClass *dc = DEVICE_CLASS(oc); 620 621 device_class_set_props(dc, pnv_quad_properties); 622 dc->user_creatable = false; 623 } 624 625 static const TypeInfo pnv_quad_infos[] = { 626 { 627 .name = TYPE_PNV_QUAD, 628 .parent = TYPE_DEVICE, 629 .instance_size = sizeof(PnvQuad), 630 .class_size = sizeof(PnvQuadClass), 631 .class_init = pnv_quad_class_init, 632 .abstract = true, 633 }, 634 { 635 .parent = TYPE_PNV_QUAD, 636 .name = PNV_QUAD_TYPE_NAME("power9"), 637 .class_init = pnv_quad_power9_class_init, 638 }, 639 { 640 .parent = TYPE_PNV_QUAD, 641 .name = PNV_QUAD_TYPE_NAME("power10"), 642 .class_init = pnv_quad_power10_class_init, 643 }, 644 }; 645 646 DEFINE_TYPES(pnv_quad_infos); 647