1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "sysemu/sysemu.h" 21 #include "qapi/error.h" 22 #include "qemu/log.h" 23 #include "target/ppc/cpu.h" 24 #include "hw/ppc/ppc.h" 25 #include "hw/ppc/pnv.h" 26 #include "hw/ppc/pnv_core.h" 27 #include "hw/ppc/pnv_xscom.h" 28 #include "hw/ppc/xics.h" 29 30 static const char *pnv_core_cpu_typename(PnvCore *pc) 31 { 32 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 33 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 34 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 35 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 36 g_free(s); 37 return cpu_type; 38 } 39 40 static void pnv_cpu_reset(void *opaque) 41 { 42 PowerPCCPU *cpu = opaque; 43 CPUState *cs = CPU(cpu); 44 CPUPPCState *env = &cpu->env; 45 46 cpu_reset(cs); 47 48 /* 49 * the skiboot firmware elects a primary thread to initialize the 50 * system and it can be any. 51 */ 52 env->gpr[3] = PNV_FDT_ADDR; 53 env->nip = 0x10; 54 env->msr |= MSR_HVB; /* Hypervisor mode */ 55 } 56 57 /* 58 * These values are read by the PowerNV HW monitors under Linux 59 */ 60 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 61 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 62 63 static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr, 64 unsigned int width) 65 { 66 uint32_t offset = addr >> 3; 67 uint64_t val = 0; 68 69 /* The result should be 38 C */ 70 switch (offset) { 71 case PNV_XSCOM_EX_DTS_RESULT0: 72 val = 0x26f024f023f0000ull; 73 break; 74 case PNV_XSCOM_EX_DTS_RESULT1: 75 val = 0x24f000000000000ull; 76 break; 77 default: 78 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 79 addr); 80 } 81 82 return val; 83 } 84 85 static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val, 86 unsigned int width) 87 { 88 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 89 addr); 90 } 91 92 static const MemoryRegionOps pnv_core_xscom_ops = { 93 .read = pnv_core_xscom_read, 94 .write = pnv_core_xscom_write, 95 .valid.min_access_size = 8, 96 .valid.max_access_size = 8, 97 .impl.min_access_size = 8, 98 .impl.max_access_size = 8, 99 .endianness = DEVICE_BIG_ENDIAN, 100 }; 101 102 static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) 103 { 104 CPUPPCState *env = &cpu->env; 105 int core_pir; 106 int thread_index = 0; /* TODO: TCG supports only one thread */ 107 ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; 108 Error *local_err = NULL; 109 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 110 111 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 112 if (local_err) { 113 error_propagate(errp, local_err); 114 return; 115 } 116 117 pcc->intc_create(chip, cpu, &local_err); 118 if (local_err) { 119 error_propagate(errp, local_err); 120 return; 121 } 122 123 core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort); 124 125 /* 126 * The PIR of a thread is the core PIR + the thread index. We will 127 * need to find a way to get the thread index when TCG supports 128 * more than 1. We could use the object name ? 129 */ 130 pir->default_value = core_pir + thread_index; 131 132 /* Set time-base frequency to 512 MHz */ 133 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 134 135 qemu_register_reset(pnv_cpu_reset, cpu); 136 } 137 138 static void pnv_core_realize(DeviceState *dev, Error **errp) 139 { 140 PnvCore *pc = PNV_CORE(OBJECT(dev)); 141 CPUCore *cc = CPU_CORE(OBJECT(dev)); 142 const char *typename = pnv_core_cpu_typename(pc); 143 Error *local_err = NULL; 144 void *obj; 145 int i, j; 146 char name[32]; 147 Object *chip; 148 149 chip = object_property_get_link(OBJECT(dev), "chip", &local_err); 150 if (!chip) { 151 error_propagate_prepend(errp, local_err, 152 "required link 'chip' not found: "); 153 return; 154 } 155 156 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 157 for (i = 0; i < cc->nr_threads; i++) { 158 PowerPCCPU *cpu; 159 160 obj = object_new(typename); 161 cpu = POWERPC_CPU(obj); 162 163 pc->threads[i] = POWERPC_CPU(obj); 164 165 snprintf(name, sizeof(name), "thread[%d]", i); 166 object_property_add_child(OBJECT(pc), name, obj, &error_abort); 167 object_property_add_alias(obj, "core-pir", OBJECT(pc), 168 "pir", &error_abort); 169 170 cpu->machine_data = g_new0(PnvCPUState, 1); 171 172 object_unref(obj); 173 } 174 175 for (j = 0; j < cc->nr_threads; j++) { 176 pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err); 177 if (local_err) { 178 goto err; 179 } 180 } 181 182 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 183 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops, 184 pc, name, PNV_XSCOM_EX_SIZE); 185 return; 186 187 err: 188 while (--i >= 0) { 189 obj = OBJECT(pc->threads[i]); 190 object_unparent(obj); 191 } 192 g_free(pc->threads); 193 error_propagate(errp, local_err); 194 } 195 196 static void pnv_unrealize_vcpu(PowerPCCPU *cpu) 197 { 198 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 199 200 qemu_unregister_reset(pnv_cpu_reset, cpu); 201 object_unparent(OBJECT(pnv_cpu_state(cpu)->icp)); 202 cpu_remove_sync(CPU(cpu)); 203 cpu->machine_data = NULL; 204 g_free(pnv_cpu); 205 object_unparent(OBJECT(cpu)); 206 } 207 208 static void pnv_core_unrealize(DeviceState *dev, Error **errp) 209 { 210 PnvCore *pc = PNV_CORE(dev); 211 CPUCore *cc = CPU_CORE(dev); 212 int i; 213 214 for (i = 0; i < cc->nr_threads; i++) { 215 pnv_unrealize_vcpu(pc->threads[i]); 216 } 217 g_free(pc->threads); 218 } 219 220 static Property pnv_core_properties[] = { 221 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), 222 DEFINE_PROP_END_OF_LIST(), 223 }; 224 225 static void pnv_core_class_init(ObjectClass *oc, void *data) 226 { 227 DeviceClass *dc = DEVICE_CLASS(oc); 228 229 dc->realize = pnv_core_realize; 230 dc->unrealize = pnv_core_unrealize; 231 dc->props = pnv_core_properties; 232 } 233 234 #define DEFINE_PNV_CORE_TYPE(cpu_model) \ 235 { \ 236 .parent = TYPE_PNV_CORE, \ 237 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 238 } 239 240 static const TypeInfo pnv_core_infos[] = { 241 { 242 .name = TYPE_PNV_CORE, 243 .parent = TYPE_CPU_CORE, 244 .instance_size = sizeof(PnvCore), 245 .class_size = sizeof(PnvCoreClass), 246 .class_init = pnv_core_class_init, 247 .abstract = true, 248 }, 249 DEFINE_PNV_CORE_TYPE("power8e_v2.1"), 250 DEFINE_PNV_CORE_TYPE("power8_v2.0"), 251 DEFINE_PNV_CORE_TYPE("power8nvl_v1.0"), 252 DEFINE_PNV_CORE_TYPE("power9_v2.0"), 253 }; 254 255 DEFINE_TYPES(pnv_core_infos) 256