1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2.1 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/reset.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "target/ppc/cpu.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_chip.h" 29 #include "hw/ppc/pnv_core.h" 30 #include "hw/ppc/pnv_xscom.h" 31 #include "hw/ppc/xics.h" 32 #include "hw/qdev-properties.h" 33 #include "helper_regs.h" 34 35 static const char *pnv_core_cpu_typename(PnvCore *pc) 36 { 37 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 39 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 40 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 41 g_free(s); 42 return cpu_type; 43 } 44 45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) 46 { 47 CPUState *cs = CPU(cpu); 48 CPUPPCState *env = &cpu->env; 49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 50 51 cpu_reset(cs); 52 53 /* 54 * the skiboot firmware elects a primary thread to initialize the 55 * system and it can be any. 56 */ 57 env->gpr[3] = PNV_FDT_ADDR; 58 env->nip = 0x10; 59 env->msr |= MSR_HVB; /* Hypervisor mode */ 60 env->spr[SPR_HRMOR] = pc->hrmor; 61 if (pc->big_core) { 62 /* Clear "small core" bit on Power9/10 (this is set in default PVR) */ 63 env->spr[SPR_PVR] &= ~PPC_BIT(51); 64 } 65 hreg_compute_hflags(env); 66 ppc_maybe_interrupt(env); 67 68 cpu_ppc_tb_reset(env); 69 70 pcc->intc_reset(pc->chip, cpu); 71 } 72 73 /* 74 * These values are read by the PowerNV HW monitors under Linux 75 */ 76 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 77 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 78 79 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 80 unsigned int width) 81 { 82 uint32_t offset = addr >> 3; 83 uint64_t val = 0; 84 85 /* The result should be 38 C */ 86 switch (offset) { 87 case PNV_XSCOM_EX_DTS_RESULT0: 88 val = 0x26f024f023f0000ull; 89 break; 90 case PNV_XSCOM_EX_DTS_RESULT1: 91 val = 0x24f000000000000ull; 92 break; 93 default: 94 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 95 offset); 96 } 97 98 return val; 99 } 100 101 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 102 unsigned int width) 103 { 104 uint32_t offset = addr >> 3; 105 106 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 107 offset); 108 } 109 110 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 111 .read = pnv_core_power8_xscom_read, 112 .write = pnv_core_power8_xscom_write, 113 .valid.min_access_size = 8, 114 .valid.max_access_size = 8, 115 .impl.min_access_size = 8, 116 .impl.max_access_size = 8, 117 .endianness = DEVICE_BIG_ENDIAN, 118 }; 119 120 121 /* 122 * POWER9 core controls 123 */ 124 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 125 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 126 127 #define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3 128 129 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 130 unsigned int width) 131 { 132 uint32_t offset = addr >> 3; 133 uint64_t val = 0; 134 135 /* The result should be 38 C */ 136 switch (offset) { 137 case PNV_XSCOM_EX_DTS_RESULT0: 138 val = 0x26f024f023f0000ull; 139 break; 140 case PNV_XSCOM_EX_DTS_RESULT1: 141 val = 0x24f000000000000ull; 142 break; 143 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 144 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 145 val = 0x0; 146 break; 147 case PNV9_XSCOM_EC_CORE_THREAD_STATE: 148 val = 0; 149 break; 150 default: 151 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 152 offset); 153 } 154 155 return val; 156 } 157 158 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 159 unsigned int width) 160 { 161 uint32_t offset = addr >> 3; 162 163 switch (offset) { 164 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 165 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 166 break; 167 default: 168 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 169 offset); 170 } 171 } 172 173 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 174 .read = pnv_core_power9_xscom_read, 175 .write = pnv_core_power9_xscom_write, 176 .valid.min_access_size = 8, 177 .valid.max_access_size = 8, 178 .impl.min_access_size = 8, 179 .impl.max_access_size = 8, 180 .endianness = DEVICE_BIG_ENDIAN, 181 }; 182 183 /* 184 * POWER10 core controls 185 */ 186 187 #define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412 188 #define PNV10_XSCOM_EC_CORE_THREAD_INFO 0x413 189 #define PNV10_XSCOM_EC_CORE_DIRECT_CONTROLS 0x449 190 #define PNV10_XSCOM_EC_CORE_RAS_STATUS 0x454 191 192 static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr, 193 unsigned int width) 194 { 195 PnvCore *pc = PNV_CORE(opaque); 196 int nr_threads = CPU_CORE(pc)->nr_threads; 197 int i; 198 uint32_t offset = addr >> 3; 199 uint64_t val = 0; 200 201 switch (offset) { 202 case PNV10_XSCOM_EC_CORE_THREAD_STATE: 203 for (i = 0; i < nr_threads; i++) { 204 PowerPCCPU *cpu = pc->threads[i]; 205 CPUState *cs = CPU(cpu); 206 207 if (cs->halted) { 208 val |= PPC_BIT(56 + i); 209 } 210 } 211 break; 212 case PNV10_XSCOM_EC_CORE_THREAD_INFO: 213 break; 214 case PNV10_XSCOM_EC_CORE_RAS_STATUS: 215 for (i = 0; i < nr_threads; i++) { 216 PowerPCCPU *cpu = pc->threads[i]; 217 CPUState *cs = CPU(cpu); 218 if (cs->stopped) { 219 val |= PPC_BIT(0 + 8 * i) | PPC_BIT(1 + 8 * i); 220 } 221 } 222 break; 223 default: 224 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 225 offset); 226 } 227 228 return val; 229 } 230 231 static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr, 232 uint64_t val, unsigned int width) 233 { 234 PnvCore *pc = PNV_CORE(opaque); 235 int nr_threads = CPU_CORE(pc)->nr_threads; 236 int i; 237 uint32_t offset = addr >> 3; 238 239 switch (offset) { 240 case PNV10_XSCOM_EC_CORE_DIRECT_CONTROLS: 241 for (i = 0; i < nr_threads; i++) { 242 PowerPCCPU *cpu = pc->threads[i]; 243 CPUState *cs = CPU(cpu); 244 245 if (val & PPC_BIT(7 + 8 * i)) { /* stop */ 246 val &= ~PPC_BIT(7 + 8 * i); 247 cpu_pause(cs); 248 } 249 if (val & PPC_BIT(6 + 8 * i)) { /* start */ 250 val &= ~PPC_BIT(6 + 8 * i); 251 cpu_resume(cs); 252 } 253 if (val & PPC_BIT(4 + 8 * i)) { /* sreset */ 254 val &= ~PPC_BIT(4 + 8 * i); 255 pnv_cpu_do_nmi_resume(cs); 256 } 257 if (val & PPC_BIT(3 + 8 * i)) { /* clear maint */ 258 /* 259 * Hardware has very particular cases for where clear maint 260 * must be used and where start must be used to resume a 261 * thread. These are not modelled exactly, just treat 262 * this and start the same. 263 */ 264 val &= ~PPC_BIT(3 + 8 * i); 265 cpu_resume(cs); 266 } 267 } 268 if (val) { 269 qemu_log_mask(LOG_UNIMP, "%s: unimp bits in DIRECT_CONTROLS " 270 "0x%016" PRIx64 "\n", __func__, val); 271 } 272 break; 273 274 default: 275 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 276 offset); 277 } 278 } 279 280 static const MemoryRegionOps pnv_core_power10_xscom_ops = { 281 .read = pnv_core_power10_xscom_read, 282 .write = pnv_core_power10_xscom_write, 283 .valid.min_access_size = 8, 284 .valid.max_access_size = 8, 285 .impl.min_access_size = 8, 286 .impl.max_access_size = 8, 287 .endianness = DEVICE_BIG_ENDIAN, 288 }; 289 290 static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, 291 int thread_index) 292 { 293 CPUPPCState *env = &cpu->env; 294 int core_hwid; 295 ppc_spr_t *pir_spr = &env->spr_cb[SPR_PIR]; 296 ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR]; 297 uint32_t pir, tir; 298 Error *local_err = NULL; 299 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 300 301 if (!qdev_realize(DEVICE(cpu), NULL, errp)) { 302 return; 303 } 304 305 pcc->intc_create(pc->chip, cpu, &local_err); 306 if (local_err) { 307 error_propagate(errp, local_err); 308 return; 309 } 310 311 core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort); 312 313 pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir); 314 pir_spr->default_value = pir; 315 tir_spr->default_value = tir; 316 317 if (pc->big_core) { 318 /* 2 "small cores" get the same core index for SMT operations */ 319 env->core_index = core_hwid >> 1; 320 } else { 321 env->core_index = core_hwid; 322 } 323 324 /* Set time-base frequency to 512 MHz */ 325 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 326 } 327 328 static void pnv_core_reset(void *dev) 329 { 330 CPUCore *cc = CPU_CORE(dev); 331 PnvCore *pc = PNV_CORE(dev); 332 int i; 333 334 for (i = 0; i < cc->nr_threads; i++) { 335 pnv_core_cpu_reset(pc, pc->threads[i]); 336 } 337 } 338 339 static void pnv_core_realize(DeviceState *dev, Error **errp) 340 { 341 PnvCore *pc = PNV_CORE(OBJECT(dev)); 342 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 343 CPUCore *cc = CPU_CORE(OBJECT(dev)); 344 const char *typename = pnv_core_cpu_typename(pc); 345 Error *local_err = NULL; 346 void *obj; 347 int i, j; 348 char name[32]; 349 350 assert(pc->chip); 351 352 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 353 for (i = 0; i < cc->nr_threads; i++) { 354 PowerPCCPU *cpu; 355 PnvCPUState *pnv_cpu; 356 357 obj = object_new(typename); 358 cpu = POWERPC_CPU(obj); 359 360 pc->threads[i] = POWERPC_CPU(obj); 361 if (cc->nr_threads > 1) { 362 cpu->env.has_smt_siblings = true; 363 } 364 365 snprintf(name, sizeof(name), "thread[%d]", i); 366 object_property_add_child(OBJECT(pc), name, obj); 367 368 cpu->machine_data = g_new0(PnvCPUState, 1); 369 pnv_cpu = pnv_cpu_state(cpu); 370 pnv_cpu->pnv_core = pc; 371 372 object_unref(obj); 373 } 374 375 for (j = 0; j < cc->nr_threads; j++) { 376 pnv_core_cpu_realize(pc, pc->threads[j], &local_err, j); 377 if (local_err) { 378 goto err; 379 } 380 } 381 382 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 383 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 384 pc, name, pcc->xscom_size); 385 386 qemu_register_reset(pnv_core_reset, pc); 387 return; 388 389 err: 390 while (--i >= 0) { 391 obj = OBJECT(pc->threads[i]); 392 object_unparent(obj); 393 } 394 g_free(pc->threads); 395 error_propagate(errp, local_err); 396 } 397 398 static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu) 399 { 400 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 401 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 402 403 pcc->intc_destroy(pc->chip, cpu); 404 cpu_remove_sync(CPU(cpu)); 405 cpu->machine_data = NULL; 406 g_free(pnv_cpu); 407 object_unparent(OBJECT(cpu)); 408 } 409 410 static void pnv_core_unrealize(DeviceState *dev) 411 { 412 PnvCore *pc = PNV_CORE(dev); 413 CPUCore *cc = CPU_CORE(dev); 414 int i; 415 416 qemu_unregister_reset(pnv_core_reset, pc); 417 418 for (i = 0; i < cc->nr_threads; i++) { 419 pnv_core_cpu_unrealize(pc, pc->threads[i]); 420 } 421 g_free(pc->threads); 422 } 423 424 static Property pnv_core_properties[] = { 425 DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0), 426 DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), 427 DEFINE_PROP_BOOL("big-core", PnvCore, big_core, false), 428 DEFINE_PROP_BOOL("quirk-tb-big-core", PnvCore, tod_state.big_core_quirk, 429 false), 430 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), 431 DEFINE_PROP_END_OF_LIST(), 432 }; 433 434 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 435 { 436 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 437 438 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 439 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 440 } 441 442 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 443 { 444 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 445 446 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 447 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 448 } 449 450 static void pnv_core_power10_class_init(ObjectClass *oc, void *data) 451 { 452 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 453 454 pcc->xscom_ops = &pnv_core_power10_xscom_ops; 455 pcc->xscom_size = PNV10_XSCOM_EC_SIZE; 456 } 457 458 static void pnv_core_class_init(ObjectClass *oc, void *data) 459 { 460 DeviceClass *dc = DEVICE_CLASS(oc); 461 462 dc->realize = pnv_core_realize; 463 dc->unrealize = pnv_core_unrealize; 464 device_class_set_props(dc, pnv_core_properties); 465 dc->user_creatable = false; 466 } 467 468 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 469 { \ 470 .parent = TYPE_PNV_CORE, \ 471 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 472 .class_init = pnv_core_##family##_class_init, \ 473 } 474 475 static const TypeInfo pnv_core_infos[] = { 476 { 477 .name = TYPE_PNV_CORE, 478 .parent = TYPE_CPU_CORE, 479 .instance_size = sizeof(PnvCore), 480 .class_size = sizeof(PnvCoreClass), 481 .class_init = pnv_core_class_init, 482 .abstract = true, 483 }, 484 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 485 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 486 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 487 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), 488 DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), 489 }; 490 491 DEFINE_TYPES(pnv_core_infos) 492 493 /* 494 * POWER9 Quads 495 */ 496 497 #define P9X_EX_NCU_SPEC_BAR 0x11010 498 499 static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr, 500 unsigned int width) 501 { 502 uint32_t offset = addr >> 3; 503 uint64_t val = -1; 504 505 switch (offset) { 506 case P9X_EX_NCU_SPEC_BAR: 507 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 508 val = 0; 509 break; 510 default: 511 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 512 offset); 513 } 514 515 return val; 516 } 517 518 static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 519 unsigned int width) 520 { 521 uint32_t offset = addr >> 3; 522 523 switch (offset) { 524 case P9X_EX_NCU_SPEC_BAR: 525 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 526 break; 527 default: 528 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 529 offset); 530 } 531 } 532 533 static const MemoryRegionOps pnv_quad_power9_xscom_ops = { 534 .read = pnv_quad_power9_xscom_read, 535 .write = pnv_quad_power9_xscom_write, 536 .valid.min_access_size = 8, 537 .valid.max_access_size = 8, 538 .impl.min_access_size = 8, 539 .impl.max_access_size = 8, 540 .endianness = DEVICE_BIG_ENDIAN, 541 }; 542 543 /* 544 * POWER10 Quads 545 */ 546 547 static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, 548 unsigned int width) 549 { 550 uint32_t offset = addr >> 3; 551 uint64_t val = -1; 552 553 switch (offset) { 554 default: 555 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 556 offset); 557 } 558 559 return val; 560 } 561 562 static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, 563 uint64_t val, unsigned int width) 564 { 565 uint32_t offset = addr >> 3; 566 567 switch (offset) { 568 default: 569 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 570 offset); 571 } 572 } 573 574 static const MemoryRegionOps pnv_quad_power10_xscom_ops = { 575 .read = pnv_quad_power10_xscom_read, 576 .write = pnv_quad_power10_xscom_write, 577 .valid.min_access_size = 8, 578 .valid.max_access_size = 8, 579 .impl.min_access_size = 8, 580 .impl.max_access_size = 8, 581 .endianness = DEVICE_BIG_ENDIAN, 582 }; 583 584 #define P10_QME_SPWU_HYP 0x83c 585 #define P10_QME_SSH_HYP 0x82c 586 587 static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr, 588 unsigned int width) 589 { 590 PnvQuad *eq = PNV_QUAD(opaque); 591 uint32_t offset = addr >> 3; 592 uint64_t val = -1; 593 594 /* 595 * Forth nibble selects the core within a quad, mask it to process read 596 * for any core. 597 */ 598 switch (offset & ~PPC_BITMASK32(16, 19)) { 599 case P10_QME_SSH_HYP: 600 val = 0; 601 if (eq->special_wakeup_done) { 602 val |= PPC_BIT(1); /* SPWU DONE */ 603 val |= PPC_BIT(4); /* SSH SPWU DONE */ 604 } 605 break; 606 default: 607 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 608 offset); 609 } 610 611 return val; 612 } 613 614 static void pnv_qme_power10_xscom_write(void *opaque, hwaddr addr, 615 uint64_t val, unsigned int width) 616 { 617 PnvQuad *eq = PNV_QUAD(opaque); 618 uint32_t offset = addr >> 3; 619 bool set; 620 int i; 621 622 switch (offset & ~PPC_BITMASK32(16, 19)) { 623 case P10_QME_SPWU_HYP: 624 set = !!(val & PPC_BIT(0)); 625 eq->special_wakeup_done = set; 626 for (i = 0; i < 4; i++) { 627 /* These bits select cores in the quad */ 628 if (offset & PPC_BIT32(16 + i)) { 629 eq->special_wakeup[i] = set; 630 } 631 } 632 break; 633 default: 634 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 635 offset); 636 } 637 } 638 639 static const MemoryRegionOps pnv_qme_power10_xscom_ops = { 640 .read = pnv_qme_power10_xscom_read, 641 .write = pnv_qme_power10_xscom_write, 642 .valid.min_access_size = 8, 643 .valid.max_access_size = 8, 644 .impl.min_access_size = 8, 645 .impl.max_access_size = 8, 646 .endianness = DEVICE_BIG_ENDIAN, 647 }; 648 649 static void pnv_quad_power9_realize(DeviceState *dev, Error **errp) 650 { 651 PnvQuad *eq = PNV_QUAD(dev); 652 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 653 char name[32]; 654 655 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 656 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 657 pqc->xscom_ops, 658 eq, name, 659 pqc->xscom_size); 660 } 661 662 static void pnv_quad_power10_realize(DeviceState *dev, Error **errp) 663 { 664 PnvQuad *eq = PNV_QUAD(dev); 665 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 666 char name[32]; 667 668 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 669 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 670 pqc->xscom_ops, 671 eq, name, 672 pqc->xscom_size); 673 674 snprintf(name, sizeof(name), "xscom-qme.%d", eq->quad_id); 675 pnv_xscom_region_init(&eq->xscom_qme_regs, OBJECT(dev), 676 pqc->xscom_qme_ops, 677 eq, name, 678 pqc->xscom_qme_size); 679 } 680 681 static Property pnv_quad_properties[] = { 682 DEFINE_PROP_UINT32("quad-id", PnvQuad, quad_id, 0), 683 DEFINE_PROP_END_OF_LIST(), 684 }; 685 686 static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) 687 { 688 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 689 DeviceClass *dc = DEVICE_CLASS(oc); 690 691 dc->realize = pnv_quad_power9_realize; 692 693 pqc->xscom_ops = &pnv_quad_power9_xscom_ops; 694 pqc->xscom_size = PNV9_XSCOM_EQ_SIZE; 695 } 696 697 static void pnv_quad_power10_class_init(ObjectClass *oc, void *data) 698 { 699 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 700 DeviceClass *dc = DEVICE_CLASS(oc); 701 702 dc->realize = pnv_quad_power10_realize; 703 704 pqc->xscom_ops = &pnv_quad_power10_xscom_ops; 705 pqc->xscom_size = PNV10_XSCOM_EQ_SIZE; 706 707 pqc->xscom_qme_ops = &pnv_qme_power10_xscom_ops; 708 pqc->xscom_qme_size = PNV10_XSCOM_QME_SIZE; 709 } 710 711 static void pnv_quad_class_init(ObjectClass *oc, void *data) 712 { 713 DeviceClass *dc = DEVICE_CLASS(oc); 714 715 device_class_set_props(dc, pnv_quad_properties); 716 dc->user_creatable = false; 717 } 718 719 static const TypeInfo pnv_quad_infos[] = { 720 { 721 .name = TYPE_PNV_QUAD, 722 .parent = TYPE_DEVICE, 723 .instance_size = sizeof(PnvQuad), 724 .class_size = sizeof(PnvQuadClass), 725 .class_init = pnv_quad_class_init, 726 .abstract = true, 727 }, 728 { 729 .parent = TYPE_PNV_QUAD, 730 .name = PNV_QUAD_TYPE_NAME("power9"), 731 .class_init = pnv_quad_power9_class_init, 732 }, 733 { 734 .parent = TYPE_PNV_QUAD, 735 .name = PNV_QUAD_TYPE_NAME("power10"), 736 .class_init = pnv_quad_power10_class_init, 737 }, 738 }; 739 740 DEFINE_TYPES(pnv_quad_infos); 741