1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2.1 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/reset.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "target/ppc/cpu.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_chip.h" 29 #include "hw/ppc/pnv_core.h" 30 #include "hw/ppc/pnv_xscom.h" 31 #include "hw/ppc/xics.h" 32 #include "hw/qdev-properties.h" 33 #include "helper_regs.h" 34 35 static const char *pnv_core_cpu_typename(PnvCore *pc) 36 { 37 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 39 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 40 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 41 g_free(s); 42 return cpu_type; 43 } 44 45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) 46 { 47 CPUState *cs = CPU(cpu); 48 CPUPPCState *env = &cpu->env; 49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 50 51 cpu_reset(cs); 52 53 /* 54 * the skiboot firmware elects a primary thread to initialize the 55 * system and it can be any. 56 */ 57 env->gpr[3] = PNV_FDT_ADDR; 58 env->nip = 0x10; 59 env->msr |= MSR_HVB; /* Hypervisor mode */ 60 env->spr[SPR_HRMOR] = pc->hrmor; 61 hreg_compute_hflags(env); 62 ppc_maybe_interrupt(env); 63 64 cpu_ppc_tb_reset(env); 65 66 pcc->intc_reset(pc->chip, cpu); 67 } 68 69 /* 70 * These values are read by the PowerNV HW monitors under Linux 71 */ 72 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 73 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 74 75 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 76 unsigned int width) 77 { 78 uint32_t offset = addr >> 3; 79 uint64_t val = 0; 80 81 /* The result should be 38 C */ 82 switch (offset) { 83 case PNV_XSCOM_EX_DTS_RESULT0: 84 val = 0x26f024f023f0000ull; 85 break; 86 case PNV_XSCOM_EX_DTS_RESULT1: 87 val = 0x24f000000000000ull; 88 break; 89 default: 90 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 91 offset); 92 } 93 94 return val; 95 } 96 97 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 98 unsigned int width) 99 { 100 uint32_t offset = addr >> 3; 101 102 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 103 offset); 104 } 105 106 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 107 .read = pnv_core_power8_xscom_read, 108 .write = pnv_core_power8_xscom_write, 109 .valid.min_access_size = 8, 110 .valid.max_access_size = 8, 111 .impl.min_access_size = 8, 112 .impl.max_access_size = 8, 113 .endianness = DEVICE_BIG_ENDIAN, 114 }; 115 116 117 /* 118 * POWER9 core controls 119 */ 120 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 121 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 122 123 #define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3 124 125 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 126 unsigned int width) 127 { 128 uint32_t offset = addr >> 3; 129 uint64_t val = 0; 130 131 /* The result should be 38 C */ 132 switch (offset) { 133 case PNV_XSCOM_EX_DTS_RESULT0: 134 val = 0x26f024f023f0000ull; 135 break; 136 case PNV_XSCOM_EX_DTS_RESULT1: 137 val = 0x24f000000000000ull; 138 break; 139 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 140 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 141 val = 0x0; 142 break; 143 case PNV9_XSCOM_EC_CORE_THREAD_STATE: 144 val = 0; 145 break; 146 default: 147 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 148 offset); 149 } 150 151 return val; 152 } 153 154 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 155 unsigned int width) 156 { 157 uint32_t offset = addr >> 3; 158 159 switch (offset) { 160 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 161 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 162 break; 163 default: 164 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 165 offset); 166 } 167 } 168 169 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 170 .read = pnv_core_power9_xscom_read, 171 .write = pnv_core_power9_xscom_write, 172 .valid.min_access_size = 8, 173 .valid.max_access_size = 8, 174 .impl.min_access_size = 8, 175 .impl.max_access_size = 8, 176 .endianness = DEVICE_BIG_ENDIAN, 177 }; 178 179 /* 180 * POWER10 core controls 181 */ 182 183 #define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412 184 185 static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr, 186 unsigned int width) 187 { 188 uint32_t offset = addr >> 3; 189 uint64_t val = 0; 190 191 switch (offset) { 192 case PNV10_XSCOM_EC_CORE_THREAD_STATE: 193 val = 0; 194 break; 195 default: 196 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 197 offset); 198 } 199 200 return val; 201 } 202 203 static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr, 204 uint64_t val, unsigned int width) 205 { 206 uint32_t offset = addr >> 3; 207 208 switch (offset) { 209 default: 210 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 211 offset); 212 } 213 } 214 215 static const MemoryRegionOps pnv_core_power10_xscom_ops = { 216 .read = pnv_core_power10_xscom_read, 217 .write = pnv_core_power10_xscom_write, 218 .valid.min_access_size = 8, 219 .valid.max_access_size = 8, 220 .impl.min_access_size = 8, 221 .impl.max_access_size = 8, 222 .endianness = DEVICE_BIG_ENDIAN, 223 }; 224 225 static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, 226 int thread_index) 227 { 228 CPUPPCState *env = &cpu->env; 229 int core_hwid; 230 ppc_spr_t *pir_spr = &env->spr_cb[SPR_PIR]; 231 ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR]; 232 uint32_t pir, tir; 233 Error *local_err = NULL; 234 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 235 236 if (!qdev_realize(DEVICE(cpu), NULL, errp)) { 237 return; 238 } 239 240 pcc->intc_create(pc->chip, cpu, &local_err); 241 if (local_err) { 242 error_propagate(errp, local_err); 243 return; 244 } 245 246 core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort); 247 248 pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir); 249 pir_spr->default_value = pir; 250 tir_spr->default_value = tir; 251 252 if (pc->big_core) { 253 /* 2 "small cores" get the same core index for SMT operations */ 254 env->core_index = core_hwid >> 1; 255 } else { 256 env->core_index = core_hwid; 257 } 258 259 /* Set time-base frequency to 512 MHz */ 260 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 261 } 262 263 static void pnv_core_reset(void *dev) 264 { 265 CPUCore *cc = CPU_CORE(dev); 266 PnvCore *pc = PNV_CORE(dev); 267 int i; 268 269 for (i = 0; i < cc->nr_threads; i++) { 270 pnv_core_cpu_reset(pc, pc->threads[i]); 271 } 272 } 273 274 static void pnv_core_realize(DeviceState *dev, Error **errp) 275 { 276 PnvCore *pc = PNV_CORE(OBJECT(dev)); 277 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 278 CPUCore *cc = CPU_CORE(OBJECT(dev)); 279 const char *typename = pnv_core_cpu_typename(pc); 280 Error *local_err = NULL; 281 void *obj; 282 int i, j; 283 char name[32]; 284 285 assert(pc->chip); 286 287 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 288 for (i = 0; i < cc->nr_threads; i++) { 289 PowerPCCPU *cpu; 290 PnvCPUState *pnv_cpu; 291 292 obj = object_new(typename); 293 cpu = POWERPC_CPU(obj); 294 295 pc->threads[i] = POWERPC_CPU(obj); 296 if (cc->nr_threads > 1) { 297 cpu->env.has_smt_siblings = true; 298 } 299 300 snprintf(name, sizeof(name), "thread[%d]", i); 301 object_property_add_child(OBJECT(pc), name, obj); 302 303 cpu->machine_data = g_new0(PnvCPUState, 1); 304 pnv_cpu = pnv_cpu_state(cpu); 305 pnv_cpu->pnv_core = pc; 306 307 object_unref(obj); 308 } 309 310 for (j = 0; j < cc->nr_threads; j++) { 311 pnv_core_cpu_realize(pc, pc->threads[j], &local_err, j); 312 if (local_err) { 313 goto err; 314 } 315 } 316 317 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 318 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 319 pc, name, pcc->xscom_size); 320 321 qemu_register_reset(pnv_core_reset, pc); 322 return; 323 324 err: 325 while (--i >= 0) { 326 obj = OBJECT(pc->threads[i]); 327 object_unparent(obj); 328 } 329 g_free(pc->threads); 330 error_propagate(errp, local_err); 331 } 332 333 static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu) 334 { 335 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 336 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 337 338 pcc->intc_destroy(pc->chip, cpu); 339 cpu_remove_sync(CPU(cpu)); 340 cpu->machine_data = NULL; 341 g_free(pnv_cpu); 342 object_unparent(OBJECT(cpu)); 343 } 344 345 static void pnv_core_unrealize(DeviceState *dev) 346 { 347 PnvCore *pc = PNV_CORE(dev); 348 CPUCore *cc = CPU_CORE(dev); 349 int i; 350 351 qemu_unregister_reset(pnv_core_reset, pc); 352 353 for (i = 0; i < cc->nr_threads; i++) { 354 pnv_core_cpu_unrealize(pc, pc->threads[i]); 355 } 356 g_free(pc->threads); 357 } 358 359 static Property pnv_core_properties[] = { 360 DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0), 361 DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), 362 DEFINE_PROP_BOOL("big-core", PnvCore, big_core, false), 363 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), 364 DEFINE_PROP_END_OF_LIST(), 365 }; 366 367 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 368 { 369 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 370 371 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 372 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 373 } 374 375 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 376 { 377 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 378 379 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 380 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 381 } 382 383 static void pnv_core_power10_class_init(ObjectClass *oc, void *data) 384 { 385 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 386 387 pcc->xscom_ops = &pnv_core_power10_xscom_ops; 388 pcc->xscom_size = PNV10_XSCOM_EC_SIZE; 389 } 390 391 static void pnv_core_class_init(ObjectClass *oc, void *data) 392 { 393 DeviceClass *dc = DEVICE_CLASS(oc); 394 395 dc->realize = pnv_core_realize; 396 dc->unrealize = pnv_core_unrealize; 397 device_class_set_props(dc, pnv_core_properties); 398 dc->user_creatable = false; 399 } 400 401 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 402 { \ 403 .parent = TYPE_PNV_CORE, \ 404 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 405 .class_init = pnv_core_##family##_class_init, \ 406 } 407 408 static const TypeInfo pnv_core_infos[] = { 409 { 410 .name = TYPE_PNV_CORE, 411 .parent = TYPE_CPU_CORE, 412 .instance_size = sizeof(PnvCore), 413 .class_size = sizeof(PnvCoreClass), 414 .class_init = pnv_core_class_init, 415 .abstract = true, 416 }, 417 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 418 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 419 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 420 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), 421 DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), 422 }; 423 424 DEFINE_TYPES(pnv_core_infos) 425 426 /* 427 * POWER9 Quads 428 */ 429 430 #define P9X_EX_NCU_SPEC_BAR 0x11010 431 432 static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr, 433 unsigned int width) 434 { 435 uint32_t offset = addr >> 3; 436 uint64_t val = -1; 437 438 switch (offset) { 439 case P9X_EX_NCU_SPEC_BAR: 440 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 441 val = 0; 442 break; 443 default: 444 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 445 offset); 446 } 447 448 return val; 449 } 450 451 static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 452 unsigned int width) 453 { 454 uint32_t offset = addr >> 3; 455 456 switch (offset) { 457 case P9X_EX_NCU_SPEC_BAR: 458 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 459 break; 460 default: 461 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 462 offset); 463 } 464 } 465 466 static const MemoryRegionOps pnv_quad_power9_xscom_ops = { 467 .read = pnv_quad_power9_xscom_read, 468 .write = pnv_quad_power9_xscom_write, 469 .valid.min_access_size = 8, 470 .valid.max_access_size = 8, 471 .impl.min_access_size = 8, 472 .impl.max_access_size = 8, 473 .endianness = DEVICE_BIG_ENDIAN, 474 }; 475 476 /* 477 * POWER10 Quads 478 */ 479 480 static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, 481 unsigned int width) 482 { 483 uint32_t offset = addr >> 3; 484 uint64_t val = -1; 485 486 switch (offset) { 487 default: 488 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 489 offset); 490 } 491 492 return val; 493 } 494 495 static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, 496 uint64_t val, unsigned int width) 497 { 498 uint32_t offset = addr >> 3; 499 500 switch (offset) { 501 default: 502 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 503 offset); 504 } 505 } 506 507 static const MemoryRegionOps pnv_quad_power10_xscom_ops = { 508 .read = pnv_quad_power10_xscom_read, 509 .write = pnv_quad_power10_xscom_write, 510 .valid.min_access_size = 8, 511 .valid.max_access_size = 8, 512 .impl.min_access_size = 8, 513 .impl.max_access_size = 8, 514 .endianness = DEVICE_BIG_ENDIAN, 515 }; 516 517 #define P10_QME_SPWU_HYP 0x83c 518 #define P10_QME_SSH_HYP 0x82c 519 520 static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr, 521 unsigned int width) 522 { 523 uint32_t offset = addr >> 3; 524 uint64_t val = -1; 525 526 /* 527 * Forth nibble selects the core within a quad, mask it to process read 528 * for any core. 529 */ 530 switch (offset & ~0xf000) { 531 case P10_QME_SPWU_HYP: 532 case P10_QME_SSH_HYP: 533 return 0; 534 default: 535 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 536 offset); 537 } 538 539 return val; 540 } 541 542 static void pnv_qme_power10_xscom_write(void *opaque, hwaddr addr, 543 uint64_t val, unsigned int width) 544 { 545 uint32_t offset = addr >> 3; 546 547 switch (offset) { 548 default: 549 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 550 offset); 551 } 552 } 553 554 static const MemoryRegionOps pnv_qme_power10_xscom_ops = { 555 .read = pnv_qme_power10_xscom_read, 556 .write = pnv_qme_power10_xscom_write, 557 .valid.min_access_size = 8, 558 .valid.max_access_size = 8, 559 .impl.min_access_size = 8, 560 .impl.max_access_size = 8, 561 .endianness = DEVICE_BIG_ENDIAN, 562 }; 563 564 static void pnv_quad_power9_realize(DeviceState *dev, Error **errp) 565 { 566 PnvQuad *eq = PNV_QUAD(dev); 567 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 568 char name[32]; 569 570 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 571 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 572 pqc->xscom_ops, 573 eq, name, 574 pqc->xscom_size); 575 } 576 577 static void pnv_quad_power10_realize(DeviceState *dev, Error **errp) 578 { 579 PnvQuad *eq = PNV_QUAD(dev); 580 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 581 char name[32]; 582 583 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 584 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 585 pqc->xscom_ops, 586 eq, name, 587 pqc->xscom_size); 588 589 snprintf(name, sizeof(name), "xscom-qme.%d", eq->quad_id); 590 pnv_xscom_region_init(&eq->xscom_qme_regs, OBJECT(dev), 591 pqc->xscom_qme_ops, 592 eq, name, 593 pqc->xscom_qme_size); 594 } 595 596 static Property pnv_quad_properties[] = { 597 DEFINE_PROP_UINT32("quad-id", PnvQuad, quad_id, 0), 598 DEFINE_PROP_END_OF_LIST(), 599 }; 600 601 static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) 602 { 603 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 604 DeviceClass *dc = DEVICE_CLASS(oc); 605 606 dc->realize = pnv_quad_power9_realize; 607 608 pqc->xscom_ops = &pnv_quad_power9_xscom_ops; 609 pqc->xscom_size = PNV9_XSCOM_EQ_SIZE; 610 } 611 612 static void pnv_quad_power10_class_init(ObjectClass *oc, void *data) 613 { 614 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 615 DeviceClass *dc = DEVICE_CLASS(oc); 616 617 dc->realize = pnv_quad_power10_realize; 618 619 pqc->xscom_ops = &pnv_quad_power10_xscom_ops; 620 pqc->xscom_size = PNV10_XSCOM_EQ_SIZE; 621 622 pqc->xscom_qme_ops = &pnv_qme_power10_xscom_ops; 623 pqc->xscom_qme_size = PNV10_XSCOM_QME_SIZE; 624 } 625 626 static void pnv_quad_class_init(ObjectClass *oc, void *data) 627 { 628 DeviceClass *dc = DEVICE_CLASS(oc); 629 630 device_class_set_props(dc, pnv_quad_properties); 631 dc->user_creatable = false; 632 } 633 634 static const TypeInfo pnv_quad_infos[] = { 635 { 636 .name = TYPE_PNV_QUAD, 637 .parent = TYPE_DEVICE, 638 .instance_size = sizeof(PnvQuad), 639 .class_size = sizeof(PnvQuadClass), 640 .class_init = pnv_quad_class_init, 641 .abstract = true, 642 }, 643 { 644 .parent = TYPE_PNV_QUAD, 645 .name = PNV_QUAD_TYPE_NAME("power9"), 646 .class_init = pnv_quad_power9_class_init, 647 }, 648 { 649 .parent = TYPE_PNV_QUAD, 650 .name = PNV_QUAD_TYPE_NAME("power10"), 651 .class_init = pnv_quad_power10_class_init, 652 }, 653 }; 654 655 DEFINE_TYPES(pnv_quad_infos); 656