1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "sysemu/sysemu.h" 21 #include "qapi/error.h" 22 #include "qemu/log.h" 23 #include "target/ppc/cpu.h" 24 #include "hw/ppc/ppc.h" 25 #include "hw/ppc/pnv.h" 26 #include "hw/ppc/pnv_core.h" 27 #include "hw/ppc/pnv_xscom.h" 28 #include "hw/ppc/xics.h" 29 30 static const char *pnv_core_cpu_typename(PnvCore *pc) 31 { 32 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 33 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 34 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 35 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 36 g_free(s); 37 return cpu_type; 38 } 39 40 static void pnv_cpu_reset(void *opaque) 41 { 42 PowerPCCPU *cpu = opaque; 43 CPUState *cs = CPU(cpu); 44 CPUPPCState *env = &cpu->env; 45 46 cpu_reset(cs); 47 48 /* 49 * the skiboot firmware elects a primary thread to initialize the 50 * system and it can be any. 51 */ 52 env->gpr[3] = PNV_FDT_ADDR; 53 env->nip = 0x10; 54 env->msr |= MSR_HVB; /* Hypervisor mode */ 55 } 56 57 /* 58 * These values are read by the PowerNV HW monitors under Linux 59 */ 60 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 61 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 62 63 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 64 unsigned int width) 65 { 66 uint32_t offset = addr >> 3; 67 uint64_t val = 0; 68 69 /* The result should be 38 C */ 70 switch (offset) { 71 case PNV_XSCOM_EX_DTS_RESULT0: 72 val = 0x26f024f023f0000ull; 73 break; 74 case PNV_XSCOM_EX_DTS_RESULT1: 75 val = 0x24f000000000000ull; 76 break; 77 default: 78 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 79 addr); 80 } 81 82 return val; 83 } 84 85 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 86 unsigned int width) 87 { 88 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 89 addr); 90 } 91 92 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 93 .read = pnv_core_power8_xscom_read, 94 .write = pnv_core_power8_xscom_write, 95 .valid.min_access_size = 8, 96 .valid.max_access_size = 8, 97 .impl.min_access_size = 8, 98 .impl.max_access_size = 8, 99 .endianness = DEVICE_BIG_ENDIAN, 100 }; 101 102 103 /* 104 * POWER9 core controls 105 */ 106 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 107 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 108 109 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 110 unsigned int width) 111 { 112 uint32_t offset = addr >> 3; 113 uint64_t val = 0; 114 115 /* The result should be 38 C */ 116 switch (offset) { 117 case PNV_XSCOM_EX_DTS_RESULT0: 118 val = 0x26f024f023f0000ull; 119 break; 120 case PNV_XSCOM_EX_DTS_RESULT1: 121 val = 0x24f000000000000ull; 122 break; 123 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 124 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 125 val = 0x0; 126 break; 127 default: 128 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 129 addr); 130 } 131 132 return val; 133 } 134 135 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 136 unsigned int width) 137 { 138 uint32_t offset = addr >> 3; 139 140 switch (offset) { 141 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 142 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 143 break; 144 default: 145 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 146 addr); 147 } 148 } 149 150 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 151 .read = pnv_core_power9_xscom_read, 152 .write = pnv_core_power9_xscom_write, 153 .valid.min_access_size = 8, 154 .valid.max_access_size = 8, 155 .impl.min_access_size = 8, 156 .impl.max_access_size = 8, 157 .endianness = DEVICE_BIG_ENDIAN, 158 }; 159 160 static void pnv_realize_vcpu(PowerPCCPU *cpu, PnvChip *chip, Error **errp) 161 { 162 CPUPPCState *env = &cpu->env; 163 int core_pir; 164 int thread_index = 0; /* TODO: TCG supports only one thread */ 165 ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; 166 Error *local_err = NULL; 167 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 168 169 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 170 if (local_err) { 171 error_propagate(errp, local_err); 172 return; 173 } 174 175 pcc->intc_create(chip, cpu, &local_err); 176 if (local_err) { 177 error_propagate(errp, local_err); 178 return; 179 } 180 181 core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort); 182 183 /* 184 * The PIR of a thread is the core PIR + the thread index. We will 185 * need to find a way to get the thread index when TCG supports 186 * more than 1. We could use the object name ? 187 */ 188 pir->default_value = core_pir + thread_index; 189 190 /* Set time-base frequency to 512 MHz */ 191 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 192 193 qemu_register_reset(pnv_cpu_reset, cpu); 194 } 195 196 static void pnv_core_realize(DeviceState *dev, Error **errp) 197 { 198 PnvCore *pc = PNV_CORE(OBJECT(dev)); 199 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 200 CPUCore *cc = CPU_CORE(OBJECT(dev)); 201 const char *typename = pnv_core_cpu_typename(pc); 202 Error *local_err = NULL; 203 void *obj; 204 int i, j; 205 char name[32]; 206 Object *chip; 207 208 chip = object_property_get_link(OBJECT(dev), "chip", &local_err); 209 if (!chip) { 210 error_propagate_prepend(errp, local_err, 211 "required link 'chip' not found: "); 212 return; 213 } 214 215 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 216 for (i = 0; i < cc->nr_threads; i++) { 217 PowerPCCPU *cpu; 218 219 obj = object_new(typename); 220 cpu = POWERPC_CPU(obj); 221 222 pc->threads[i] = POWERPC_CPU(obj); 223 224 snprintf(name, sizeof(name), "thread[%d]", i); 225 object_property_add_child(OBJECT(pc), name, obj, &error_abort); 226 object_property_add_alias(obj, "core-pir", OBJECT(pc), 227 "pir", &error_abort); 228 229 cpu->machine_data = g_new0(PnvCPUState, 1); 230 231 object_unref(obj); 232 } 233 234 for (j = 0; j < cc->nr_threads; j++) { 235 pnv_realize_vcpu(pc->threads[j], PNV_CHIP(chip), &local_err); 236 if (local_err) { 237 goto err; 238 } 239 } 240 241 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 242 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 243 pc, name, PNV_XSCOM_EX_SIZE); 244 return; 245 246 err: 247 while (--i >= 0) { 248 obj = OBJECT(pc->threads[i]); 249 object_unparent(obj); 250 } 251 g_free(pc->threads); 252 error_propagate(errp, local_err); 253 } 254 255 static void pnv_unrealize_vcpu(PowerPCCPU *cpu) 256 { 257 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 258 259 qemu_unregister_reset(pnv_cpu_reset, cpu); 260 object_unparent(OBJECT(pnv_cpu_state(cpu)->intc)); 261 cpu_remove_sync(CPU(cpu)); 262 cpu->machine_data = NULL; 263 g_free(pnv_cpu); 264 object_unparent(OBJECT(cpu)); 265 } 266 267 static void pnv_core_unrealize(DeviceState *dev, Error **errp) 268 { 269 PnvCore *pc = PNV_CORE(dev); 270 CPUCore *cc = CPU_CORE(dev); 271 int i; 272 273 for (i = 0; i < cc->nr_threads; i++) { 274 pnv_unrealize_vcpu(pc->threads[i]); 275 } 276 g_free(pc->threads); 277 } 278 279 static Property pnv_core_properties[] = { 280 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), 281 DEFINE_PROP_END_OF_LIST(), 282 }; 283 284 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 285 { 286 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 287 288 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 289 } 290 291 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 292 { 293 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 294 295 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 296 } 297 298 static void pnv_core_class_init(ObjectClass *oc, void *data) 299 { 300 DeviceClass *dc = DEVICE_CLASS(oc); 301 302 dc->realize = pnv_core_realize; 303 dc->unrealize = pnv_core_unrealize; 304 dc->props = pnv_core_properties; 305 } 306 307 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 308 { \ 309 .parent = TYPE_PNV_CORE, \ 310 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 311 .class_init = pnv_core_##family##_class_init, \ 312 } 313 314 static const TypeInfo pnv_core_infos[] = { 315 { 316 .name = TYPE_PNV_CORE, 317 .parent = TYPE_CPU_CORE, 318 .instance_size = sizeof(PnvCore), 319 .class_size = sizeof(PnvCoreClass), 320 .class_init = pnv_core_class_init, 321 .abstract = true, 322 }, 323 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 324 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 325 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 326 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), 327 }; 328 329 DEFINE_TYPES(pnv_core_infos) 330 331 /* 332 * POWER9 Quads 333 */ 334 335 #define P9X_EX_NCU_SPEC_BAR 0x11010 336 337 static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, 338 unsigned int width) 339 { 340 uint32_t offset = addr >> 3; 341 uint64_t val = -1; 342 343 switch (offset) { 344 case P9X_EX_NCU_SPEC_BAR: 345 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 346 val = 0; 347 break; 348 default: 349 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 350 offset); 351 } 352 353 return val; 354 } 355 356 static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val, 357 unsigned int width) 358 { 359 uint32_t offset = addr >> 3; 360 361 switch (offset) { 362 case P9X_EX_NCU_SPEC_BAR: 363 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 364 break; 365 default: 366 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 367 offset); 368 } 369 } 370 371 static const MemoryRegionOps pnv_quad_xscom_ops = { 372 .read = pnv_quad_xscom_read, 373 .write = pnv_quad_xscom_write, 374 .valid.min_access_size = 8, 375 .valid.max_access_size = 8, 376 .impl.min_access_size = 8, 377 .impl.max_access_size = 8, 378 .endianness = DEVICE_BIG_ENDIAN, 379 }; 380 381 static void pnv_quad_realize(DeviceState *dev, Error **errp) 382 { 383 PnvQuad *eq = PNV_QUAD(dev); 384 char name[32]; 385 386 snprintf(name, sizeof(name), "xscom-quad.%d", eq->id); 387 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops, 388 eq, name, PNV9_XSCOM_EQ_SIZE); 389 } 390 391 static Property pnv_quad_properties[] = { 392 DEFINE_PROP_UINT32("id", PnvQuad, id, 0), 393 DEFINE_PROP_END_OF_LIST(), 394 }; 395 396 static void pnv_quad_class_init(ObjectClass *oc, void *data) 397 { 398 DeviceClass *dc = DEVICE_CLASS(oc); 399 400 dc->realize = pnv_quad_realize; 401 dc->props = pnv_quad_properties; 402 } 403 404 static const TypeInfo pnv_quad_info = { 405 .name = TYPE_PNV_QUAD, 406 .parent = TYPE_DEVICE, 407 .instance_size = sizeof(PnvQuad), 408 .class_init = pnv_quad_class_init, 409 }; 410 411 static void pnv_core_register_types(void) 412 { 413 type_register_static(&pnv_quad_info); 414 } 415 416 type_init(pnv_core_register_types) 417