1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #include "qemu/osdep.h" 20 #include "sysemu/sysemu.h" 21 #include "qapi/error.h" 22 #include "qemu/log.h" 23 #include "target-ppc/cpu.h" 24 #include "hw/ppc/ppc.h" 25 #include "hw/ppc/pnv.h" 26 #include "hw/ppc/pnv_core.h" 27 28 static void powernv_cpu_reset(void *opaque) 29 { 30 PowerPCCPU *cpu = opaque; 31 CPUState *cs = CPU(cpu); 32 CPUPPCState *env = &cpu->env; 33 34 cpu_reset(cs); 35 36 /* 37 * the skiboot firmware elects a primary thread to initialize the 38 * system and it can be any. 39 */ 40 env->gpr[3] = PNV_FDT_ADDR; 41 env->nip = 0x10; 42 env->msr |= MSR_HVB; /* Hypervisor mode */ 43 } 44 45 static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp) 46 { 47 CPUPPCState *env = &cpu->env; 48 int core_pir; 49 int thread_index = 0; /* TODO: TCG supports only one thread */ 50 ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; 51 52 core_pir = object_property_get_int(OBJECT(cpu), "core-pir", &error_abort); 53 54 /* 55 * The PIR of a thread is the core PIR + the thread index. We will 56 * need to find a way to get the thread index when TCG supports 57 * more than 1. We could use the object name ? 58 */ 59 pir->default_value = core_pir + thread_index; 60 61 /* Set time-base frequency to 512 MHz */ 62 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 63 64 qemu_register_reset(powernv_cpu_reset, cpu); 65 } 66 67 /* 68 * These values are read by the PowerNV HW monitors under Linux 69 */ 70 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 71 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 72 73 static uint64_t pnv_core_xscom_read(void *opaque, hwaddr addr, 74 unsigned int width) 75 { 76 uint32_t offset = addr >> 3; 77 uint64_t val = 0; 78 79 /* The result should be 38 C */ 80 switch (offset) { 81 case PNV_XSCOM_EX_DTS_RESULT0: 82 val = 0x26f024f023f0000ull; 83 break; 84 case PNV_XSCOM_EX_DTS_RESULT1: 85 val = 0x24f000000000000ull; 86 break; 87 default: 88 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx, 89 addr); 90 } 91 92 return val; 93 } 94 95 static void pnv_core_xscom_write(void *opaque, hwaddr addr, uint64_t val, 96 unsigned int width) 97 { 98 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx, 99 addr); 100 } 101 102 static const MemoryRegionOps pnv_core_xscom_ops = { 103 .read = pnv_core_xscom_read, 104 .write = pnv_core_xscom_write, 105 .valid.min_access_size = 8, 106 .valid.max_access_size = 8, 107 .impl.min_access_size = 8, 108 .impl.max_access_size = 8, 109 .endianness = DEVICE_BIG_ENDIAN, 110 }; 111 112 static void pnv_core_realize_child(Object *child, Error **errp) 113 { 114 Error *local_err = NULL; 115 CPUState *cs = CPU(child); 116 PowerPCCPU *cpu = POWERPC_CPU(cs); 117 118 object_property_set_bool(child, true, "realized", &local_err); 119 if (local_err) { 120 error_propagate(errp, local_err); 121 return; 122 } 123 124 powernv_cpu_init(cpu, &local_err); 125 if (local_err) { 126 error_propagate(errp, local_err); 127 return; 128 } 129 } 130 131 static void pnv_core_realize(DeviceState *dev, Error **errp) 132 { 133 PnvCore *pc = PNV_CORE(OBJECT(dev)); 134 CPUCore *cc = CPU_CORE(OBJECT(dev)); 135 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(OBJECT(dev)); 136 const char *typename = object_class_get_name(pcc->cpu_oc); 137 size_t size = object_type_get_instance_size(typename); 138 Error *local_err = NULL; 139 void *obj; 140 int i, j; 141 char name[32]; 142 143 pc->threads = g_malloc0(size * cc->nr_threads); 144 for (i = 0; i < cc->nr_threads; i++) { 145 obj = pc->threads + i * size; 146 147 object_initialize(obj, size, typename); 148 149 snprintf(name, sizeof(name), "thread[%d]", i); 150 object_property_add_child(OBJECT(pc), name, obj, &local_err); 151 object_property_add_alias(obj, "core-pir", OBJECT(pc), 152 "pir", &local_err); 153 if (local_err) { 154 goto err; 155 } 156 object_unref(obj); 157 } 158 159 for (j = 0; j < cc->nr_threads; j++) { 160 obj = pc->threads + j * size; 161 162 pnv_core_realize_child(obj, &local_err); 163 if (local_err) { 164 goto err; 165 } 166 } 167 168 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 169 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops, 170 pc, name, PNV_XSCOM_EX_CORE_SIZE); 171 return; 172 173 err: 174 while (--i >= 0) { 175 obj = pc->threads + i * size; 176 object_unparent(obj); 177 } 178 g_free(pc->threads); 179 error_propagate(errp, local_err); 180 } 181 182 static Property pnv_core_properties[] = { 183 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), 184 DEFINE_PROP_END_OF_LIST(), 185 }; 186 187 static void pnv_core_class_init(ObjectClass *oc, void *data) 188 { 189 DeviceClass *dc = DEVICE_CLASS(oc); 190 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 191 192 dc->realize = pnv_core_realize; 193 dc->props = pnv_core_properties; 194 pcc->cpu_oc = cpu_class_by_name(TYPE_POWERPC_CPU, data); 195 } 196 197 static const TypeInfo pnv_core_info = { 198 .name = TYPE_PNV_CORE, 199 .parent = TYPE_CPU_CORE, 200 .instance_size = sizeof(PnvCore), 201 .class_size = sizeof(PnvCoreClass), 202 .abstract = true, 203 }; 204 205 static const char *pnv_core_models[] = { 206 "POWER8E", "POWER8", "POWER8NVL", "POWER9" 207 }; 208 209 static void pnv_core_register_types(void) 210 { 211 int i ; 212 213 type_register_static(&pnv_core_info); 214 for (i = 0; i < ARRAY_SIZE(pnv_core_models); ++i) { 215 TypeInfo ti = { 216 .parent = TYPE_PNV_CORE, 217 .instance_size = sizeof(PnvCore), 218 .class_init = pnv_core_class_init, 219 .class_data = (void *) pnv_core_models[i], 220 }; 221 ti.name = pnv_core_typename(pnv_core_models[i]); 222 type_register(&ti); 223 g_free((void *)ti.name); 224 } 225 } 226 227 type_init(pnv_core_register_types) 228 229 char *pnv_core_typename(const char *model) 230 { 231 return g_strdup_printf(TYPE_PNV_CORE "-%s", model); 232 } 233