1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2.1 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/reset.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "target/ppc/cpu.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_chip.h" 29 #include "hw/ppc/pnv_core.h" 30 #include "hw/ppc/pnv_xscom.h" 31 #include "hw/ppc/xics.h" 32 #include "hw/qdev-properties.h" 33 #include "helper_regs.h" 34 35 static const char *pnv_core_cpu_typename(PnvCore *pc) 36 { 37 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 39 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 40 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 41 g_free(s); 42 return cpu_type; 43 } 44 45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) 46 { 47 CPUState *cs = CPU(cpu); 48 CPUPPCState *env = &cpu->env; 49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 50 51 cpu_reset(cs); 52 53 /* 54 * the skiboot firmware elects a primary thread to initialize the 55 * system and it can be any. 56 */ 57 env->gpr[3] = PNV_FDT_ADDR; 58 env->nip = 0x10; 59 env->msr |= MSR_HVB; /* Hypervisor mode */ 60 env->spr[SPR_HRMOR] = pc->hrmor; 61 hreg_compute_hflags(env); 62 ppc_maybe_interrupt(env); 63 64 cpu_ppc_tb_reset(env); 65 66 pcc->intc_reset(pc->chip, cpu); 67 } 68 69 /* 70 * These values are read by the PowerNV HW monitors under Linux 71 */ 72 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 73 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 74 75 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 76 unsigned int width) 77 { 78 uint32_t offset = addr >> 3; 79 uint64_t val = 0; 80 81 /* The result should be 38 C */ 82 switch (offset) { 83 case PNV_XSCOM_EX_DTS_RESULT0: 84 val = 0x26f024f023f0000ull; 85 break; 86 case PNV_XSCOM_EX_DTS_RESULT1: 87 val = 0x24f000000000000ull; 88 break; 89 default: 90 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 91 offset); 92 } 93 94 return val; 95 } 96 97 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 98 unsigned int width) 99 { 100 uint32_t offset = addr >> 3; 101 102 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 103 offset); 104 } 105 106 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 107 .read = pnv_core_power8_xscom_read, 108 .write = pnv_core_power8_xscom_write, 109 .valid.min_access_size = 8, 110 .valid.max_access_size = 8, 111 .impl.min_access_size = 8, 112 .impl.max_access_size = 8, 113 .endianness = DEVICE_BIG_ENDIAN, 114 }; 115 116 117 /* 118 * POWER9 core controls 119 */ 120 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 121 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 122 123 #define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3 124 125 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 126 unsigned int width) 127 { 128 uint32_t offset = addr >> 3; 129 uint64_t val = 0; 130 131 /* The result should be 38 C */ 132 switch (offset) { 133 case PNV_XSCOM_EX_DTS_RESULT0: 134 val = 0x26f024f023f0000ull; 135 break; 136 case PNV_XSCOM_EX_DTS_RESULT1: 137 val = 0x24f000000000000ull; 138 break; 139 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 140 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 141 val = 0x0; 142 break; 143 case PNV9_XSCOM_EC_CORE_THREAD_STATE: 144 val = 0; 145 break; 146 default: 147 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 148 offset); 149 } 150 151 return val; 152 } 153 154 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 155 unsigned int width) 156 { 157 uint32_t offset = addr >> 3; 158 159 switch (offset) { 160 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 161 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 162 break; 163 default: 164 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 165 offset); 166 } 167 } 168 169 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 170 .read = pnv_core_power9_xscom_read, 171 .write = pnv_core_power9_xscom_write, 172 .valid.min_access_size = 8, 173 .valid.max_access_size = 8, 174 .impl.min_access_size = 8, 175 .impl.max_access_size = 8, 176 .endianness = DEVICE_BIG_ENDIAN, 177 }; 178 179 /* 180 * POWER10 core controls 181 */ 182 183 #define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412 184 185 static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr, 186 unsigned int width) 187 { 188 uint32_t offset = addr >> 3; 189 uint64_t val = 0; 190 191 switch (offset) { 192 case PNV10_XSCOM_EC_CORE_THREAD_STATE: 193 val = 0; 194 break; 195 default: 196 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 197 offset); 198 } 199 200 return val; 201 } 202 203 static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr, 204 uint64_t val, unsigned int width) 205 { 206 uint32_t offset = addr >> 3; 207 208 switch (offset) { 209 default: 210 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 211 offset); 212 } 213 } 214 215 static const MemoryRegionOps pnv_core_power10_xscom_ops = { 216 .read = pnv_core_power10_xscom_read, 217 .write = pnv_core_power10_xscom_write, 218 .valid.min_access_size = 8, 219 .valid.max_access_size = 8, 220 .impl.min_access_size = 8, 221 .impl.max_access_size = 8, 222 .endianness = DEVICE_BIG_ENDIAN, 223 }; 224 225 static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, 226 int thread_index) 227 { 228 CPUPPCState *env = &cpu->env; 229 int core_hwid; 230 ppc_spr_t *pir_spr = &env->spr_cb[SPR_PIR]; 231 ppc_spr_t *tir_spr = &env->spr_cb[SPR_TIR]; 232 uint32_t pir, tir; 233 Error *local_err = NULL; 234 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 235 236 if (!qdev_realize(DEVICE(cpu), NULL, errp)) { 237 return; 238 } 239 240 pcc->intc_create(pc->chip, cpu, &local_err); 241 if (local_err) { 242 error_propagate(errp, local_err); 243 return; 244 } 245 246 core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort); 247 248 pcc->get_pir_tir(pc->chip, core_hwid, thread_index, &pir, &tir); 249 pir_spr->default_value = pir; 250 tir_spr->default_value = tir; 251 252 env->core_index = core_hwid; 253 254 /* Set time-base frequency to 512 MHz */ 255 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 256 } 257 258 static void pnv_core_reset(void *dev) 259 { 260 CPUCore *cc = CPU_CORE(dev); 261 PnvCore *pc = PNV_CORE(dev); 262 int i; 263 264 for (i = 0; i < cc->nr_threads; i++) { 265 pnv_core_cpu_reset(pc, pc->threads[i]); 266 } 267 } 268 269 static void pnv_core_realize(DeviceState *dev, Error **errp) 270 { 271 PnvCore *pc = PNV_CORE(OBJECT(dev)); 272 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 273 CPUCore *cc = CPU_CORE(OBJECT(dev)); 274 const char *typename = pnv_core_cpu_typename(pc); 275 Error *local_err = NULL; 276 void *obj; 277 int i, j; 278 char name[32]; 279 280 assert(pc->chip); 281 282 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 283 for (i = 0; i < cc->nr_threads; i++) { 284 PowerPCCPU *cpu; 285 PnvCPUState *pnv_cpu; 286 287 obj = object_new(typename); 288 cpu = POWERPC_CPU(obj); 289 290 pc->threads[i] = POWERPC_CPU(obj); 291 if (cc->nr_threads > 1) { 292 cpu->env.has_smt_siblings = true; 293 } 294 295 snprintf(name, sizeof(name), "thread[%d]", i); 296 object_property_add_child(OBJECT(pc), name, obj); 297 298 cpu->machine_data = g_new0(PnvCPUState, 1); 299 pnv_cpu = pnv_cpu_state(cpu); 300 pnv_cpu->pnv_core = pc; 301 302 object_unref(obj); 303 } 304 305 for (j = 0; j < cc->nr_threads; j++) { 306 pnv_core_cpu_realize(pc, pc->threads[j], &local_err, j); 307 if (local_err) { 308 goto err; 309 } 310 } 311 312 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 313 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 314 pc, name, pcc->xscom_size); 315 316 qemu_register_reset(pnv_core_reset, pc); 317 return; 318 319 err: 320 while (--i >= 0) { 321 obj = OBJECT(pc->threads[i]); 322 object_unparent(obj); 323 } 324 g_free(pc->threads); 325 error_propagate(errp, local_err); 326 } 327 328 static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu) 329 { 330 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 331 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 332 333 pcc->intc_destroy(pc->chip, cpu); 334 cpu_remove_sync(CPU(cpu)); 335 cpu->machine_data = NULL; 336 g_free(pnv_cpu); 337 object_unparent(OBJECT(cpu)); 338 } 339 340 static void pnv_core_unrealize(DeviceState *dev) 341 { 342 PnvCore *pc = PNV_CORE(dev); 343 CPUCore *cc = CPU_CORE(dev); 344 int i; 345 346 qemu_unregister_reset(pnv_core_reset, pc); 347 348 for (i = 0; i < cc->nr_threads; i++) { 349 pnv_core_cpu_unrealize(pc, pc->threads[i]); 350 } 351 g_free(pc->threads); 352 } 353 354 static Property pnv_core_properties[] = { 355 DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0), 356 DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), 357 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), 358 DEFINE_PROP_END_OF_LIST(), 359 }; 360 361 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 362 { 363 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 364 365 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 366 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 367 } 368 369 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 370 { 371 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 372 373 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 374 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 375 } 376 377 static void pnv_core_power10_class_init(ObjectClass *oc, void *data) 378 { 379 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 380 381 pcc->xscom_ops = &pnv_core_power10_xscom_ops; 382 pcc->xscom_size = PNV10_XSCOM_EC_SIZE; 383 } 384 385 static void pnv_core_class_init(ObjectClass *oc, void *data) 386 { 387 DeviceClass *dc = DEVICE_CLASS(oc); 388 389 dc->realize = pnv_core_realize; 390 dc->unrealize = pnv_core_unrealize; 391 device_class_set_props(dc, pnv_core_properties); 392 dc->user_creatable = false; 393 } 394 395 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 396 { \ 397 .parent = TYPE_PNV_CORE, \ 398 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 399 .class_init = pnv_core_##family##_class_init, \ 400 } 401 402 static const TypeInfo pnv_core_infos[] = { 403 { 404 .name = TYPE_PNV_CORE, 405 .parent = TYPE_CPU_CORE, 406 .instance_size = sizeof(PnvCore), 407 .class_size = sizeof(PnvCoreClass), 408 .class_init = pnv_core_class_init, 409 .abstract = true, 410 }, 411 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 412 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 413 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 414 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), 415 DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), 416 }; 417 418 DEFINE_TYPES(pnv_core_infos) 419 420 /* 421 * POWER9 Quads 422 */ 423 424 #define P9X_EX_NCU_SPEC_BAR 0x11010 425 426 static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr, 427 unsigned int width) 428 { 429 uint32_t offset = addr >> 3; 430 uint64_t val = -1; 431 432 switch (offset) { 433 case P9X_EX_NCU_SPEC_BAR: 434 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 435 val = 0; 436 break; 437 default: 438 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 439 offset); 440 } 441 442 return val; 443 } 444 445 static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 446 unsigned int width) 447 { 448 uint32_t offset = addr >> 3; 449 450 switch (offset) { 451 case P9X_EX_NCU_SPEC_BAR: 452 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 453 break; 454 default: 455 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 456 offset); 457 } 458 } 459 460 static const MemoryRegionOps pnv_quad_power9_xscom_ops = { 461 .read = pnv_quad_power9_xscom_read, 462 .write = pnv_quad_power9_xscom_write, 463 .valid.min_access_size = 8, 464 .valid.max_access_size = 8, 465 .impl.min_access_size = 8, 466 .impl.max_access_size = 8, 467 .endianness = DEVICE_BIG_ENDIAN, 468 }; 469 470 /* 471 * POWER10 Quads 472 */ 473 474 static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, 475 unsigned int width) 476 { 477 uint32_t offset = addr >> 3; 478 uint64_t val = -1; 479 480 switch (offset) { 481 default: 482 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 483 offset); 484 } 485 486 return val; 487 } 488 489 static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, 490 uint64_t val, unsigned int width) 491 { 492 uint32_t offset = addr >> 3; 493 494 switch (offset) { 495 default: 496 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 497 offset); 498 } 499 } 500 501 static const MemoryRegionOps pnv_quad_power10_xscom_ops = { 502 .read = pnv_quad_power10_xscom_read, 503 .write = pnv_quad_power10_xscom_write, 504 .valid.min_access_size = 8, 505 .valid.max_access_size = 8, 506 .impl.min_access_size = 8, 507 .impl.max_access_size = 8, 508 .endianness = DEVICE_BIG_ENDIAN, 509 }; 510 511 #define P10_QME_SPWU_HYP 0x83c 512 #define P10_QME_SSH_HYP 0x82c 513 514 static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr, 515 unsigned int width) 516 { 517 uint32_t offset = addr >> 3; 518 uint64_t val = -1; 519 520 /* 521 * Forth nibble selects the core within a quad, mask it to process read 522 * for any core. 523 */ 524 switch (offset & ~0xf000) { 525 case P10_QME_SPWU_HYP: 526 case P10_QME_SSH_HYP: 527 return 0; 528 default: 529 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 530 offset); 531 } 532 533 return val; 534 } 535 536 static void pnv_qme_power10_xscom_write(void *opaque, hwaddr addr, 537 uint64_t val, unsigned int width) 538 { 539 uint32_t offset = addr >> 3; 540 541 switch (offset) { 542 default: 543 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 544 offset); 545 } 546 } 547 548 static const MemoryRegionOps pnv_qme_power10_xscom_ops = { 549 .read = pnv_qme_power10_xscom_read, 550 .write = pnv_qme_power10_xscom_write, 551 .valid.min_access_size = 8, 552 .valid.max_access_size = 8, 553 .impl.min_access_size = 8, 554 .impl.max_access_size = 8, 555 .endianness = DEVICE_BIG_ENDIAN, 556 }; 557 558 static void pnv_quad_power9_realize(DeviceState *dev, Error **errp) 559 { 560 PnvQuad *eq = PNV_QUAD(dev); 561 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 562 char name[32]; 563 564 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 565 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 566 pqc->xscom_ops, 567 eq, name, 568 pqc->xscom_size); 569 } 570 571 static void pnv_quad_power10_realize(DeviceState *dev, Error **errp) 572 { 573 PnvQuad *eq = PNV_QUAD(dev); 574 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 575 char name[32]; 576 577 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 578 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 579 pqc->xscom_ops, 580 eq, name, 581 pqc->xscom_size); 582 583 snprintf(name, sizeof(name), "xscom-qme.%d", eq->quad_id); 584 pnv_xscom_region_init(&eq->xscom_qme_regs, OBJECT(dev), 585 pqc->xscom_qme_ops, 586 eq, name, 587 pqc->xscom_qme_size); 588 } 589 590 static Property pnv_quad_properties[] = { 591 DEFINE_PROP_UINT32("quad-id", PnvQuad, quad_id, 0), 592 DEFINE_PROP_END_OF_LIST(), 593 }; 594 595 static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) 596 { 597 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 598 DeviceClass *dc = DEVICE_CLASS(oc); 599 600 dc->realize = pnv_quad_power9_realize; 601 602 pqc->xscom_ops = &pnv_quad_power9_xscom_ops; 603 pqc->xscom_size = PNV9_XSCOM_EQ_SIZE; 604 } 605 606 static void pnv_quad_power10_class_init(ObjectClass *oc, void *data) 607 { 608 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 609 DeviceClass *dc = DEVICE_CLASS(oc); 610 611 dc->realize = pnv_quad_power10_realize; 612 613 pqc->xscom_ops = &pnv_quad_power10_xscom_ops; 614 pqc->xscom_size = PNV10_XSCOM_EQ_SIZE; 615 616 pqc->xscom_qme_ops = &pnv_qme_power10_xscom_ops; 617 pqc->xscom_qme_size = PNV10_XSCOM_QME_SIZE; 618 } 619 620 static void pnv_quad_class_init(ObjectClass *oc, void *data) 621 { 622 DeviceClass *dc = DEVICE_CLASS(oc); 623 624 device_class_set_props(dc, pnv_quad_properties); 625 dc->user_creatable = false; 626 } 627 628 static const TypeInfo pnv_quad_infos[] = { 629 { 630 .name = TYPE_PNV_QUAD, 631 .parent = TYPE_DEVICE, 632 .instance_size = sizeof(PnvQuad), 633 .class_size = sizeof(PnvQuadClass), 634 .class_init = pnv_quad_class_init, 635 .abstract = true, 636 }, 637 { 638 .parent = TYPE_PNV_QUAD, 639 .name = PNV_QUAD_TYPE_NAME("power9"), 640 .class_init = pnv_quad_power9_class_init, 641 }, 642 { 643 .parent = TYPE_PNV_QUAD, 644 .name = PNV_QUAD_TYPE_NAME("power10"), 645 .class_init = pnv_quad_power10_class_init, 646 }, 647 }; 648 649 DEFINE_TYPES(pnv_quad_infos); 650