1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/reset.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "target/ppc/cpu.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_core.h" 29 #include "hw/ppc/pnv_xscom.h" 30 #include "hw/ppc/xics.h" 31 #include "hw/qdev-properties.h" 32 33 static const char *pnv_core_cpu_typename(PnvCore *pc) 34 { 35 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 36 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 37 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 38 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 39 g_free(s); 40 return cpu_type; 41 } 42 43 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) 44 { 45 CPUState *cs = CPU(cpu); 46 CPUPPCState *env = &cpu->env; 47 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 48 49 cpu_reset(cs); 50 51 /* 52 * the skiboot firmware elects a primary thread to initialize the 53 * system and it can be any. 54 */ 55 env->gpr[3] = PNV_FDT_ADDR; 56 env->nip = 0x10; 57 env->msr |= MSR_HVB; /* Hypervisor mode */ 58 59 env->spr[SPR_HRMOR] = pc->hrmor; 60 61 pcc->intc_reset(pc->chip, cpu); 62 } 63 64 /* 65 * These values are read by the PowerNV HW monitors under Linux 66 */ 67 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 68 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 69 70 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 71 unsigned int width) 72 { 73 uint32_t offset = addr >> 3; 74 uint64_t val = 0; 75 76 /* The result should be 38 C */ 77 switch (offset) { 78 case PNV_XSCOM_EX_DTS_RESULT0: 79 val = 0x26f024f023f0000ull; 80 break; 81 case PNV_XSCOM_EX_DTS_RESULT1: 82 val = 0x24f000000000000ull; 83 break; 84 default: 85 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 86 addr); 87 } 88 89 return val; 90 } 91 92 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 93 unsigned int width) 94 { 95 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 96 addr); 97 } 98 99 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 100 .read = pnv_core_power8_xscom_read, 101 .write = pnv_core_power8_xscom_write, 102 .valid.min_access_size = 8, 103 .valid.max_access_size = 8, 104 .impl.min_access_size = 8, 105 .impl.max_access_size = 8, 106 .endianness = DEVICE_BIG_ENDIAN, 107 }; 108 109 110 /* 111 * POWER9 core controls 112 */ 113 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 114 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 115 116 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 117 unsigned int width) 118 { 119 uint32_t offset = addr >> 3; 120 uint64_t val = 0; 121 122 /* The result should be 38 C */ 123 switch (offset) { 124 case PNV_XSCOM_EX_DTS_RESULT0: 125 val = 0x26f024f023f0000ull; 126 break; 127 case PNV_XSCOM_EX_DTS_RESULT1: 128 val = 0x24f000000000000ull; 129 break; 130 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 131 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 132 val = 0x0; 133 break; 134 default: 135 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 136 addr); 137 } 138 139 return val; 140 } 141 142 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 143 unsigned int width) 144 { 145 uint32_t offset = addr >> 3; 146 147 switch (offset) { 148 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 149 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 150 break; 151 default: 152 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 153 addr); 154 } 155 } 156 157 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 158 .read = pnv_core_power9_xscom_read, 159 .write = pnv_core_power9_xscom_write, 160 .valid.min_access_size = 8, 161 .valid.max_access_size = 8, 162 .impl.min_access_size = 8, 163 .impl.max_access_size = 8, 164 .endianness = DEVICE_BIG_ENDIAN, 165 }; 166 167 static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp) 168 { 169 CPUPPCState *env = &cpu->env; 170 int core_pir; 171 int thread_index = 0; /* TODO: TCG supports only one thread */ 172 ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; 173 Error *local_err = NULL; 174 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 175 176 qdev_realize(DEVICE(cpu), NULL, &local_err); 177 if (local_err) { 178 error_propagate(errp, local_err); 179 return; 180 } 181 182 pcc->intc_create(pc->chip, cpu, &local_err); 183 if (local_err) { 184 error_propagate(errp, local_err); 185 return; 186 } 187 188 core_pir = object_property_get_uint(OBJECT(pc), "pir", &error_abort); 189 190 /* 191 * The PIR of a thread is the core PIR + the thread index. We will 192 * need to find a way to get the thread index when TCG supports 193 * more than 1. We could use the object name ? 194 */ 195 pir->default_value = core_pir + thread_index; 196 197 /* Set time-base frequency to 512 MHz */ 198 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 199 } 200 201 static void pnv_core_reset(void *dev) 202 { 203 CPUCore *cc = CPU_CORE(dev); 204 PnvCore *pc = PNV_CORE(dev); 205 int i; 206 207 for (i = 0; i < cc->nr_threads; i++) { 208 pnv_core_cpu_reset(pc, pc->threads[i]); 209 } 210 } 211 212 static void pnv_core_realize(DeviceState *dev, Error **errp) 213 { 214 PnvCore *pc = PNV_CORE(OBJECT(dev)); 215 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 216 CPUCore *cc = CPU_CORE(OBJECT(dev)); 217 const char *typename = pnv_core_cpu_typename(pc); 218 Error *local_err = NULL; 219 void *obj; 220 int i, j; 221 char name[32]; 222 223 assert(pc->chip); 224 225 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 226 for (i = 0; i < cc->nr_threads; i++) { 227 PowerPCCPU *cpu; 228 229 obj = object_new(typename); 230 cpu = POWERPC_CPU(obj); 231 232 pc->threads[i] = POWERPC_CPU(obj); 233 234 snprintf(name, sizeof(name), "thread[%d]", i); 235 object_property_add_child(OBJECT(pc), name, obj); 236 237 cpu->machine_data = g_new0(PnvCPUState, 1); 238 239 object_unref(obj); 240 } 241 242 for (j = 0; j < cc->nr_threads; j++) { 243 pnv_core_cpu_realize(pc, pc->threads[j], &local_err); 244 if (local_err) { 245 goto err; 246 } 247 } 248 249 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 250 /* TODO: check PNV_XSCOM_EX_SIZE for p10 */ 251 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 252 pc, name, PNV_XSCOM_EX_SIZE); 253 254 qemu_register_reset(pnv_core_reset, pc); 255 return; 256 257 err: 258 while (--i >= 0) { 259 obj = OBJECT(pc->threads[i]); 260 object_unparent(obj); 261 } 262 g_free(pc->threads); 263 error_propagate(errp, local_err); 264 } 265 266 static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu) 267 { 268 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 269 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 270 271 pcc->intc_destroy(pc->chip, cpu); 272 cpu_remove_sync(CPU(cpu)); 273 cpu->machine_data = NULL; 274 g_free(pnv_cpu); 275 object_unparent(OBJECT(cpu)); 276 } 277 278 static void pnv_core_unrealize(DeviceState *dev) 279 { 280 PnvCore *pc = PNV_CORE(dev); 281 CPUCore *cc = CPU_CORE(dev); 282 int i; 283 284 qemu_unregister_reset(pnv_core_reset, pc); 285 286 for (i = 0; i < cc->nr_threads; i++) { 287 pnv_core_cpu_unrealize(pc, pc->threads[i]); 288 } 289 g_free(pc->threads); 290 } 291 292 static Property pnv_core_properties[] = { 293 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), 294 DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), 295 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), 296 DEFINE_PROP_END_OF_LIST(), 297 }; 298 299 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 300 { 301 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 302 303 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 304 } 305 306 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 307 { 308 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 309 310 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 311 } 312 313 static void pnv_core_power10_class_init(ObjectClass *oc, void *data) 314 { 315 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 316 317 /* TODO: Use the P9 XSCOMs for now on P10 */ 318 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 319 } 320 321 static void pnv_core_class_init(ObjectClass *oc, void *data) 322 { 323 DeviceClass *dc = DEVICE_CLASS(oc); 324 325 dc->realize = pnv_core_realize; 326 dc->unrealize = pnv_core_unrealize; 327 device_class_set_props(dc, pnv_core_properties); 328 dc->user_creatable = false; 329 } 330 331 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 332 { \ 333 .parent = TYPE_PNV_CORE, \ 334 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 335 .class_init = pnv_core_##family##_class_init, \ 336 } 337 338 static const TypeInfo pnv_core_infos[] = { 339 { 340 .name = TYPE_PNV_CORE, 341 .parent = TYPE_CPU_CORE, 342 .instance_size = sizeof(PnvCore), 343 .class_size = sizeof(PnvCoreClass), 344 .class_init = pnv_core_class_init, 345 .abstract = true, 346 }, 347 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 348 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 349 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 350 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), 351 DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"), 352 }; 353 354 DEFINE_TYPES(pnv_core_infos) 355 356 /* 357 * POWER9 Quads 358 */ 359 360 #define P9X_EX_NCU_SPEC_BAR 0x11010 361 362 static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, 363 unsigned int width) 364 { 365 uint32_t offset = addr >> 3; 366 uint64_t val = -1; 367 368 switch (offset) { 369 case P9X_EX_NCU_SPEC_BAR: 370 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 371 val = 0; 372 break; 373 default: 374 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 375 offset); 376 } 377 378 return val; 379 } 380 381 static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val, 382 unsigned int width) 383 { 384 uint32_t offset = addr >> 3; 385 386 switch (offset) { 387 case P9X_EX_NCU_SPEC_BAR: 388 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 389 break; 390 default: 391 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 392 offset); 393 } 394 } 395 396 static const MemoryRegionOps pnv_quad_xscom_ops = { 397 .read = pnv_quad_xscom_read, 398 .write = pnv_quad_xscom_write, 399 .valid.min_access_size = 8, 400 .valid.max_access_size = 8, 401 .impl.min_access_size = 8, 402 .impl.max_access_size = 8, 403 .endianness = DEVICE_BIG_ENDIAN, 404 }; 405 406 static void pnv_quad_realize(DeviceState *dev, Error **errp) 407 { 408 PnvQuad *eq = PNV_QUAD(dev); 409 char name[32]; 410 411 snprintf(name, sizeof(name), "xscom-quad.%d", eq->id); 412 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops, 413 eq, name, PNV9_XSCOM_EQ_SIZE); 414 } 415 416 static Property pnv_quad_properties[] = { 417 DEFINE_PROP_UINT32("id", PnvQuad, id, 0), 418 DEFINE_PROP_END_OF_LIST(), 419 }; 420 421 static void pnv_quad_class_init(ObjectClass *oc, void *data) 422 { 423 DeviceClass *dc = DEVICE_CLASS(oc); 424 425 dc->realize = pnv_quad_realize; 426 device_class_set_props(dc, pnv_quad_properties); 427 dc->user_creatable = false; 428 } 429 430 static const TypeInfo pnv_quad_info = { 431 .name = TYPE_PNV_QUAD, 432 .parent = TYPE_DEVICE, 433 .instance_size = sizeof(PnvQuad), 434 .class_init = pnv_quad_class_init, 435 }; 436 437 static void pnv_core_register_types(void) 438 { 439 type_register_static(&pnv_quad_info); 440 } 441 442 type_init(pnv_core_register_types) 443