1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/reset.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "target/ppc/cpu.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_core.h" 29 #include "hw/ppc/pnv_xscom.h" 30 #include "hw/ppc/xics.h" 31 #include "hw/qdev-properties.h" 32 33 static const char *pnv_core_cpu_typename(PnvCore *pc) 34 { 35 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 36 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 37 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 38 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 39 g_free(s); 40 return cpu_type; 41 } 42 43 static void pnv_core_cpu_reset(PowerPCCPU *cpu, PnvChip *chip) 44 { 45 CPUState *cs = CPU(cpu); 46 CPUPPCState *env = &cpu->env; 47 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 48 49 cpu_reset(cs); 50 51 /* 52 * the skiboot firmware elects a primary thread to initialize the 53 * system and it can be any. 54 */ 55 env->gpr[3] = PNV_FDT_ADDR; 56 env->nip = 0x10; 57 env->msr |= MSR_HVB; /* Hypervisor mode */ 58 59 pcc->intc_reset(chip, cpu); 60 } 61 62 /* 63 * These values are read by the PowerNV HW monitors under Linux 64 */ 65 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 66 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 67 68 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 69 unsigned int width) 70 { 71 uint32_t offset = addr >> 3; 72 uint64_t val = 0; 73 74 /* The result should be 38 C */ 75 switch (offset) { 76 case PNV_XSCOM_EX_DTS_RESULT0: 77 val = 0x26f024f023f0000ull; 78 break; 79 case PNV_XSCOM_EX_DTS_RESULT1: 80 val = 0x24f000000000000ull; 81 break; 82 default: 83 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 84 addr); 85 } 86 87 return val; 88 } 89 90 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 91 unsigned int width) 92 { 93 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 94 addr); 95 } 96 97 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 98 .read = pnv_core_power8_xscom_read, 99 .write = pnv_core_power8_xscom_write, 100 .valid.min_access_size = 8, 101 .valid.max_access_size = 8, 102 .impl.min_access_size = 8, 103 .impl.max_access_size = 8, 104 .endianness = DEVICE_BIG_ENDIAN, 105 }; 106 107 108 /* 109 * POWER9 core controls 110 */ 111 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 112 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 113 114 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 115 unsigned int width) 116 { 117 uint32_t offset = addr >> 3; 118 uint64_t val = 0; 119 120 /* The result should be 38 C */ 121 switch (offset) { 122 case PNV_XSCOM_EX_DTS_RESULT0: 123 val = 0x26f024f023f0000ull; 124 break; 125 case PNV_XSCOM_EX_DTS_RESULT1: 126 val = 0x24f000000000000ull; 127 break; 128 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 129 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 130 val = 0x0; 131 break; 132 default: 133 qemu_log_mask(LOG_UNIMP, "Warning: reading reg=0x%" HWADDR_PRIx "\n", 134 addr); 135 } 136 137 return val; 138 } 139 140 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 141 unsigned int width) 142 { 143 uint32_t offset = addr >> 3; 144 145 switch (offset) { 146 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 147 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 148 break; 149 default: 150 qemu_log_mask(LOG_UNIMP, "Warning: writing to reg=0x%" HWADDR_PRIx "\n", 151 addr); 152 } 153 } 154 155 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 156 .read = pnv_core_power9_xscom_read, 157 .write = pnv_core_power9_xscom_write, 158 .valid.min_access_size = 8, 159 .valid.max_access_size = 8, 160 .impl.min_access_size = 8, 161 .impl.max_access_size = 8, 162 .endianness = DEVICE_BIG_ENDIAN, 163 }; 164 165 static void pnv_core_cpu_realize(PowerPCCPU *cpu, PnvChip *chip, Error **errp) 166 { 167 CPUPPCState *env = &cpu->env; 168 int core_pir; 169 int thread_index = 0; /* TODO: TCG supports only one thread */ 170 ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; 171 Error *local_err = NULL; 172 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 173 174 object_property_set_bool(OBJECT(cpu), true, "realized", &local_err); 175 if (local_err) { 176 error_propagate(errp, local_err); 177 return; 178 } 179 180 pcc->intc_create(chip, cpu, &local_err); 181 if (local_err) { 182 error_propagate(errp, local_err); 183 return; 184 } 185 186 core_pir = object_property_get_uint(OBJECT(cpu), "core-pir", &error_abort); 187 188 /* 189 * The PIR of a thread is the core PIR + the thread index. We will 190 * need to find a way to get the thread index when TCG supports 191 * more than 1. We could use the object name ? 192 */ 193 pir->default_value = core_pir + thread_index; 194 195 /* Set time-base frequency to 512 MHz */ 196 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 197 } 198 199 static void pnv_core_reset(void *dev) 200 { 201 CPUCore *cc = CPU_CORE(dev); 202 PnvCore *pc = PNV_CORE(dev); 203 int i; 204 205 for (i = 0; i < cc->nr_threads; i++) { 206 pnv_core_cpu_reset(pc->threads[i], pc->chip); 207 } 208 } 209 210 static void pnv_core_realize(DeviceState *dev, Error **errp) 211 { 212 PnvCore *pc = PNV_CORE(OBJECT(dev)); 213 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 214 CPUCore *cc = CPU_CORE(OBJECT(dev)); 215 const char *typename = pnv_core_cpu_typename(pc); 216 Error *local_err = NULL; 217 void *obj; 218 int i, j; 219 char name[32]; 220 221 assert(pc->chip); 222 223 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 224 for (i = 0; i < cc->nr_threads; i++) { 225 PowerPCCPU *cpu; 226 227 obj = object_new(typename); 228 cpu = POWERPC_CPU(obj); 229 230 pc->threads[i] = POWERPC_CPU(obj); 231 232 snprintf(name, sizeof(name), "thread[%d]", i); 233 object_property_add_child(OBJECT(pc), name, obj, &error_abort); 234 object_property_add_alias(obj, "core-pir", OBJECT(pc), 235 "pir", &error_abort); 236 237 cpu->machine_data = g_new0(PnvCPUState, 1); 238 239 object_unref(obj); 240 } 241 242 for (j = 0; j < cc->nr_threads; j++) { 243 pnv_core_cpu_realize(pc->threads[j], pc->chip, &local_err); 244 if (local_err) { 245 goto err; 246 } 247 } 248 249 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 250 /* TODO: check PNV_XSCOM_EX_SIZE for p10 */ 251 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 252 pc, name, PNV_XSCOM_EX_SIZE); 253 254 qemu_register_reset(pnv_core_reset, pc); 255 return; 256 257 err: 258 while (--i >= 0) { 259 obj = OBJECT(pc->threads[i]); 260 object_unparent(obj); 261 } 262 g_free(pc->threads); 263 error_propagate(errp, local_err); 264 } 265 266 static void pnv_core_cpu_unrealize(PowerPCCPU *cpu, PnvChip *chip) 267 { 268 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 269 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 270 271 pcc->intc_destroy(chip, cpu); 272 cpu_remove_sync(CPU(cpu)); 273 cpu->machine_data = NULL; 274 g_free(pnv_cpu); 275 object_unparent(OBJECT(cpu)); 276 } 277 278 static void pnv_core_unrealize(DeviceState *dev, Error **errp) 279 { 280 PnvCore *pc = PNV_CORE(dev); 281 CPUCore *cc = CPU_CORE(dev); 282 int i; 283 284 qemu_unregister_reset(pnv_core_reset, pc); 285 286 for (i = 0; i < cc->nr_threads; i++) { 287 pnv_core_cpu_unrealize(pc->threads[i], pc->chip); 288 } 289 g_free(pc->threads); 290 } 291 292 static Property pnv_core_properties[] = { 293 DEFINE_PROP_UINT32("pir", PnvCore, pir, 0), 294 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), 295 DEFINE_PROP_END_OF_LIST(), 296 }; 297 298 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 299 { 300 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 301 302 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 303 } 304 305 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 306 { 307 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 308 309 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 310 } 311 312 static void pnv_core_power10_class_init(ObjectClass *oc, void *data) 313 { 314 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 315 316 /* TODO: Use the P9 XSCOMs for now on P10 */ 317 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 318 } 319 320 static void pnv_core_class_init(ObjectClass *oc, void *data) 321 { 322 DeviceClass *dc = DEVICE_CLASS(oc); 323 324 dc->realize = pnv_core_realize; 325 dc->unrealize = pnv_core_unrealize; 326 dc->props = pnv_core_properties; 327 } 328 329 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 330 { \ 331 .parent = TYPE_PNV_CORE, \ 332 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 333 .class_init = pnv_core_##family##_class_init, \ 334 } 335 336 static const TypeInfo pnv_core_infos[] = { 337 { 338 .name = TYPE_PNV_CORE, 339 .parent = TYPE_CPU_CORE, 340 .instance_size = sizeof(PnvCore), 341 .class_size = sizeof(PnvCoreClass), 342 .class_init = pnv_core_class_init, 343 .abstract = true, 344 }, 345 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 346 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 347 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 348 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.0"), 349 DEFINE_PNV_CORE_TYPE(power10, "power10_v1.0"), 350 }; 351 352 DEFINE_TYPES(pnv_core_infos) 353 354 /* 355 * POWER9 Quads 356 */ 357 358 #define P9X_EX_NCU_SPEC_BAR 0x11010 359 360 static uint64_t pnv_quad_xscom_read(void *opaque, hwaddr addr, 361 unsigned int width) 362 { 363 uint32_t offset = addr >> 3; 364 uint64_t val = -1; 365 366 switch (offset) { 367 case P9X_EX_NCU_SPEC_BAR: 368 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 369 val = 0; 370 break; 371 default: 372 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 373 offset); 374 } 375 376 return val; 377 } 378 379 static void pnv_quad_xscom_write(void *opaque, hwaddr addr, uint64_t val, 380 unsigned int width) 381 { 382 uint32_t offset = addr >> 3; 383 384 switch (offset) { 385 case P9X_EX_NCU_SPEC_BAR: 386 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 387 break; 388 default: 389 qemu_log_mask(LOG_UNIMP, "%s: writing @0x%08x\n", __func__, 390 offset); 391 } 392 } 393 394 static const MemoryRegionOps pnv_quad_xscom_ops = { 395 .read = pnv_quad_xscom_read, 396 .write = pnv_quad_xscom_write, 397 .valid.min_access_size = 8, 398 .valid.max_access_size = 8, 399 .impl.min_access_size = 8, 400 .impl.max_access_size = 8, 401 .endianness = DEVICE_BIG_ENDIAN, 402 }; 403 404 static void pnv_quad_realize(DeviceState *dev, Error **errp) 405 { 406 PnvQuad *eq = PNV_QUAD(dev); 407 char name[32]; 408 409 snprintf(name, sizeof(name), "xscom-quad.%d", eq->id); 410 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), &pnv_quad_xscom_ops, 411 eq, name, PNV9_XSCOM_EQ_SIZE); 412 } 413 414 static Property pnv_quad_properties[] = { 415 DEFINE_PROP_UINT32("id", PnvQuad, id, 0), 416 DEFINE_PROP_END_OF_LIST(), 417 }; 418 419 static void pnv_quad_class_init(ObjectClass *oc, void *data) 420 { 421 DeviceClass *dc = DEVICE_CLASS(oc); 422 423 dc->realize = pnv_quad_realize; 424 dc->props = pnv_quad_properties; 425 } 426 427 static const TypeInfo pnv_quad_info = { 428 .name = TYPE_PNV_QUAD, 429 .parent = TYPE_DEVICE, 430 .instance_size = sizeof(PnvQuad), 431 .class_init = pnv_quad_class_init, 432 }; 433 434 static void pnv_core_register_types(void) 435 { 436 type_register_static(&pnv_quad_info); 437 } 438 439 type_init(pnv_core_register_types) 440