1 /* 2 * QEMU PowerPC PowerNV CPU Core model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public License 8 * as published by the Free Software Foundation; either version 2.1 of 9 * the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "sysemu/reset.h" 22 #include "qapi/error.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 #include "target/ppc/cpu.h" 26 #include "hw/ppc/ppc.h" 27 #include "hw/ppc/pnv.h" 28 #include "hw/ppc/pnv_chip.h" 29 #include "hw/ppc/pnv_core.h" 30 #include "hw/ppc/pnv_xscom.h" 31 #include "hw/ppc/xics.h" 32 #include "hw/qdev-properties.h" 33 #include "helper_regs.h" 34 35 static const char *pnv_core_cpu_typename(PnvCore *pc) 36 { 37 const char *core_type = object_class_get_name(object_get_class(OBJECT(pc))); 38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); 39 char *s = g_strdup_printf(POWERPC_CPU_TYPE_NAME("%.*s"), len, core_type); 40 const char *cpu_type = object_class_get_name(object_class_by_name(s)); 41 g_free(s); 42 return cpu_type; 43 } 44 45 static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) 46 { 47 CPUState *cs = CPU(cpu); 48 CPUPPCState *env = &cpu->env; 49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 50 51 cpu_reset(cs); 52 53 /* 54 * the skiboot firmware elects a primary thread to initialize the 55 * system and it can be any. 56 */ 57 env->gpr[3] = PNV_FDT_ADDR; 58 env->nip = 0x10; 59 env->msr |= MSR_HVB; /* Hypervisor mode */ 60 env->spr[SPR_HRMOR] = pc->hrmor; 61 hreg_compute_hflags(env); 62 ppc_maybe_interrupt(env); 63 64 cpu_ppc_tb_reset(env); 65 66 pcc->intc_reset(pc->chip, cpu); 67 } 68 69 /* 70 * These values are read by the PowerNV HW monitors under Linux 71 */ 72 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000 73 #define PNV_XSCOM_EX_DTS_RESULT1 0x50001 74 75 static uint64_t pnv_core_power8_xscom_read(void *opaque, hwaddr addr, 76 unsigned int width) 77 { 78 uint32_t offset = addr >> 3; 79 uint64_t val = 0; 80 81 /* The result should be 38 C */ 82 switch (offset) { 83 case PNV_XSCOM_EX_DTS_RESULT0: 84 val = 0x26f024f023f0000ull; 85 break; 86 case PNV_XSCOM_EX_DTS_RESULT1: 87 val = 0x24f000000000000ull; 88 break; 89 default: 90 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 91 offset); 92 } 93 94 return val; 95 } 96 97 static void pnv_core_power8_xscom_write(void *opaque, hwaddr addr, uint64_t val, 98 unsigned int width) 99 { 100 uint32_t offset = addr >> 3; 101 102 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 103 offset); 104 } 105 106 static const MemoryRegionOps pnv_core_power8_xscom_ops = { 107 .read = pnv_core_power8_xscom_read, 108 .write = pnv_core_power8_xscom_write, 109 .valid.min_access_size = 8, 110 .valid.max_access_size = 8, 111 .impl.min_access_size = 8, 112 .impl.max_access_size = 8, 113 .endianness = DEVICE_BIG_ENDIAN, 114 }; 115 116 117 /* 118 * POWER9 core controls 119 */ 120 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP 0xf010d 121 #define PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR 0xf010a 122 123 #define PNV9_XSCOM_EC_CORE_THREAD_STATE 0x10ab3 124 125 static uint64_t pnv_core_power9_xscom_read(void *opaque, hwaddr addr, 126 unsigned int width) 127 { 128 uint32_t offset = addr >> 3; 129 uint64_t val = 0; 130 131 /* The result should be 38 C */ 132 switch (offset) { 133 case PNV_XSCOM_EX_DTS_RESULT0: 134 val = 0x26f024f023f0000ull; 135 break; 136 case PNV_XSCOM_EX_DTS_RESULT1: 137 val = 0x24f000000000000ull; 138 break; 139 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 140 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 141 val = 0x0; 142 break; 143 case PNV9_XSCOM_EC_CORE_THREAD_STATE: 144 val = 0; 145 break; 146 default: 147 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 148 offset); 149 } 150 151 return val; 152 } 153 154 static void pnv_core_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 155 unsigned int width) 156 { 157 uint32_t offset = addr >> 3; 158 159 switch (offset) { 160 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_HYP: 161 case PNV9_XSCOM_EC_PPM_SPECIAL_WKUP_OTR: 162 break; 163 default: 164 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 165 offset); 166 } 167 } 168 169 static const MemoryRegionOps pnv_core_power9_xscom_ops = { 170 .read = pnv_core_power9_xscom_read, 171 .write = pnv_core_power9_xscom_write, 172 .valid.min_access_size = 8, 173 .valid.max_access_size = 8, 174 .impl.min_access_size = 8, 175 .impl.max_access_size = 8, 176 .endianness = DEVICE_BIG_ENDIAN, 177 }; 178 179 /* 180 * POWER10 core controls 181 */ 182 183 #define PNV10_XSCOM_EC_CORE_THREAD_STATE 0x412 184 185 static uint64_t pnv_core_power10_xscom_read(void *opaque, hwaddr addr, 186 unsigned int width) 187 { 188 uint32_t offset = addr >> 3; 189 uint64_t val = 0; 190 191 switch (offset) { 192 case PNV10_XSCOM_EC_CORE_THREAD_STATE: 193 val = 0; 194 break; 195 default: 196 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 197 offset); 198 } 199 200 return val; 201 } 202 203 static void pnv_core_power10_xscom_write(void *opaque, hwaddr addr, 204 uint64_t val, unsigned int width) 205 { 206 uint32_t offset = addr >> 3; 207 208 switch (offset) { 209 default: 210 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 211 offset); 212 } 213 } 214 215 static const MemoryRegionOps pnv_core_power10_xscom_ops = { 216 .read = pnv_core_power10_xscom_read, 217 .write = pnv_core_power10_xscom_write, 218 .valid.min_access_size = 8, 219 .valid.max_access_size = 8, 220 .impl.min_access_size = 8, 221 .impl.max_access_size = 8, 222 .endianness = DEVICE_BIG_ENDIAN, 223 }; 224 225 static void pnv_core_cpu_realize(PnvCore *pc, PowerPCCPU *cpu, Error **errp, 226 int thread_index) 227 { 228 CPUPPCState *env = &cpu->env; 229 int core_hwid; 230 ppc_spr_t *pir = &env->spr_cb[SPR_PIR]; 231 ppc_spr_t *tir = &env->spr_cb[SPR_TIR]; 232 Error *local_err = NULL; 233 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 234 235 if (!qdev_realize(DEVICE(cpu), NULL, errp)) { 236 return; 237 } 238 239 pcc->intc_create(pc->chip, cpu, &local_err); 240 if (local_err) { 241 error_propagate(errp, local_err); 242 return; 243 } 244 245 core_hwid = object_property_get_uint(OBJECT(pc), "hwid", &error_abort); 246 247 tir->default_value = thread_index; 248 pir->default_value = pcc->chip_pir(pc->chip, core_hwid, thread_index); 249 250 /* Set time-base frequency to 512 MHz */ 251 cpu_ppc_tb_init(env, PNV_TIMEBASE_FREQ); 252 } 253 254 static void pnv_core_reset(void *dev) 255 { 256 CPUCore *cc = CPU_CORE(dev); 257 PnvCore *pc = PNV_CORE(dev); 258 int i; 259 260 for (i = 0; i < cc->nr_threads; i++) { 261 pnv_core_cpu_reset(pc, pc->threads[i]); 262 } 263 } 264 265 static void pnv_core_realize(DeviceState *dev, Error **errp) 266 { 267 PnvCore *pc = PNV_CORE(OBJECT(dev)); 268 PnvCoreClass *pcc = PNV_CORE_GET_CLASS(pc); 269 CPUCore *cc = CPU_CORE(OBJECT(dev)); 270 const char *typename = pnv_core_cpu_typename(pc); 271 Error *local_err = NULL; 272 void *obj; 273 int i, j; 274 char name[32]; 275 276 assert(pc->chip); 277 278 pc->threads = g_new(PowerPCCPU *, cc->nr_threads); 279 for (i = 0; i < cc->nr_threads; i++) { 280 PowerPCCPU *cpu; 281 PnvCPUState *pnv_cpu; 282 283 obj = object_new(typename); 284 cpu = POWERPC_CPU(obj); 285 286 pc->threads[i] = POWERPC_CPU(obj); 287 288 snprintf(name, sizeof(name), "thread[%d]", i); 289 object_property_add_child(OBJECT(pc), name, obj); 290 291 cpu->machine_data = g_new0(PnvCPUState, 1); 292 pnv_cpu = pnv_cpu_state(cpu); 293 pnv_cpu->pnv_core = pc; 294 295 object_unref(obj); 296 } 297 298 for (j = 0; j < cc->nr_threads; j++) { 299 pnv_core_cpu_realize(pc, pc->threads[j], &local_err, j); 300 if (local_err) { 301 goto err; 302 } 303 } 304 305 snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id); 306 pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), pcc->xscom_ops, 307 pc, name, pcc->xscom_size); 308 309 qemu_register_reset(pnv_core_reset, pc); 310 return; 311 312 err: 313 while (--i >= 0) { 314 obj = OBJECT(pc->threads[i]); 315 object_unparent(obj); 316 } 317 g_free(pc->threads); 318 error_propagate(errp, local_err); 319 } 320 321 static void pnv_core_cpu_unrealize(PnvCore *pc, PowerPCCPU *cpu) 322 { 323 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 324 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); 325 326 pcc->intc_destroy(pc->chip, cpu); 327 cpu_remove_sync(CPU(cpu)); 328 cpu->machine_data = NULL; 329 g_free(pnv_cpu); 330 object_unparent(OBJECT(cpu)); 331 } 332 333 static void pnv_core_unrealize(DeviceState *dev) 334 { 335 PnvCore *pc = PNV_CORE(dev); 336 CPUCore *cc = CPU_CORE(dev); 337 int i; 338 339 qemu_unregister_reset(pnv_core_reset, pc); 340 341 for (i = 0; i < cc->nr_threads; i++) { 342 pnv_core_cpu_unrealize(pc, pc->threads[i]); 343 } 344 g_free(pc->threads); 345 } 346 347 static Property pnv_core_properties[] = { 348 DEFINE_PROP_UINT32("hwid", PnvCore, hwid, 0), 349 DEFINE_PROP_UINT64("hrmor", PnvCore, hrmor, 0), 350 DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), 351 DEFINE_PROP_END_OF_LIST(), 352 }; 353 354 static void pnv_core_power8_class_init(ObjectClass *oc, void *data) 355 { 356 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 357 358 pcc->xscom_ops = &pnv_core_power8_xscom_ops; 359 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 360 } 361 362 static void pnv_core_power9_class_init(ObjectClass *oc, void *data) 363 { 364 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 365 366 pcc->xscom_ops = &pnv_core_power9_xscom_ops; 367 pcc->xscom_size = PNV_XSCOM_EX_SIZE; 368 } 369 370 static void pnv_core_power10_class_init(ObjectClass *oc, void *data) 371 { 372 PnvCoreClass *pcc = PNV_CORE_CLASS(oc); 373 374 pcc->xscom_ops = &pnv_core_power10_xscom_ops; 375 pcc->xscom_size = PNV10_XSCOM_EC_SIZE; 376 } 377 378 static void pnv_core_class_init(ObjectClass *oc, void *data) 379 { 380 DeviceClass *dc = DEVICE_CLASS(oc); 381 382 dc->realize = pnv_core_realize; 383 dc->unrealize = pnv_core_unrealize; 384 device_class_set_props(dc, pnv_core_properties); 385 dc->user_creatable = false; 386 } 387 388 #define DEFINE_PNV_CORE_TYPE(family, cpu_model) \ 389 { \ 390 .parent = TYPE_PNV_CORE, \ 391 .name = PNV_CORE_TYPE_NAME(cpu_model), \ 392 .class_init = pnv_core_##family##_class_init, \ 393 } 394 395 static const TypeInfo pnv_core_infos[] = { 396 { 397 .name = TYPE_PNV_CORE, 398 .parent = TYPE_CPU_CORE, 399 .instance_size = sizeof(PnvCore), 400 .class_size = sizeof(PnvCoreClass), 401 .class_init = pnv_core_class_init, 402 .abstract = true, 403 }, 404 DEFINE_PNV_CORE_TYPE(power8, "power8e_v2.1"), 405 DEFINE_PNV_CORE_TYPE(power8, "power8_v2.0"), 406 DEFINE_PNV_CORE_TYPE(power8, "power8nvl_v1.0"), 407 DEFINE_PNV_CORE_TYPE(power9, "power9_v2.2"), 408 DEFINE_PNV_CORE_TYPE(power10, "power10_v2.0"), 409 }; 410 411 DEFINE_TYPES(pnv_core_infos) 412 413 /* 414 * POWER9 Quads 415 */ 416 417 #define P9X_EX_NCU_SPEC_BAR 0x11010 418 419 static uint64_t pnv_quad_power9_xscom_read(void *opaque, hwaddr addr, 420 unsigned int width) 421 { 422 uint32_t offset = addr >> 3; 423 uint64_t val = -1; 424 425 switch (offset) { 426 case P9X_EX_NCU_SPEC_BAR: 427 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 428 val = 0; 429 break; 430 default: 431 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 432 offset); 433 } 434 435 return val; 436 } 437 438 static void pnv_quad_power9_xscom_write(void *opaque, hwaddr addr, uint64_t val, 439 unsigned int width) 440 { 441 uint32_t offset = addr >> 3; 442 443 switch (offset) { 444 case P9X_EX_NCU_SPEC_BAR: 445 case P9X_EX_NCU_SPEC_BAR + 0x400: /* Second EX */ 446 break; 447 default: 448 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 449 offset); 450 } 451 } 452 453 static const MemoryRegionOps pnv_quad_power9_xscom_ops = { 454 .read = pnv_quad_power9_xscom_read, 455 .write = pnv_quad_power9_xscom_write, 456 .valid.min_access_size = 8, 457 .valid.max_access_size = 8, 458 .impl.min_access_size = 8, 459 .impl.max_access_size = 8, 460 .endianness = DEVICE_BIG_ENDIAN, 461 }; 462 463 /* 464 * POWER10 Quads 465 */ 466 467 static uint64_t pnv_quad_power10_xscom_read(void *opaque, hwaddr addr, 468 unsigned int width) 469 { 470 uint32_t offset = addr >> 3; 471 uint64_t val = -1; 472 473 switch (offset) { 474 default: 475 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 476 offset); 477 } 478 479 return val; 480 } 481 482 static void pnv_quad_power10_xscom_write(void *opaque, hwaddr addr, 483 uint64_t val, unsigned int width) 484 { 485 uint32_t offset = addr >> 3; 486 487 switch (offset) { 488 default: 489 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 490 offset); 491 } 492 } 493 494 static const MemoryRegionOps pnv_quad_power10_xscom_ops = { 495 .read = pnv_quad_power10_xscom_read, 496 .write = pnv_quad_power10_xscom_write, 497 .valid.min_access_size = 8, 498 .valid.max_access_size = 8, 499 .impl.min_access_size = 8, 500 .impl.max_access_size = 8, 501 .endianness = DEVICE_BIG_ENDIAN, 502 }; 503 504 #define P10_QME_SPWU_HYP 0x83c 505 #define P10_QME_SSH_HYP 0x82c 506 507 static uint64_t pnv_qme_power10_xscom_read(void *opaque, hwaddr addr, 508 unsigned int width) 509 { 510 uint32_t offset = addr >> 3; 511 uint64_t val = -1; 512 513 /* 514 * Forth nibble selects the core within a quad, mask it to process read 515 * for any core. 516 */ 517 switch (offset & ~0xf000) { 518 case P10_QME_SPWU_HYP: 519 case P10_QME_SSH_HYP: 520 return 0; 521 default: 522 qemu_log_mask(LOG_UNIMP, "%s: unimp read 0x%08x\n", __func__, 523 offset); 524 } 525 526 return val; 527 } 528 529 static void pnv_qme_power10_xscom_write(void *opaque, hwaddr addr, 530 uint64_t val, unsigned int width) 531 { 532 uint32_t offset = addr >> 3; 533 534 switch (offset) { 535 default: 536 qemu_log_mask(LOG_UNIMP, "%s: unimp write 0x%08x\n", __func__, 537 offset); 538 } 539 } 540 541 static const MemoryRegionOps pnv_qme_power10_xscom_ops = { 542 .read = pnv_qme_power10_xscom_read, 543 .write = pnv_qme_power10_xscom_write, 544 .valid.min_access_size = 8, 545 .valid.max_access_size = 8, 546 .impl.min_access_size = 8, 547 .impl.max_access_size = 8, 548 .endianness = DEVICE_BIG_ENDIAN, 549 }; 550 551 static void pnv_quad_power9_realize(DeviceState *dev, Error **errp) 552 { 553 PnvQuad *eq = PNV_QUAD(dev); 554 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 555 char name[32]; 556 557 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 558 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 559 pqc->xscom_ops, 560 eq, name, 561 pqc->xscom_size); 562 } 563 564 static void pnv_quad_power10_realize(DeviceState *dev, Error **errp) 565 { 566 PnvQuad *eq = PNV_QUAD(dev); 567 PnvQuadClass *pqc = PNV_QUAD_GET_CLASS(eq); 568 char name[32]; 569 570 snprintf(name, sizeof(name), "xscom-quad.%d", eq->quad_id); 571 pnv_xscom_region_init(&eq->xscom_regs, OBJECT(dev), 572 pqc->xscom_ops, 573 eq, name, 574 pqc->xscom_size); 575 576 snprintf(name, sizeof(name), "xscom-qme.%d", eq->quad_id); 577 pnv_xscom_region_init(&eq->xscom_qme_regs, OBJECT(dev), 578 pqc->xscom_qme_ops, 579 eq, name, 580 pqc->xscom_qme_size); 581 } 582 583 static Property pnv_quad_properties[] = { 584 DEFINE_PROP_UINT32("quad-id", PnvQuad, quad_id, 0), 585 DEFINE_PROP_END_OF_LIST(), 586 }; 587 588 static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) 589 { 590 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 591 DeviceClass *dc = DEVICE_CLASS(oc); 592 593 dc->realize = pnv_quad_power9_realize; 594 595 pqc->xscom_ops = &pnv_quad_power9_xscom_ops; 596 pqc->xscom_size = PNV9_XSCOM_EQ_SIZE; 597 } 598 599 static void pnv_quad_power10_class_init(ObjectClass *oc, void *data) 600 { 601 PnvQuadClass *pqc = PNV_QUAD_CLASS(oc); 602 DeviceClass *dc = DEVICE_CLASS(oc); 603 604 dc->realize = pnv_quad_power10_realize; 605 606 pqc->xscom_ops = &pnv_quad_power10_xscom_ops; 607 pqc->xscom_size = PNV10_XSCOM_EQ_SIZE; 608 609 pqc->xscom_qme_ops = &pnv_qme_power10_xscom_ops; 610 pqc->xscom_qme_size = PNV10_XSCOM_QME_SIZE; 611 } 612 613 static void pnv_quad_class_init(ObjectClass *oc, void *data) 614 { 615 DeviceClass *dc = DEVICE_CLASS(oc); 616 617 device_class_set_props(dc, pnv_quad_properties); 618 dc->user_creatable = false; 619 } 620 621 static const TypeInfo pnv_quad_infos[] = { 622 { 623 .name = TYPE_PNV_QUAD, 624 .parent = TYPE_DEVICE, 625 .instance_size = sizeof(PnvQuad), 626 .class_size = sizeof(PnvQuadClass), 627 .class_init = pnv_quad_class_init, 628 .abstract = true, 629 }, 630 { 631 .parent = TYPE_PNV_QUAD, 632 .name = PNV_QUAD_TYPE_NAME("power9"), 633 .class_init = pnv_quad_power9_class_init, 634 }, 635 { 636 .parent = TYPE_PNV_QUAD, 637 .name = PNV_QUAD_TYPE_NAME("power10"), 638 .class_init = pnv_quad_power10_class_init, 639 }, 640 }; 641 642 DEFINE_TYPES(pnv_quad_infos); 643