1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 #include "hw/ppc/pnv_pnor.h" 48 49 #include "hw/isa/isa.h" 50 #include "hw/boards.h" 51 #include "hw/char/serial.h" 52 #include "hw/rtc/mc146818rtc.h" 53 54 #include <libfdt.h> 55 56 #define FDT_MAX_SIZE (1 * MiB) 57 58 #define FW_FILE_NAME "skiboot.lid" 59 #define FW_LOAD_ADDR 0x0 60 #define FW_MAX_SIZE (4 * MiB) 61 62 #define KERNEL_LOAD_ADDR 0x20000000 63 #define KERNEL_MAX_SIZE (256 * MiB) 64 #define INITRD_LOAD_ADDR 0x60000000 65 #define INITRD_MAX_SIZE (256 * MiB) 66 67 static const char *pnv_chip_core_typename(const PnvChip *o) 68 { 69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 72 const char *core_type = object_class_get_name(object_class_by_name(s)); 73 g_free(s); 74 return core_type; 75 } 76 77 /* 78 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 79 * 4 * 4 sockets * 12 cores * 8 threads = 1536 80 * Let's make it 2^11 81 */ 82 #define MAX_CPUS 2048 83 84 /* 85 * Memory nodes are created by hostboot, one for each range of memory 86 * that has a different "affinity". In practice, it means one range 87 * per chip. 88 */ 89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 90 { 91 char *mem_name; 92 uint64_t mem_reg_property[2]; 93 int off; 94 95 mem_reg_property[0] = cpu_to_be64(start); 96 mem_reg_property[1] = cpu_to_be64(size); 97 98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 99 off = fdt_add_subnode(fdt, 0, mem_name); 100 g_free(mem_name); 101 102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 104 sizeof(mem_reg_property)))); 105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 106 } 107 108 static int get_cpus_node(void *fdt) 109 { 110 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 111 112 if (cpus_offset < 0) { 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 114 if (cpus_offset) { 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 117 } 118 } 119 _FDT(cpus_offset); 120 return cpus_offset; 121 } 122 123 /* 124 * The PowerNV cores (and threads) need to use real HW ids and not an 125 * incremental index like it has been done on other platforms. This HW 126 * id is stored in the CPU PIR, it is used to create cpu nodes in the 127 * device tree, used in XSCOM to address cores and in interrupt 128 * servers. 129 */ 130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 131 { 132 PowerPCCPU *cpu = pc->threads[0]; 133 CPUState *cs = CPU(cpu); 134 DeviceClass *dc = DEVICE_GET_CLASS(cs); 135 int smt_threads = CPU_CORE(pc)->nr_threads; 136 CPUPPCState *env = &cpu->env; 137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 138 uint32_t servers_prop[smt_threads]; 139 int i; 140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 141 0xffffffff, 0xffffffff}; 142 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 143 uint32_t cpufreq = 1000000000; 144 uint32_t page_sizes_prop[64]; 145 size_t page_sizes_prop_size; 146 const uint8_t pa_features[] = { 24, 0, 147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 151 int offset; 152 char *nodename; 153 int cpus_offset = get_cpus_node(fdt); 154 155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 156 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 157 _FDT(offset); 158 g_free(nodename); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 172 env->icache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 174 env->icache_line_size))); 175 176 if (pcc->l1_dcache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 178 pcc->l1_dcache_size))); 179 } else { 180 warn_report("Unknown L1 dcache size for cpu"); 181 } 182 if (pcc->l1_icache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 184 pcc->l1_icache_size))); 185 } else { 186 warn_report("Unknown L1 icache size for cpu"); 187 } 188 189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 192 cpu->hash64_opts->slb_size))); 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 195 196 if (env->spr_cb[SPR_PURR].oea_read) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 198 } 199 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 202 segs, sizeof(segs)))); 203 } 204 205 /* 206 * Advertise VMX/VSX (vector extensions) if available 207 * 0 / no property == no vector extensions 208 * 1 == VMX / Altivec available 209 * 2 == VSX available 210 */ 211 if (env->insns_flags & PPC_ALTIVEC) { 212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 213 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 215 } 216 217 /* 218 * Advertise DFP (Decimal Floating Point) if available 219 * 0 / no property == no DFP 220 * 1 == DFP available 221 */ 222 if (env->insns_flags2 & PPC2_DFP) { 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 224 } 225 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 227 sizeof(page_sizes_prop)); 228 if (page_sizes_prop_size) { 229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 230 page_sizes_prop, page_sizes_prop_size))); 231 } 232 233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 234 pa_features, sizeof(pa_features)))); 235 236 /* Build interrupt servers properties */ 237 for (i = 0; i < smt_threads; i++) { 238 servers_prop[i] = cpu_to_be32(pc->pir + i); 239 } 240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 241 servers_prop, sizeof(servers_prop)))); 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 282 { 283 int i; 284 285 pnv_dt_xscom(chip, fdt, 0); 286 287 for (i = 0; i < chip->nr_cores; i++) { 288 PnvCore *pnv_core = chip->cores[i]; 289 290 pnv_dt_core(chip, pnv_core, fdt); 291 292 /* Interrupt Control Presenters (ICP). One per core. */ 293 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 294 } 295 296 if (chip->ram_size) { 297 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 298 } 299 } 300 301 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 302 { 303 int i; 304 305 pnv_dt_xscom(chip, fdt, 0); 306 307 for (i = 0; i < chip->nr_cores; i++) { 308 PnvCore *pnv_core = chip->cores[i]; 309 310 pnv_dt_core(chip, pnv_core, fdt); 311 } 312 313 if (chip->ram_size) { 314 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 315 } 316 317 pnv_dt_lpc(chip, fdt, 0); 318 } 319 320 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 321 { 322 uint32_t io_base = d->ioport_id; 323 uint32_t io_regs[] = { 324 cpu_to_be32(1), 325 cpu_to_be32(io_base), 326 cpu_to_be32(2) 327 }; 328 char *name; 329 int node; 330 331 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 332 node = fdt_add_subnode(fdt, lpc_off, name); 333 _FDT(node); 334 g_free(name); 335 336 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 337 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 338 } 339 340 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 341 { 342 const char compatible[] = "ns16550\0pnpPNP,501"; 343 uint32_t io_base = d->ioport_id; 344 uint32_t io_regs[] = { 345 cpu_to_be32(1), 346 cpu_to_be32(io_base), 347 cpu_to_be32(8) 348 }; 349 char *name; 350 int node; 351 352 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 353 node = fdt_add_subnode(fdt, lpc_off, name); 354 _FDT(node); 355 g_free(name); 356 357 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 358 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 359 sizeof(compatible)))); 360 361 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 362 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 363 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 364 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 365 fdt_get_phandle(fdt, lpc_off)))); 366 367 /* This is needed by Linux */ 368 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 369 } 370 371 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 372 { 373 const char compatible[] = "bt\0ipmi-bt"; 374 uint32_t io_base; 375 uint32_t io_regs[] = { 376 cpu_to_be32(1), 377 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 378 cpu_to_be32(3) 379 }; 380 uint32_t irq; 381 char *name; 382 int node; 383 384 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 385 io_regs[1] = cpu_to_be32(io_base); 386 387 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 388 389 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 390 node = fdt_add_subnode(fdt, lpc_off, name); 391 _FDT(node); 392 g_free(name); 393 394 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 395 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 396 sizeof(compatible)))); 397 398 /* Mark it as reserved to avoid Linux trying to claim it */ 399 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 400 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 401 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 402 fdt_get_phandle(fdt, lpc_off)))); 403 } 404 405 typedef struct ForeachPopulateArgs { 406 void *fdt; 407 int offset; 408 } ForeachPopulateArgs; 409 410 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 411 { 412 ForeachPopulateArgs *args = opaque; 413 ISADevice *d = ISA_DEVICE(dev); 414 415 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 416 pnv_dt_rtc(d, args->fdt, args->offset); 417 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 418 pnv_dt_serial(d, args->fdt, args->offset); 419 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 420 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 421 } else { 422 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 423 d->ioport_id); 424 } 425 426 return 0; 427 } 428 429 /* 430 * The default LPC bus of a multichip system is on chip 0. It's 431 * recognized by the firmware (skiboot) using a "primary" property. 432 */ 433 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 434 { 435 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 436 ForeachPopulateArgs args = { 437 .fdt = fdt, 438 .offset = isa_offset, 439 }; 440 uint32_t phandle; 441 442 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 443 444 phandle = qemu_fdt_alloc_phandle(fdt); 445 assert(phandle > 0); 446 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 447 448 /* 449 * ISA devices are not necessarily parented to the ISA bus so we 450 * can not use object_child_foreach() 451 */ 452 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 453 &args); 454 } 455 456 static void pnv_dt_power_mgt(void *fdt) 457 { 458 int off; 459 460 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 461 off = fdt_add_subnode(fdt, off, "power-mgt"); 462 463 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 464 } 465 466 static void *pnv_dt_create(MachineState *machine) 467 { 468 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 469 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; 470 PnvMachineState *pnv = PNV_MACHINE(machine); 471 void *fdt; 472 char *buf; 473 int off; 474 int i; 475 476 fdt = g_malloc0(FDT_MAX_SIZE); 477 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 478 479 /* /qemu node */ 480 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 481 482 /* Root node */ 483 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 484 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 485 _FDT((fdt_setprop_string(fdt, 0, "model", 486 "IBM PowerNV (emulated by qemu)"))); 487 if (pnv_is_power9(pnv)) { 488 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, 489 sizeof(plat_compat9)))); 490 } else { 491 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, 492 sizeof(plat_compat8)))); 493 } 494 495 496 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 497 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 498 if (qemu_uuid_set) { 499 _FDT((fdt_property_string(fdt, "system-id", buf))); 500 } 501 g_free(buf); 502 503 off = fdt_add_subnode(fdt, 0, "chosen"); 504 if (machine->kernel_cmdline) { 505 _FDT((fdt_setprop_string(fdt, off, "bootargs", 506 machine->kernel_cmdline))); 507 } 508 509 if (pnv->initrd_size) { 510 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 511 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 512 513 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 514 &start_prop, sizeof(start_prop)))); 515 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 516 &end_prop, sizeof(end_prop)))); 517 } 518 519 /* Populate device tree for each chip */ 520 for (i = 0; i < pnv->num_chips; i++) { 521 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 522 } 523 524 /* Populate ISA devices on chip 0 */ 525 pnv_dt_isa(pnv, fdt); 526 527 if (pnv->bmc) { 528 pnv_dt_bmc_sensors(pnv->bmc, fdt); 529 } 530 531 /* Create an extra node for power management on Power9 */ 532 if (pnv_is_power9(pnv)) { 533 pnv_dt_power_mgt(fdt); 534 } 535 536 return fdt; 537 } 538 539 static void pnv_powerdown_notify(Notifier *n, void *opaque) 540 { 541 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 542 543 if (pnv->bmc) { 544 pnv_bmc_powerdown(pnv->bmc); 545 } 546 } 547 548 static void pnv_reset(MachineState *machine) 549 { 550 void *fdt; 551 552 qemu_devices_reset(); 553 554 fdt = pnv_dt_create(machine); 555 556 /* Pack resulting tree */ 557 _FDT((fdt_pack(fdt))); 558 559 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 560 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 561 } 562 563 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 564 { 565 Pnv8Chip *chip8 = PNV8_CHIP(chip); 566 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 567 } 568 569 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 570 { 571 Pnv8Chip *chip8 = PNV8_CHIP(chip); 572 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 573 } 574 575 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 576 { 577 Pnv9Chip *chip9 = PNV9_CHIP(chip); 578 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 579 } 580 581 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 582 { 583 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 584 } 585 586 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 587 { 588 Pnv8Chip *chip8 = PNV8_CHIP(chip); 589 590 ics_pic_print_info(&chip8->psi.ics, mon); 591 } 592 593 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 594 { 595 Pnv9Chip *chip9 = PNV9_CHIP(chip); 596 597 pnv_xive_pic_print_info(&chip9->xive, mon); 598 pnv_psi_pic_print_info(&chip9->psi, mon); 599 } 600 601 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 602 { 603 PowerPCCPUClass *ppc_default = 604 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 605 PowerPCCPUClass *ppc = 606 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 607 608 return ppc_default->pvr_match(ppc_default, ppc->pvr); 609 } 610 611 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 612 { 613 Object *obj; 614 615 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 616 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 617 object_property_set_int(obj, irq, "irq", &error_fatal); 618 object_property_set_bool(obj, true, "realized", &error_fatal); 619 } 620 621 static void pnv_init(MachineState *machine) 622 { 623 PnvMachineState *pnv = PNV_MACHINE(machine); 624 MachineClass *mc = MACHINE_GET_CLASS(machine); 625 MemoryRegion *ram; 626 char *fw_filename; 627 long fw_size; 628 int i; 629 char *chip_typename; 630 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 631 DeviceState *dev; 632 633 /* allocate RAM */ 634 if (machine->ram_size < (1 * GiB)) { 635 warn_report("skiboot may not work with < 1GB of RAM"); 636 } 637 638 ram = g_new(MemoryRegion, 1); 639 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 640 machine->ram_size); 641 memory_region_add_subregion(get_system_memory(), 0, ram); 642 643 /* 644 * Create our simple PNOR device 645 */ 646 dev = qdev_create(NULL, TYPE_PNV_PNOR); 647 if (pnor) { 648 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 649 &error_abort); 650 } 651 qdev_init_nofail(dev); 652 pnv->pnor = PNV_PNOR(dev); 653 654 /* load skiboot firmware */ 655 if (bios_name == NULL) { 656 bios_name = FW_FILE_NAME; 657 } 658 659 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 660 if (!fw_filename) { 661 error_report("Could not find OPAL firmware '%s'", bios_name); 662 exit(1); 663 } 664 665 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 666 if (fw_size < 0) { 667 error_report("Could not load OPAL firmware '%s'", fw_filename); 668 exit(1); 669 } 670 g_free(fw_filename); 671 672 /* load kernel */ 673 if (machine->kernel_filename) { 674 long kernel_size; 675 676 kernel_size = load_image_targphys(machine->kernel_filename, 677 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 678 if (kernel_size < 0) { 679 error_report("Could not load kernel '%s'", 680 machine->kernel_filename); 681 exit(1); 682 } 683 } 684 685 /* load initrd */ 686 if (machine->initrd_filename) { 687 pnv->initrd_base = INITRD_LOAD_ADDR; 688 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 689 pnv->initrd_base, INITRD_MAX_SIZE); 690 if (pnv->initrd_size < 0) { 691 error_report("Could not load initial ram disk '%s'", 692 machine->initrd_filename); 693 exit(1); 694 } 695 } 696 697 /* 698 * Check compatibility of the specified CPU with the machine 699 * default. 700 */ 701 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 702 error_report("invalid CPU model '%s' for %s machine", 703 machine->cpu_type, mc->name); 704 exit(1); 705 } 706 707 /* Create the processor chips */ 708 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 709 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 710 i, machine->cpu_type); 711 if (!object_class_by_name(chip_typename)) { 712 error_report("invalid chip model '%.*s' for %s machine", 713 i, machine->cpu_type, mc->name); 714 exit(1); 715 } 716 717 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 718 for (i = 0; i < pnv->num_chips; i++) { 719 char chip_name[32]; 720 Object *chip = object_new(chip_typename); 721 722 pnv->chips[i] = PNV_CHIP(chip); 723 724 /* 725 * TODO: put all the memory in one node on chip 0 until we find a 726 * way to specify different ranges for each chip 727 */ 728 if (i == 0) { 729 object_property_set_int(chip, machine->ram_size, "ram-size", 730 &error_fatal); 731 } 732 733 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 734 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 735 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 736 &error_fatal); 737 object_property_set_int(chip, machine->smp.cores, 738 "nr-cores", &error_fatal); 739 object_property_set_bool(chip, true, "realized", &error_fatal); 740 } 741 g_free(chip_typename); 742 743 /* Create the machine BMC simulator */ 744 pnv->bmc = pnv_bmc_create(); 745 746 /* Instantiate ISA bus on chip 0 */ 747 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 748 749 /* Create serial port */ 750 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 751 752 /* Create an RTC ISA device too */ 753 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 754 755 /* Create the IPMI BT device for communication with the BMC */ 756 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 757 758 /* 759 * OpenPOWER systems use a IPMI SEL Event message to notify the 760 * host to powerdown 761 */ 762 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 763 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 764 } 765 766 /* 767 * 0:21 Reserved - Read as zeros 768 * 22:24 Chip ID 769 * 25:28 Core number 770 * 29:31 Thread ID 771 */ 772 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 773 { 774 return (chip->chip_id << 7) | (core_id << 3); 775 } 776 777 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 778 Error **errp) 779 { 780 Error *local_err = NULL; 781 Object *obj; 782 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 783 784 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 785 &local_err); 786 if (local_err) { 787 error_propagate(errp, local_err); 788 return; 789 } 790 791 pnv_cpu->intc = obj; 792 } 793 794 795 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 796 { 797 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 798 799 icp_reset(ICP(pnv_cpu->intc)); 800 } 801 802 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 803 { 804 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 805 806 icp_destroy(ICP(pnv_cpu->intc)); 807 pnv_cpu->intc = NULL; 808 } 809 810 /* 811 * 0:48 Reserved - Read as zeroes 812 * 49:52 Node ID 813 * 53:55 Chip ID 814 * 56 Reserved - Read as zero 815 * 57:61 Core number 816 * 62:63 Thread ID 817 * 818 * We only care about the lower bits. uint32_t is fine for the moment. 819 */ 820 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 821 { 822 return (chip->chip_id << 8) | (core_id << 2); 823 } 824 825 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 826 Error **errp) 827 { 828 Pnv9Chip *chip9 = PNV9_CHIP(chip); 829 Error *local_err = NULL; 830 Object *obj; 831 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 832 833 /* 834 * The core creates its interrupt presenter but the XIVE interrupt 835 * controller object is initialized afterwards. Hopefully, it's 836 * only used at runtime. 837 */ 838 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 839 if (local_err) { 840 error_propagate(errp, local_err); 841 return; 842 } 843 844 pnv_cpu->intc = obj; 845 } 846 847 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 848 { 849 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 850 851 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 852 } 853 854 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 855 { 856 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 857 858 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 859 pnv_cpu->intc = NULL; 860 } 861 862 /* 863 * Allowed core identifiers on a POWER8 Processor Chip : 864 * 865 * <EX0 reserved> 866 * EX1 - Venice only 867 * EX2 - Venice only 868 * EX3 - Venice only 869 * EX4 870 * EX5 871 * EX6 872 * <EX7,8 reserved> <reserved> 873 * EX9 - Venice only 874 * EX10 - Venice only 875 * EX11 - Venice only 876 * EX12 877 * EX13 878 * EX14 879 * <EX15 reserved> 880 */ 881 #define POWER8E_CORE_MASK (0x7070ull) 882 #define POWER8_CORE_MASK (0x7e7eull) 883 884 /* 885 * POWER9 has 24 cores, ids starting at 0x0 886 */ 887 #define POWER9_CORE_MASK (0xffffffffffffffull) 888 889 static void pnv_chip_power8_instance_init(Object *obj) 890 { 891 Pnv8Chip *chip8 = PNV8_CHIP(obj); 892 893 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 894 TYPE_PNV8_PSI, &error_abort, NULL); 895 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 896 OBJECT(qdev_get_machine()), &error_abort); 897 898 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 899 TYPE_PNV8_LPC, &error_abort, NULL); 900 901 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 902 TYPE_PNV8_OCC, &error_abort, NULL); 903 904 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 905 TYPE_PNV8_HOMER, &error_abort, NULL); 906 } 907 908 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 909 { 910 PnvChip *chip = PNV_CHIP(chip8); 911 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 912 int i, j; 913 char *name; 914 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 915 916 name = g_strdup_printf("icp-%x", chip->chip_id); 917 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 918 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 919 g_free(name); 920 921 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 922 923 /* Map the ICP registers for each thread */ 924 for (i = 0; i < chip->nr_cores; i++) { 925 PnvCore *pnv_core = chip->cores[i]; 926 int core_hwid = CPU_CORE(pnv_core)->core_id; 927 928 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 929 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 930 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 931 932 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 933 &icp->mmio); 934 } 935 } 936 } 937 938 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 939 { 940 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 941 PnvChip *chip = PNV_CHIP(dev); 942 Pnv8Chip *chip8 = PNV8_CHIP(dev); 943 Pnv8Psi *psi8 = &chip8->psi; 944 Error *local_err = NULL; 945 946 /* XSCOM bridge is first */ 947 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 948 if (local_err) { 949 error_propagate(errp, local_err); 950 return; 951 } 952 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 953 954 pcc->parent_realize(dev, &local_err); 955 if (local_err) { 956 error_propagate(errp, local_err); 957 return; 958 } 959 960 /* Processor Service Interface (PSI) Host Bridge */ 961 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 962 "bar", &error_fatal); 963 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 964 if (local_err) { 965 error_propagate(errp, local_err); 966 return; 967 } 968 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 969 &PNV_PSI(psi8)->xscom_regs); 970 971 /* Create LPC controller */ 972 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 973 &error_abort); 974 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 975 &error_fatal); 976 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 977 978 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 979 (uint64_t) PNV_XSCOM_BASE(chip), 980 PNV_XSCOM_LPC_BASE); 981 982 /* 983 * Interrupt Management Area. This is the memory region holding 984 * all the Interrupt Control Presenter (ICP) registers 985 */ 986 pnv_chip_icp_realize(chip8, &local_err); 987 if (local_err) { 988 error_propagate(errp, local_err); 989 return; 990 } 991 992 /* Create the simplified OCC model */ 993 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 994 &error_abort); 995 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 996 if (local_err) { 997 error_propagate(errp, local_err); 998 return; 999 } 1000 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1001 1002 /* OCC SRAM model */ 1003 memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip), 1004 &chip8->occ.sram_regs); 1005 1006 /* HOMER */ 1007 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1008 &error_abort); 1009 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1010 &local_err); 1011 if (local_err) { 1012 error_propagate(errp, local_err); 1013 return; 1014 } 1015 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1016 &chip8->homer.regs); 1017 } 1018 1019 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1020 { 1021 DeviceClass *dc = DEVICE_CLASS(klass); 1022 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1023 1024 k->chip_type = PNV_CHIP_POWER8E; 1025 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1026 k->cores_mask = POWER8E_CORE_MASK; 1027 k->core_pir = pnv_chip_core_pir_p8; 1028 k->intc_create = pnv_chip_power8_intc_create; 1029 k->intc_reset = pnv_chip_power8_intc_reset; 1030 k->intc_destroy = pnv_chip_power8_intc_destroy; 1031 k->isa_create = pnv_chip_power8_isa_create; 1032 k->dt_populate = pnv_chip_power8_dt_populate; 1033 k->pic_print_info = pnv_chip_power8_pic_print_info; 1034 dc->desc = "PowerNV Chip POWER8E"; 1035 1036 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1037 &k->parent_realize); 1038 } 1039 1040 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1041 { 1042 DeviceClass *dc = DEVICE_CLASS(klass); 1043 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1044 1045 k->chip_type = PNV_CHIP_POWER8; 1046 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1047 k->cores_mask = POWER8_CORE_MASK; 1048 k->core_pir = pnv_chip_core_pir_p8; 1049 k->intc_create = pnv_chip_power8_intc_create; 1050 k->intc_reset = pnv_chip_power8_intc_reset; 1051 k->intc_destroy = pnv_chip_power8_intc_destroy; 1052 k->isa_create = pnv_chip_power8_isa_create; 1053 k->dt_populate = pnv_chip_power8_dt_populate; 1054 k->pic_print_info = pnv_chip_power8_pic_print_info; 1055 dc->desc = "PowerNV Chip POWER8"; 1056 1057 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1058 &k->parent_realize); 1059 } 1060 1061 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1062 { 1063 DeviceClass *dc = DEVICE_CLASS(klass); 1064 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1065 1066 k->chip_type = PNV_CHIP_POWER8NVL; 1067 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1068 k->cores_mask = POWER8_CORE_MASK; 1069 k->core_pir = pnv_chip_core_pir_p8; 1070 k->intc_create = pnv_chip_power8_intc_create; 1071 k->intc_reset = pnv_chip_power8_intc_reset; 1072 k->intc_destroy = pnv_chip_power8_intc_destroy; 1073 k->isa_create = pnv_chip_power8nvl_isa_create; 1074 k->dt_populate = pnv_chip_power8_dt_populate; 1075 k->pic_print_info = pnv_chip_power8_pic_print_info; 1076 dc->desc = "PowerNV Chip POWER8NVL"; 1077 1078 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1079 &k->parent_realize); 1080 } 1081 1082 static void pnv_chip_power9_instance_init(Object *obj) 1083 { 1084 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1085 1086 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1087 TYPE_PNV_XIVE, &error_abort, NULL); 1088 1089 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1090 TYPE_PNV9_PSI, &error_abort, NULL); 1091 1092 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1093 TYPE_PNV9_LPC, &error_abort, NULL); 1094 1095 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1096 TYPE_PNV9_OCC, &error_abort, NULL); 1097 1098 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1099 TYPE_PNV9_HOMER, &error_abort, NULL); 1100 } 1101 1102 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1103 { 1104 PnvChip *chip = PNV_CHIP(chip9); 1105 int i; 1106 1107 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1108 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1109 1110 for (i = 0; i < chip9->nr_quads; i++) { 1111 char eq_name[32]; 1112 PnvQuad *eq = &chip9->quads[i]; 1113 PnvCore *pnv_core = chip->cores[i * 4]; 1114 int core_id = CPU_CORE(pnv_core)->core_id; 1115 1116 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1117 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1118 TYPE_PNV_QUAD, &error_fatal, NULL); 1119 1120 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1121 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1122 1123 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1124 &eq->xscom_regs); 1125 } 1126 } 1127 1128 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1129 { 1130 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1131 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1132 PnvChip *chip = PNV_CHIP(dev); 1133 Pnv9Psi *psi9 = &chip9->psi; 1134 Error *local_err = NULL; 1135 1136 /* XSCOM bridge is first */ 1137 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1138 if (local_err) { 1139 error_propagate(errp, local_err); 1140 return; 1141 } 1142 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1143 1144 pcc->parent_realize(dev, &local_err); 1145 if (local_err) { 1146 error_propagate(errp, local_err); 1147 return; 1148 } 1149 1150 pnv_chip_quad_realize(chip9, &local_err); 1151 if (local_err) { 1152 error_propagate(errp, local_err); 1153 return; 1154 } 1155 1156 /* XIVE interrupt controller (POWER9) */ 1157 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1158 "ic-bar", &error_fatal); 1159 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1160 "vc-bar", &error_fatal); 1161 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1162 "pc-bar", &error_fatal); 1163 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1164 "tm-bar", &error_fatal); 1165 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1166 &error_abort); 1167 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1168 &local_err); 1169 if (local_err) { 1170 error_propagate(errp, local_err); 1171 return; 1172 } 1173 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1174 &chip9->xive.xscom_regs); 1175 1176 /* Processor Service Interface (PSI) Host Bridge */ 1177 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1178 "bar", &error_fatal); 1179 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1180 if (local_err) { 1181 error_propagate(errp, local_err); 1182 return; 1183 } 1184 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1185 &PNV_PSI(psi9)->xscom_regs); 1186 1187 /* LPC */ 1188 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1189 &error_abort); 1190 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1191 if (local_err) { 1192 error_propagate(errp, local_err); 1193 return; 1194 } 1195 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1196 &chip9->lpc.xscom_regs); 1197 1198 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1199 (uint64_t) PNV9_LPCM_BASE(chip)); 1200 1201 /* Create the simplified OCC model */ 1202 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1203 &error_abort); 1204 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1205 if (local_err) { 1206 error_propagate(errp, local_err); 1207 return; 1208 } 1209 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1210 1211 /* OCC SRAM model */ 1212 memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip), 1213 &chip9->occ.sram_regs); 1214 1215 /* HOMER */ 1216 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1217 &error_abort); 1218 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1219 &local_err); 1220 if (local_err) { 1221 error_propagate(errp, local_err); 1222 return; 1223 } 1224 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1225 &chip9->homer.regs); 1226 } 1227 1228 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1229 { 1230 DeviceClass *dc = DEVICE_CLASS(klass); 1231 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1232 1233 k->chip_type = PNV_CHIP_POWER9; 1234 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1235 k->cores_mask = POWER9_CORE_MASK; 1236 k->core_pir = pnv_chip_core_pir_p9; 1237 k->intc_create = pnv_chip_power9_intc_create; 1238 k->intc_reset = pnv_chip_power9_intc_reset; 1239 k->intc_destroy = pnv_chip_power9_intc_destroy; 1240 k->isa_create = pnv_chip_power9_isa_create; 1241 k->dt_populate = pnv_chip_power9_dt_populate; 1242 k->pic_print_info = pnv_chip_power9_pic_print_info; 1243 dc->desc = "PowerNV Chip POWER9"; 1244 1245 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1246 &k->parent_realize); 1247 } 1248 1249 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1250 { 1251 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1252 int cores_max; 1253 1254 /* 1255 * No custom mask for this chip, let's use the default one from * 1256 * the chip class 1257 */ 1258 if (!chip->cores_mask) { 1259 chip->cores_mask = pcc->cores_mask; 1260 } 1261 1262 /* filter alien core ids ! some are reserved */ 1263 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1264 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1265 chip->cores_mask); 1266 return; 1267 } 1268 chip->cores_mask &= pcc->cores_mask; 1269 1270 /* now that we have a sane layout, let check the number of cores */ 1271 cores_max = ctpop64(chip->cores_mask); 1272 if (chip->nr_cores > cores_max) { 1273 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1274 cores_max); 1275 return; 1276 } 1277 } 1278 1279 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1280 { 1281 MachineState *ms = MACHINE(qdev_get_machine()); 1282 Error *error = NULL; 1283 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1284 const char *typename = pnv_chip_core_typename(chip); 1285 int i, core_hwid; 1286 1287 if (!object_class_by_name(typename)) { 1288 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1289 return; 1290 } 1291 1292 /* Cores */ 1293 pnv_chip_core_sanitize(chip, &error); 1294 if (error) { 1295 error_propagate(errp, error); 1296 return; 1297 } 1298 1299 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1300 1301 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1302 && (i < chip->nr_cores); core_hwid++) { 1303 char core_name[32]; 1304 PnvCore *pnv_core; 1305 uint64_t xscom_core_base; 1306 1307 if (!(chip->cores_mask & (1ull << core_hwid))) { 1308 continue; 1309 } 1310 1311 pnv_core = PNV_CORE(object_new(typename)); 1312 1313 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1314 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1315 &error_abort); 1316 chip->cores[i] = pnv_core; 1317 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1318 &error_fatal); 1319 object_property_set_int(OBJECT(pnv_core), core_hwid, 1320 CPU_CORE_PROP_CORE_ID, &error_fatal); 1321 object_property_set_int(OBJECT(pnv_core), 1322 pcc->core_pir(chip, core_hwid), 1323 "pir", &error_fatal); 1324 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1325 &error_abort); 1326 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1327 &error_fatal); 1328 1329 /* Each core has an XSCOM MMIO region */ 1330 if (!pnv_chip_is_power9(chip)) { 1331 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1332 } else { 1333 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1334 } 1335 1336 pnv_xscom_add_subregion(chip, xscom_core_base, 1337 &pnv_core->xscom_regs); 1338 i++; 1339 } 1340 } 1341 1342 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1343 { 1344 PnvChip *chip = PNV_CHIP(dev); 1345 Error *error = NULL; 1346 1347 /* Cores */ 1348 pnv_chip_core_realize(chip, &error); 1349 if (error) { 1350 error_propagate(errp, error); 1351 return; 1352 } 1353 } 1354 1355 static Property pnv_chip_properties[] = { 1356 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1357 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1358 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1359 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1360 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1361 DEFINE_PROP_END_OF_LIST(), 1362 }; 1363 1364 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1365 { 1366 DeviceClass *dc = DEVICE_CLASS(klass); 1367 1368 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1369 dc->realize = pnv_chip_realize; 1370 dc->props = pnv_chip_properties; 1371 dc->desc = "PowerNV Chip"; 1372 } 1373 1374 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1375 { 1376 PnvMachineState *pnv = PNV_MACHINE(xi); 1377 int i; 1378 1379 for (i = 0; i < pnv->num_chips; i++) { 1380 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1381 1382 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1383 return &chip8->psi.ics; 1384 } 1385 } 1386 return NULL; 1387 } 1388 1389 static void pnv_ics_resend(XICSFabric *xi) 1390 { 1391 PnvMachineState *pnv = PNV_MACHINE(xi); 1392 int i; 1393 1394 for (i = 0; i < pnv->num_chips; i++) { 1395 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1396 ics_resend(&chip8->psi.ics); 1397 } 1398 } 1399 1400 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1401 { 1402 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1403 1404 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1405 } 1406 1407 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1408 Monitor *mon) 1409 { 1410 PnvMachineState *pnv = PNV_MACHINE(obj); 1411 int i; 1412 CPUState *cs; 1413 1414 CPU_FOREACH(cs) { 1415 PowerPCCPU *cpu = POWERPC_CPU(cs); 1416 1417 if (pnv_chip_is_power9(pnv->chips[0])) { 1418 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1419 } else { 1420 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1421 } 1422 } 1423 1424 for (i = 0; i < pnv->num_chips; i++) { 1425 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1426 } 1427 } 1428 1429 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1430 void *opaque, Error **errp) 1431 { 1432 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1433 } 1434 1435 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1436 void *opaque, Error **errp) 1437 { 1438 PnvMachineState *pnv = PNV_MACHINE(obj); 1439 uint32_t num_chips; 1440 Error *local_err = NULL; 1441 1442 visit_type_uint32(v, name, &num_chips, &local_err); 1443 if (local_err) { 1444 error_propagate(errp, local_err); 1445 return; 1446 } 1447 1448 /* 1449 * TODO: should we decide on how many chips we can create based 1450 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1451 */ 1452 if (!is_power_of_2(num_chips) || num_chips > 4) { 1453 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1454 return; 1455 } 1456 1457 pnv->num_chips = num_chips; 1458 } 1459 1460 static void pnv_machine_instance_init(Object *obj) 1461 { 1462 PnvMachineState *pnv = PNV_MACHINE(obj); 1463 pnv->num_chips = 1; 1464 } 1465 1466 static void pnv_machine_class_props_init(ObjectClass *oc) 1467 { 1468 object_class_property_add(oc, "num-chips", "uint32", 1469 pnv_get_num_chips, pnv_set_num_chips, 1470 NULL, NULL, NULL); 1471 object_class_property_set_description(oc, "num-chips", 1472 "Specifies the number of processor chips", 1473 NULL); 1474 } 1475 1476 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1477 { 1478 MachineClass *mc = MACHINE_CLASS(oc); 1479 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1480 1481 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1482 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1483 1484 xic->icp_get = pnv_icp_get; 1485 xic->ics_get = pnv_ics_get; 1486 xic->ics_resend = pnv_ics_resend; 1487 } 1488 1489 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1490 { 1491 MachineClass *mc = MACHINE_CLASS(oc); 1492 1493 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1494 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1495 1496 mc->alias = "powernv"; 1497 } 1498 1499 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1500 { 1501 MachineClass *mc = MACHINE_CLASS(oc); 1502 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1503 1504 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1505 mc->init = pnv_init; 1506 mc->reset = pnv_reset; 1507 mc->max_cpus = MAX_CPUS; 1508 /* Pnv provides a AHCI device for storage */ 1509 mc->block_default_type = IF_IDE; 1510 mc->no_parallel = 1; 1511 mc->default_boot_order = NULL; 1512 /* 1513 * RAM defaults to less than 2048 for 32-bit hosts, and large 1514 * enough to fit the maximum initrd size at it's load address 1515 */ 1516 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1517 ispc->print_info = pnv_pic_print_info; 1518 1519 pnv_machine_class_props_init(oc); 1520 } 1521 1522 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1523 { \ 1524 .name = type, \ 1525 .class_init = class_initfn, \ 1526 .parent = TYPE_PNV8_CHIP, \ 1527 } 1528 1529 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1530 { \ 1531 .name = type, \ 1532 .class_init = class_initfn, \ 1533 .parent = TYPE_PNV9_CHIP, \ 1534 } 1535 1536 static const TypeInfo types[] = { 1537 { 1538 .name = MACHINE_TYPE_NAME("powernv9"), 1539 .parent = TYPE_PNV_MACHINE, 1540 .class_init = pnv_machine_power9_class_init, 1541 }, 1542 { 1543 .name = MACHINE_TYPE_NAME("powernv8"), 1544 .parent = TYPE_PNV_MACHINE, 1545 .class_init = pnv_machine_power8_class_init, 1546 .interfaces = (InterfaceInfo[]) { 1547 { TYPE_XICS_FABRIC }, 1548 { }, 1549 }, 1550 }, 1551 { 1552 .name = TYPE_PNV_MACHINE, 1553 .parent = TYPE_MACHINE, 1554 .abstract = true, 1555 .instance_size = sizeof(PnvMachineState), 1556 .instance_init = pnv_machine_instance_init, 1557 .class_init = pnv_machine_class_init, 1558 .interfaces = (InterfaceInfo[]) { 1559 { TYPE_INTERRUPT_STATS_PROVIDER }, 1560 { }, 1561 }, 1562 }, 1563 { 1564 .name = TYPE_PNV_CHIP, 1565 .parent = TYPE_SYS_BUS_DEVICE, 1566 .class_init = pnv_chip_class_init, 1567 .instance_size = sizeof(PnvChip), 1568 .class_size = sizeof(PnvChipClass), 1569 .abstract = true, 1570 }, 1571 1572 /* 1573 * P9 chip and variants 1574 */ 1575 { 1576 .name = TYPE_PNV9_CHIP, 1577 .parent = TYPE_PNV_CHIP, 1578 .instance_init = pnv_chip_power9_instance_init, 1579 .instance_size = sizeof(Pnv9Chip), 1580 }, 1581 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1582 1583 /* 1584 * P8 chip and variants 1585 */ 1586 { 1587 .name = TYPE_PNV8_CHIP, 1588 .parent = TYPE_PNV_CHIP, 1589 .instance_init = pnv_chip_power8_instance_init, 1590 .instance_size = sizeof(Pnv8Chip), 1591 }, 1592 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1593 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1594 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1595 pnv_chip_power8nvl_class_init), 1596 }; 1597 1598 DEFINE_TYPES(types) 1599