1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "sysemu/sysemu.h" 23 #include "sysemu/numa.h" 24 #include "hw/hw.h" 25 #include "target/ppc/cpu.h" 26 #include "qemu/log.h" 27 #include "hw/ppc/fdt.h" 28 #include "hw/ppc/ppc.h" 29 #include "hw/ppc/pnv.h" 30 #include "hw/ppc/pnv_core.h" 31 #include "hw/loader.h" 32 #include "exec/address-spaces.h" 33 #include "qemu/cutils.h" 34 #include "qapi/visitor.h" 35 36 #include "hw/ppc/pnv_xscom.h" 37 38 #include "hw/isa/isa.h" 39 #include "hw/char/serial.h" 40 #include "hw/timer/mc146818rtc.h" 41 42 #include <libfdt.h> 43 44 #define FDT_MAX_SIZE 0x00100000 45 46 #define FW_FILE_NAME "skiboot.lid" 47 #define FW_LOAD_ADDR 0x0 48 #define FW_MAX_SIZE 0x00400000 49 50 #define KERNEL_LOAD_ADDR 0x20000000 51 #define INITRD_LOAD_ADDR 0x40000000 52 53 /* 54 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 55 * 4 * 4 sockets * 12 cores * 8 threads = 1536 56 * Let's make it 2^11 57 */ 58 #define MAX_CPUS 2048 59 60 /* 61 * Memory nodes are created by hostboot, one for each range of memory 62 * that has a different "affinity". In practice, it means one range 63 * per chip. 64 */ 65 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start, 66 hwaddr size) 67 { 68 char *mem_name; 69 uint64_t mem_reg_property[2]; 70 int off; 71 72 mem_reg_property[0] = cpu_to_be64(start); 73 mem_reg_property[1] = cpu_to_be64(size); 74 75 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 76 off = fdt_add_subnode(fdt, 0, mem_name); 77 g_free(mem_name); 78 79 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 80 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 81 sizeof(mem_reg_property)))); 82 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 83 } 84 85 static int get_cpus_node(void *fdt) 86 { 87 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 88 89 if (cpus_offset < 0) { 90 cpus_offset = fdt_add_subnode(fdt, fdt_path_offset(fdt, "/"), 91 "cpus"); 92 if (cpus_offset) { 93 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 94 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 95 } 96 } 97 _FDT(cpus_offset); 98 return cpus_offset; 99 } 100 101 /* 102 * The PowerNV cores (and threads) need to use real HW ids and not an 103 * incremental index like it has been done on other platforms. This HW 104 * id is stored in the CPU PIR, it is used to create cpu nodes in the 105 * device tree, used in XSCOM to address cores and in interrupt 106 * servers. 107 */ 108 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) 109 { 110 CPUState *cs = CPU(DEVICE(pc->threads)); 111 DeviceClass *dc = DEVICE_GET_CLASS(cs); 112 PowerPCCPU *cpu = POWERPC_CPU(cs); 113 int smt_threads = CPU_CORE(pc)->nr_threads; 114 CPUPPCState *env = &cpu->env; 115 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 116 uint32_t servers_prop[smt_threads]; 117 int i; 118 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 119 0xffffffff, 0xffffffff}; 120 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 121 uint32_t cpufreq = 1000000000; 122 uint32_t page_sizes_prop[64]; 123 size_t page_sizes_prop_size; 124 const uint8_t pa_features[] = { 24, 0, 125 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 126 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 127 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 128 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 129 int offset; 130 char *nodename; 131 int cpus_offset = get_cpus_node(fdt); 132 133 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 134 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 135 _FDT(offset); 136 g_free(nodename); 137 138 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 139 140 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 141 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 142 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 143 144 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 145 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 146 env->dcache_line_size))); 147 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 148 env->dcache_line_size))); 149 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 150 env->icache_line_size))); 151 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 152 env->icache_line_size))); 153 154 if (pcc->l1_dcache_size) { 155 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 156 pcc->l1_dcache_size))); 157 } else { 158 error_report("Warning: Unknown L1 dcache size for cpu"); 159 } 160 if (pcc->l1_icache_size) { 161 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 162 pcc->l1_icache_size))); 163 } else { 164 error_report("Warning: Unknown L1 icache size for cpu"); 165 } 166 167 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 168 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 170 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 171 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 172 173 if (env->spr_cb[SPR_PURR].oea_read) { 174 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 175 } 176 177 if (env->mmu_model & POWERPC_MMU_1TSEG) { 178 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 179 segs, sizeof(segs)))); 180 } 181 182 /* Advertise VMX/VSX (vector extensions) if available 183 * 0 / no property == no vector extensions 184 * 1 == VMX / Altivec available 185 * 2 == VSX available */ 186 if (env->insns_flags & PPC_ALTIVEC) { 187 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 188 189 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 190 } 191 192 /* Advertise DFP (Decimal Floating Point) if available 193 * 0 / no property == no DFP 194 * 1 == DFP available */ 195 if (env->insns_flags2 & PPC2_DFP) { 196 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 197 } 198 199 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 200 sizeof(page_sizes_prop)); 201 if (page_sizes_prop_size) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 203 page_sizes_prop, page_sizes_prop_size))); 204 } 205 206 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 207 pa_features, sizeof(pa_features)))); 208 209 /* Build interrupt servers properties */ 210 for (i = 0; i < smt_threads; i++) { 211 servers_prop[i] = cpu_to_be32(pc->pir + i); 212 } 213 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 214 servers_prop, sizeof(servers_prop)))); 215 } 216 217 static void powernv_populate_chip(PnvChip *chip, void *fdt) 218 { 219 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 220 char *typename = pnv_core_typename(pcc->cpu_model); 221 size_t typesize = object_type_get_instance_size(typename); 222 int i; 223 224 pnv_xscom_populate(chip, fdt, 0); 225 226 for (i = 0; i < chip->nr_cores; i++) { 227 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 228 229 powernv_create_core_node(chip, pnv_core, fdt); 230 } 231 232 if (chip->ram_size) { 233 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, 234 chip->ram_size); 235 } 236 g_free(typename); 237 } 238 239 static void *powernv_create_fdt(MachineState *machine) 240 { 241 const char plat_compat[] = "qemu,powernv\0ibm,powernv"; 242 PnvMachineState *pnv = POWERNV_MACHINE(machine); 243 void *fdt; 244 char *buf; 245 int off; 246 int i; 247 248 fdt = g_malloc0(FDT_MAX_SIZE); 249 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 250 251 /* Root node */ 252 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 253 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 254 _FDT((fdt_setprop_string(fdt, 0, "model", 255 "IBM PowerNV (emulated by qemu)"))); 256 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat, 257 sizeof(plat_compat)))); 258 259 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 260 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 261 if (qemu_uuid_set) { 262 _FDT((fdt_property_string(fdt, "system-id", buf))); 263 } 264 g_free(buf); 265 266 off = fdt_add_subnode(fdt, 0, "chosen"); 267 if (machine->kernel_cmdline) { 268 _FDT((fdt_setprop_string(fdt, off, "bootargs", 269 machine->kernel_cmdline))); 270 } 271 272 if (pnv->initrd_size) { 273 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 274 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 275 276 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 277 &start_prop, sizeof(start_prop)))); 278 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 279 &end_prop, sizeof(end_prop)))); 280 } 281 282 /* Populate device tree for each chip */ 283 for (i = 0; i < pnv->num_chips; i++) { 284 powernv_populate_chip(pnv->chips[i], fdt); 285 } 286 return fdt; 287 } 288 289 static void ppc_powernv_reset(void) 290 { 291 MachineState *machine = MACHINE(qdev_get_machine()); 292 void *fdt; 293 294 qemu_devices_reset(); 295 296 fdt = powernv_create_fdt(machine); 297 298 /* Pack resulting tree */ 299 _FDT((fdt_pack(fdt))); 300 301 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 302 } 303 304 /* If we don't use the built-in LPC interrupt deserializer, we need 305 * to provide a set of qirqs for the ISA bus or things will go bad. 306 * 307 * Most machines using pre-Naples chips (without said deserializer) 308 * have a CPLD that will collect the SerIRQ and shoot them as a 309 * single level interrupt to the P8 chip. So let's setup a hook 310 * for doing just that. 311 * 312 * Note: The actual interrupt input isn't emulated yet, this will 313 * come with the PSI bridge model. 314 */ 315 static void pnv_lpc_isa_irq_handler_cpld(void *opaque, int n, int level) 316 { 317 /* We don't yet emulate the PSI bridge which provides the external 318 * interrupt, so just drop interrupts on the floor 319 */ 320 } 321 322 static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level) 323 { 324 /* XXX TODO */ 325 } 326 327 static ISABus *pnv_isa_create(PnvChip *chip) 328 { 329 PnvLpcController *lpc = &chip->lpc; 330 ISABus *isa_bus; 331 qemu_irq *irqs; 332 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 333 334 /* let isa_bus_new() create its own bridge on SysBus otherwise 335 * devices speficied on the command line won't find the bus and 336 * will fail to create. 337 */ 338 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, 339 &error_fatal); 340 341 /* Not all variants have a working serial irq decoder. If not, 342 * handling of LPC interrupts becomes a platform issue (some 343 * platforms have a CPLD to do it). 344 */ 345 if (pcc->chip_type == PNV_CHIP_POWER8NVL) { 346 irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler, chip, ISA_NUM_IRQS); 347 } else { 348 irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, chip, 349 ISA_NUM_IRQS); 350 } 351 352 isa_bus_irqs(isa_bus, irqs); 353 return isa_bus; 354 } 355 356 static void ppc_powernv_init(MachineState *machine) 357 { 358 PnvMachineState *pnv = POWERNV_MACHINE(machine); 359 MemoryRegion *ram; 360 char *fw_filename; 361 long fw_size; 362 int i; 363 char *chip_typename; 364 365 /* allocate RAM */ 366 if (machine->ram_size < (1 * G_BYTE)) { 367 error_report("Warning: skiboot may not work with < 1GB of RAM"); 368 } 369 370 ram = g_new(MemoryRegion, 1); 371 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram", 372 machine->ram_size); 373 memory_region_add_subregion(get_system_memory(), 0, ram); 374 375 /* load skiboot firmware */ 376 if (bios_name == NULL) { 377 bios_name = FW_FILE_NAME; 378 } 379 380 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 381 382 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 383 if (fw_size < 0) { 384 hw_error("qemu: could not load OPAL '%s'\n", fw_filename); 385 exit(1); 386 } 387 g_free(fw_filename); 388 389 /* load kernel */ 390 if (machine->kernel_filename) { 391 long kernel_size; 392 393 kernel_size = load_image_targphys(machine->kernel_filename, 394 KERNEL_LOAD_ADDR, 0x2000000); 395 if (kernel_size < 0) { 396 hw_error("qemu: could not load kernel'%s'\n", 397 machine->kernel_filename); 398 exit(1); 399 } 400 } 401 402 /* load initrd */ 403 if (machine->initrd_filename) { 404 pnv->initrd_base = INITRD_LOAD_ADDR; 405 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 406 pnv->initrd_base, 0x10000000); /* 128MB max */ 407 if (pnv->initrd_size < 0) { 408 error_report("qemu: could not load initial ram disk '%s'", 409 machine->initrd_filename); 410 exit(1); 411 } 412 } 413 414 /* We need some cpu model to instantiate the PnvChip class */ 415 if (machine->cpu_model == NULL) { 416 machine->cpu_model = "POWER8"; 417 } 418 419 /* Create the processor chips */ 420 chip_typename = g_strdup_printf(TYPE_PNV_CHIP "-%s", machine->cpu_model); 421 if (!object_class_by_name(chip_typename)) { 422 error_report("qemu: invalid CPU model '%s' for %s machine", 423 machine->cpu_model, MACHINE_GET_CLASS(machine)->name); 424 exit(1); 425 } 426 427 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 428 for (i = 0; i < pnv->num_chips; i++) { 429 char chip_name[32]; 430 Object *chip = object_new(chip_typename); 431 432 pnv->chips[i] = PNV_CHIP(chip); 433 434 /* TODO: put all the memory in one node on chip 0 until we find a 435 * way to specify different ranges for each chip 436 */ 437 if (i == 0) { 438 object_property_set_int(chip, machine->ram_size, "ram-size", 439 &error_fatal); 440 } 441 442 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 443 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 444 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 445 &error_fatal); 446 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); 447 object_property_set_bool(chip, true, "realized", &error_fatal); 448 } 449 g_free(chip_typename); 450 451 /* Instantiate ISA bus on chip 0 */ 452 pnv->isa_bus = pnv_isa_create(pnv->chips[0]); 453 454 /* Create serial port */ 455 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS); 456 457 /* Create an RTC ISA device too */ 458 rtc_init(pnv->isa_bus, 2000, NULL); 459 } 460 461 /* 462 * 0:21 Reserved - Read as zeros 463 * 22:24 Chip ID 464 * 25:28 Core number 465 * 29:31 Thread ID 466 */ 467 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 468 { 469 return (chip->chip_id << 7) | (core_id << 3); 470 } 471 472 /* 473 * 0:48 Reserved - Read as zeroes 474 * 49:52 Node ID 475 * 53:55 Chip ID 476 * 56 Reserved - Read as zero 477 * 57:61 Core number 478 * 62:63 Thread ID 479 * 480 * We only care about the lower bits. uint32_t is fine for the moment. 481 */ 482 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 483 { 484 return (chip->chip_id << 8) | (core_id << 2); 485 } 486 487 /* Allowed core identifiers on a POWER8 Processor Chip : 488 * 489 * <EX0 reserved> 490 * EX1 - Venice only 491 * EX2 - Venice only 492 * EX3 - Venice only 493 * EX4 494 * EX5 495 * EX6 496 * <EX7,8 reserved> <reserved> 497 * EX9 - Venice only 498 * EX10 - Venice only 499 * EX11 - Venice only 500 * EX12 501 * EX13 502 * EX14 503 * <EX15 reserved> 504 */ 505 #define POWER8E_CORE_MASK (0x7070ull) 506 #define POWER8_CORE_MASK (0x7e7eull) 507 508 /* 509 * POWER9 has 24 cores, ids starting at 0x20 510 */ 511 #define POWER9_CORE_MASK (0xffffff00000000ull) 512 513 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 514 { 515 DeviceClass *dc = DEVICE_CLASS(klass); 516 PnvChipClass *k = PNV_CHIP_CLASS(klass); 517 518 k->cpu_model = "POWER8E"; 519 k->chip_type = PNV_CHIP_POWER8E; 520 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 521 k->cores_mask = POWER8E_CORE_MASK; 522 k->core_pir = pnv_chip_core_pir_p8; 523 k->xscom_base = 0x003fc0000000000ull; 524 k->xscom_core_base = 0x10000000ull; 525 dc->desc = "PowerNV Chip POWER8E"; 526 } 527 528 static const TypeInfo pnv_chip_power8e_info = { 529 .name = TYPE_PNV_CHIP_POWER8E, 530 .parent = TYPE_PNV_CHIP, 531 .instance_size = sizeof(PnvChip), 532 .class_init = pnv_chip_power8e_class_init, 533 }; 534 535 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 536 { 537 DeviceClass *dc = DEVICE_CLASS(klass); 538 PnvChipClass *k = PNV_CHIP_CLASS(klass); 539 540 k->cpu_model = "POWER8"; 541 k->chip_type = PNV_CHIP_POWER8; 542 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 543 k->cores_mask = POWER8_CORE_MASK; 544 k->core_pir = pnv_chip_core_pir_p8; 545 k->xscom_base = 0x003fc0000000000ull; 546 k->xscom_core_base = 0x10000000ull; 547 dc->desc = "PowerNV Chip POWER8"; 548 } 549 550 static const TypeInfo pnv_chip_power8_info = { 551 .name = TYPE_PNV_CHIP_POWER8, 552 .parent = TYPE_PNV_CHIP, 553 .instance_size = sizeof(PnvChip), 554 .class_init = pnv_chip_power8_class_init, 555 }; 556 557 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 558 { 559 DeviceClass *dc = DEVICE_CLASS(klass); 560 PnvChipClass *k = PNV_CHIP_CLASS(klass); 561 562 k->cpu_model = "POWER8NVL"; 563 k->chip_type = PNV_CHIP_POWER8NVL; 564 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 565 k->cores_mask = POWER8_CORE_MASK; 566 k->core_pir = pnv_chip_core_pir_p8; 567 k->xscom_base = 0x003fc0000000000ull; 568 k->xscom_core_base = 0x10000000ull; 569 dc->desc = "PowerNV Chip POWER8NVL"; 570 } 571 572 static const TypeInfo pnv_chip_power8nvl_info = { 573 .name = TYPE_PNV_CHIP_POWER8NVL, 574 .parent = TYPE_PNV_CHIP, 575 .instance_size = sizeof(PnvChip), 576 .class_init = pnv_chip_power8nvl_class_init, 577 }; 578 579 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 580 { 581 DeviceClass *dc = DEVICE_CLASS(klass); 582 PnvChipClass *k = PNV_CHIP_CLASS(klass); 583 584 k->cpu_model = "POWER9"; 585 k->chip_type = PNV_CHIP_POWER9; 586 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ 587 k->cores_mask = POWER9_CORE_MASK; 588 k->core_pir = pnv_chip_core_pir_p9; 589 k->xscom_base = 0x00603fc00000000ull; 590 k->xscom_core_base = 0x0ull; 591 dc->desc = "PowerNV Chip POWER9"; 592 } 593 594 static const TypeInfo pnv_chip_power9_info = { 595 .name = TYPE_PNV_CHIP_POWER9, 596 .parent = TYPE_PNV_CHIP, 597 .instance_size = sizeof(PnvChip), 598 .class_init = pnv_chip_power9_class_init, 599 }; 600 601 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 602 { 603 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 604 int cores_max; 605 606 /* 607 * No custom mask for this chip, let's use the default one from * 608 * the chip class 609 */ 610 if (!chip->cores_mask) { 611 chip->cores_mask = pcc->cores_mask; 612 } 613 614 /* filter alien core ids ! some are reserved */ 615 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 616 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 617 chip->cores_mask); 618 return; 619 } 620 chip->cores_mask &= pcc->cores_mask; 621 622 /* now that we have a sane layout, let check the number of cores */ 623 cores_max = ctpop64(chip->cores_mask); 624 if (chip->nr_cores > cores_max) { 625 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 626 cores_max); 627 return; 628 } 629 } 630 631 static void pnv_chip_init(Object *obj) 632 { 633 PnvChip *chip = PNV_CHIP(obj); 634 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 635 636 chip->xscom_base = pcc->xscom_base; 637 638 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); 639 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); 640 } 641 642 static void pnv_chip_realize(DeviceState *dev, Error **errp) 643 { 644 PnvChip *chip = PNV_CHIP(dev); 645 Error *error = NULL; 646 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 647 char *typename = pnv_core_typename(pcc->cpu_model); 648 size_t typesize = object_type_get_instance_size(typename); 649 int i, core_hwid; 650 651 if (!object_class_by_name(typename)) { 652 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 653 return; 654 } 655 656 /* XSCOM bridge */ 657 pnv_xscom_realize(chip, &error); 658 if (error) { 659 error_propagate(errp, error); 660 return; 661 } 662 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 663 664 /* Cores */ 665 pnv_chip_core_sanitize(chip, &error); 666 if (error) { 667 error_propagate(errp, error); 668 return; 669 } 670 671 chip->cores = g_malloc0(typesize * chip->nr_cores); 672 673 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 674 && (i < chip->nr_cores); core_hwid++) { 675 char core_name[32]; 676 void *pnv_core = chip->cores + i * typesize; 677 678 if (!(chip->cores_mask & (1ull << core_hwid))) { 679 continue; 680 } 681 682 object_initialize(pnv_core, typesize, typename); 683 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 684 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 685 &error_fatal); 686 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", 687 &error_fatal); 688 object_property_set_int(OBJECT(pnv_core), core_hwid, 689 CPU_CORE_PROP_CORE_ID, &error_fatal); 690 object_property_set_int(OBJECT(pnv_core), 691 pcc->core_pir(chip, core_hwid), 692 "pir", &error_fatal); 693 object_property_set_bool(OBJECT(pnv_core), true, "realized", 694 &error_fatal); 695 object_unref(OBJECT(pnv_core)); 696 697 /* Each core has an XSCOM MMIO region */ 698 pnv_xscom_add_subregion(chip, 699 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base, 700 core_hwid), 701 &PNV_CORE(pnv_core)->xscom_regs); 702 i++; 703 } 704 g_free(typename); 705 706 /* Create LPC controller */ 707 object_property_set_bool(OBJECT(&chip->lpc), true, "realized", 708 &error_fatal); 709 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs); 710 } 711 712 static Property pnv_chip_properties[] = { 713 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 714 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 715 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 716 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 717 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 718 DEFINE_PROP_END_OF_LIST(), 719 }; 720 721 static void pnv_chip_class_init(ObjectClass *klass, void *data) 722 { 723 DeviceClass *dc = DEVICE_CLASS(klass); 724 725 dc->realize = pnv_chip_realize; 726 dc->props = pnv_chip_properties; 727 dc->desc = "PowerNV Chip"; 728 } 729 730 static const TypeInfo pnv_chip_info = { 731 .name = TYPE_PNV_CHIP, 732 .parent = TYPE_SYS_BUS_DEVICE, 733 .class_init = pnv_chip_class_init, 734 .instance_init = pnv_chip_init, 735 .class_size = sizeof(PnvChipClass), 736 .abstract = true, 737 }; 738 739 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 740 void *opaque, Error **errp) 741 { 742 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); 743 } 744 745 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 746 void *opaque, Error **errp) 747 { 748 PnvMachineState *pnv = POWERNV_MACHINE(obj); 749 uint32_t num_chips; 750 Error *local_err = NULL; 751 752 visit_type_uint32(v, name, &num_chips, &local_err); 753 if (local_err) { 754 error_propagate(errp, local_err); 755 return; 756 } 757 758 /* 759 * TODO: should we decide on how many chips we can create based 760 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 761 */ 762 if (!is_power_of_2(num_chips) || num_chips > 4) { 763 error_setg(errp, "invalid number of chips: '%d'", num_chips); 764 return; 765 } 766 767 pnv->num_chips = num_chips; 768 } 769 770 static void powernv_machine_initfn(Object *obj) 771 { 772 PnvMachineState *pnv = POWERNV_MACHINE(obj); 773 pnv->num_chips = 1; 774 } 775 776 static void powernv_machine_class_props_init(ObjectClass *oc) 777 { 778 object_class_property_add(oc, "num-chips", "uint32_t", 779 pnv_get_num_chips, pnv_set_num_chips, 780 NULL, NULL, NULL); 781 object_class_property_set_description(oc, "num-chips", 782 "Specifies the number of processor chips", 783 NULL); 784 } 785 786 static void powernv_machine_class_init(ObjectClass *oc, void *data) 787 { 788 MachineClass *mc = MACHINE_CLASS(oc); 789 790 mc->desc = "IBM PowerNV (Non-Virtualized)"; 791 mc->init = ppc_powernv_init; 792 mc->reset = ppc_powernv_reset; 793 mc->max_cpus = MAX_CPUS; 794 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 795 * storage */ 796 mc->no_parallel = 1; 797 mc->default_boot_order = NULL; 798 mc->default_ram_size = 1 * G_BYTE; 799 800 powernv_machine_class_props_init(oc); 801 } 802 803 static const TypeInfo powernv_machine_info = { 804 .name = TYPE_POWERNV_MACHINE, 805 .parent = TYPE_MACHINE, 806 .instance_size = sizeof(PnvMachineState), 807 .instance_init = powernv_machine_initfn, 808 .class_init = powernv_machine_class_init, 809 }; 810 811 static void powernv_machine_register_types(void) 812 { 813 type_register_static(&powernv_machine_info); 814 type_register_static(&pnv_chip_info); 815 type_register_static(&pnv_chip_power8e_info); 816 type_register_static(&pnv_chip_power8_info); 817 type_register_static(&pnv_chip_power8nvl_info); 818 type_register_static(&pnv_chip_power9_info); 819 } 820 821 type_init(powernv_machine_register_types) 822