1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 #include "hw/pci-host/pnv_phb3.h" 48 #include "hw/pci-host/pnv_phb4.h" 49 50 #include "hw/ppc/xics.h" 51 #include "hw/qdev-properties.h" 52 #include "hw/ppc/pnv_chip.h" 53 #include "hw/ppc/pnv_xscom.h" 54 #include "hw/ppc/pnv_pnor.h" 55 56 #include "hw/isa/isa.h" 57 #include "hw/char/serial.h" 58 #include "hw/rtc/mc146818rtc.h" 59 60 #include <libfdt.h> 61 62 #define FDT_MAX_SIZE (1 * MiB) 63 64 #define FW_FILE_NAME "skiboot.lid" 65 #define FW_LOAD_ADDR 0x0 66 #define FW_MAX_SIZE (16 * MiB) 67 68 #define KERNEL_LOAD_ADDR 0x20000000 69 #define KERNEL_MAX_SIZE (128 * MiB) 70 #define INITRD_LOAD_ADDR 0x28000000 71 #define INITRD_MAX_SIZE (128 * MiB) 72 73 static const char *pnv_chip_core_typename(const PnvChip *o) 74 { 75 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 76 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 77 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 78 const char *core_type = object_class_get_name(object_class_by_name(s)); 79 g_free(s); 80 return core_type; 81 } 82 83 /* 84 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 85 * 4 * 4 sockets * 12 cores * 8 threads = 1536 86 * Let's make it 2^11 87 */ 88 #define MAX_CPUS 2048 89 90 /* 91 * Memory nodes are created by hostboot, one for each range of memory 92 * that has a different "affinity". In practice, it means one range 93 * per chip. 94 */ 95 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 96 { 97 char *mem_name; 98 uint64_t mem_reg_property[2]; 99 int off; 100 101 mem_reg_property[0] = cpu_to_be64(start); 102 mem_reg_property[1] = cpu_to_be64(size); 103 104 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 105 off = fdt_add_subnode(fdt, 0, mem_name); 106 g_free(mem_name); 107 108 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 109 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 110 sizeof(mem_reg_property)))); 111 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 112 } 113 114 static int get_cpus_node(void *fdt) 115 { 116 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 117 118 if (cpus_offset < 0) { 119 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 120 if (cpus_offset) { 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 123 } 124 } 125 _FDT(cpus_offset); 126 return cpus_offset; 127 } 128 129 /* 130 * The PowerNV cores (and threads) need to use real HW ids and not an 131 * incremental index like it has been done on other platforms. This HW 132 * id is stored in the CPU PIR, it is used to create cpu nodes in the 133 * device tree, used in XSCOM to address cores and in interrupt 134 * servers. 135 */ 136 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 137 { 138 PowerPCCPU *cpu = pc->threads[0]; 139 CPUState *cs = CPU(cpu); 140 DeviceClass *dc = DEVICE_GET_CLASS(cs); 141 int smt_threads = CPU_CORE(pc)->nr_threads; 142 CPUPPCState *env = &cpu->env; 143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 147 0xffffffff, 0xffffffff}; 148 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 149 uint32_t cpufreq = 1000000000; 150 uint32_t page_sizes_prop[64]; 151 size_t page_sizes_prop_size; 152 const uint8_t pa_features[] = { 24, 0, 153 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 154 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 155 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 156 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 157 int offset; 158 char *nodename; 159 int cpus_offset = get_cpus_node(fdt); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 240 pa_features, sizeof(pa_features)))); 241 242 /* Build interrupt servers properties */ 243 for (i = 0; i < smt_threads; i++) { 244 servers_prop[i] = cpu_to_be32(pc->pir + i); 245 } 246 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 247 servers_prop, sizeof(*servers_prop) * smt_threads))); 248 } 249 250 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 251 uint32_t nr_threads) 252 { 253 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 254 char *name; 255 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 256 uint32_t irange[2], i, rsize; 257 uint64_t *reg; 258 int offset; 259 260 irange[0] = cpu_to_be32(pir); 261 irange[1] = cpu_to_be32(nr_threads); 262 263 rsize = sizeof(uint64_t) * 2 * nr_threads; 264 reg = g_malloc(rsize); 265 for (i = 0; i < nr_threads; i++) { 266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 267 reg[i * 2 + 1] = cpu_to_be64(0x1000); 268 } 269 270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 271 offset = fdt_add_subnode(fdt, 0, name); 272 _FDT(offset); 273 g_free(name); 274 275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 277 _FDT((fdt_setprop_string(fdt, offset, "device_type", 278 "PowerPC-External-Interrupt-Presentation"))); 279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 281 irange, sizeof(irange)))); 282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 284 g_free(reg); 285 } 286 287 /* 288 * Adds a PnvPHB to the chip. Returns the parent obj of the 289 * PHB which varies with each version (phb version 3 is parented 290 * by the chip, version 4 and 5 are parented by the PEC 291 * device). 292 * 293 * TODO: for version 3 we're still parenting the PHB with the 294 * chip. We should parent with a (so far not implemented) 295 * PHB3 PEC device. 296 */ 297 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp) 298 { 299 if (phb->version == 3) { 300 Pnv8Chip *chip8 = PNV8_CHIP(chip); 301 302 phb->chip = chip; 303 304 chip8->phbs[chip8->num_phbs] = phb; 305 chip8->num_phbs++; 306 307 return OBJECT(chip); 308 } 309 310 phb->pec = pnv_phb4_get_pec(chip, phb, errp); 311 312 return OBJECT(phb->pec); 313 } 314 315 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 316 { 317 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 318 int i; 319 320 pnv_dt_xscom(chip, fdt, 0, 321 cpu_to_be64(PNV_XSCOM_BASE(chip)), 322 cpu_to_be64(PNV_XSCOM_SIZE), 323 compat, sizeof(compat)); 324 325 for (i = 0; i < chip->nr_cores; i++) { 326 PnvCore *pnv_core = chip->cores[i]; 327 328 pnv_dt_core(chip, pnv_core, fdt); 329 330 /* Interrupt Control Presenters (ICP). One per core. */ 331 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 332 } 333 334 if (chip->ram_size) { 335 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 336 } 337 } 338 339 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 340 { 341 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 342 int i; 343 344 pnv_dt_xscom(chip, fdt, 0, 345 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 346 cpu_to_be64(PNV9_XSCOM_SIZE), 347 compat, sizeof(compat)); 348 349 for (i = 0; i < chip->nr_cores; i++) { 350 PnvCore *pnv_core = chip->cores[i]; 351 352 pnv_dt_core(chip, pnv_core, fdt); 353 } 354 355 if (chip->ram_size) { 356 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 357 } 358 359 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 360 } 361 362 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 363 { 364 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 365 int i; 366 367 pnv_dt_xscom(chip, fdt, 0, 368 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 369 cpu_to_be64(PNV10_XSCOM_SIZE), 370 compat, sizeof(compat)); 371 372 for (i = 0; i < chip->nr_cores; i++) { 373 PnvCore *pnv_core = chip->cores[i]; 374 375 pnv_dt_core(chip, pnv_core, fdt); 376 } 377 378 if (chip->ram_size) { 379 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 380 } 381 382 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 383 } 384 385 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 386 { 387 uint32_t io_base = d->ioport_id; 388 uint32_t io_regs[] = { 389 cpu_to_be32(1), 390 cpu_to_be32(io_base), 391 cpu_to_be32(2) 392 }; 393 char *name; 394 int node; 395 396 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 397 node = fdt_add_subnode(fdt, lpc_off, name); 398 _FDT(node); 399 g_free(name); 400 401 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 402 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 403 } 404 405 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 406 { 407 const char compatible[] = "ns16550\0pnpPNP,501"; 408 uint32_t io_base = d->ioport_id; 409 uint32_t io_regs[] = { 410 cpu_to_be32(1), 411 cpu_to_be32(io_base), 412 cpu_to_be32(8) 413 }; 414 uint32_t irq; 415 char *name; 416 int node; 417 418 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 419 420 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 421 node = fdt_add_subnode(fdt, lpc_off, name); 422 _FDT(node); 423 g_free(name); 424 425 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 426 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 427 sizeof(compatible)))); 428 429 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 430 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 431 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 432 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 433 fdt_get_phandle(fdt, lpc_off)))); 434 435 /* This is needed by Linux */ 436 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 437 } 438 439 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 440 { 441 const char compatible[] = "bt\0ipmi-bt"; 442 uint32_t io_base; 443 uint32_t io_regs[] = { 444 cpu_to_be32(1), 445 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 446 cpu_to_be32(3) 447 }; 448 uint32_t irq; 449 char *name; 450 int node; 451 452 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 453 io_regs[1] = cpu_to_be32(io_base); 454 455 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 456 457 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 458 node = fdt_add_subnode(fdt, lpc_off, name); 459 _FDT(node); 460 g_free(name); 461 462 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 463 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 464 sizeof(compatible)))); 465 466 /* Mark it as reserved to avoid Linux trying to claim it */ 467 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 468 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 469 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 470 fdt_get_phandle(fdt, lpc_off)))); 471 } 472 473 typedef struct ForeachPopulateArgs { 474 void *fdt; 475 int offset; 476 } ForeachPopulateArgs; 477 478 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 479 { 480 ForeachPopulateArgs *args = opaque; 481 ISADevice *d = ISA_DEVICE(dev); 482 483 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 484 pnv_dt_rtc(d, args->fdt, args->offset); 485 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 486 pnv_dt_serial(d, args->fdt, args->offset); 487 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 488 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 489 } else { 490 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 491 d->ioport_id); 492 } 493 494 return 0; 495 } 496 497 /* 498 * The default LPC bus of a multichip system is on chip 0. It's 499 * recognized by the firmware (skiboot) using a "primary" property. 500 */ 501 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 502 { 503 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 504 ForeachPopulateArgs args = { 505 .fdt = fdt, 506 .offset = isa_offset, 507 }; 508 uint32_t phandle; 509 510 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 511 512 phandle = qemu_fdt_alloc_phandle(fdt); 513 assert(phandle > 0); 514 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 515 516 /* 517 * ISA devices are not necessarily parented to the ISA bus so we 518 * can not use object_child_foreach() 519 */ 520 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 521 &args); 522 } 523 524 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 525 { 526 int off; 527 528 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 529 off = fdt_add_subnode(fdt, off, "power-mgt"); 530 531 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 532 } 533 534 static void *pnv_dt_create(MachineState *machine) 535 { 536 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 537 PnvMachineState *pnv = PNV_MACHINE(machine); 538 void *fdt; 539 char *buf; 540 int off; 541 int i; 542 543 fdt = g_malloc0(FDT_MAX_SIZE); 544 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 545 546 /* /qemu node */ 547 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 548 549 /* Root node */ 550 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 551 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 552 _FDT((fdt_setprop_string(fdt, 0, "model", 553 "IBM PowerNV (emulated by qemu)"))); 554 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 555 556 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 557 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 558 if (qemu_uuid_set) { 559 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 560 } 561 g_free(buf); 562 563 off = fdt_add_subnode(fdt, 0, "chosen"); 564 if (machine->kernel_cmdline) { 565 _FDT((fdt_setprop_string(fdt, off, "bootargs", 566 machine->kernel_cmdline))); 567 } 568 569 if (pnv->initrd_size) { 570 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 571 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 572 573 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 574 &start_prop, sizeof(start_prop)))); 575 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 576 &end_prop, sizeof(end_prop)))); 577 } 578 579 /* Populate device tree for each chip */ 580 for (i = 0; i < pnv->num_chips; i++) { 581 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 582 } 583 584 /* Populate ISA devices on chip 0 */ 585 pnv_dt_isa(pnv, fdt); 586 587 if (pnv->bmc) { 588 pnv_dt_bmc_sensors(pnv->bmc, fdt); 589 } 590 591 /* Create an extra node for power management on machines that support it */ 592 if (pmc->dt_power_mgt) { 593 pmc->dt_power_mgt(pnv, fdt); 594 } 595 596 return fdt; 597 } 598 599 static void pnv_powerdown_notify(Notifier *n, void *opaque) 600 { 601 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 602 603 if (pnv->bmc) { 604 pnv_bmc_powerdown(pnv->bmc); 605 } 606 } 607 608 static void pnv_reset(MachineState *machine, ShutdownCause reason) 609 { 610 PnvMachineState *pnv = PNV_MACHINE(machine); 611 IPMIBmc *bmc; 612 void *fdt; 613 614 qemu_devices_reset(reason); 615 616 /* 617 * The machine should provide by default an internal BMC simulator. 618 * If not, try to use the BMC device that was provided on the command 619 * line. 620 */ 621 bmc = pnv_bmc_find(&error_fatal); 622 if (!pnv->bmc) { 623 if (!bmc) { 624 if (!qtest_enabled()) { 625 warn_report("machine has no BMC device. Use '-device " 626 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 627 "to define one"); 628 } 629 } else { 630 pnv_bmc_set_pnor(bmc, pnv->pnor); 631 pnv->bmc = bmc; 632 } 633 } 634 635 fdt = pnv_dt_create(machine); 636 637 /* Pack resulting tree */ 638 _FDT((fdt_pack(fdt))); 639 640 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 641 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 642 643 /* 644 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 645 * the existing machine->fdt to avoid leaking it during 646 * a reset. 647 */ 648 g_free(machine->fdt); 649 machine->fdt = fdt; 650 } 651 652 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 653 { 654 Pnv8Chip *chip8 = PNV8_CHIP(chip); 655 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 656 657 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 658 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 659 } 660 661 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 662 { 663 Pnv8Chip *chip8 = PNV8_CHIP(chip); 664 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 665 666 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 667 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 668 } 669 670 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 671 { 672 Pnv9Chip *chip9 = PNV9_CHIP(chip); 673 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 674 675 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 676 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 677 } 678 679 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 680 { 681 Pnv10Chip *chip10 = PNV10_CHIP(chip); 682 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 683 684 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 685 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 686 } 687 688 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 689 { 690 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 691 } 692 693 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 694 { 695 Pnv8Chip *chip8 = PNV8_CHIP(chip); 696 int i; 697 698 ics_pic_print_info(&chip8->psi.ics, mon); 699 700 for (i = 0; i < chip8->num_phbs; i++) { 701 PnvPHB *phb = chip8->phbs[i]; 702 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 703 704 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 705 ics_pic_print_info(&phb3->lsis, mon); 706 } 707 } 708 709 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 710 { 711 Monitor *mon = opaque; 712 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 713 714 if (!phb) { 715 return 0; 716 } 717 718 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 719 720 return 0; 721 } 722 723 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 724 { 725 Pnv9Chip *chip9 = PNV9_CHIP(chip); 726 727 pnv_xive_pic_print_info(&chip9->xive, mon); 728 pnv_psi_pic_print_info(&chip9->psi, mon); 729 730 object_child_foreach_recursive(OBJECT(chip), 731 pnv_chip_power9_pic_print_info_child, mon); 732 } 733 734 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 735 uint32_t core_id) 736 { 737 return PNV_XSCOM_EX_BASE(core_id); 738 } 739 740 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 741 uint32_t core_id) 742 { 743 return PNV9_XSCOM_EC_BASE(core_id); 744 } 745 746 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 747 uint32_t core_id) 748 { 749 return PNV10_XSCOM_EC_BASE(core_id); 750 } 751 752 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 753 { 754 PowerPCCPUClass *ppc_default = 755 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 756 PowerPCCPUClass *ppc = 757 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 758 759 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 760 } 761 762 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 763 { 764 ISADevice *dev = isa_new("isa-ipmi-bt"); 765 766 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 767 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 768 isa_realize_and_unref(dev, bus, &error_fatal); 769 } 770 771 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 772 { 773 Pnv10Chip *chip10 = PNV10_CHIP(chip); 774 775 pnv_xive2_pic_print_info(&chip10->xive, mon); 776 pnv_psi_pic_print_info(&chip10->psi, mon); 777 778 object_child_foreach_recursive(OBJECT(chip), 779 pnv_chip_power9_pic_print_info_child, mon); 780 } 781 782 /* Always give the first 1GB to chip 0 else we won't boot */ 783 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 784 { 785 MachineState *machine = MACHINE(pnv); 786 uint64_t ram_per_chip; 787 788 assert(machine->ram_size >= 1 * GiB); 789 790 ram_per_chip = machine->ram_size / pnv->num_chips; 791 if (ram_per_chip >= 1 * GiB) { 792 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 793 } 794 795 assert(pnv->num_chips > 1); 796 797 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 798 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 799 } 800 801 static void pnv_init(MachineState *machine) 802 { 803 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 804 PnvMachineState *pnv = PNV_MACHINE(machine); 805 MachineClass *mc = MACHINE_GET_CLASS(machine); 806 char *fw_filename; 807 long fw_size; 808 uint64_t chip_ram_start = 0; 809 int i; 810 char *chip_typename; 811 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 812 DeviceState *dev; 813 814 if (kvm_enabled()) { 815 error_report("The powernv machine does not work with KVM acceleration"); 816 exit(EXIT_FAILURE); 817 } 818 819 /* allocate RAM */ 820 if (machine->ram_size < mc->default_ram_size) { 821 char *sz = size_to_str(mc->default_ram_size); 822 error_report("Invalid RAM size, should be bigger than %s", sz); 823 g_free(sz); 824 exit(EXIT_FAILURE); 825 } 826 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 827 828 /* 829 * Create our simple PNOR device 830 */ 831 dev = qdev_new(TYPE_PNV_PNOR); 832 if (pnor) { 833 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 834 } 835 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 836 pnv->pnor = PNV_PNOR(dev); 837 838 /* load skiboot firmware */ 839 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 840 if (!fw_filename) { 841 error_report("Could not find OPAL firmware '%s'", bios_name); 842 exit(1); 843 } 844 845 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 846 if (fw_size < 0) { 847 error_report("Could not load OPAL firmware '%s'", fw_filename); 848 exit(1); 849 } 850 g_free(fw_filename); 851 852 /* load kernel */ 853 if (machine->kernel_filename) { 854 long kernel_size; 855 856 kernel_size = load_image_targphys(machine->kernel_filename, 857 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 858 if (kernel_size < 0) { 859 error_report("Could not load kernel '%s'", 860 machine->kernel_filename); 861 exit(1); 862 } 863 } 864 865 /* load initrd */ 866 if (machine->initrd_filename) { 867 pnv->initrd_base = INITRD_LOAD_ADDR; 868 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 869 pnv->initrd_base, INITRD_MAX_SIZE); 870 if (pnv->initrd_size < 0) { 871 error_report("Could not load initial ram disk '%s'", 872 machine->initrd_filename); 873 exit(1); 874 } 875 } 876 877 /* MSIs are supported on this platform */ 878 msi_nonbroken = true; 879 880 /* 881 * Check compatibility of the specified CPU with the machine 882 * default. 883 */ 884 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 885 error_report("invalid CPU model '%s' for %s machine", 886 machine->cpu_type, mc->name); 887 exit(1); 888 } 889 890 /* Create the processor chips */ 891 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 892 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 893 i, machine->cpu_type); 894 if (!object_class_by_name(chip_typename)) { 895 error_report("invalid chip model '%.*s' for %s machine", 896 i, machine->cpu_type, mc->name); 897 exit(1); 898 } 899 900 pnv->num_chips = 901 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 902 /* 903 * TODO: should we decide on how many chips we can create based 904 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 905 */ 906 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 907 error_report("invalid number of chips: '%d'", pnv->num_chips); 908 error_printf( 909 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 910 exit(1); 911 } 912 913 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 914 for (i = 0; i < pnv->num_chips; i++) { 915 char chip_name[32]; 916 Object *chip = OBJECT(qdev_new(chip_typename)); 917 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 918 919 pnv->chips[i] = PNV_CHIP(chip); 920 921 /* Distribute RAM among the chips */ 922 object_property_set_int(chip, "ram-start", chip_ram_start, 923 &error_fatal); 924 object_property_set_int(chip, "ram-size", chip_ram_size, 925 &error_fatal); 926 chip_ram_start += chip_ram_size; 927 928 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 929 object_property_add_child(OBJECT(pnv), chip_name, chip); 930 object_property_set_int(chip, "chip-id", i, &error_fatal); 931 object_property_set_int(chip, "nr-cores", machine->smp.cores, 932 &error_fatal); 933 object_property_set_int(chip, "nr-threads", machine->smp.threads, 934 &error_fatal); 935 /* 936 * The POWER8 machine use the XICS interrupt interface. 937 * Propagate the XICS fabric to the chip and its controllers. 938 */ 939 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 940 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 941 } 942 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 943 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 944 &error_abort); 945 } 946 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 947 } 948 g_free(chip_typename); 949 950 /* Instantiate ISA bus on chip 0 */ 951 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 952 953 /* Create serial port */ 954 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 955 956 /* Create an RTC ISA device too */ 957 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 958 959 /* 960 * Create the machine BMC simulator and the IPMI BT device for 961 * communication with the BMC 962 */ 963 if (defaults_enabled()) { 964 pnv->bmc = pnv_bmc_create(pnv->pnor); 965 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 966 } 967 968 /* 969 * The PNOR is mapped on the LPC FW address space by the BMC. 970 * Since we can not reach the remote BMC machine with LPC memops, 971 * map it always for now. 972 */ 973 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 974 &pnv->pnor->mmio); 975 976 /* 977 * OpenPOWER systems use a IPMI SEL Event message to notify the 978 * host to powerdown 979 */ 980 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 981 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 982 } 983 984 /* 985 * 0:21 Reserved - Read as zeros 986 * 22:24 Chip ID 987 * 25:28 Core number 988 * 29:31 Thread ID 989 */ 990 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 991 { 992 return (chip->chip_id << 7) | (core_id << 3); 993 } 994 995 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 996 Error **errp) 997 { 998 Pnv8Chip *chip8 = PNV8_CHIP(chip); 999 Error *local_err = NULL; 1000 Object *obj; 1001 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1002 1003 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1004 if (local_err) { 1005 error_propagate(errp, local_err); 1006 return; 1007 } 1008 1009 pnv_cpu->intc = obj; 1010 } 1011 1012 1013 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1014 { 1015 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1016 1017 icp_reset(ICP(pnv_cpu->intc)); 1018 } 1019 1020 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1021 { 1022 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1023 1024 icp_destroy(ICP(pnv_cpu->intc)); 1025 pnv_cpu->intc = NULL; 1026 } 1027 1028 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1029 Monitor *mon) 1030 { 1031 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1032 } 1033 1034 /* 1035 * 0:48 Reserved - Read as zeroes 1036 * 49:52 Node ID 1037 * 53:55 Chip ID 1038 * 56 Reserved - Read as zero 1039 * 57:61 Core number 1040 * 62:63 Thread ID 1041 * 1042 * We only care about the lower bits. uint32_t is fine for the moment. 1043 */ 1044 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1045 { 1046 return (chip->chip_id << 8) | (core_id << 2); 1047 } 1048 1049 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1050 { 1051 return (chip->chip_id << 8) | (core_id << 2); 1052 } 1053 1054 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1055 Error **errp) 1056 { 1057 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1058 Error *local_err = NULL; 1059 Object *obj; 1060 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1061 1062 /* 1063 * The core creates its interrupt presenter but the XIVE interrupt 1064 * controller object is initialized afterwards. Hopefully, it's 1065 * only used at runtime. 1066 */ 1067 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1068 &local_err); 1069 if (local_err) { 1070 error_propagate(errp, local_err); 1071 return; 1072 } 1073 1074 pnv_cpu->intc = obj; 1075 } 1076 1077 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1078 { 1079 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1080 1081 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1082 } 1083 1084 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1085 { 1086 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1087 1088 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1089 pnv_cpu->intc = NULL; 1090 } 1091 1092 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1093 Monitor *mon) 1094 { 1095 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1096 } 1097 1098 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1099 Error **errp) 1100 { 1101 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1102 Error *local_err = NULL; 1103 Object *obj; 1104 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1105 1106 /* 1107 * The core creates its interrupt presenter but the XIVE2 interrupt 1108 * controller object is initialized afterwards. Hopefully, it's 1109 * only used at runtime. 1110 */ 1111 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1112 &local_err); 1113 if (local_err) { 1114 error_propagate(errp, local_err); 1115 return; 1116 } 1117 1118 pnv_cpu->intc = obj; 1119 } 1120 1121 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1122 { 1123 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1124 1125 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1126 } 1127 1128 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1129 { 1130 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1131 1132 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1133 pnv_cpu->intc = NULL; 1134 } 1135 1136 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1137 Monitor *mon) 1138 { 1139 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1140 } 1141 1142 /* 1143 * Allowed core identifiers on a POWER8 Processor Chip : 1144 * 1145 * <EX0 reserved> 1146 * EX1 - Venice only 1147 * EX2 - Venice only 1148 * EX3 - Venice only 1149 * EX4 1150 * EX5 1151 * EX6 1152 * <EX7,8 reserved> <reserved> 1153 * EX9 - Venice only 1154 * EX10 - Venice only 1155 * EX11 - Venice only 1156 * EX12 1157 * EX13 1158 * EX14 1159 * <EX15 reserved> 1160 */ 1161 #define POWER8E_CORE_MASK (0x7070ull) 1162 #define POWER8_CORE_MASK (0x7e7eull) 1163 1164 /* 1165 * POWER9 has 24 cores, ids starting at 0x0 1166 */ 1167 #define POWER9_CORE_MASK (0xffffffffffffffull) 1168 1169 1170 #define POWER10_CORE_MASK (0xffffffffffffffull) 1171 1172 static void pnv_chip_power8_instance_init(Object *obj) 1173 { 1174 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1175 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1176 int i; 1177 1178 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1179 (Object **)&chip8->xics, 1180 object_property_allow_set_link, 1181 OBJ_PROP_LINK_STRONG); 1182 1183 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1184 1185 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1186 1187 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1188 1189 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1190 1191 if (defaults_enabled()) { 1192 chip8->num_phbs = pcc->num_phbs; 1193 1194 for (i = 0; i < chip8->num_phbs; i++) { 1195 Object *phb = object_new(TYPE_PNV_PHB); 1196 1197 /* 1198 * We need the chip to parent the PHB to allow the DT 1199 * to build correctly (via pnv_xscom_dt()). 1200 * 1201 * TODO: the PHB should be parented by a PEC device that, at 1202 * this moment, is not modelled powernv8/phb3. 1203 */ 1204 object_property_add_child(obj, "phb[*]", phb); 1205 chip8->phbs[i] = PNV_PHB(phb); 1206 } 1207 } 1208 1209 } 1210 1211 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1212 { 1213 PnvChip *chip = PNV_CHIP(chip8); 1214 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1215 int i, j; 1216 char *name; 1217 1218 name = g_strdup_printf("icp-%x", chip->chip_id); 1219 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1220 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1221 g_free(name); 1222 1223 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1224 1225 /* Map the ICP registers for each thread */ 1226 for (i = 0; i < chip->nr_cores; i++) { 1227 PnvCore *pnv_core = chip->cores[i]; 1228 int core_hwid = CPU_CORE(pnv_core)->core_id; 1229 1230 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1231 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1232 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1233 1234 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1235 &icp->mmio); 1236 } 1237 } 1238 } 1239 1240 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1241 { 1242 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1243 PnvChip *chip = PNV_CHIP(dev); 1244 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1245 Pnv8Psi *psi8 = &chip8->psi; 1246 Error *local_err = NULL; 1247 int i; 1248 1249 assert(chip8->xics); 1250 1251 /* XSCOM bridge is first */ 1252 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1253 if (local_err) { 1254 error_propagate(errp, local_err); 1255 return; 1256 } 1257 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1258 1259 pcc->parent_realize(dev, &local_err); 1260 if (local_err) { 1261 error_propagate(errp, local_err); 1262 return; 1263 } 1264 1265 /* Processor Service Interface (PSI) Host Bridge */ 1266 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1267 &error_fatal); 1268 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1269 OBJECT(chip8->xics), &error_abort); 1270 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1271 return; 1272 } 1273 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1274 &PNV_PSI(psi8)->xscom_regs); 1275 1276 /* Create LPC controller */ 1277 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1278 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1279 1280 chip->fw_mr = &chip8->lpc.isa_fw; 1281 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1282 (uint64_t) PNV_XSCOM_BASE(chip), 1283 PNV_XSCOM_LPC_BASE); 1284 1285 /* 1286 * Interrupt Management Area. This is the memory region holding 1287 * all the Interrupt Control Presenter (ICP) registers 1288 */ 1289 pnv_chip_icp_realize(chip8, &local_err); 1290 if (local_err) { 1291 error_propagate(errp, local_err); 1292 return; 1293 } 1294 1295 /* Create the simplified OCC model */ 1296 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1297 return; 1298 } 1299 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1300 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1301 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1302 1303 /* OCC SRAM model */ 1304 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1305 &chip8->occ.sram_regs); 1306 1307 /* HOMER */ 1308 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1309 &error_abort); 1310 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1311 return; 1312 } 1313 /* Homer Xscom region */ 1314 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1315 1316 /* Homer mmio region */ 1317 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1318 &chip8->homer.regs); 1319 1320 /* PHB controllers */ 1321 for (i = 0; i < chip8->num_phbs; i++) { 1322 PnvPHB *phb = chip8->phbs[i]; 1323 1324 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1325 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1326 &error_fatal); 1327 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1328 &error_fatal); 1329 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1330 return; 1331 } 1332 } 1333 } 1334 1335 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1336 { 1337 addr &= (PNV_XSCOM_SIZE - 1); 1338 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1339 } 1340 1341 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1342 { 1343 DeviceClass *dc = DEVICE_CLASS(klass); 1344 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1345 1346 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1347 k->cores_mask = POWER8E_CORE_MASK; 1348 k->num_phbs = 3; 1349 k->core_pir = pnv_chip_core_pir_p8; 1350 k->intc_create = pnv_chip_power8_intc_create; 1351 k->intc_reset = pnv_chip_power8_intc_reset; 1352 k->intc_destroy = pnv_chip_power8_intc_destroy; 1353 k->intc_print_info = pnv_chip_power8_intc_print_info; 1354 k->isa_create = pnv_chip_power8_isa_create; 1355 k->dt_populate = pnv_chip_power8_dt_populate; 1356 k->pic_print_info = pnv_chip_power8_pic_print_info; 1357 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1358 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1359 dc->desc = "PowerNV Chip POWER8E"; 1360 1361 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1362 &k->parent_realize); 1363 } 1364 1365 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1366 { 1367 DeviceClass *dc = DEVICE_CLASS(klass); 1368 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1369 1370 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1371 k->cores_mask = POWER8_CORE_MASK; 1372 k->num_phbs = 3; 1373 k->core_pir = pnv_chip_core_pir_p8; 1374 k->intc_create = pnv_chip_power8_intc_create; 1375 k->intc_reset = pnv_chip_power8_intc_reset; 1376 k->intc_destroy = pnv_chip_power8_intc_destroy; 1377 k->intc_print_info = pnv_chip_power8_intc_print_info; 1378 k->isa_create = pnv_chip_power8_isa_create; 1379 k->dt_populate = pnv_chip_power8_dt_populate; 1380 k->pic_print_info = pnv_chip_power8_pic_print_info; 1381 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1382 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1383 dc->desc = "PowerNV Chip POWER8"; 1384 1385 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1386 &k->parent_realize); 1387 } 1388 1389 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1390 { 1391 DeviceClass *dc = DEVICE_CLASS(klass); 1392 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1393 1394 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1395 k->cores_mask = POWER8_CORE_MASK; 1396 k->num_phbs = 4; 1397 k->core_pir = pnv_chip_core_pir_p8; 1398 k->intc_create = pnv_chip_power8_intc_create; 1399 k->intc_reset = pnv_chip_power8_intc_reset; 1400 k->intc_destroy = pnv_chip_power8_intc_destroy; 1401 k->intc_print_info = pnv_chip_power8_intc_print_info; 1402 k->isa_create = pnv_chip_power8nvl_isa_create; 1403 k->dt_populate = pnv_chip_power8_dt_populate; 1404 k->pic_print_info = pnv_chip_power8_pic_print_info; 1405 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1406 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1407 dc->desc = "PowerNV Chip POWER8NVL"; 1408 1409 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1410 &k->parent_realize); 1411 } 1412 1413 static void pnv_chip_power9_instance_init(Object *obj) 1414 { 1415 PnvChip *chip = PNV_CHIP(obj); 1416 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1417 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1418 int i; 1419 1420 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1421 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1422 "xive-fabric"); 1423 1424 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1425 1426 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1427 1428 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1429 1430 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1431 1432 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1433 1434 /* Number of PECs is the chip default */ 1435 chip->num_pecs = pcc->num_pecs; 1436 1437 for (i = 0; i < chip->num_pecs; i++) { 1438 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1439 TYPE_PNV_PHB4_PEC); 1440 } 1441 } 1442 1443 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1444 PnvCore *pnv_core) 1445 { 1446 char eq_name[32]; 1447 int core_id = CPU_CORE(pnv_core)->core_id; 1448 1449 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1450 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1451 sizeof(*eq), TYPE_PNV_QUAD, 1452 &error_fatal, NULL); 1453 1454 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1455 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1456 } 1457 1458 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1459 { 1460 PnvChip *chip = PNV_CHIP(chip9); 1461 int i; 1462 1463 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1464 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1465 1466 for (i = 0; i < chip9->nr_quads; i++) { 1467 PnvQuad *eq = &chip9->quads[i]; 1468 1469 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1470 1471 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1472 &eq->xscom_regs); 1473 } 1474 } 1475 1476 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1477 { 1478 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1479 int i; 1480 1481 for (i = 0; i < chip->num_pecs; i++) { 1482 PnvPhb4PecState *pec = &chip9->pecs[i]; 1483 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1484 uint32_t pec_nest_base; 1485 uint32_t pec_pci_base; 1486 1487 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1488 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1489 &error_fatal); 1490 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1491 &error_fatal); 1492 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1493 return; 1494 } 1495 1496 pec_nest_base = pecc->xscom_nest_base(pec); 1497 pec_pci_base = pecc->xscom_pci_base(pec); 1498 1499 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1500 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1501 } 1502 } 1503 1504 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1505 { 1506 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1507 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1508 PnvChip *chip = PNV_CHIP(dev); 1509 Pnv9Psi *psi9 = &chip9->psi; 1510 Error *local_err = NULL; 1511 1512 /* XSCOM bridge is first */ 1513 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1514 if (local_err) { 1515 error_propagate(errp, local_err); 1516 return; 1517 } 1518 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1519 1520 pcc->parent_realize(dev, &local_err); 1521 if (local_err) { 1522 error_propagate(errp, local_err); 1523 return; 1524 } 1525 1526 pnv_chip_quad_realize(chip9, &local_err); 1527 if (local_err) { 1528 error_propagate(errp, local_err); 1529 return; 1530 } 1531 1532 /* XIVE interrupt controller (POWER9) */ 1533 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1534 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1535 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1536 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1537 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1538 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1539 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1540 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1541 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1542 &error_abort); 1543 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1544 return; 1545 } 1546 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1547 &chip9->xive.xscom_regs); 1548 1549 /* Processor Service Interface (PSI) Host Bridge */ 1550 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1551 &error_fatal); 1552 /* This is the only device with 4k ESB pages */ 1553 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1554 &error_fatal); 1555 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1556 return; 1557 } 1558 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1559 &PNV_PSI(psi9)->xscom_regs); 1560 1561 /* LPC */ 1562 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1563 return; 1564 } 1565 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1566 &chip9->lpc.xscom_regs); 1567 1568 chip->fw_mr = &chip9->lpc.isa_fw; 1569 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1570 (uint64_t) PNV9_LPCM_BASE(chip)); 1571 1572 /* Create the simplified OCC model */ 1573 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1574 return; 1575 } 1576 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1577 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1578 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1579 1580 /* OCC SRAM model */ 1581 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1582 &chip9->occ.sram_regs); 1583 1584 /* SBE */ 1585 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1586 return; 1587 } 1588 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1589 &chip9->sbe.xscom_ctrl_regs); 1590 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1591 &chip9->sbe.xscom_mbox_regs); 1592 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1593 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1594 1595 /* HOMER */ 1596 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1597 &error_abort); 1598 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1599 return; 1600 } 1601 /* Homer Xscom region */ 1602 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1603 1604 /* Homer mmio region */ 1605 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1606 &chip9->homer.regs); 1607 1608 /* PEC PHBs */ 1609 pnv_chip_power9_pec_realize(chip, &local_err); 1610 if (local_err) { 1611 error_propagate(errp, local_err); 1612 return; 1613 } 1614 } 1615 1616 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1617 { 1618 addr &= (PNV9_XSCOM_SIZE - 1); 1619 return addr >> 3; 1620 } 1621 1622 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1623 { 1624 DeviceClass *dc = DEVICE_CLASS(klass); 1625 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1626 1627 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1628 k->cores_mask = POWER9_CORE_MASK; 1629 k->core_pir = pnv_chip_core_pir_p9; 1630 k->intc_create = pnv_chip_power9_intc_create; 1631 k->intc_reset = pnv_chip_power9_intc_reset; 1632 k->intc_destroy = pnv_chip_power9_intc_destroy; 1633 k->intc_print_info = pnv_chip_power9_intc_print_info; 1634 k->isa_create = pnv_chip_power9_isa_create; 1635 k->dt_populate = pnv_chip_power9_dt_populate; 1636 k->pic_print_info = pnv_chip_power9_pic_print_info; 1637 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1638 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1639 dc->desc = "PowerNV Chip POWER9"; 1640 k->num_pecs = PNV9_CHIP_MAX_PEC; 1641 1642 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1643 &k->parent_realize); 1644 } 1645 1646 static void pnv_chip_power10_instance_init(Object *obj) 1647 { 1648 PnvChip *chip = PNV_CHIP(obj); 1649 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1650 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1651 int i; 1652 1653 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1654 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1655 "xive-fabric"); 1656 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1657 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1658 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1659 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1660 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1661 1662 chip->num_pecs = pcc->num_pecs; 1663 1664 for (i = 0; i < chip->num_pecs; i++) { 1665 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1666 TYPE_PNV_PHB5_PEC); 1667 } 1668 } 1669 1670 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1671 { 1672 PnvChip *chip = PNV_CHIP(chip10); 1673 int i; 1674 1675 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1676 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1677 1678 for (i = 0; i < chip10->nr_quads; i++) { 1679 PnvQuad *eq = &chip10->quads[i]; 1680 1681 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1682 1683 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1684 &eq->xscom_regs); 1685 } 1686 } 1687 1688 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1689 { 1690 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1691 int i; 1692 1693 for (i = 0; i < chip->num_pecs; i++) { 1694 PnvPhb4PecState *pec = &chip10->pecs[i]; 1695 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1696 uint32_t pec_nest_base; 1697 uint32_t pec_pci_base; 1698 1699 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1700 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1701 &error_fatal); 1702 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1703 &error_fatal); 1704 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1705 return; 1706 } 1707 1708 pec_nest_base = pecc->xscom_nest_base(pec); 1709 pec_pci_base = pecc->xscom_pci_base(pec); 1710 1711 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1712 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1713 } 1714 } 1715 1716 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1717 { 1718 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1719 PnvChip *chip = PNV_CHIP(dev); 1720 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1721 Error *local_err = NULL; 1722 1723 /* XSCOM bridge is first */ 1724 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1725 if (local_err) { 1726 error_propagate(errp, local_err); 1727 return; 1728 } 1729 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1730 1731 pcc->parent_realize(dev, &local_err); 1732 if (local_err) { 1733 error_propagate(errp, local_err); 1734 return; 1735 } 1736 1737 pnv_chip_power10_quad_realize(chip10, &local_err); 1738 if (local_err) { 1739 error_propagate(errp, local_err); 1740 return; 1741 } 1742 1743 /* XIVE2 interrupt controller (POWER10) */ 1744 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1745 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1746 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1747 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1748 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1749 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1750 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1751 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1752 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1753 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1754 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1755 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1756 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1757 &error_abort); 1758 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1759 return; 1760 } 1761 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1762 &chip10->xive.xscom_regs); 1763 1764 /* Processor Service Interface (PSI) Host Bridge */ 1765 object_property_set_int(OBJECT(&chip10->psi), "bar", 1766 PNV10_PSIHB_BASE(chip), &error_fatal); 1767 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1768 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1769 &error_fatal); 1770 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1771 return; 1772 } 1773 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1774 &PNV_PSI(&chip10->psi)->xscom_regs); 1775 1776 /* LPC */ 1777 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1778 return; 1779 } 1780 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1781 &chip10->lpc.xscom_regs); 1782 1783 chip->fw_mr = &chip10->lpc.isa_fw; 1784 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1785 (uint64_t) PNV10_LPCM_BASE(chip)); 1786 1787 /* Create the simplified OCC model */ 1788 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1789 return; 1790 } 1791 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1792 &chip10->occ.xscom_regs); 1793 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1794 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1795 1796 /* OCC SRAM model */ 1797 memory_region_add_subregion(get_system_memory(), 1798 PNV10_OCC_SENSOR_BASE(chip), 1799 &chip10->occ.sram_regs); 1800 1801 /* SBE */ 1802 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1803 return; 1804 } 1805 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1806 &chip10->sbe.xscom_ctrl_regs); 1807 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1808 &chip10->sbe.xscom_mbox_regs); 1809 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1810 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1811 1812 /* HOMER */ 1813 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1814 &error_abort); 1815 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1816 return; 1817 } 1818 /* Homer Xscom region */ 1819 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1820 &chip10->homer.pba_regs); 1821 1822 /* Homer mmio region */ 1823 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1824 &chip10->homer.regs); 1825 1826 /* PHBs */ 1827 pnv_chip_power10_phb_realize(chip, &local_err); 1828 if (local_err) { 1829 error_propagate(errp, local_err); 1830 return; 1831 } 1832 } 1833 1834 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1835 { 1836 addr &= (PNV10_XSCOM_SIZE - 1); 1837 return addr >> 3; 1838 } 1839 1840 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1841 { 1842 DeviceClass *dc = DEVICE_CLASS(klass); 1843 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1844 1845 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1846 k->cores_mask = POWER10_CORE_MASK; 1847 k->core_pir = pnv_chip_core_pir_p10; 1848 k->intc_create = pnv_chip_power10_intc_create; 1849 k->intc_reset = pnv_chip_power10_intc_reset; 1850 k->intc_destroy = pnv_chip_power10_intc_destroy; 1851 k->intc_print_info = pnv_chip_power10_intc_print_info; 1852 k->isa_create = pnv_chip_power10_isa_create; 1853 k->dt_populate = pnv_chip_power10_dt_populate; 1854 k->pic_print_info = pnv_chip_power10_pic_print_info; 1855 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1856 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1857 dc->desc = "PowerNV Chip POWER10"; 1858 k->num_pecs = PNV10_CHIP_MAX_PEC; 1859 1860 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1861 &k->parent_realize); 1862 } 1863 1864 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1865 { 1866 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1867 int cores_max; 1868 1869 /* 1870 * No custom mask for this chip, let's use the default one from * 1871 * the chip class 1872 */ 1873 if (!chip->cores_mask) { 1874 chip->cores_mask = pcc->cores_mask; 1875 } 1876 1877 /* filter alien core ids ! some are reserved */ 1878 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1879 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1880 chip->cores_mask); 1881 return; 1882 } 1883 chip->cores_mask &= pcc->cores_mask; 1884 1885 /* now that we have a sane layout, let check the number of cores */ 1886 cores_max = ctpop64(chip->cores_mask); 1887 if (chip->nr_cores > cores_max) { 1888 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1889 cores_max); 1890 return; 1891 } 1892 } 1893 1894 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1895 { 1896 Error *error = NULL; 1897 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1898 const char *typename = pnv_chip_core_typename(chip); 1899 int i, core_hwid; 1900 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1901 1902 if (!object_class_by_name(typename)) { 1903 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1904 return; 1905 } 1906 1907 /* Cores */ 1908 pnv_chip_core_sanitize(chip, &error); 1909 if (error) { 1910 error_propagate(errp, error); 1911 return; 1912 } 1913 1914 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1915 1916 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1917 && (i < chip->nr_cores); core_hwid++) { 1918 char core_name[32]; 1919 PnvCore *pnv_core; 1920 uint64_t xscom_core_base; 1921 1922 if (!(chip->cores_mask & (1ull << core_hwid))) { 1923 continue; 1924 } 1925 1926 pnv_core = PNV_CORE(object_new(typename)); 1927 1928 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1929 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1930 chip->cores[i] = pnv_core; 1931 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1932 chip->nr_threads, &error_fatal); 1933 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1934 core_hwid, &error_fatal); 1935 object_property_set_int(OBJECT(pnv_core), "pir", 1936 pcc->core_pir(chip, core_hwid), &error_fatal); 1937 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1938 &error_fatal); 1939 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1940 &error_abort); 1941 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1942 1943 /* Each core has an XSCOM MMIO region */ 1944 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1945 1946 pnv_xscom_add_subregion(chip, xscom_core_base, 1947 &pnv_core->xscom_regs); 1948 i++; 1949 } 1950 } 1951 1952 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1953 { 1954 PnvChip *chip = PNV_CHIP(dev); 1955 Error *error = NULL; 1956 1957 /* Cores */ 1958 pnv_chip_core_realize(chip, &error); 1959 if (error) { 1960 error_propagate(errp, error); 1961 return; 1962 } 1963 } 1964 1965 static Property pnv_chip_properties[] = { 1966 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1967 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1968 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1969 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1970 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1971 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1972 DEFINE_PROP_END_OF_LIST(), 1973 }; 1974 1975 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1976 { 1977 DeviceClass *dc = DEVICE_CLASS(klass); 1978 1979 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1980 dc->realize = pnv_chip_realize; 1981 device_class_set_props(dc, pnv_chip_properties); 1982 dc->desc = "PowerNV Chip"; 1983 } 1984 1985 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1986 { 1987 int i, j; 1988 1989 for (i = 0; i < chip->nr_cores; i++) { 1990 PnvCore *pc = chip->cores[i]; 1991 CPUCore *cc = CPU_CORE(pc); 1992 1993 for (j = 0; j < cc->nr_threads; j++) { 1994 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1995 return pc->threads[j]; 1996 } 1997 } 1998 } 1999 return NULL; 2000 } 2001 2002 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2003 { 2004 PnvMachineState *pnv = PNV_MACHINE(xi); 2005 int i, j; 2006 2007 for (i = 0; i < pnv->num_chips; i++) { 2008 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2009 2010 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2011 return &chip8->psi.ics; 2012 } 2013 2014 for (j = 0; j < chip8->num_phbs; j++) { 2015 PnvPHB *phb = chip8->phbs[j]; 2016 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2017 2018 if (ics_valid_irq(&phb3->lsis, irq)) { 2019 return &phb3->lsis; 2020 } 2021 2022 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2023 return ICS(&phb3->msis); 2024 } 2025 } 2026 } 2027 return NULL; 2028 } 2029 2030 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2031 { 2032 int i; 2033 2034 for (i = 0; i < pnv->num_chips; i++) { 2035 PnvChip *chip = pnv->chips[i]; 2036 if (chip->chip_id == chip_id) { 2037 return chip; 2038 } 2039 } 2040 return NULL; 2041 } 2042 2043 static void pnv_ics_resend(XICSFabric *xi) 2044 { 2045 PnvMachineState *pnv = PNV_MACHINE(xi); 2046 int i, j; 2047 2048 for (i = 0; i < pnv->num_chips; i++) { 2049 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2050 2051 ics_resend(&chip8->psi.ics); 2052 2053 for (j = 0; j < chip8->num_phbs; j++) { 2054 PnvPHB *phb = chip8->phbs[j]; 2055 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2056 2057 ics_resend(&phb3->lsis); 2058 ics_resend(ICS(&phb3->msis)); 2059 } 2060 } 2061 } 2062 2063 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2064 { 2065 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2066 2067 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2068 } 2069 2070 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2071 Monitor *mon) 2072 { 2073 PnvMachineState *pnv = PNV_MACHINE(obj); 2074 int i; 2075 CPUState *cs; 2076 2077 CPU_FOREACH(cs) { 2078 PowerPCCPU *cpu = POWERPC_CPU(cs); 2079 2080 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2081 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2082 mon); 2083 } 2084 2085 for (i = 0; i < pnv->num_chips; i++) { 2086 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2087 } 2088 } 2089 2090 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2091 uint8_t nvt_blk, uint32_t nvt_idx, 2092 bool cam_ignore, uint8_t priority, 2093 uint32_t logic_serv, 2094 XiveTCTXMatch *match) 2095 { 2096 PnvMachineState *pnv = PNV_MACHINE(xfb); 2097 int total_count = 0; 2098 int i; 2099 2100 for (i = 0; i < pnv->num_chips; i++) { 2101 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2102 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2103 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2104 int count; 2105 2106 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2107 priority, logic_serv, match); 2108 2109 if (count < 0) { 2110 return count; 2111 } 2112 2113 total_count += count; 2114 } 2115 2116 return total_count; 2117 } 2118 2119 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2120 uint8_t nvt_blk, uint32_t nvt_idx, 2121 bool cam_ignore, uint8_t priority, 2122 uint32_t logic_serv, 2123 XiveTCTXMatch *match) 2124 { 2125 PnvMachineState *pnv = PNV_MACHINE(xfb); 2126 int total_count = 0; 2127 int i; 2128 2129 for (i = 0; i < pnv->num_chips; i++) { 2130 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2131 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2132 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2133 int count; 2134 2135 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2136 priority, logic_serv, match); 2137 2138 if (count < 0) { 2139 return count; 2140 } 2141 2142 total_count += count; 2143 } 2144 2145 return total_count; 2146 } 2147 2148 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2149 { 2150 MachineClass *mc = MACHINE_CLASS(oc); 2151 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2152 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2153 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2154 2155 static GlobalProperty phb_compat[] = { 2156 { TYPE_PNV_PHB, "version", "3" }, 2157 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2158 }; 2159 2160 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2161 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2162 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2163 2164 xic->icp_get = pnv_icp_get; 2165 xic->ics_get = pnv_ics_get; 2166 xic->ics_resend = pnv_ics_resend; 2167 2168 pmc->compat = compat; 2169 pmc->compat_size = sizeof(compat); 2170 2171 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2172 } 2173 2174 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2175 { 2176 MachineClass *mc = MACHINE_CLASS(oc); 2177 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2178 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2179 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2180 2181 static GlobalProperty phb_compat[] = { 2182 { TYPE_PNV_PHB, "version", "4" }, 2183 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2184 }; 2185 2186 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2187 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2188 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2189 2190 xfc->match_nvt = pnv_match_nvt; 2191 2192 mc->alias = "powernv"; 2193 2194 pmc->compat = compat; 2195 pmc->compat_size = sizeof(compat); 2196 pmc->dt_power_mgt = pnv_dt_power_mgt; 2197 2198 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2199 } 2200 2201 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2202 { 2203 MachineClass *mc = MACHINE_CLASS(oc); 2204 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2205 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2206 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2207 2208 static GlobalProperty phb_compat[] = { 2209 { TYPE_PNV_PHB, "version", "5" }, 2210 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2211 }; 2212 2213 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2214 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2215 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2216 2217 pmc->compat = compat; 2218 pmc->compat_size = sizeof(compat); 2219 pmc->dt_power_mgt = pnv_dt_power_mgt; 2220 2221 xfc->match_nvt = pnv10_xive_match_nvt; 2222 2223 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2224 } 2225 2226 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2227 { 2228 PnvMachineState *pnv = PNV_MACHINE(obj); 2229 2230 return !!pnv->fw_load_addr; 2231 } 2232 2233 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2234 { 2235 PnvMachineState *pnv = PNV_MACHINE(obj); 2236 2237 if (value) { 2238 pnv->fw_load_addr = 0x8000000; 2239 } 2240 } 2241 2242 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2243 { 2244 PowerPCCPU *cpu = POWERPC_CPU(cs); 2245 CPUPPCState *env = &cpu->env; 2246 2247 cpu_synchronize_state(cs); 2248 ppc_cpu_do_system_reset(cs); 2249 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2250 /* 2251 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2252 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2253 * (PPC_BIT(43)). 2254 */ 2255 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2256 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2257 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2258 } 2259 } else { 2260 /* 2261 * For non-powersave system resets, SRR1[42:45] are defined to be 2262 * implementation-dependent. The POWER9 User Manual specifies that 2263 * an external (SCOM driven, which may come from a BMC nmi command or 2264 * another CPU requesting a NMI IPI) system reset exception should be 2265 * 0b0010 (PPC_BIT(44)). 2266 */ 2267 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2268 } 2269 } 2270 2271 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2272 { 2273 CPUState *cs; 2274 2275 CPU_FOREACH(cs) { 2276 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2277 } 2278 } 2279 2280 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2281 { 2282 MachineClass *mc = MACHINE_CLASS(oc); 2283 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2284 NMIClass *nc = NMI_CLASS(oc); 2285 2286 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2287 mc->init = pnv_init; 2288 mc->reset = pnv_reset; 2289 mc->max_cpus = MAX_CPUS; 2290 /* Pnv provides a AHCI device for storage */ 2291 mc->block_default_type = IF_IDE; 2292 mc->no_parallel = 1; 2293 mc->default_boot_order = NULL; 2294 /* 2295 * RAM defaults to less than 2048 for 32-bit hosts, and large 2296 * enough to fit the maximum initrd size at it's load address 2297 */ 2298 mc->default_ram_size = 1 * GiB; 2299 mc->default_ram_id = "pnv.ram"; 2300 ispc->print_info = pnv_pic_print_info; 2301 nc->nmi_monitor_handler = pnv_nmi; 2302 2303 object_class_property_add_bool(oc, "hb-mode", 2304 pnv_machine_get_hb, pnv_machine_set_hb); 2305 object_class_property_set_description(oc, "hb-mode", 2306 "Use a hostboot like boot loader"); 2307 } 2308 2309 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2310 { \ 2311 .name = type, \ 2312 .class_init = class_initfn, \ 2313 .parent = TYPE_PNV8_CHIP, \ 2314 } 2315 2316 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2317 { \ 2318 .name = type, \ 2319 .class_init = class_initfn, \ 2320 .parent = TYPE_PNV9_CHIP, \ 2321 } 2322 2323 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2324 { \ 2325 .name = type, \ 2326 .class_init = class_initfn, \ 2327 .parent = TYPE_PNV10_CHIP, \ 2328 } 2329 2330 static const TypeInfo types[] = { 2331 { 2332 .name = MACHINE_TYPE_NAME("powernv10"), 2333 .parent = TYPE_PNV_MACHINE, 2334 .class_init = pnv_machine_power10_class_init, 2335 .interfaces = (InterfaceInfo[]) { 2336 { TYPE_XIVE_FABRIC }, 2337 { }, 2338 }, 2339 }, 2340 { 2341 .name = MACHINE_TYPE_NAME("powernv9"), 2342 .parent = TYPE_PNV_MACHINE, 2343 .class_init = pnv_machine_power9_class_init, 2344 .interfaces = (InterfaceInfo[]) { 2345 { TYPE_XIVE_FABRIC }, 2346 { }, 2347 }, 2348 }, 2349 { 2350 .name = MACHINE_TYPE_NAME("powernv8"), 2351 .parent = TYPE_PNV_MACHINE, 2352 .class_init = pnv_machine_power8_class_init, 2353 .interfaces = (InterfaceInfo[]) { 2354 { TYPE_XICS_FABRIC }, 2355 { }, 2356 }, 2357 }, 2358 { 2359 .name = TYPE_PNV_MACHINE, 2360 .parent = TYPE_MACHINE, 2361 .abstract = true, 2362 .instance_size = sizeof(PnvMachineState), 2363 .class_init = pnv_machine_class_init, 2364 .class_size = sizeof(PnvMachineClass), 2365 .interfaces = (InterfaceInfo[]) { 2366 { TYPE_INTERRUPT_STATS_PROVIDER }, 2367 { TYPE_NMI }, 2368 { }, 2369 }, 2370 }, 2371 { 2372 .name = TYPE_PNV_CHIP, 2373 .parent = TYPE_SYS_BUS_DEVICE, 2374 .class_init = pnv_chip_class_init, 2375 .instance_size = sizeof(PnvChip), 2376 .class_size = sizeof(PnvChipClass), 2377 .abstract = true, 2378 }, 2379 2380 /* 2381 * P10 chip and variants 2382 */ 2383 { 2384 .name = TYPE_PNV10_CHIP, 2385 .parent = TYPE_PNV_CHIP, 2386 .instance_init = pnv_chip_power10_instance_init, 2387 .instance_size = sizeof(Pnv10Chip), 2388 }, 2389 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2390 2391 /* 2392 * P9 chip and variants 2393 */ 2394 { 2395 .name = TYPE_PNV9_CHIP, 2396 .parent = TYPE_PNV_CHIP, 2397 .instance_init = pnv_chip_power9_instance_init, 2398 .instance_size = sizeof(Pnv9Chip), 2399 }, 2400 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2401 2402 /* 2403 * P8 chip and variants 2404 */ 2405 { 2406 .name = TYPE_PNV8_CHIP, 2407 .parent = TYPE_PNV_CHIP, 2408 .instance_init = pnv_chip_power8_instance_init, 2409 .instance_size = sizeof(Pnv8Chip), 2410 }, 2411 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2412 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2413 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2414 pnv_chip_power8nvl_class_init), 2415 }; 2416 2417 DEFINE_TYPES(types) 2418