1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/cutils.h" 25 #include "qapi/error.h" 26 #include "sysemu/qtest.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/runstate.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/device_tree.h" 33 #include "sysemu/hw_accel.h" 34 #include "target/ppc/cpu.h" 35 #include "hw/ppc/fdt.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/ppc/pnv.h" 38 #include "hw/ppc/pnv_core.h" 39 #include "hw/loader.h" 40 #include "hw/nmi.h" 41 #include "qapi/visitor.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (16 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (128 * MiB) 67 #define INITRD_LOAD_ADDR 0x28000000 68 #define INITRD_MAX_SIZE (128 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (ppc_has_spr(cpu, SPR_PURR)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 uint32_t irq; 384 char *name; 385 int node; 386 387 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 388 389 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 390 node = fdt_add_subnode(fdt, lpc_off, name); 391 _FDT(node); 392 g_free(name); 393 394 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 395 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 396 sizeof(compatible)))); 397 398 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 399 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 400 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 401 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 402 fdt_get_phandle(fdt, lpc_off)))); 403 404 /* This is needed by Linux */ 405 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 406 } 407 408 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 409 { 410 const char compatible[] = "bt\0ipmi-bt"; 411 uint32_t io_base; 412 uint32_t io_regs[] = { 413 cpu_to_be32(1), 414 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 415 cpu_to_be32(3) 416 }; 417 uint32_t irq; 418 char *name; 419 int node; 420 421 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 422 io_regs[1] = cpu_to_be32(io_base); 423 424 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 425 426 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 427 node = fdt_add_subnode(fdt, lpc_off, name); 428 _FDT(node); 429 g_free(name); 430 431 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 432 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 433 sizeof(compatible)))); 434 435 /* Mark it as reserved to avoid Linux trying to claim it */ 436 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 437 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 438 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 439 fdt_get_phandle(fdt, lpc_off)))); 440 } 441 442 typedef struct ForeachPopulateArgs { 443 void *fdt; 444 int offset; 445 } ForeachPopulateArgs; 446 447 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 448 { 449 ForeachPopulateArgs *args = opaque; 450 ISADevice *d = ISA_DEVICE(dev); 451 452 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 453 pnv_dt_rtc(d, args->fdt, args->offset); 454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 455 pnv_dt_serial(d, args->fdt, args->offset); 456 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 457 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 458 } else { 459 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 460 d->ioport_id); 461 } 462 463 return 0; 464 } 465 466 /* 467 * The default LPC bus of a multichip system is on chip 0. It's 468 * recognized by the firmware (skiboot) using a "primary" property. 469 */ 470 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 471 { 472 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 473 ForeachPopulateArgs args = { 474 .fdt = fdt, 475 .offset = isa_offset, 476 }; 477 uint32_t phandle; 478 479 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 480 481 phandle = qemu_fdt_alloc_phandle(fdt); 482 assert(phandle > 0); 483 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 484 485 /* 486 * ISA devices are not necessarily parented to the ISA bus so we 487 * can not use object_child_foreach() 488 */ 489 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 490 &args); 491 } 492 493 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 494 { 495 int off; 496 497 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 498 off = fdt_add_subnode(fdt, off, "power-mgt"); 499 500 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 501 } 502 503 static void *pnv_dt_create(MachineState *machine) 504 { 505 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 506 PnvMachineState *pnv = PNV_MACHINE(machine); 507 void *fdt; 508 char *buf; 509 int off; 510 int i; 511 512 fdt = g_malloc0(FDT_MAX_SIZE); 513 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 514 515 /* /qemu node */ 516 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 517 518 /* Root node */ 519 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 520 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 521 _FDT((fdt_setprop_string(fdt, 0, "model", 522 "IBM PowerNV (emulated by qemu)"))); 523 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 524 525 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 526 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 527 if (qemu_uuid_set) { 528 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 529 } 530 g_free(buf); 531 532 off = fdt_add_subnode(fdt, 0, "chosen"); 533 if (machine->kernel_cmdline) { 534 _FDT((fdt_setprop_string(fdt, off, "bootargs", 535 machine->kernel_cmdline))); 536 } 537 538 if (pnv->initrd_size) { 539 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 540 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 541 542 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 543 &start_prop, sizeof(start_prop)))); 544 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 545 &end_prop, sizeof(end_prop)))); 546 } 547 548 /* Populate device tree for each chip */ 549 for (i = 0; i < pnv->num_chips; i++) { 550 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 551 } 552 553 /* Populate ISA devices on chip 0 */ 554 pnv_dt_isa(pnv, fdt); 555 556 if (pnv->bmc) { 557 pnv_dt_bmc_sensors(pnv->bmc, fdt); 558 } 559 560 /* Create an extra node for power management on machines that support it */ 561 if (pmc->dt_power_mgt) { 562 pmc->dt_power_mgt(pnv, fdt); 563 } 564 565 return fdt; 566 } 567 568 static void pnv_powerdown_notify(Notifier *n, void *opaque) 569 { 570 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 571 572 if (pnv->bmc) { 573 pnv_bmc_powerdown(pnv->bmc); 574 } 575 } 576 577 static void pnv_reset(MachineState *machine) 578 { 579 PnvMachineState *pnv = PNV_MACHINE(machine); 580 IPMIBmc *bmc; 581 void *fdt; 582 583 qemu_devices_reset(); 584 585 /* 586 * The machine should provide by default an internal BMC simulator. 587 * If not, try to use the BMC device that was provided on the command 588 * line. 589 */ 590 bmc = pnv_bmc_find(&error_fatal); 591 if (!pnv->bmc) { 592 if (!bmc) { 593 if (!qtest_enabled()) { 594 warn_report("machine has no BMC device. Use '-device " 595 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 596 "to define one"); 597 } 598 } else { 599 pnv_bmc_set_pnor(bmc, pnv->pnor); 600 pnv->bmc = bmc; 601 } 602 } 603 604 fdt = pnv_dt_create(machine); 605 606 /* Pack resulting tree */ 607 _FDT((fdt_pack(fdt))); 608 609 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 610 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 611 612 g_free(fdt); 613 } 614 615 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 616 { 617 Pnv8Chip *chip8 = PNV8_CHIP(chip); 618 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 619 } 620 621 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 622 { 623 Pnv8Chip *chip8 = PNV8_CHIP(chip); 624 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 625 } 626 627 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 628 { 629 Pnv9Chip *chip9 = PNV9_CHIP(chip); 630 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 631 } 632 633 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 634 { 635 Pnv10Chip *chip10 = PNV10_CHIP(chip); 636 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 637 } 638 639 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 640 { 641 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 642 } 643 644 static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaque) 645 { 646 Monitor *mon = opaque; 647 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 648 649 if (phb3) { 650 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 651 ics_pic_print_info(&phb3->lsis, mon); 652 } 653 return 0; 654 } 655 656 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 657 { 658 Pnv8Chip *chip8 = PNV8_CHIP(chip); 659 660 ics_pic_print_info(&chip8->psi.ics, mon); 661 object_child_foreach(OBJECT(chip), 662 pnv_chip_power8_pic_print_info_child, mon); 663 } 664 665 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 666 { 667 Monitor *mon = opaque; 668 PnvPHB4 *phb4 = (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4); 669 670 if (phb4) { 671 pnv_phb4_pic_print_info(phb4, mon); 672 } 673 return 0; 674 } 675 676 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 677 { 678 Pnv9Chip *chip9 = PNV9_CHIP(chip); 679 680 pnv_xive_pic_print_info(&chip9->xive, mon); 681 pnv_psi_pic_print_info(&chip9->psi, mon); 682 683 object_child_foreach_recursive(OBJECT(chip), 684 pnv_chip_power9_pic_print_info_child, mon); 685 } 686 687 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 688 uint32_t core_id) 689 { 690 return PNV_XSCOM_EX_BASE(core_id); 691 } 692 693 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 694 uint32_t core_id) 695 { 696 return PNV9_XSCOM_EC_BASE(core_id); 697 } 698 699 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 700 uint32_t core_id) 701 { 702 return PNV10_XSCOM_EC_BASE(core_id); 703 } 704 705 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 706 { 707 PowerPCCPUClass *ppc_default = 708 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 709 PowerPCCPUClass *ppc = 710 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 711 712 return ppc_default->pvr_match(ppc_default, ppc->pvr); 713 } 714 715 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 716 { 717 ISADevice *dev = isa_new("isa-ipmi-bt"); 718 719 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 720 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 721 isa_realize_and_unref(dev, bus, &error_fatal); 722 } 723 724 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 725 { 726 Pnv10Chip *chip10 = PNV10_CHIP(chip); 727 728 pnv_psi_pic_print_info(&chip10->psi, mon); 729 } 730 731 /* Always give the first 1GB to chip 0 else we won't boot */ 732 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 733 { 734 MachineState *machine = MACHINE(pnv); 735 uint64_t ram_per_chip; 736 737 assert(machine->ram_size >= 1 * GiB); 738 739 ram_per_chip = machine->ram_size / pnv->num_chips; 740 if (ram_per_chip >= 1 * GiB) { 741 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 742 } 743 744 assert(pnv->num_chips > 1); 745 746 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 747 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 748 } 749 750 static void pnv_init(MachineState *machine) 751 { 752 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 753 PnvMachineState *pnv = PNV_MACHINE(machine); 754 MachineClass *mc = MACHINE_GET_CLASS(machine); 755 char *fw_filename; 756 long fw_size; 757 uint64_t chip_ram_start = 0; 758 int i; 759 char *chip_typename; 760 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 761 DeviceState *dev; 762 763 if (kvm_enabled()) { 764 error_report("The powernv machine does not work with KVM acceleration"); 765 exit(EXIT_FAILURE); 766 } 767 768 /* allocate RAM */ 769 if (machine->ram_size < mc->default_ram_size) { 770 char *sz = size_to_str(mc->default_ram_size); 771 error_report("Invalid RAM size, should be bigger than %s", sz); 772 g_free(sz); 773 exit(EXIT_FAILURE); 774 } 775 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 776 777 /* 778 * Create our simple PNOR device 779 */ 780 dev = qdev_new(TYPE_PNV_PNOR); 781 if (pnor) { 782 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 783 } 784 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 785 pnv->pnor = PNV_PNOR(dev); 786 787 /* load skiboot firmware */ 788 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 789 if (!fw_filename) { 790 error_report("Could not find OPAL firmware '%s'", bios_name); 791 exit(1); 792 } 793 794 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 795 if (fw_size < 0) { 796 error_report("Could not load OPAL firmware '%s'", fw_filename); 797 exit(1); 798 } 799 g_free(fw_filename); 800 801 /* load kernel */ 802 if (machine->kernel_filename) { 803 long kernel_size; 804 805 kernel_size = load_image_targphys(machine->kernel_filename, 806 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 807 if (kernel_size < 0) { 808 error_report("Could not load kernel '%s'", 809 machine->kernel_filename); 810 exit(1); 811 } 812 } 813 814 /* load initrd */ 815 if (machine->initrd_filename) { 816 pnv->initrd_base = INITRD_LOAD_ADDR; 817 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 818 pnv->initrd_base, INITRD_MAX_SIZE); 819 if (pnv->initrd_size < 0) { 820 error_report("Could not load initial ram disk '%s'", 821 machine->initrd_filename); 822 exit(1); 823 } 824 } 825 826 /* MSIs are supported on this platform */ 827 msi_nonbroken = true; 828 829 /* 830 * Check compatibility of the specified CPU with the machine 831 * default. 832 */ 833 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 834 error_report("invalid CPU model '%s' for %s machine", 835 machine->cpu_type, mc->name); 836 exit(1); 837 } 838 839 /* Create the processor chips */ 840 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 841 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 842 i, machine->cpu_type); 843 if (!object_class_by_name(chip_typename)) { 844 error_report("invalid chip model '%.*s' for %s machine", 845 i, machine->cpu_type, mc->name); 846 exit(1); 847 } 848 849 pnv->num_chips = 850 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 851 /* 852 * TODO: should we decide on how many chips we can create based 853 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 854 */ 855 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 856 error_report("invalid number of chips: '%d'", pnv->num_chips); 857 error_printf( 858 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 859 exit(1); 860 } 861 862 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 863 for (i = 0; i < pnv->num_chips; i++) { 864 char chip_name[32]; 865 Object *chip = OBJECT(qdev_new(chip_typename)); 866 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 867 868 pnv->chips[i] = PNV_CHIP(chip); 869 870 /* Distribute RAM among the chips */ 871 object_property_set_int(chip, "ram-start", chip_ram_start, 872 &error_fatal); 873 object_property_set_int(chip, "ram-size", chip_ram_size, 874 &error_fatal); 875 chip_ram_start += chip_ram_size; 876 877 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 878 object_property_add_child(OBJECT(pnv), chip_name, chip); 879 object_property_set_int(chip, "chip-id", i, &error_fatal); 880 object_property_set_int(chip, "nr-cores", machine->smp.cores, 881 &error_fatal); 882 object_property_set_int(chip, "nr-threads", machine->smp.threads, 883 &error_fatal); 884 /* 885 * The POWER8 machine use the XICS interrupt interface. 886 * Propagate the XICS fabric to the chip and its controllers. 887 */ 888 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 889 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 890 } 891 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 892 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 893 &error_abort); 894 } 895 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 896 } 897 g_free(chip_typename); 898 899 /* Instantiate ISA bus on chip 0 */ 900 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 901 902 /* Create serial port */ 903 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 904 905 /* Create an RTC ISA device too */ 906 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 907 908 /* 909 * Create the machine BMC simulator and the IPMI BT device for 910 * communication with the BMC 911 */ 912 if (defaults_enabled()) { 913 pnv->bmc = pnv_bmc_create(pnv->pnor); 914 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 915 } 916 917 /* 918 * The PNOR is mapped on the LPC FW address space by the BMC. 919 * Since we can not reach the remote BMC machine with LPC memops, 920 * map it always for now. 921 */ 922 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 923 &pnv->pnor->mmio); 924 925 /* 926 * OpenPOWER systems use a IPMI SEL Event message to notify the 927 * host to powerdown 928 */ 929 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 930 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 931 } 932 933 /* 934 * 0:21 Reserved - Read as zeros 935 * 22:24 Chip ID 936 * 25:28 Core number 937 * 29:31 Thread ID 938 */ 939 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 940 { 941 return (chip->chip_id << 7) | (core_id << 3); 942 } 943 944 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 945 Error **errp) 946 { 947 Pnv8Chip *chip8 = PNV8_CHIP(chip); 948 Error *local_err = NULL; 949 Object *obj; 950 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 951 952 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 953 if (local_err) { 954 error_propagate(errp, local_err); 955 return; 956 } 957 958 pnv_cpu->intc = obj; 959 } 960 961 962 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 963 { 964 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 965 966 icp_reset(ICP(pnv_cpu->intc)); 967 } 968 969 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 970 { 971 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 972 973 icp_destroy(ICP(pnv_cpu->intc)); 974 pnv_cpu->intc = NULL; 975 } 976 977 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 978 Monitor *mon) 979 { 980 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 981 } 982 983 /* 984 * 0:48 Reserved - Read as zeroes 985 * 49:52 Node ID 986 * 53:55 Chip ID 987 * 56 Reserved - Read as zero 988 * 57:61 Core number 989 * 62:63 Thread ID 990 * 991 * We only care about the lower bits. uint32_t is fine for the moment. 992 */ 993 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 994 { 995 return (chip->chip_id << 8) | (core_id << 2); 996 } 997 998 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 999 { 1000 return (chip->chip_id << 8) | (core_id << 2); 1001 } 1002 1003 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1004 Error **errp) 1005 { 1006 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1007 Error *local_err = NULL; 1008 Object *obj; 1009 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1010 1011 /* 1012 * The core creates its interrupt presenter but the XIVE interrupt 1013 * controller object is initialized afterwards. Hopefully, it's 1014 * only used at runtime. 1015 */ 1016 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1017 &local_err); 1018 if (local_err) { 1019 error_propagate(errp, local_err); 1020 return; 1021 } 1022 1023 pnv_cpu->intc = obj; 1024 } 1025 1026 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1027 { 1028 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1029 1030 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1031 } 1032 1033 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1034 { 1035 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1036 1037 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1038 pnv_cpu->intc = NULL; 1039 } 1040 1041 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1042 Monitor *mon) 1043 { 1044 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1045 } 1046 1047 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1048 Error **errp) 1049 { 1050 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1051 1052 /* Will be defined when the interrupt controller is */ 1053 pnv_cpu->intc = NULL; 1054 } 1055 1056 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1057 { 1058 ; 1059 } 1060 1061 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1062 { 1063 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1064 1065 pnv_cpu->intc = NULL; 1066 } 1067 1068 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1069 Monitor *mon) 1070 { 1071 } 1072 1073 /* 1074 * Allowed core identifiers on a POWER8 Processor Chip : 1075 * 1076 * <EX0 reserved> 1077 * EX1 - Venice only 1078 * EX2 - Venice only 1079 * EX3 - Venice only 1080 * EX4 1081 * EX5 1082 * EX6 1083 * <EX7,8 reserved> <reserved> 1084 * EX9 - Venice only 1085 * EX10 - Venice only 1086 * EX11 - Venice only 1087 * EX12 1088 * EX13 1089 * EX14 1090 * <EX15 reserved> 1091 */ 1092 #define POWER8E_CORE_MASK (0x7070ull) 1093 #define POWER8_CORE_MASK (0x7e7eull) 1094 1095 /* 1096 * POWER9 has 24 cores, ids starting at 0x0 1097 */ 1098 #define POWER9_CORE_MASK (0xffffffffffffffull) 1099 1100 1101 #define POWER10_CORE_MASK (0xffffffffffffffull) 1102 1103 static void pnv_chip_power8_instance_init(Object *obj) 1104 { 1105 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1106 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1107 int i; 1108 1109 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1110 (Object **)&chip8->xics, 1111 object_property_allow_set_link, 1112 OBJ_PROP_LINK_STRONG); 1113 1114 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1115 1116 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1117 1118 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1119 1120 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1121 1122 if (defaults_enabled()) { 1123 chip8->num_phbs = pcc->num_phbs; 1124 } 1125 1126 for (i = 0; i < chip8->num_phbs; i++) { 1127 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1128 } 1129 1130 } 1131 1132 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1133 { 1134 PnvChip *chip = PNV_CHIP(chip8); 1135 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1136 int i, j; 1137 char *name; 1138 1139 name = g_strdup_printf("icp-%x", chip->chip_id); 1140 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1141 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1142 g_free(name); 1143 1144 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1145 1146 /* Map the ICP registers for each thread */ 1147 for (i = 0; i < chip->nr_cores; i++) { 1148 PnvCore *pnv_core = chip->cores[i]; 1149 int core_hwid = CPU_CORE(pnv_core)->core_id; 1150 1151 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1152 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1153 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1154 1155 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1156 &icp->mmio); 1157 } 1158 } 1159 } 1160 1161 /* Attach a root port device */ 1162 void pnv_phb_attach_root_port(PCIHostState *pci, const char *name) 1163 { 1164 PCIDevice *root = pci_new(PCI_DEVFN(0, 0), name); 1165 1166 pci_realize_and_unref(root, pci->bus, &error_fatal); 1167 } 1168 1169 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1170 { 1171 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1172 PnvChip *chip = PNV_CHIP(dev); 1173 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1174 Pnv8Psi *psi8 = &chip8->psi; 1175 Error *local_err = NULL; 1176 int i; 1177 1178 assert(chip8->xics); 1179 1180 /* XSCOM bridge is first */ 1181 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1182 if (local_err) { 1183 error_propagate(errp, local_err); 1184 return; 1185 } 1186 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1187 1188 pcc->parent_realize(dev, &local_err); 1189 if (local_err) { 1190 error_propagate(errp, local_err); 1191 return; 1192 } 1193 1194 /* Processor Service Interface (PSI) Host Bridge */ 1195 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1196 &error_fatal); 1197 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1198 OBJECT(chip8->xics), &error_abort); 1199 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1200 return; 1201 } 1202 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1203 &PNV_PSI(psi8)->xscom_regs); 1204 1205 /* Create LPC controller */ 1206 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1207 &error_abort); 1208 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1209 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1210 1211 chip->fw_mr = &chip8->lpc.isa_fw; 1212 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1213 (uint64_t) PNV_XSCOM_BASE(chip), 1214 PNV_XSCOM_LPC_BASE); 1215 1216 /* 1217 * Interrupt Management Area. This is the memory region holding 1218 * all the Interrupt Control Presenter (ICP) registers 1219 */ 1220 pnv_chip_icp_realize(chip8, &local_err); 1221 if (local_err) { 1222 error_propagate(errp, local_err); 1223 return; 1224 } 1225 1226 /* Create the simplified OCC model */ 1227 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1228 &error_abort); 1229 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1230 return; 1231 } 1232 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1233 1234 /* OCC SRAM model */ 1235 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1236 &chip8->occ.sram_regs); 1237 1238 /* HOMER */ 1239 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1240 &error_abort); 1241 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1242 return; 1243 } 1244 /* Homer Xscom region */ 1245 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1246 1247 /* Homer mmio region */ 1248 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1249 &chip8->homer.regs); 1250 1251 /* PHB3 controllers */ 1252 for (i = 0; i < chip8->num_phbs; i++) { 1253 PnvPHB3 *phb = &chip8->phbs[i]; 1254 1255 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1256 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1257 &error_fatal); 1258 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1259 &error_fatal); 1260 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1261 return; 1262 } 1263 } 1264 } 1265 1266 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1267 { 1268 addr &= (PNV_XSCOM_SIZE - 1); 1269 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1270 } 1271 1272 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1273 { 1274 DeviceClass *dc = DEVICE_CLASS(klass); 1275 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1276 1277 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1278 k->cores_mask = POWER8E_CORE_MASK; 1279 k->num_phbs = 3; 1280 k->core_pir = pnv_chip_core_pir_p8; 1281 k->intc_create = pnv_chip_power8_intc_create; 1282 k->intc_reset = pnv_chip_power8_intc_reset; 1283 k->intc_destroy = pnv_chip_power8_intc_destroy; 1284 k->intc_print_info = pnv_chip_power8_intc_print_info; 1285 k->isa_create = pnv_chip_power8_isa_create; 1286 k->dt_populate = pnv_chip_power8_dt_populate; 1287 k->pic_print_info = pnv_chip_power8_pic_print_info; 1288 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1289 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1290 dc->desc = "PowerNV Chip POWER8E"; 1291 1292 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1293 &k->parent_realize); 1294 } 1295 1296 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1297 { 1298 DeviceClass *dc = DEVICE_CLASS(klass); 1299 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1300 1301 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1302 k->cores_mask = POWER8_CORE_MASK; 1303 k->num_phbs = 3; 1304 k->core_pir = pnv_chip_core_pir_p8; 1305 k->intc_create = pnv_chip_power8_intc_create; 1306 k->intc_reset = pnv_chip_power8_intc_reset; 1307 k->intc_destroy = pnv_chip_power8_intc_destroy; 1308 k->intc_print_info = pnv_chip_power8_intc_print_info; 1309 k->isa_create = pnv_chip_power8_isa_create; 1310 k->dt_populate = pnv_chip_power8_dt_populate; 1311 k->pic_print_info = pnv_chip_power8_pic_print_info; 1312 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1313 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1314 dc->desc = "PowerNV Chip POWER8"; 1315 1316 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1317 &k->parent_realize); 1318 } 1319 1320 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1321 { 1322 DeviceClass *dc = DEVICE_CLASS(klass); 1323 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1324 1325 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1326 k->cores_mask = POWER8_CORE_MASK; 1327 k->num_phbs = 4; 1328 k->core_pir = pnv_chip_core_pir_p8; 1329 k->intc_create = pnv_chip_power8_intc_create; 1330 k->intc_reset = pnv_chip_power8_intc_reset; 1331 k->intc_destroy = pnv_chip_power8_intc_destroy; 1332 k->intc_print_info = pnv_chip_power8_intc_print_info; 1333 k->isa_create = pnv_chip_power8nvl_isa_create; 1334 k->dt_populate = pnv_chip_power8_dt_populate; 1335 k->pic_print_info = pnv_chip_power8_pic_print_info; 1336 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1337 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1338 dc->desc = "PowerNV Chip POWER8NVL"; 1339 1340 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1341 &k->parent_realize); 1342 } 1343 1344 static void pnv_chip_power9_instance_init(Object *obj) 1345 { 1346 PnvChip *chip = PNV_CHIP(obj); 1347 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1348 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1349 int i; 1350 1351 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1352 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1353 "xive-fabric"); 1354 1355 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1356 1357 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1358 1359 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1360 1361 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1362 1363 /* Number of PECs is the chip default */ 1364 chip->num_pecs = pcc->num_pecs; 1365 1366 for (i = 0; i < chip->num_pecs; i++) { 1367 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1368 TYPE_PNV_PHB4_PEC); 1369 } 1370 } 1371 1372 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1373 { 1374 PnvChip *chip = PNV_CHIP(chip9); 1375 int i; 1376 1377 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1378 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1379 1380 for (i = 0; i < chip9->nr_quads; i++) { 1381 char eq_name[32]; 1382 PnvQuad *eq = &chip9->quads[i]; 1383 PnvCore *pnv_core = chip->cores[i * 4]; 1384 int core_id = CPU_CORE(pnv_core)->core_id; 1385 1386 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1387 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1388 sizeof(*eq), TYPE_PNV_QUAD, 1389 &error_fatal, NULL); 1390 1391 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1392 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1393 1394 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1395 &eq->xscom_regs); 1396 } 1397 } 1398 1399 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1400 { 1401 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1402 int i; 1403 1404 for (i = 0; i < chip->num_pecs; i++) { 1405 PnvPhb4PecState *pec = &chip9->pecs[i]; 1406 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1407 uint32_t pec_nest_base; 1408 uint32_t pec_pci_base; 1409 1410 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1411 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1412 &error_fatal); 1413 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1414 &error_fatal); 1415 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1416 return; 1417 } 1418 1419 pec_nest_base = pecc->xscom_nest_base(pec); 1420 pec_pci_base = pecc->xscom_pci_base(pec); 1421 1422 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1423 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1424 } 1425 } 1426 1427 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1428 { 1429 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1430 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1431 PnvChip *chip = PNV_CHIP(dev); 1432 Pnv9Psi *psi9 = &chip9->psi; 1433 Error *local_err = NULL; 1434 1435 /* XSCOM bridge is first */ 1436 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1437 if (local_err) { 1438 error_propagate(errp, local_err); 1439 return; 1440 } 1441 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1442 1443 pcc->parent_realize(dev, &local_err); 1444 if (local_err) { 1445 error_propagate(errp, local_err); 1446 return; 1447 } 1448 1449 pnv_chip_quad_realize(chip9, &local_err); 1450 if (local_err) { 1451 error_propagate(errp, local_err); 1452 return; 1453 } 1454 1455 /* XIVE interrupt controller (POWER9) */ 1456 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1457 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1458 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1459 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1460 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1461 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1462 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1463 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1464 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1465 &error_abort); 1466 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1467 return; 1468 } 1469 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1470 &chip9->xive.xscom_regs); 1471 1472 /* Processor Service Interface (PSI) Host Bridge */ 1473 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1474 &error_fatal); 1475 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1476 return; 1477 } 1478 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1479 &PNV_PSI(psi9)->xscom_regs); 1480 1481 /* LPC */ 1482 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1483 &error_abort); 1484 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1485 return; 1486 } 1487 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1488 &chip9->lpc.xscom_regs); 1489 1490 chip->fw_mr = &chip9->lpc.isa_fw; 1491 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1492 (uint64_t) PNV9_LPCM_BASE(chip)); 1493 1494 /* Create the simplified OCC model */ 1495 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1496 &error_abort); 1497 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1498 return; 1499 } 1500 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1501 1502 /* OCC SRAM model */ 1503 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1504 &chip9->occ.sram_regs); 1505 1506 /* HOMER */ 1507 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1508 &error_abort); 1509 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1510 return; 1511 } 1512 /* Homer Xscom region */ 1513 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1514 1515 /* Homer mmio region */ 1516 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1517 &chip9->homer.regs); 1518 1519 /* PEC PHBs */ 1520 pnv_chip_power9_pec_realize(chip, &local_err); 1521 if (local_err) { 1522 error_propagate(errp, local_err); 1523 return; 1524 } 1525 } 1526 1527 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1528 { 1529 addr &= (PNV9_XSCOM_SIZE - 1); 1530 return addr >> 3; 1531 } 1532 1533 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1534 { 1535 DeviceClass *dc = DEVICE_CLASS(klass); 1536 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1537 1538 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1539 k->cores_mask = POWER9_CORE_MASK; 1540 k->core_pir = pnv_chip_core_pir_p9; 1541 k->intc_create = pnv_chip_power9_intc_create; 1542 k->intc_reset = pnv_chip_power9_intc_reset; 1543 k->intc_destroy = pnv_chip_power9_intc_destroy; 1544 k->intc_print_info = pnv_chip_power9_intc_print_info; 1545 k->isa_create = pnv_chip_power9_isa_create; 1546 k->dt_populate = pnv_chip_power9_dt_populate; 1547 k->pic_print_info = pnv_chip_power9_pic_print_info; 1548 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1549 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1550 dc->desc = "PowerNV Chip POWER9"; 1551 k->num_pecs = PNV9_CHIP_MAX_PEC; 1552 1553 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1554 &k->parent_realize); 1555 } 1556 1557 static void pnv_chip_power10_instance_init(Object *obj) 1558 { 1559 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1560 1561 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1562 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1563 } 1564 1565 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1566 { 1567 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1568 PnvChip *chip = PNV_CHIP(dev); 1569 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1570 Error *local_err = NULL; 1571 1572 /* XSCOM bridge is first */ 1573 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1574 if (local_err) { 1575 error_propagate(errp, local_err); 1576 return; 1577 } 1578 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1579 1580 pcc->parent_realize(dev, &local_err); 1581 if (local_err) { 1582 error_propagate(errp, local_err); 1583 return; 1584 } 1585 1586 /* Processor Service Interface (PSI) Host Bridge */ 1587 object_property_set_int(OBJECT(&chip10->psi), "bar", 1588 PNV10_PSIHB_BASE(chip), &error_fatal); 1589 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1590 return; 1591 } 1592 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1593 &PNV_PSI(&chip10->psi)->xscom_regs); 1594 1595 /* LPC */ 1596 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1597 OBJECT(&chip10->psi), &error_abort); 1598 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1599 return; 1600 } 1601 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1602 &chip10->lpc.xscom_regs); 1603 1604 chip->fw_mr = &chip10->lpc.isa_fw; 1605 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1606 (uint64_t) PNV10_LPCM_BASE(chip)); 1607 } 1608 1609 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1610 { 1611 addr &= (PNV10_XSCOM_SIZE - 1); 1612 return addr >> 3; 1613 } 1614 1615 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1616 { 1617 DeviceClass *dc = DEVICE_CLASS(klass); 1618 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1619 1620 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1621 k->cores_mask = POWER10_CORE_MASK; 1622 k->core_pir = pnv_chip_core_pir_p10; 1623 k->intc_create = pnv_chip_power10_intc_create; 1624 k->intc_reset = pnv_chip_power10_intc_reset; 1625 k->intc_destroy = pnv_chip_power10_intc_destroy; 1626 k->intc_print_info = pnv_chip_power10_intc_print_info; 1627 k->isa_create = pnv_chip_power10_isa_create; 1628 k->dt_populate = pnv_chip_power10_dt_populate; 1629 k->pic_print_info = pnv_chip_power10_pic_print_info; 1630 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1631 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1632 dc->desc = "PowerNV Chip POWER10"; 1633 1634 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1635 &k->parent_realize); 1636 } 1637 1638 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1639 { 1640 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1641 int cores_max; 1642 1643 /* 1644 * No custom mask for this chip, let's use the default one from * 1645 * the chip class 1646 */ 1647 if (!chip->cores_mask) { 1648 chip->cores_mask = pcc->cores_mask; 1649 } 1650 1651 /* filter alien core ids ! some are reserved */ 1652 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1653 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1654 chip->cores_mask); 1655 return; 1656 } 1657 chip->cores_mask &= pcc->cores_mask; 1658 1659 /* now that we have a sane layout, let check the number of cores */ 1660 cores_max = ctpop64(chip->cores_mask); 1661 if (chip->nr_cores > cores_max) { 1662 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1663 cores_max); 1664 return; 1665 } 1666 } 1667 1668 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1669 { 1670 Error *error = NULL; 1671 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1672 const char *typename = pnv_chip_core_typename(chip); 1673 int i, core_hwid; 1674 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1675 1676 if (!object_class_by_name(typename)) { 1677 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1678 return; 1679 } 1680 1681 /* Cores */ 1682 pnv_chip_core_sanitize(chip, &error); 1683 if (error) { 1684 error_propagate(errp, error); 1685 return; 1686 } 1687 1688 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1689 1690 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1691 && (i < chip->nr_cores); core_hwid++) { 1692 char core_name[32]; 1693 PnvCore *pnv_core; 1694 uint64_t xscom_core_base; 1695 1696 if (!(chip->cores_mask & (1ull << core_hwid))) { 1697 continue; 1698 } 1699 1700 pnv_core = PNV_CORE(object_new(typename)); 1701 1702 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1703 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1704 chip->cores[i] = pnv_core; 1705 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1706 chip->nr_threads, &error_fatal); 1707 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1708 core_hwid, &error_fatal); 1709 object_property_set_int(OBJECT(pnv_core), "pir", 1710 pcc->core_pir(chip, core_hwid), &error_fatal); 1711 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1712 &error_fatal); 1713 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1714 &error_abort); 1715 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1716 1717 /* Each core has an XSCOM MMIO region */ 1718 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1719 1720 pnv_xscom_add_subregion(chip, xscom_core_base, 1721 &pnv_core->xscom_regs); 1722 i++; 1723 } 1724 } 1725 1726 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1727 { 1728 PnvChip *chip = PNV_CHIP(dev); 1729 Error *error = NULL; 1730 1731 /* Cores */ 1732 pnv_chip_core_realize(chip, &error); 1733 if (error) { 1734 error_propagate(errp, error); 1735 return; 1736 } 1737 } 1738 1739 static Property pnv_chip_properties[] = { 1740 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1741 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1742 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1743 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1744 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1745 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1746 DEFINE_PROP_END_OF_LIST(), 1747 }; 1748 1749 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1750 { 1751 DeviceClass *dc = DEVICE_CLASS(klass); 1752 1753 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1754 dc->realize = pnv_chip_realize; 1755 device_class_set_props(dc, pnv_chip_properties); 1756 dc->desc = "PowerNV Chip"; 1757 } 1758 1759 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1760 { 1761 int i, j; 1762 1763 for (i = 0; i < chip->nr_cores; i++) { 1764 PnvCore *pc = chip->cores[i]; 1765 CPUCore *cc = CPU_CORE(pc); 1766 1767 for (j = 0; j < cc->nr_threads; j++) { 1768 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1769 return pc->threads[j]; 1770 } 1771 } 1772 } 1773 return NULL; 1774 } 1775 1776 typedef struct ForeachPhb3Args { 1777 int irq; 1778 ICSState *ics; 1779 } ForeachPhb3Args; 1780 1781 static int pnv_ics_get_child(Object *child, void *opaque) 1782 { 1783 ForeachPhb3Args *args = opaque; 1784 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 1785 1786 if (phb3) { 1787 if (ics_valid_irq(&phb3->lsis, args->irq)) { 1788 args->ics = &phb3->lsis; 1789 } 1790 if (ics_valid_irq(ICS(&phb3->msis), args->irq)) { 1791 args->ics = ICS(&phb3->msis); 1792 } 1793 } 1794 return args->ics ? 1 : 0; 1795 } 1796 1797 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1798 { 1799 PnvMachineState *pnv = PNV_MACHINE(xi); 1800 ForeachPhb3Args args = { irq, NULL }; 1801 int i; 1802 1803 for (i = 0; i < pnv->num_chips; i++) { 1804 PnvChip *chip = pnv->chips[i]; 1805 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1806 1807 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1808 return &chip8->psi.ics; 1809 } 1810 1811 object_child_foreach(OBJECT(chip), pnv_ics_get_child, &args); 1812 if (args.ics) { 1813 return args.ics; 1814 } 1815 } 1816 return NULL; 1817 } 1818 1819 void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index) 1820 { 1821 Object *parent = OBJECT(chip); 1822 g_autofree char *default_id = 1823 g_strdup_printf("%s[%d]", object_get_typename(obj), index); 1824 1825 if (obj->parent == parent) { 1826 return; 1827 } 1828 1829 object_ref(obj); 1830 object_unparent(obj); 1831 object_property_add_child( 1832 parent, DEVICE(obj)->id ? DEVICE(obj)->id : default_id, obj); 1833 object_unref(obj); 1834 } 1835 1836 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 1837 { 1838 int i; 1839 1840 for (i = 0; i < pnv->num_chips; i++) { 1841 PnvChip *chip = pnv->chips[i]; 1842 if (chip->chip_id == chip_id) { 1843 return chip; 1844 } 1845 } 1846 return NULL; 1847 } 1848 1849 static int pnv_ics_resend_child(Object *child, void *opaque) 1850 { 1851 PnvPHB3 *phb3 = (PnvPHB3 *) object_dynamic_cast(child, TYPE_PNV_PHB3); 1852 1853 if (phb3) { 1854 ics_resend(&phb3->lsis); 1855 ics_resend(ICS(&phb3->msis)); 1856 } 1857 return 0; 1858 } 1859 1860 static void pnv_ics_resend(XICSFabric *xi) 1861 { 1862 PnvMachineState *pnv = PNV_MACHINE(xi); 1863 int i; 1864 1865 for (i = 0; i < pnv->num_chips; i++) { 1866 PnvChip *chip = pnv->chips[i]; 1867 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1868 1869 ics_resend(&chip8->psi.ics); 1870 object_child_foreach(OBJECT(chip), pnv_ics_resend_child, NULL); 1871 } 1872 } 1873 1874 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1875 { 1876 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1877 1878 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1879 } 1880 1881 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1882 Monitor *mon) 1883 { 1884 PnvMachineState *pnv = PNV_MACHINE(obj); 1885 int i; 1886 CPUState *cs; 1887 1888 CPU_FOREACH(cs) { 1889 PowerPCCPU *cpu = POWERPC_CPU(cs); 1890 1891 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1892 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1893 mon); 1894 } 1895 1896 for (i = 0; i < pnv->num_chips; i++) { 1897 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1898 } 1899 } 1900 1901 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1902 uint8_t nvt_blk, uint32_t nvt_idx, 1903 bool cam_ignore, uint8_t priority, 1904 uint32_t logic_serv, 1905 XiveTCTXMatch *match) 1906 { 1907 PnvMachineState *pnv = PNV_MACHINE(xfb); 1908 int total_count = 0; 1909 int i; 1910 1911 for (i = 0; i < pnv->num_chips; i++) { 1912 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1913 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1914 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1915 int count; 1916 1917 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1918 priority, logic_serv, match); 1919 1920 if (count < 0) { 1921 return count; 1922 } 1923 1924 total_count += count; 1925 } 1926 1927 return total_count; 1928 } 1929 1930 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1931 { 1932 MachineClass *mc = MACHINE_CLASS(oc); 1933 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1934 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1935 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1936 1937 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1938 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1939 1940 xic->icp_get = pnv_icp_get; 1941 xic->ics_get = pnv_ics_get; 1942 xic->ics_resend = pnv_ics_resend; 1943 1944 pmc->compat = compat; 1945 pmc->compat_size = sizeof(compat); 1946 1947 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB3); 1948 } 1949 1950 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1951 { 1952 MachineClass *mc = MACHINE_CLASS(oc); 1953 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1954 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1955 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1956 1957 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1958 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1959 xfc->match_nvt = pnv_match_nvt; 1960 1961 mc->alias = "powernv"; 1962 1963 pmc->compat = compat; 1964 pmc->compat_size = sizeof(compat); 1965 pmc->dt_power_mgt = pnv_dt_power_mgt; 1966 1967 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB4); 1968 } 1969 1970 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1971 { 1972 MachineClass *mc = MACHINE_CLASS(oc); 1973 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1974 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1975 1976 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1977 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 1978 1979 pmc->compat = compat; 1980 pmc->compat_size = sizeof(compat); 1981 pmc->dt_power_mgt = pnv_dt_power_mgt; 1982 } 1983 1984 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1985 { 1986 PnvMachineState *pnv = PNV_MACHINE(obj); 1987 1988 return !!pnv->fw_load_addr; 1989 } 1990 1991 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1992 { 1993 PnvMachineState *pnv = PNV_MACHINE(obj); 1994 1995 if (value) { 1996 pnv->fw_load_addr = 0x8000000; 1997 } 1998 } 1999 2000 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2001 { 2002 PowerPCCPU *cpu = POWERPC_CPU(cs); 2003 CPUPPCState *env = &cpu->env; 2004 2005 cpu_synchronize_state(cs); 2006 ppc_cpu_do_system_reset(cs); 2007 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2008 /* 2009 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2010 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2011 * (PPC_BIT(43)). 2012 */ 2013 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2014 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2015 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2016 } 2017 } else { 2018 /* 2019 * For non-powersave system resets, SRR1[42:45] are defined to be 2020 * implementation-dependent. The POWER9 User Manual specifies that 2021 * an external (SCOM driven, which may come from a BMC nmi command or 2022 * another CPU requesting a NMI IPI) system reset exception should be 2023 * 0b0010 (PPC_BIT(44)). 2024 */ 2025 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2026 } 2027 } 2028 2029 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2030 { 2031 CPUState *cs; 2032 2033 CPU_FOREACH(cs) { 2034 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2035 } 2036 } 2037 2038 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2039 { 2040 MachineClass *mc = MACHINE_CLASS(oc); 2041 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2042 NMIClass *nc = NMI_CLASS(oc); 2043 2044 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2045 mc->init = pnv_init; 2046 mc->reset = pnv_reset; 2047 mc->max_cpus = MAX_CPUS; 2048 /* Pnv provides a AHCI device for storage */ 2049 mc->block_default_type = IF_IDE; 2050 mc->no_parallel = 1; 2051 mc->default_boot_order = NULL; 2052 /* 2053 * RAM defaults to less than 2048 for 32-bit hosts, and large 2054 * enough to fit the maximum initrd size at it's load address 2055 */ 2056 mc->default_ram_size = 1 * GiB; 2057 mc->default_ram_id = "pnv.ram"; 2058 ispc->print_info = pnv_pic_print_info; 2059 nc->nmi_monitor_handler = pnv_nmi; 2060 2061 object_class_property_add_bool(oc, "hb-mode", 2062 pnv_machine_get_hb, pnv_machine_set_hb); 2063 object_class_property_set_description(oc, "hb-mode", 2064 "Use a hostboot like boot loader"); 2065 } 2066 2067 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2068 { \ 2069 .name = type, \ 2070 .class_init = class_initfn, \ 2071 .parent = TYPE_PNV8_CHIP, \ 2072 } 2073 2074 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2075 { \ 2076 .name = type, \ 2077 .class_init = class_initfn, \ 2078 .parent = TYPE_PNV9_CHIP, \ 2079 } 2080 2081 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2082 { \ 2083 .name = type, \ 2084 .class_init = class_initfn, \ 2085 .parent = TYPE_PNV10_CHIP, \ 2086 } 2087 2088 static const TypeInfo types[] = { 2089 { 2090 .name = MACHINE_TYPE_NAME("powernv10"), 2091 .parent = TYPE_PNV_MACHINE, 2092 .class_init = pnv_machine_power10_class_init, 2093 }, 2094 { 2095 .name = MACHINE_TYPE_NAME("powernv9"), 2096 .parent = TYPE_PNV_MACHINE, 2097 .class_init = pnv_machine_power9_class_init, 2098 .interfaces = (InterfaceInfo[]) { 2099 { TYPE_XIVE_FABRIC }, 2100 { }, 2101 }, 2102 }, 2103 { 2104 .name = MACHINE_TYPE_NAME("powernv8"), 2105 .parent = TYPE_PNV_MACHINE, 2106 .class_init = pnv_machine_power8_class_init, 2107 .interfaces = (InterfaceInfo[]) { 2108 { TYPE_XICS_FABRIC }, 2109 { }, 2110 }, 2111 }, 2112 { 2113 .name = TYPE_PNV_MACHINE, 2114 .parent = TYPE_MACHINE, 2115 .abstract = true, 2116 .instance_size = sizeof(PnvMachineState), 2117 .class_init = pnv_machine_class_init, 2118 .class_size = sizeof(PnvMachineClass), 2119 .interfaces = (InterfaceInfo[]) { 2120 { TYPE_INTERRUPT_STATS_PROVIDER }, 2121 { TYPE_NMI }, 2122 { }, 2123 }, 2124 }, 2125 { 2126 .name = TYPE_PNV_CHIP, 2127 .parent = TYPE_SYS_BUS_DEVICE, 2128 .class_init = pnv_chip_class_init, 2129 .instance_size = sizeof(PnvChip), 2130 .class_size = sizeof(PnvChipClass), 2131 .abstract = true, 2132 }, 2133 2134 /* 2135 * P10 chip and variants 2136 */ 2137 { 2138 .name = TYPE_PNV10_CHIP, 2139 .parent = TYPE_PNV_CHIP, 2140 .instance_init = pnv_chip_power10_instance_init, 2141 .instance_size = sizeof(Pnv10Chip), 2142 }, 2143 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2144 2145 /* 2146 * P9 chip and variants 2147 */ 2148 { 2149 .name = TYPE_PNV9_CHIP, 2150 .parent = TYPE_PNV_CHIP, 2151 .instance_init = pnv_chip_power9_instance_init, 2152 .instance_size = sizeof(Pnv9Chip), 2153 }, 2154 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2155 2156 /* 2157 * P8 chip and variants 2158 */ 2159 { 2160 .name = TYPE_PNV8_CHIP, 2161 .parent = TYPE_PNV_CHIP, 2162 .instance_init = pnv_chip_power8_instance_init, 2163 .instance_size = sizeof(Pnv8Chip), 2164 }, 2165 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2166 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2167 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2168 pnv_chip_power8nvl_class_init), 2169 }; 2170 2171 DEFINE_TYPES(types) 2172