1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "sysemu/hw_accel.h" 31 #include "target/ppc/cpu.h" 32 #include "qemu/log.h" 33 #include "hw/ppc/fdt.h" 34 #include "hw/ppc/ppc.h" 35 #include "hw/ppc/pnv.h" 36 #include "hw/ppc/pnv_core.h" 37 #include "hw/loader.h" 38 #include "hw/nmi.h" 39 #include "exec/address-spaces.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 47 #include "hw/ppc/xics.h" 48 #include "hw/qdev-properties.h" 49 #include "hw/ppc/pnv_xscom.h" 50 #include "hw/ppc/pnv_pnor.h" 51 52 #include "hw/isa/isa.h" 53 #include "hw/boards.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (4 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (256 * MiB) 67 #define INITRD_LOAD_ADDR 0x60000000 68 #define INITRD_MAX_SIZE (256 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (env->spr_cb[SPR_PURR].oea_read) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 char *name; 384 int node; 385 386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 387 node = fdt_add_subnode(fdt, lpc_off, name); 388 _FDT(node); 389 g_free(name); 390 391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 392 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 393 sizeof(compatible)))); 394 395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 399 fdt_get_phandle(fdt, lpc_off)))); 400 401 /* This is needed by Linux */ 402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 403 } 404 405 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 406 { 407 const char compatible[] = "bt\0ipmi-bt"; 408 uint32_t io_base; 409 uint32_t io_regs[] = { 410 cpu_to_be32(1), 411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 412 cpu_to_be32(3) 413 }; 414 uint32_t irq; 415 char *name; 416 int node; 417 418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 419 io_regs[1] = cpu_to_be32(io_base); 420 421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 422 423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 424 node = fdt_add_subnode(fdt, lpc_off, name); 425 _FDT(node); 426 g_free(name); 427 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 429 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 430 sizeof(compatible)))); 431 432 /* Mark it as reserved to avoid Linux trying to claim it */ 433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 436 fdt_get_phandle(fdt, lpc_off)))); 437 } 438 439 typedef struct ForeachPopulateArgs { 440 void *fdt; 441 int offset; 442 } ForeachPopulateArgs; 443 444 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 445 { 446 ForeachPopulateArgs *args = opaque; 447 ISADevice *d = ISA_DEVICE(dev); 448 449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 450 pnv_dt_rtc(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 452 pnv_dt_serial(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 455 } else { 456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 457 d->ioport_id); 458 } 459 460 return 0; 461 } 462 463 /* 464 * The default LPC bus of a multichip system is on chip 0. It's 465 * recognized by the firmware (skiboot) using a "primary" property. 466 */ 467 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 468 { 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 470 ForeachPopulateArgs args = { 471 .fdt = fdt, 472 .offset = isa_offset, 473 }; 474 uint32_t phandle; 475 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 477 478 phandle = qemu_fdt_alloc_phandle(fdt); 479 assert(phandle > 0); 480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 481 482 /* 483 * ISA devices are not necessarily parented to the ISA bus so we 484 * can not use object_child_foreach() 485 */ 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 487 &args); 488 } 489 490 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 491 { 492 int off; 493 494 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 495 off = fdt_add_subnode(fdt, off, "power-mgt"); 496 497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 498 } 499 500 static void *pnv_dt_create(MachineState *machine) 501 { 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 503 PnvMachineState *pnv = PNV_MACHINE(machine); 504 void *fdt; 505 char *buf; 506 int off; 507 int i; 508 509 fdt = g_malloc0(FDT_MAX_SIZE); 510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 511 512 /* /qemu node */ 513 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 514 515 /* Root node */ 516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 518 _FDT((fdt_setprop_string(fdt, 0, "model", 519 "IBM PowerNV (emulated by qemu)"))); 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 521 522 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 524 if (qemu_uuid_set) { 525 _FDT((fdt_property_string(fdt, "system-id", buf))); 526 } 527 g_free(buf); 528 529 off = fdt_add_subnode(fdt, 0, "chosen"); 530 if (machine->kernel_cmdline) { 531 _FDT((fdt_setprop_string(fdt, off, "bootargs", 532 machine->kernel_cmdline))); 533 } 534 535 if (pnv->initrd_size) { 536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 538 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 540 &start_prop, sizeof(start_prop)))); 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 542 &end_prop, sizeof(end_prop)))); 543 } 544 545 /* Populate device tree for each chip */ 546 for (i = 0; i < pnv->num_chips; i++) { 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 548 } 549 550 /* Populate ISA devices on chip 0 */ 551 pnv_dt_isa(pnv, fdt); 552 553 if (pnv->bmc) { 554 pnv_dt_bmc_sensors(pnv->bmc, fdt); 555 } 556 557 /* Create an extra node for power management on machines that support it */ 558 if (pmc->dt_power_mgt) { 559 pmc->dt_power_mgt(pnv, fdt); 560 } 561 562 return fdt; 563 } 564 565 static void pnv_powerdown_notify(Notifier *n, void *opaque) 566 { 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 568 569 if (pnv->bmc) { 570 pnv_bmc_powerdown(pnv->bmc); 571 } 572 } 573 574 static void pnv_reset(MachineState *machine) 575 { 576 PnvMachineState *pnv = PNV_MACHINE(machine); 577 IPMIBmc *bmc; 578 void *fdt; 579 580 qemu_devices_reset(); 581 582 /* 583 * The machine should provide by default an internal BMC simulator. 584 * If not, try to use the BMC device that was provided on the command 585 * line. 586 */ 587 bmc = pnv_bmc_find(&error_fatal); 588 if (!pnv->bmc) { 589 if (!bmc) { 590 warn_report("machine has no BMC device. Use '-device " 591 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 592 "to define one"); 593 } else { 594 pnv_bmc_set_pnor(bmc, pnv->pnor); 595 pnv->bmc = bmc; 596 } 597 } 598 599 fdt = pnv_dt_create(machine); 600 601 /* Pack resulting tree */ 602 _FDT((fdt_pack(fdt))); 603 604 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 605 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 606 607 g_free(fdt); 608 } 609 610 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 611 { 612 Pnv8Chip *chip8 = PNV8_CHIP(chip); 613 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 614 } 615 616 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 617 { 618 Pnv8Chip *chip8 = PNV8_CHIP(chip); 619 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 620 } 621 622 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 623 { 624 Pnv9Chip *chip9 = PNV9_CHIP(chip); 625 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 626 } 627 628 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 629 { 630 Pnv10Chip *chip10 = PNV10_CHIP(chip); 631 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 632 } 633 634 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 635 { 636 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 637 } 638 639 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 640 { 641 Pnv8Chip *chip8 = PNV8_CHIP(chip); 642 int i; 643 644 ics_pic_print_info(&chip8->psi.ics, mon); 645 for (i = 0; i < chip->num_phbs; i++) { 646 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 647 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 648 } 649 } 650 651 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 652 { 653 Pnv9Chip *chip9 = PNV9_CHIP(chip); 654 int i, j; 655 656 pnv_xive_pic_print_info(&chip9->xive, mon); 657 pnv_psi_pic_print_info(&chip9->psi, mon); 658 659 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 660 PnvPhb4PecState *pec = &chip9->pecs[i]; 661 for (j = 0; j < pec->num_stacks; j++) { 662 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 663 } 664 } 665 } 666 667 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 668 uint32_t core_id) 669 { 670 return PNV_XSCOM_EX_BASE(core_id); 671 } 672 673 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 674 uint32_t core_id) 675 { 676 return PNV9_XSCOM_EC_BASE(core_id); 677 } 678 679 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 680 uint32_t core_id) 681 { 682 return PNV10_XSCOM_EC_BASE(core_id); 683 } 684 685 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 686 { 687 PowerPCCPUClass *ppc_default = 688 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 689 PowerPCCPUClass *ppc = 690 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 691 692 return ppc_default->pvr_match(ppc_default, ppc->pvr); 693 } 694 695 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 696 { 697 ISADevice *dev = isa_new("isa-ipmi-bt"); 698 699 object_property_set_link(OBJECT(dev), OBJECT(bmc), "bmc", &error_fatal); 700 object_property_set_int(OBJECT(dev), irq, "irq", &error_fatal); 701 isa_realize_and_unref(dev, bus, &error_fatal); 702 } 703 704 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 705 { 706 Pnv10Chip *chip10 = PNV10_CHIP(chip); 707 708 pnv_psi_pic_print_info(&chip10->psi, mon); 709 } 710 711 static void pnv_init(MachineState *machine) 712 { 713 PnvMachineState *pnv = PNV_MACHINE(machine); 714 MachineClass *mc = MACHINE_GET_CLASS(machine); 715 char *fw_filename; 716 long fw_size; 717 int i; 718 char *chip_typename; 719 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 720 DeviceState *dev; 721 722 /* allocate RAM */ 723 if (machine->ram_size < (1 * GiB)) { 724 warn_report("skiboot may not work with < 1GB of RAM"); 725 } 726 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 727 728 /* 729 * Create our simple PNOR device 730 */ 731 dev = qdev_new(TYPE_PNV_PNOR); 732 if (pnor) { 733 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 734 &error_abort); 735 } 736 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 737 pnv->pnor = PNV_PNOR(dev); 738 739 /* load skiboot firmware */ 740 if (bios_name == NULL) { 741 bios_name = FW_FILE_NAME; 742 } 743 744 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 745 if (!fw_filename) { 746 error_report("Could not find OPAL firmware '%s'", bios_name); 747 exit(1); 748 } 749 750 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 751 if (fw_size < 0) { 752 error_report("Could not load OPAL firmware '%s'", fw_filename); 753 exit(1); 754 } 755 g_free(fw_filename); 756 757 /* load kernel */ 758 if (machine->kernel_filename) { 759 long kernel_size; 760 761 kernel_size = load_image_targphys(machine->kernel_filename, 762 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 763 if (kernel_size < 0) { 764 error_report("Could not load kernel '%s'", 765 machine->kernel_filename); 766 exit(1); 767 } 768 } 769 770 /* load initrd */ 771 if (machine->initrd_filename) { 772 pnv->initrd_base = INITRD_LOAD_ADDR; 773 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 774 pnv->initrd_base, INITRD_MAX_SIZE); 775 if (pnv->initrd_size < 0) { 776 error_report("Could not load initial ram disk '%s'", 777 machine->initrd_filename); 778 exit(1); 779 } 780 } 781 782 /* MSIs are supported on this platform */ 783 msi_nonbroken = true; 784 785 /* 786 * Check compatibility of the specified CPU with the machine 787 * default. 788 */ 789 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 790 error_report("invalid CPU model '%s' for %s machine", 791 machine->cpu_type, mc->name); 792 exit(1); 793 } 794 795 /* Create the processor chips */ 796 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 797 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 798 i, machine->cpu_type); 799 if (!object_class_by_name(chip_typename)) { 800 error_report("invalid chip model '%.*s' for %s machine", 801 i, machine->cpu_type, mc->name); 802 exit(1); 803 } 804 805 pnv->num_chips = 806 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 807 /* 808 * TODO: should we decide on how many chips we can create based 809 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 810 */ 811 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 812 error_report("invalid number of chips: '%d'", pnv->num_chips); 813 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 814 exit(1); 815 } 816 817 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 818 for (i = 0; i < pnv->num_chips; i++) { 819 char chip_name[32]; 820 Object *chip = OBJECT(qdev_new(chip_typename)); 821 822 pnv->chips[i] = PNV_CHIP(chip); 823 824 /* 825 * TODO: put all the memory in one node on chip 0 until we find a 826 * way to specify different ranges for each chip 827 */ 828 if (i == 0) { 829 object_property_set_int(chip, machine->ram_size, "ram-size", 830 &error_fatal); 831 } 832 833 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 834 object_property_add_child(OBJECT(pnv), chip_name, chip); 835 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 836 &error_fatal); 837 object_property_set_int(chip, machine->smp.cores, 838 "nr-cores", &error_fatal); 839 object_property_set_int(chip, machine->smp.threads, 840 "nr-threads", &error_fatal); 841 /* 842 * The POWER8 machine use the XICS interrupt interface. 843 * Propagate the XICS fabric to the chip and its controllers. 844 */ 845 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 846 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 847 } 848 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 849 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 850 &error_abort); 851 } 852 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 853 } 854 g_free(chip_typename); 855 856 /* Instantiate ISA bus on chip 0 */ 857 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 858 859 /* Create serial port */ 860 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 861 862 /* Create an RTC ISA device too */ 863 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 864 865 /* 866 * Create the machine BMC simulator and the IPMI BT device for 867 * communication with the BMC 868 */ 869 if (defaults_enabled()) { 870 pnv->bmc = pnv_bmc_create(pnv->pnor); 871 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 872 } 873 874 /* 875 * OpenPOWER systems use a IPMI SEL Event message to notify the 876 * host to powerdown 877 */ 878 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 879 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 880 } 881 882 /* 883 * 0:21 Reserved - Read as zeros 884 * 22:24 Chip ID 885 * 25:28 Core number 886 * 29:31 Thread ID 887 */ 888 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 889 { 890 return (chip->chip_id << 7) | (core_id << 3); 891 } 892 893 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 894 Error **errp) 895 { 896 Pnv8Chip *chip8 = PNV8_CHIP(chip); 897 Error *local_err = NULL; 898 Object *obj; 899 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 900 901 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 902 if (local_err) { 903 error_propagate(errp, local_err); 904 return; 905 } 906 907 pnv_cpu->intc = obj; 908 } 909 910 911 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 912 { 913 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 914 915 icp_reset(ICP(pnv_cpu->intc)); 916 } 917 918 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 919 { 920 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 921 922 icp_destroy(ICP(pnv_cpu->intc)); 923 pnv_cpu->intc = NULL; 924 } 925 926 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 927 Monitor *mon) 928 { 929 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 930 } 931 932 /* 933 * 0:48 Reserved - Read as zeroes 934 * 49:52 Node ID 935 * 53:55 Chip ID 936 * 56 Reserved - Read as zero 937 * 57:61 Core number 938 * 62:63 Thread ID 939 * 940 * We only care about the lower bits. uint32_t is fine for the moment. 941 */ 942 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 943 { 944 return (chip->chip_id << 8) | (core_id << 2); 945 } 946 947 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 948 { 949 return (chip->chip_id << 8) | (core_id << 2); 950 } 951 952 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 953 Error **errp) 954 { 955 Pnv9Chip *chip9 = PNV9_CHIP(chip); 956 Error *local_err = NULL; 957 Object *obj; 958 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 959 960 /* 961 * The core creates its interrupt presenter but the XIVE interrupt 962 * controller object is initialized afterwards. Hopefully, it's 963 * only used at runtime. 964 */ 965 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 966 &local_err); 967 if (local_err) { 968 error_propagate(errp, local_err); 969 return; 970 } 971 972 pnv_cpu->intc = obj; 973 } 974 975 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 976 { 977 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 978 979 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 980 } 981 982 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 983 { 984 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 985 986 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 987 pnv_cpu->intc = NULL; 988 } 989 990 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 991 Monitor *mon) 992 { 993 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 994 } 995 996 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 997 Error **errp) 998 { 999 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1000 1001 /* Will be defined when the interrupt controller is */ 1002 pnv_cpu->intc = NULL; 1003 } 1004 1005 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1006 { 1007 ; 1008 } 1009 1010 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1011 { 1012 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1013 1014 pnv_cpu->intc = NULL; 1015 } 1016 1017 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1018 Monitor *mon) 1019 { 1020 } 1021 1022 /* 1023 * Allowed core identifiers on a POWER8 Processor Chip : 1024 * 1025 * <EX0 reserved> 1026 * EX1 - Venice only 1027 * EX2 - Venice only 1028 * EX3 - Venice only 1029 * EX4 1030 * EX5 1031 * EX6 1032 * <EX7,8 reserved> <reserved> 1033 * EX9 - Venice only 1034 * EX10 - Venice only 1035 * EX11 - Venice only 1036 * EX12 1037 * EX13 1038 * EX14 1039 * <EX15 reserved> 1040 */ 1041 #define POWER8E_CORE_MASK (0x7070ull) 1042 #define POWER8_CORE_MASK (0x7e7eull) 1043 1044 /* 1045 * POWER9 has 24 cores, ids starting at 0x0 1046 */ 1047 #define POWER9_CORE_MASK (0xffffffffffffffull) 1048 1049 1050 #define POWER10_CORE_MASK (0xffffffffffffffull) 1051 1052 static void pnv_chip_power8_instance_init(Object *obj) 1053 { 1054 PnvChip *chip = PNV_CHIP(obj); 1055 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1056 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1057 int i; 1058 1059 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1060 (Object **)&chip8->xics, 1061 object_property_allow_set_link, 1062 OBJ_PROP_LINK_STRONG); 1063 1064 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1065 1066 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1067 1068 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1069 1070 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1071 1072 for (i = 0; i < pcc->num_phbs; i++) { 1073 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1074 } 1075 1076 /* 1077 * Number of PHBs is the chip default 1078 */ 1079 chip->num_phbs = pcc->num_phbs; 1080 } 1081 1082 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1083 { 1084 PnvChip *chip = PNV_CHIP(chip8); 1085 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1086 int i, j; 1087 char *name; 1088 1089 name = g_strdup_printf("icp-%x", chip->chip_id); 1090 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1091 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1092 g_free(name); 1093 1094 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1095 1096 /* Map the ICP registers for each thread */ 1097 for (i = 0; i < chip->nr_cores; i++) { 1098 PnvCore *pnv_core = chip->cores[i]; 1099 int core_hwid = CPU_CORE(pnv_core)->core_id; 1100 1101 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1102 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1103 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1104 1105 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1106 &icp->mmio); 1107 } 1108 } 1109 } 1110 1111 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1112 { 1113 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1114 PnvChip *chip = PNV_CHIP(dev); 1115 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1116 Pnv8Psi *psi8 = &chip8->psi; 1117 Error *local_err = NULL; 1118 int i; 1119 1120 assert(chip8->xics); 1121 1122 /* XSCOM bridge is first */ 1123 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1124 if (local_err) { 1125 error_propagate(errp, local_err); 1126 return; 1127 } 1128 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1129 1130 pcc->parent_realize(dev, &local_err); 1131 if (local_err) { 1132 error_propagate(errp, local_err); 1133 return; 1134 } 1135 1136 /* Processor Service Interface (PSI) Host Bridge */ 1137 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1138 "bar", &error_fatal); 1139 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1140 ICS_PROP_XICS, &error_abort); 1141 qdev_realize(DEVICE(&chip8->psi), NULL, &local_err); 1142 if (local_err) { 1143 error_propagate(errp, local_err); 1144 return; 1145 } 1146 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1147 &PNV_PSI(psi8)->xscom_regs); 1148 1149 /* Create LPC controller */ 1150 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1151 &error_abort); 1152 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1153 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1154 1155 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1156 (uint64_t) PNV_XSCOM_BASE(chip), 1157 PNV_XSCOM_LPC_BASE); 1158 1159 /* 1160 * Interrupt Management Area. This is the memory region holding 1161 * all the Interrupt Control Presenter (ICP) registers 1162 */ 1163 pnv_chip_icp_realize(chip8, &local_err); 1164 if (local_err) { 1165 error_propagate(errp, local_err); 1166 return; 1167 } 1168 1169 /* Create the simplified OCC model */ 1170 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1171 &error_abort); 1172 qdev_realize(DEVICE(&chip8->occ), NULL, &local_err); 1173 if (local_err) { 1174 error_propagate(errp, local_err); 1175 return; 1176 } 1177 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1178 1179 /* OCC SRAM model */ 1180 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1181 &chip8->occ.sram_regs); 1182 1183 /* HOMER */ 1184 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1185 &error_abort); 1186 qdev_realize(DEVICE(&chip8->homer), NULL, &local_err); 1187 if (local_err) { 1188 error_propagate(errp, local_err); 1189 return; 1190 } 1191 /* Homer Xscom region */ 1192 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1193 1194 /* Homer mmio region */ 1195 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1196 &chip8->homer.regs); 1197 1198 /* PHB3 controllers */ 1199 for (i = 0; i < chip->num_phbs; i++) { 1200 PnvPHB3 *phb = &chip8->phbs[i]; 1201 PnvPBCQState *pbcq = &phb->pbcq; 1202 1203 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1204 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1205 &error_fatal); 1206 sysbus_realize(SYS_BUS_DEVICE(phb), &local_err); 1207 if (local_err) { 1208 error_propagate(errp, local_err); 1209 return; 1210 } 1211 1212 /* Populate the XSCOM address space. */ 1213 pnv_xscom_add_subregion(chip, 1214 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1215 &pbcq->xscom_nest_regs); 1216 pnv_xscom_add_subregion(chip, 1217 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1218 &pbcq->xscom_pci_regs); 1219 pnv_xscom_add_subregion(chip, 1220 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1221 &pbcq->xscom_spci_regs); 1222 } 1223 } 1224 1225 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1226 { 1227 addr &= (PNV_XSCOM_SIZE - 1); 1228 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1229 } 1230 1231 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1232 { 1233 DeviceClass *dc = DEVICE_CLASS(klass); 1234 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1235 1236 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1237 k->cores_mask = POWER8E_CORE_MASK; 1238 k->num_phbs = 3; 1239 k->core_pir = pnv_chip_core_pir_p8; 1240 k->intc_create = pnv_chip_power8_intc_create; 1241 k->intc_reset = pnv_chip_power8_intc_reset; 1242 k->intc_destroy = pnv_chip_power8_intc_destroy; 1243 k->intc_print_info = pnv_chip_power8_intc_print_info; 1244 k->isa_create = pnv_chip_power8_isa_create; 1245 k->dt_populate = pnv_chip_power8_dt_populate; 1246 k->pic_print_info = pnv_chip_power8_pic_print_info; 1247 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1248 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1249 dc->desc = "PowerNV Chip POWER8E"; 1250 1251 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1252 &k->parent_realize); 1253 } 1254 1255 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1256 { 1257 DeviceClass *dc = DEVICE_CLASS(klass); 1258 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1259 1260 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1261 k->cores_mask = POWER8_CORE_MASK; 1262 k->num_phbs = 3; 1263 k->core_pir = pnv_chip_core_pir_p8; 1264 k->intc_create = pnv_chip_power8_intc_create; 1265 k->intc_reset = pnv_chip_power8_intc_reset; 1266 k->intc_destroy = pnv_chip_power8_intc_destroy; 1267 k->intc_print_info = pnv_chip_power8_intc_print_info; 1268 k->isa_create = pnv_chip_power8_isa_create; 1269 k->dt_populate = pnv_chip_power8_dt_populate; 1270 k->pic_print_info = pnv_chip_power8_pic_print_info; 1271 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1272 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1273 dc->desc = "PowerNV Chip POWER8"; 1274 1275 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1276 &k->parent_realize); 1277 } 1278 1279 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1280 { 1281 DeviceClass *dc = DEVICE_CLASS(klass); 1282 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1283 1284 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1285 k->cores_mask = POWER8_CORE_MASK; 1286 k->num_phbs = 3; 1287 k->core_pir = pnv_chip_core_pir_p8; 1288 k->intc_create = pnv_chip_power8_intc_create; 1289 k->intc_reset = pnv_chip_power8_intc_reset; 1290 k->intc_destroy = pnv_chip_power8_intc_destroy; 1291 k->intc_print_info = pnv_chip_power8_intc_print_info; 1292 k->isa_create = pnv_chip_power8nvl_isa_create; 1293 k->dt_populate = pnv_chip_power8_dt_populate; 1294 k->pic_print_info = pnv_chip_power8_pic_print_info; 1295 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1296 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1297 dc->desc = "PowerNV Chip POWER8NVL"; 1298 1299 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1300 &k->parent_realize); 1301 } 1302 1303 static void pnv_chip_power9_instance_init(Object *obj) 1304 { 1305 PnvChip *chip = PNV_CHIP(obj); 1306 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1307 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1308 int i; 1309 1310 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1311 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1312 "xive-fabric"); 1313 1314 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1315 1316 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1317 1318 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1319 1320 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1321 1322 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1323 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1324 TYPE_PNV_PHB4_PEC); 1325 } 1326 1327 /* 1328 * Number of PHBs is the chip default 1329 */ 1330 chip->num_phbs = pcc->num_phbs; 1331 } 1332 1333 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1334 { 1335 PnvChip *chip = PNV_CHIP(chip9); 1336 int i; 1337 1338 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1339 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1340 1341 for (i = 0; i < chip9->nr_quads; i++) { 1342 char eq_name[32]; 1343 PnvQuad *eq = &chip9->quads[i]; 1344 PnvCore *pnv_core = chip->cores[i * 4]; 1345 int core_id = CPU_CORE(pnv_core)->core_id; 1346 1347 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1348 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1349 sizeof(*eq), TYPE_PNV_QUAD, 1350 &error_fatal, NULL); 1351 1352 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1353 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1354 1355 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1356 &eq->xscom_regs); 1357 } 1358 } 1359 1360 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1361 { 1362 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1363 Error *local_err = NULL; 1364 int i, j; 1365 int phb_id = 0; 1366 1367 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1368 PnvPhb4PecState *pec = &chip9->pecs[i]; 1369 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1370 uint32_t pec_nest_base; 1371 uint32_t pec_pci_base; 1372 1373 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1374 /* 1375 * PEC0 -> 1 stack 1376 * PEC1 -> 2 stacks 1377 * PEC2 -> 3 stacks 1378 */ 1379 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1380 &error_fatal); 1381 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1382 &error_fatal); 1383 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1384 "system-memory", &error_abort); 1385 qdev_realize(DEVICE(pec), NULL, &local_err); 1386 if (local_err) { 1387 error_propagate(errp, local_err); 1388 return; 1389 } 1390 1391 pec_nest_base = pecc->xscom_nest_base(pec); 1392 pec_pci_base = pecc->xscom_pci_base(pec); 1393 1394 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1395 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1396 1397 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1398 j++, phb_id++) { 1399 PnvPhb4PecStack *stack = &pec->stacks[j]; 1400 Object *obj = OBJECT(&stack->phb); 1401 1402 object_property_set_int(obj, phb_id, "index", &error_fatal); 1403 object_property_set_int(obj, chip->chip_id, "chip-id", 1404 &error_fatal); 1405 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1406 &error_fatal); 1407 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1408 &error_fatal); 1409 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1410 sysbus_realize(SYS_BUS_DEVICE(obj), &local_err); 1411 if (local_err) { 1412 error_propagate(errp, local_err); 1413 return; 1414 } 1415 1416 /* Populate the XSCOM address space. */ 1417 pnv_xscom_add_subregion(chip, 1418 pec_nest_base + 0x40 * (stack->stack_no + 1), 1419 &stack->nest_regs_mr); 1420 pnv_xscom_add_subregion(chip, 1421 pec_pci_base + 0x40 * (stack->stack_no + 1), 1422 &stack->pci_regs_mr); 1423 pnv_xscom_add_subregion(chip, 1424 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1425 0x40 * stack->stack_no, 1426 &stack->phb_regs_mr); 1427 } 1428 } 1429 } 1430 1431 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1432 { 1433 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1434 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1435 PnvChip *chip = PNV_CHIP(dev); 1436 Pnv9Psi *psi9 = &chip9->psi; 1437 Error *local_err = NULL; 1438 1439 /* XSCOM bridge is first */ 1440 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1441 if (local_err) { 1442 error_propagate(errp, local_err); 1443 return; 1444 } 1445 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1446 1447 pcc->parent_realize(dev, &local_err); 1448 if (local_err) { 1449 error_propagate(errp, local_err); 1450 return; 1451 } 1452 1453 pnv_chip_quad_realize(chip9, &local_err); 1454 if (local_err) { 1455 error_propagate(errp, local_err); 1456 return; 1457 } 1458 1459 /* XIVE interrupt controller (POWER9) */ 1460 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1461 "ic-bar", &error_fatal); 1462 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1463 "vc-bar", &error_fatal); 1464 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1465 "pc-bar", &error_fatal); 1466 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1467 "tm-bar", &error_fatal); 1468 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1469 &error_abort); 1470 sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), &local_err); 1471 if (local_err) { 1472 error_propagate(errp, local_err); 1473 return; 1474 } 1475 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1476 &chip9->xive.xscom_regs); 1477 1478 /* Processor Service Interface (PSI) Host Bridge */ 1479 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1480 "bar", &error_fatal); 1481 qdev_realize(DEVICE(&chip9->psi), NULL, &local_err); 1482 if (local_err) { 1483 error_propagate(errp, local_err); 1484 return; 1485 } 1486 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1487 &PNV_PSI(psi9)->xscom_regs); 1488 1489 /* LPC */ 1490 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1491 &error_abort); 1492 qdev_realize(DEVICE(&chip9->lpc), NULL, &local_err); 1493 if (local_err) { 1494 error_propagate(errp, local_err); 1495 return; 1496 } 1497 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1498 &chip9->lpc.xscom_regs); 1499 1500 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1501 (uint64_t) PNV9_LPCM_BASE(chip)); 1502 1503 /* Create the simplified OCC model */ 1504 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1505 &error_abort); 1506 qdev_realize(DEVICE(&chip9->occ), NULL, &local_err); 1507 if (local_err) { 1508 error_propagate(errp, local_err); 1509 return; 1510 } 1511 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1512 1513 /* OCC SRAM model */ 1514 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1515 &chip9->occ.sram_regs); 1516 1517 /* HOMER */ 1518 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1519 &error_abort); 1520 qdev_realize(DEVICE(&chip9->homer), NULL, &local_err); 1521 if (local_err) { 1522 error_propagate(errp, local_err); 1523 return; 1524 } 1525 /* Homer Xscom region */ 1526 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1527 1528 /* Homer mmio region */ 1529 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1530 &chip9->homer.regs); 1531 1532 /* PHBs */ 1533 pnv_chip_power9_phb_realize(chip, &local_err); 1534 if (local_err) { 1535 error_propagate(errp, local_err); 1536 return; 1537 } 1538 } 1539 1540 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1541 { 1542 addr &= (PNV9_XSCOM_SIZE - 1); 1543 return addr >> 3; 1544 } 1545 1546 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1547 { 1548 DeviceClass *dc = DEVICE_CLASS(klass); 1549 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1550 1551 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1552 k->cores_mask = POWER9_CORE_MASK; 1553 k->core_pir = pnv_chip_core_pir_p9; 1554 k->intc_create = pnv_chip_power9_intc_create; 1555 k->intc_reset = pnv_chip_power9_intc_reset; 1556 k->intc_destroy = pnv_chip_power9_intc_destroy; 1557 k->intc_print_info = pnv_chip_power9_intc_print_info; 1558 k->isa_create = pnv_chip_power9_isa_create; 1559 k->dt_populate = pnv_chip_power9_dt_populate; 1560 k->pic_print_info = pnv_chip_power9_pic_print_info; 1561 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1562 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1563 dc->desc = "PowerNV Chip POWER9"; 1564 k->num_phbs = 6; 1565 1566 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1567 &k->parent_realize); 1568 } 1569 1570 static void pnv_chip_power10_instance_init(Object *obj) 1571 { 1572 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1573 1574 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1575 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1576 } 1577 1578 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1579 { 1580 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1581 PnvChip *chip = PNV_CHIP(dev); 1582 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1583 Error *local_err = NULL; 1584 1585 /* XSCOM bridge is first */ 1586 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1587 if (local_err) { 1588 error_propagate(errp, local_err); 1589 return; 1590 } 1591 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1592 1593 pcc->parent_realize(dev, &local_err); 1594 if (local_err) { 1595 error_propagate(errp, local_err); 1596 return; 1597 } 1598 1599 /* Processor Service Interface (PSI) Host Bridge */ 1600 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1601 "bar", &error_fatal); 1602 qdev_realize(DEVICE(&chip10->psi), NULL, &local_err); 1603 if (local_err) { 1604 error_propagate(errp, local_err); 1605 return; 1606 } 1607 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1608 &PNV_PSI(&chip10->psi)->xscom_regs); 1609 1610 /* LPC */ 1611 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1612 &error_abort); 1613 qdev_realize(DEVICE(&chip10->lpc), NULL, &local_err); 1614 if (local_err) { 1615 error_propagate(errp, local_err); 1616 return; 1617 } 1618 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1619 &chip10->lpc.xscom_regs); 1620 1621 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1622 (uint64_t) PNV10_LPCM_BASE(chip)); 1623 } 1624 1625 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1626 { 1627 addr &= (PNV10_XSCOM_SIZE - 1); 1628 return addr >> 3; 1629 } 1630 1631 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1632 { 1633 DeviceClass *dc = DEVICE_CLASS(klass); 1634 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1635 1636 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1637 k->cores_mask = POWER10_CORE_MASK; 1638 k->core_pir = pnv_chip_core_pir_p10; 1639 k->intc_create = pnv_chip_power10_intc_create; 1640 k->intc_reset = pnv_chip_power10_intc_reset; 1641 k->intc_destroy = pnv_chip_power10_intc_destroy; 1642 k->intc_print_info = pnv_chip_power10_intc_print_info; 1643 k->isa_create = pnv_chip_power10_isa_create; 1644 k->dt_populate = pnv_chip_power10_dt_populate; 1645 k->pic_print_info = pnv_chip_power10_pic_print_info; 1646 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1647 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1648 dc->desc = "PowerNV Chip POWER10"; 1649 1650 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1651 &k->parent_realize); 1652 } 1653 1654 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1655 { 1656 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1657 int cores_max; 1658 1659 /* 1660 * No custom mask for this chip, let's use the default one from * 1661 * the chip class 1662 */ 1663 if (!chip->cores_mask) { 1664 chip->cores_mask = pcc->cores_mask; 1665 } 1666 1667 /* filter alien core ids ! some are reserved */ 1668 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1669 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1670 chip->cores_mask); 1671 return; 1672 } 1673 chip->cores_mask &= pcc->cores_mask; 1674 1675 /* now that we have a sane layout, let check the number of cores */ 1676 cores_max = ctpop64(chip->cores_mask); 1677 if (chip->nr_cores > cores_max) { 1678 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1679 cores_max); 1680 return; 1681 } 1682 } 1683 1684 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1685 { 1686 Error *error = NULL; 1687 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1688 const char *typename = pnv_chip_core_typename(chip); 1689 int i, core_hwid; 1690 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1691 1692 if (!object_class_by_name(typename)) { 1693 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1694 return; 1695 } 1696 1697 /* Cores */ 1698 pnv_chip_core_sanitize(chip, &error); 1699 if (error) { 1700 error_propagate(errp, error); 1701 return; 1702 } 1703 1704 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1705 1706 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1707 && (i < chip->nr_cores); core_hwid++) { 1708 char core_name[32]; 1709 PnvCore *pnv_core; 1710 uint64_t xscom_core_base; 1711 1712 if (!(chip->cores_mask & (1ull << core_hwid))) { 1713 continue; 1714 } 1715 1716 pnv_core = PNV_CORE(object_new(typename)); 1717 1718 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1719 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1720 chip->cores[i] = pnv_core; 1721 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1722 "nr-threads", &error_fatal); 1723 object_property_set_int(OBJECT(pnv_core), core_hwid, 1724 CPU_CORE_PROP_CORE_ID, &error_fatal); 1725 object_property_set_int(OBJECT(pnv_core), 1726 pcc->core_pir(chip, core_hwid), 1727 "pir", &error_fatal); 1728 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1729 "hrmor", &error_fatal); 1730 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1731 &error_abort); 1732 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1733 1734 /* Each core has an XSCOM MMIO region */ 1735 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1736 1737 pnv_xscom_add_subregion(chip, xscom_core_base, 1738 &pnv_core->xscom_regs); 1739 i++; 1740 } 1741 } 1742 1743 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1744 { 1745 PnvChip *chip = PNV_CHIP(dev); 1746 Error *error = NULL; 1747 1748 /* Cores */ 1749 pnv_chip_core_realize(chip, &error); 1750 if (error) { 1751 error_propagate(errp, error); 1752 return; 1753 } 1754 } 1755 1756 static Property pnv_chip_properties[] = { 1757 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1758 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1759 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1760 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1761 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1762 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1763 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1764 DEFINE_PROP_END_OF_LIST(), 1765 }; 1766 1767 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1768 { 1769 DeviceClass *dc = DEVICE_CLASS(klass); 1770 1771 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1772 dc->realize = pnv_chip_realize; 1773 device_class_set_props(dc, pnv_chip_properties); 1774 dc->desc = "PowerNV Chip"; 1775 } 1776 1777 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1778 { 1779 int i, j; 1780 1781 for (i = 0; i < chip->nr_cores; i++) { 1782 PnvCore *pc = chip->cores[i]; 1783 CPUCore *cc = CPU_CORE(pc); 1784 1785 for (j = 0; j < cc->nr_threads; j++) { 1786 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1787 return pc->threads[j]; 1788 } 1789 } 1790 } 1791 return NULL; 1792 } 1793 1794 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1795 { 1796 PnvMachineState *pnv = PNV_MACHINE(xi); 1797 int i, j; 1798 1799 for (i = 0; i < pnv->num_chips; i++) { 1800 PnvChip *chip = pnv->chips[i]; 1801 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1802 1803 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1804 return &chip8->psi.ics; 1805 } 1806 for (j = 0; j < chip->num_phbs; j++) { 1807 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1808 return &chip8->phbs[j].lsis; 1809 } 1810 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1811 return ICS(&chip8->phbs[j].msis); 1812 } 1813 } 1814 } 1815 return NULL; 1816 } 1817 1818 static void pnv_ics_resend(XICSFabric *xi) 1819 { 1820 PnvMachineState *pnv = PNV_MACHINE(xi); 1821 int i, j; 1822 1823 for (i = 0; i < pnv->num_chips; i++) { 1824 PnvChip *chip = pnv->chips[i]; 1825 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1826 1827 ics_resend(&chip8->psi.ics); 1828 for (j = 0; j < chip->num_phbs; j++) { 1829 ics_resend(&chip8->phbs[j].lsis); 1830 ics_resend(ICS(&chip8->phbs[j].msis)); 1831 } 1832 } 1833 } 1834 1835 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1836 { 1837 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1838 1839 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1840 } 1841 1842 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1843 Monitor *mon) 1844 { 1845 PnvMachineState *pnv = PNV_MACHINE(obj); 1846 int i; 1847 CPUState *cs; 1848 1849 CPU_FOREACH(cs) { 1850 PowerPCCPU *cpu = POWERPC_CPU(cs); 1851 1852 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1853 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1854 mon); 1855 } 1856 1857 for (i = 0; i < pnv->num_chips; i++) { 1858 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1859 } 1860 } 1861 1862 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1863 uint8_t nvt_blk, uint32_t nvt_idx, 1864 bool cam_ignore, uint8_t priority, 1865 uint32_t logic_serv, 1866 XiveTCTXMatch *match) 1867 { 1868 PnvMachineState *pnv = PNV_MACHINE(xfb); 1869 int total_count = 0; 1870 int i; 1871 1872 for (i = 0; i < pnv->num_chips; i++) { 1873 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1874 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1875 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1876 int count; 1877 1878 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1879 priority, logic_serv, match); 1880 1881 if (count < 0) { 1882 return count; 1883 } 1884 1885 total_count += count; 1886 } 1887 1888 return total_count; 1889 } 1890 1891 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1892 { 1893 MachineClass *mc = MACHINE_CLASS(oc); 1894 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1895 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1896 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1897 1898 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1899 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1900 1901 xic->icp_get = pnv_icp_get; 1902 xic->ics_get = pnv_ics_get; 1903 xic->ics_resend = pnv_ics_resend; 1904 1905 pmc->compat = compat; 1906 pmc->compat_size = sizeof(compat); 1907 } 1908 1909 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1910 { 1911 MachineClass *mc = MACHINE_CLASS(oc); 1912 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1913 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1914 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1915 1916 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1917 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1918 xfc->match_nvt = pnv_match_nvt; 1919 1920 mc->alias = "powernv"; 1921 1922 pmc->compat = compat; 1923 pmc->compat_size = sizeof(compat); 1924 pmc->dt_power_mgt = pnv_dt_power_mgt; 1925 } 1926 1927 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1928 { 1929 MachineClass *mc = MACHINE_CLASS(oc); 1930 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1931 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1932 1933 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1934 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1935 1936 pmc->compat = compat; 1937 pmc->compat_size = sizeof(compat); 1938 pmc->dt_power_mgt = pnv_dt_power_mgt; 1939 } 1940 1941 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1942 { 1943 PnvMachineState *pnv = PNV_MACHINE(obj); 1944 1945 return !!pnv->fw_load_addr; 1946 } 1947 1948 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1949 { 1950 PnvMachineState *pnv = PNV_MACHINE(obj); 1951 1952 if (value) { 1953 pnv->fw_load_addr = 0x8000000; 1954 } 1955 } 1956 1957 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1958 { 1959 PowerPCCPU *cpu = POWERPC_CPU(cs); 1960 CPUPPCState *env = &cpu->env; 1961 1962 cpu_synchronize_state(cs); 1963 ppc_cpu_do_system_reset(cs); 1964 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1965 /* 1966 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1967 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1968 * (PPC_BIT(43)). 1969 */ 1970 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1971 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1972 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1973 } 1974 } else { 1975 /* 1976 * For non-powersave system resets, SRR1[42:45] are defined to be 1977 * implementation-dependent. The POWER9 User Manual specifies that 1978 * an external (SCOM driven, which may come from a BMC nmi command or 1979 * another CPU requesting a NMI IPI) system reset exception should be 1980 * 0b0010 (PPC_BIT(44)). 1981 */ 1982 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1983 } 1984 } 1985 1986 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1987 { 1988 CPUState *cs; 1989 1990 CPU_FOREACH(cs) { 1991 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 1992 } 1993 } 1994 1995 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1996 { 1997 MachineClass *mc = MACHINE_CLASS(oc); 1998 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1999 NMIClass *nc = NMI_CLASS(oc); 2000 2001 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2002 mc->init = pnv_init; 2003 mc->reset = pnv_reset; 2004 mc->max_cpus = MAX_CPUS; 2005 /* Pnv provides a AHCI device for storage */ 2006 mc->block_default_type = IF_IDE; 2007 mc->no_parallel = 1; 2008 mc->default_boot_order = NULL; 2009 /* 2010 * RAM defaults to less than 2048 for 32-bit hosts, and large 2011 * enough to fit the maximum initrd size at it's load address 2012 */ 2013 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 2014 mc->default_ram_id = "pnv.ram"; 2015 ispc->print_info = pnv_pic_print_info; 2016 nc->nmi_monitor_handler = pnv_nmi; 2017 2018 object_class_property_add_bool(oc, "hb-mode", 2019 pnv_machine_get_hb, pnv_machine_set_hb); 2020 object_class_property_set_description(oc, "hb-mode", 2021 "Use a hostboot like boot loader"); 2022 } 2023 2024 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2025 { \ 2026 .name = type, \ 2027 .class_init = class_initfn, \ 2028 .parent = TYPE_PNV8_CHIP, \ 2029 } 2030 2031 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2032 { \ 2033 .name = type, \ 2034 .class_init = class_initfn, \ 2035 .parent = TYPE_PNV9_CHIP, \ 2036 } 2037 2038 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2039 { \ 2040 .name = type, \ 2041 .class_init = class_initfn, \ 2042 .parent = TYPE_PNV10_CHIP, \ 2043 } 2044 2045 static const TypeInfo types[] = { 2046 { 2047 .name = MACHINE_TYPE_NAME("powernv10"), 2048 .parent = TYPE_PNV_MACHINE, 2049 .class_init = pnv_machine_power10_class_init, 2050 }, 2051 { 2052 .name = MACHINE_TYPE_NAME("powernv9"), 2053 .parent = TYPE_PNV_MACHINE, 2054 .class_init = pnv_machine_power9_class_init, 2055 .interfaces = (InterfaceInfo[]) { 2056 { TYPE_XIVE_FABRIC }, 2057 { }, 2058 }, 2059 }, 2060 { 2061 .name = MACHINE_TYPE_NAME("powernv8"), 2062 .parent = TYPE_PNV_MACHINE, 2063 .class_init = pnv_machine_power8_class_init, 2064 .interfaces = (InterfaceInfo[]) { 2065 { TYPE_XICS_FABRIC }, 2066 { }, 2067 }, 2068 }, 2069 { 2070 .name = TYPE_PNV_MACHINE, 2071 .parent = TYPE_MACHINE, 2072 .abstract = true, 2073 .instance_size = sizeof(PnvMachineState), 2074 .class_init = pnv_machine_class_init, 2075 .class_size = sizeof(PnvMachineClass), 2076 .interfaces = (InterfaceInfo[]) { 2077 { TYPE_INTERRUPT_STATS_PROVIDER }, 2078 { TYPE_NMI }, 2079 { }, 2080 }, 2081 }, 2082 { 2083 .name = TYPE_PNV_CHIP, 2084 .parent = TYPE_SYS_BUS_DEVICE, 2085 .class_init = pnv_chip_class_init, 2086 .instance_size = sizeof(PnvChip), 2087 .class_size = sizeof(PnvChipClass), 2088 .abstract = true, 2089 }, 2090 2091 /* 2092 * P10 chip and variants 2093 */ 2094 { 2095 .name = TYPE_PNV10_CHIP, 2096 .parent = TYPE_PNV_CHIP, 2097 .instance_init = pnv_chip_power10_instance_init, 2098 .instance_size = sizeof(Pnv10Chip), 2099 }, 2100 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2101 2102 /* 2103 * P9 chip and variants 2104 */ 2105 { 2106 .name = TYPE_PNV9_CHIP, 2107 .parent = TYPE_PNV_CHIP, 2108 .instance_init = pnv_chip_power9_instance_init, 2109 .instance_size = sizeof(Pnv9Chip), 2110 }, 2111 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2112 2113 /* 2114 * P8 chip and variants 2115 */ 2116 { 2117 .name = TYPE_PNV8_CHIP, 2118 .parent = TYPE_PNV_CHIP, 2119 .instance_init = pnv_chip_power8_instance_init, 2120 .instance_size = sizeof(Pnv8Chip), 2121 }, 2122 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2123 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2124 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2125 pnv_chip_power8nvl_class_init), 2126 }; 2127 2128 DEFINE_TYPES(types) 2129