1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "qapi/type-helpers.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci-host/pnv_phb.h" 48 #include "hw/pci-host/pnv_phb3.h" 49 #include "hw/pci-host/pnv_phb4.h" 50 51 #include "hw/ppc/xics.h" 52 #include "hw/qdev-properties.h" 53 #include "hw/ppc/pnv_chip.h" 54 #include "hw/ppc/pnv_xscom.h" 55 #include "hw/ppc/pnv_pnor.h" 56 57 #include "hw/isa/isa.h" 58 #include "hw/char/serial.h" 59 #include "hw/rtc/mc146818rtc.h" 60 61 #include <libfdt.h> 62 63 #define FDT_MAX_SIZE (1 * MiB) 64 65 #define FW_FILE_NAME "skiboot.lid" 66 #define FW_LOAD_ADDR 0x0 67 #define FW_MAX_SIZE (16 * MiB) 68 69 #define KERNEL_LOAD_ADDR 0x20000000 70 #define KERNEL_MAX_SIZE (128 * MiB) 71 #define INITRD_LOAD_ADDR 0x28000000 72 #define INITRD_MAX_SIZE (128 * MiB) 73 74 static const char *pnv_chip_core_typename(const PnvChip *o) 75 { 76 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 77 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 78 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 79 const char *core_type = object_class_get_name(object_class_by_name(s)); 80 g_free(s); 81 return core_type; 82 } 83 84 /* 85 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 86 * 4 * 4 sockets * 12 cores * 8 threads = 1536 87 * Let's make it 2^11 88 */ 89 #define MAX_CPUS 2048 90 91 /* 92 * Memory nodes are created by hostboot, one for each range of memory 93 * that has a different "affinity". In practice, it means one range 94 * per chip. 95 */ 96 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 97 { 98 char *mem_name; 99 uint64_t mem_reg_property[2]; 100 int off; 101 102 mem_reg_property[0] = cpu_to_be64(start); 103 mem_reg_property[1] = cpu_to_be64(size); 104 105 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 106 off = fdt_add_subnode(fdt, 0, mem_name); 107 g_free(mem_name); 108 109 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 110 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 111 sizeof(mem_reg_property)))); 112 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 113 } 114 115 static int get_cpus_node(void *fdt) 116 { 117 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 118 119 if (cpus_offset < 0) { 120 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 121 if (cpus_offset) { 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 123 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 124 } 125 } 126 _FDT(cpus_offset); 127 return cpus_offset; 128 } 129 130 /* 131 * The PowerNV cores (and threads) need to use real HW ids and not an 132 * incremental index like it has been done on other platforms. This HW 133 * id is stored in the CPU PIR, it is used to create cpu nodes in the 134 * device tree, used in XSCOM to address cores and in interrupt 135 * servers. 136 */ 137 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 138 { 139 PowerPCCPU *cpu = pc->threads[0]; 140 CPUState *cs = CPU(cpu); 141 DeviceClass *dc = DEVICE_GET_CLASS(cs); 142 int smt_threads = CPU_CORE(pc)->nr_threads; 143 CPUPPCState *env = &cpu->env; 144 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 145 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 146 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 147 int i; 148 uint32_t pir; 149 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 150 0xffffffff, 0xffffffff}; 151 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 152 uint32_t cpufreq = 1000000000; 153 uint32_t page_sizes_prop[64]; 154 size_t page_sizes_prop_size; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 pir = pnv_cc->chip_pir(chip, pc->hwid, 0); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i)); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(*servers_prop) * smt_threads))); 245 246 return offset; 247 } 248 249 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 250 uint32_t nr_threads) 251 { 252 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 253 uint32_t pir = pcc->chip_pir(chip, hwid, 0); 254 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 255 char *name; 256 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 257 uint32_t irange[2], i, rsize; 258 uint64_t *reg; 259 int offset; 260 261 irange[0] = cpu_to_be32(pir); 262 irange[1] = cpu_to_be32(nr_threads); 263 264 rsize = sizeof(uint64_t) * 2 * nr_threads; 265 reg = g_malloc(rsize); 266 for (i = 0; i < nr_threads; i++) { 267 /* We know P8 PIR is linear with thread id */ 268 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 269 reg[i * 2 + 1] = cpu_to_be64(0x1000); 270 } 271 272 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 273 offset = fdt_add_subnode(fdt, 0, name); 274 _FDT(offset); 275 g_free(name); 276 277 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 278 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 279 _FDT((fdt_setprop_string(fdt, offset, "device_type", 280 "PowerPC-External-Interrupt-Presentation"))); 281 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 282 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 283 irange, sizeof(irange)))); 284 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 285 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 286 g_free(reg); 287 } 288 289 /* 290 * Adds a PnvPHB to the chip on P8. 291 * Implemented here, like for defaults PHBs 292 */ 293 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 294 { 295 Pnv8Chip *chip8 = PNV8_CHIP(chip); 296 297 phb->chip = chip; 298 299 chip8->phbs[chip8->num_phbs] = phb; 300 chip8->num_phbs++; 301 return chip; 302 } 303 304 /* 305 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 306 * HTM is always enabled because TCG does implement HTM, it's just a 307 * degenerate implementation. 308 */ 309 static const uint8_t pa_features_207[] = { 24, 0, 310 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 311 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 312 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 313 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 314 315 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 316 { 317 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 318 int i; 319 320 pnv_dt_xscom(chip, fdt, 0, 321 cpu_to_be64(PNV_XSCOM_BASE(chip)), 322 cpu_to_be64(PNV_XSCOM_SIZE), 323 compat, sizeof(compat)); 324 325 for (i = 0; i < chip->nr_cores; i++) { 326 PnvCore *pnv_core = chip->cores[i]; 327 int offset; 328 329 offset = pnv_dt_core(chip, pnv_core, fdt); 330 331 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 332 pa_features_207, sizeof(pa_features_207)))); 333 334 /* Interrupt Control Presenters (ICP). One per core. */ 335 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 336 } 337 338 if (chip->ram_size) { 339 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 340 } 341 } 342 343 /* 344 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 345 */ 346 static const uint8_t pa_features_300[] = { 66, 0, 347 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 348 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 349 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 350 /* 6: DS207 */ 351 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 352 /* 16: Vector */ 353 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 354 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 356 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 357 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 358 /* 32: LE atomic, 34: EBB + ext EBB */ 359 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 360 /* 40: Radix MMU */ 361 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 362 /* 42: PM, 44: PC RA, 46: SC vec'd */ 363 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 364 /* 48: SIMD, 50: QP BFP, 52: String */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 366 /* 54: DecFP, 56: DecI, 58: SHA */ 367 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 368 /* 60: NM atomic, 62: RNG */ 369 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 370 }; 371 372 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 373 { 374 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 375 int i; 376 377 pnv_dt_xscom(chip, fdt, 0, 378 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 379 cpu_to_be64(PNV9_XSCOM_SIZE), 380 compat, sizeof(compat)); 381 382 for (i = 0; i < chip->nr_cores; i++) { 383 PnvCore *pnv_core = chip->cores[i]; 384 int offset; 385 386 offset = pnv_dt_core(chip, pnv_core, fdt); 387 388 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 389 pa_features_300, sizeof(pa_features_300)))); 390 } 391 392 if (chip->ram_size) { 393 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 394 } 395 396 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 397 } 398 399 /* 400 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 401 * always disables copy/paste. 402 */ 403 static const uint8_t pa_features_31[] = { 74, 0, 404 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 405 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 406 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 407 /* 6: DS207 */ 408 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 409 /* 16: Vector */ 410 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 411 /* 18: Vec. Scalar, 20: Vec. XOR */ 412 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 413 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 414 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 415 /* 32: LE atomic, 34: EBB + ext EBB */ 416 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 417 /* 40: Radix MMU */ 418 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 419 /* 42: PM, 44: PC RA, 46: SC vec'd */ 420 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 421 /* 48: SIMD, 50: QP BFP, 52: String */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 423 /* 54: DecFP, 56: DecI, 58: SHA */ 424 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 425 /* 60: NM atomic, 62: RNG */ 426 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 427 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 428 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 429 /* 72: [P]HASHST/[P]HASHCHK */ 430 0x80, 0x00, /* 72 - 73 */ 431 }; 432 433 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 434 { 435 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 436 int i; 437 438 pnv_dt_xscom(chip, fdt, 0, 439 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 440 cpu_to_be64(PNV10_XSCOM_SIZE), 441 compat, sizeof(compat)); 442 443 for (i = 0; i < chip->nr_cores; i++) { 444 PnvCore *pnv_core = chip->cores[i]; 445 int offset; 446 447 offset = pnv_dt_core(chip, pnv_core, fdt); 448 449 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 450 pa_features_31, sizeof(pa_features_31)))); 451 } 452 453 if (chip->ram_size) { 454 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 455 } 456 457 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 458 } 459 460 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 461 { 462 uint32_t io_base = d->ioport_id; 463 uint32_t io_regs[] = { 464 cpu_to_be32(1), 465 cpu_to_be32(io_base), 466 cpu_to_be32(2) 467 }; 468 char *name; 469 int node; 470 471 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 472 node = fdt_add_subnode(fdt, lpc_off, name); 473 _FDT(node); 474 g_free(name); 475 476 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 477 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 478 } 479 480 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 481 { 482 const char compatible[] = "ns16550\0pnpPNP,501"; 483 uint32_t io_base = d->ioport_id; 484 uint32_t io_regs[] = { 485 cpu_to_be32(1), 486 cpu_to_be32(io_base), 487 cpu_to_be32(8) 488 }; 489 uint32_t irq; 490 char *name; 491 int node; 492 493 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 494 495 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 496 node = fdt_add_subnode(fdt, lpc_off, name); 497 _FDT(node); 498 g_free(name); 499 500 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 501 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 502 sizeof(compatible)))); 503 504 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 505 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 506 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 507 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 508 fdt_get_phandle(fdt, lpc_off)))); 509 510 /* This is needed by Linux */ 511 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 512 } 513 514 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 515 { 516 const char compatible[] = "bt\0ipmi-bt"; 517 uint32_t io_base; 518 uint32_t io_regs[] = { 519 cpu_to_be32(1), 520 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 521 cpu_to_be32(3) 522 }; 523 uint32_t irq; 524 char *name; 525 int node; 526 527 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 528 io_regs[1] = cpu_to_be32(io_base); 529 530 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 531 532 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 533 node = fdt_add_subnode(fdt, lpc_off, name); 534 _FDT(node); 535 g_free(name); 536 537 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 538 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 539 sizeof(compatible)))); 540 541 /* Mark it as reserved to avoid Linux trying to claim it */ 542 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 543 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 544 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 545 fdt_get_phandle(fdt, lpc_off)))); 546 } 547 548 typedef struct ForeachPopulateArgs { 549 void *fdt; 550 int offset; 551 } ForeachPopulateArgs; 552 553 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 554 { 555 ForeachPopulateArgs *args = opaque; 556 ISADevice *d = ISA_DEVICE(dev); 557 558 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 559 pnv_dt_rtc(d, args->fdt, args->offset); 560 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 561 pnv_dt_serial(d, args->fdt, args->offset); 562 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 563 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 564 } else { 565 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 566 d->ioport_id); 567 } 568 569 return 0; 570 } 571 572 /* 573 * The default LPC bus of a multichip system is on chip 0. It's 574 * recognized by the firmware (skiboot) using a "primary" property. 575 */ 576 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 577 { 578 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 579 ForeachPopulateArgs args = { 580 .fdt = fdt, 581 .offset = isa_offset, 582 }; 583 uint32_t phandle; 584 585 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 586 587 phandle = qemu_fdt_alloc_phandle(fdt); 588 assert(phandle > 0); 589 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 590 591 /* 592 * ISA devices are not necessarily parented to the ISA bus so we 593 * can not use object_child_foreach() 594 */ 595 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 596 &args); 597 } 598 599 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 600 { 601 int off; 602 603 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 604 off = fdt_add_subnode(fdt, off, "power-mgt"); 605 606 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 607 } 608 609 static void *pnv_dt_create(MachineState *machine) 610 { 611 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 612 PnvMachineState *pnv = PNV_MACHINE(machine); 613 void *fdt; 614 char *buf; 615 int off; 616 int i; 617 618 fdt = g_malloc0(FDT_MAX_SIZE); 619 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 620 621 /* /qemu node */ 622 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 623 624 /* Root node */ 625 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 626 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 627 _FDT((fdt_setprop_string(fdt, 0, "model", 628 "IBM PowerNV (emulated by qemu)"))); 629 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 630 631 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 632 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 633 if (qemu_uuid_set) { 634 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 635 } 636 g_free(buf); 637 638 off = fdt_add_subnode(fdt, 0, "chosen"); 639 if (machine->kernel_cmdline) { 640 _FDT((fdt_setprop_string(fdt, off, "bootargs", 641 machine->kernel_cmdline))); 642 } 643 644 if (pnv->initrd_size) { 645 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 646 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 647 648 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 649 &start_prop, sizeof(start_prop)))); 650 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 651 &end_prop, sizeof(end_prop)))); 652 } 653 654 /* Populate device tree for each chip */ 655 for (i = 0; i < pnv->num_chips; i++) { 656 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 657 } 658 659 /* Populate ISA devices on chip 0 */ 660 pnv_dt_isa(pnv, fdt); 661 662 if (pnv->bmc) { 663 pnv_dt_bmc_sensors(pnv->bmc, fdt); 664 } 665 666 /* Create an extra node for power management on machines that support it */ 667 if (pmc->dt_power_mgt) { 668 pmc->dt_power_mgt(pnv, fdt); 669 } 670 671 return fdt; 672 } 673 674 static void pnv_powerdown_notify(Notifier *n, void *opaque) 675 { 676 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 677 678 if (pnv->bmc) { 679 pnv_bmc_powerdown(pnv->bmc); 680 } 681 } 682 683 static void pnv_reset(MachineState *machine, ShutdownCause reason) 684 { 685 PnvMachineState *pnv = PNV_MACHINE(machine); 686 IPMIBmc *bmc; 687 void *fdt; 688 689 qemu_devices_reset(reason); 690 691 /* 692 * The machine should provide by default an internal BMC simulator. 693 * If not, try to use the BMC device that was provided on the command 694 * line. 695 */ 696 bmc = pnv_bmc_find(&error_fatal); 697 if (!pnv->bmc) { 698 if (!bmc) { 699 if (!qtest_enabled()) { 700 warn_report("machine has no BMC device. Use '-device " 701 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 702 "to define one"); 703 } 704 } else { 705 pnv_bmc_set_pnor(bmc, pnv->pnor); 706 pnv->bmc = bmc; 707 } 708 } 709 710 fdt = pnv_dt_create(machine); 711 712 /* Pack resulting tree */ 713 _FDT((fdt_pack(fdt))); 714 715 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 716 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 717 718 /* 719 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 720 * the existing machine->fdt to avoid leaking it during 721 * a reset. 722 */ 723 g_free(machine->fdt); 724 machine->fdt = fdt; 725 } 726 727 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 728 { 729 Pnv8Chip *chip8 = PNV8_CHIP(chip); 730 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 731 732 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 733 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 734 } 735 736 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 737 { 738 Pnv8Chip *chip8 = PNV8_CHIP(chip); 739 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 740 741 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 742 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 743 } 744 745 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 746 { 747 Pnv9Chip *chip9 = PNV9_CHIP(chip); 748 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 749 750 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 751 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 752 } 753 754 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 755 { 756 Pnv10Chip *chip10 = PNV10_CHIP(chip); 757 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 758 759 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 760 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 761 } 762 763 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 764 { 765 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 766 } 767 768 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 769 { 770 Pnv8Chip *chip8 = PNV8_CHIP(chip); 771 int i; 772 773 ics_pic_print_info(&chip8->psi.ics, mon); 774 775 for (i = 0; i < chip8->num_phbs; i++) { 776 PnvPHB *phb = chip8->phbs[i]; 777 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 778 g_autoptr(GString) buf = g_string_new(""); 779 g_autoptr(HumanReadableText) info = NULL; 780 781 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 782 info = human_readable_text_from_str(buf); 783 monitor_puts(mon, info->human_readable_text); 784 785 ics_pic_print_info(&phb3->lsis, mon); 786 } 787 } 788 789 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 790 { 791 Monitor *mon = opaque; 792 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 793 794 if (!phb) { 795 return 0; 796 } 797 798 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 799 800 return 0; 801 } 802 803 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 804 { 805 Pnv9Chip *chip9 = PNV9_CHIP(chip); 806 807 pnv_xive_pic_print_info(&chip9->xive, mon); 808 pnv_psi_pic_print_info(&chip9->psi, mon); 809 810 object_child_foreach_recursive(OBJECT(chip), 811 pnv_chip_power9_pic_print_info_child, mon); 812 } 813 814 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 815 uint32_t core_id) 816 { 817 return PNV_XSCOM_EX_BASE(core_id); 818 } 819 820 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 821 uint32_t core_id) 822 { 823 return PNV9_XSCOM_EC_BASE(core_id); 824 } 825 826 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 827 uint32_t core_id) 828 { 829 return PNV10_XSCOM_EC_BASE(core_id); 830 } 831 832 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 833 { 834 PowerPCCPUClass *ppc_default = 835 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 836 PowerPCCPUClass *ppc = 837 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 838 839 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 840 } 841 842 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 843 { 844 ISADevice *dev = isa_new("isa-ipmi-bt"); 845 846 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 847 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 848 isa_realize_and_unref(dev, bus, &error_fatal); 849 } 850 851 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 852 { 853 Pnv10Chip *chip10 = PNV10_CHIP(chip); 854 855 pnv_xive2_pic_print_info(&chip10->xive, mon); 856 pnv_psi_pic_print_info(&chip10->psi, mon); 857 858 object_child_foreach_recursive(OBJECT(chip), 859 pnv_chip_power9_pic_print_info_child, mon); 860 } 861 862 /* Always give the first 1GB to chip 0 else we won't boot */ 863 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 864 { 865 MachineState *machine = MACHINE(pnv); 866 uint64_t ram_per_chip; 867 868 assert(machine->ram_size >= 1 * GiB); 869 870 ram_per_chip = machine->ram_size / pnv->num_chips; 871 if (ram_per_chip >= 1 * GiB) { 872 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 873 } 874 875 assert(pnv->num_chips > 1); 876 877 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 878 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 879 } 880 881 static void pnv_init(MachineState *machine) 882 { 883 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 884 PnvMachineState *pnv = PNV_MACHINE(machine); 885 MachineClass *mc = MACHINE_GET_CLASS(machine); 886 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 887 char *fw_filename; 888 long fw_size; 889 uint64_t chip_ram_start = 0; 890 int i; 891 char *chip_typename; 892 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 893 DeviceState *dev; 894 895 if (kvm_enabled()) { 896 error_report("machine %s does not support the KVM accelerator", 897 mc->name); 898 exit(EXIT_FAILURE); 899 } 900 901 /* allocate RAM */ 902 if (machine->ram_size < mc->default_ram_size) { 903 char *sz = size_to_str(mc->default_ram_size); 904 error_report("Invalid RAM size, should be bigger than %s", sz); 905 g_free(sz); 906 exit(EXIT_FAILURE); 907 } 908 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 909 910 /* 911 * Create our simple PNOR device 912 */ 913 dev = qdev_new(TYPE_PNV_PNOR); 914 if (pnor) { 915 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 916 } 917 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 918 pnv->pnor = PNV_PNOR(dev); 919 920 /* load skiboot firmware */ 921 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 922 if (!fw_filename) { 923 error_report("Could not find OPAL firmware '%s'", bios_name); 924 exit(1); 925 } 926 927 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 928 if (fw_size < 0) { 929 error_report("Could not load OPAL firmware '%s'", fw_filename); 930 exit(1); 931 } 932 g_free(fw_filename); 933 934 /* load kernel */ 935 if (machine->kernel_filename) { 936 long kernel_size; 937 938 kernel_size = load_image_targphys(machine->kernel_filename, 939 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 940 if (kernel_size < 0) { 941 error_report("Could not load kernel '%s'", 942 machine->kernel_filename); 943 exit(1); 944 } 945 } 946 947 /* load initrd */ 948 if (machine->initrd_filename) { 949 pnv->initrd_base = INITRD_LOAD_ADDR; 950 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 951 pnv->initrd_base, INITRD_MAX_SIZE); 952 if (pnv->initrd_size < 0) { 953 error_report("Could not load initial ram disk '%s'", 954 machine->initrd_filename); 955 exit(1); 956 } 957 } 958 959 /* MSIs are supported on this platform */ 960 msi_nonbroken = true; 961 962 /* 963 * Check compatibility of the specified CPU with the machine 964 * default. 965 */ 966 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 967 error_report("invalid CPU model '%s' for %s machine", 968 machine->cpu_type, mc->name); 969 exit(1); 970 } 971 972 /* Create the processor chips */ 973 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 974 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 975 i, machine->cpu_type); 976 if (!object_class_by_name(chip_typename)) { 977 error_report("invalid chip model '%.*s' for %s machine", 978 i, machine->cpu_type, mc->name); 979 exit(1); 980 } 981 982 pnv->num_chips = 983 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 984 985 if (machine->smp.threads > 8) { 986 error_report("Cannot support more than 8 threads/core " 987 "on a powernv machine"); 988 exit(1); 989 } 990 if (!is_power_of_2(machine->smp.threads)) { 991 error_report("Cannot support %d threads/core on a powernv" 992 "machine because it must be a power of 2", 993 machine->smp.threads); 994 exit(1); 995 } 996 /* 997 * TODO: should we decide on how many chips we can create based 998 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 999 */ 1000 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1001 error_report("invalid number of chips: '%d'", pnv->num_chips); 1002 error_printf( 1003 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1004 exit(1); 1005 } 1006 1007 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1008 for (i = 0; i < pnv->num_chips; i++) { 1009 char chip_name[32]; 1010 Object *chip = OBJECT(qdev_new(chip_typename)); 1011 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1012 1013 pnv->chips[i] = PNV_CHIP(chip); 1014 1015 /* Distribute RAM among the chips */ 1016 object_property_set_int(chip, "ram-start", chip_ram_start, 1017 &error_fatal); 1018 object_property_set_int(chip, "ram-size", chip_ram_size, 1019 &error_fatal); 1020 chip_ram_start += chip_ram_size; 1021 1022 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1023 object_property_add_child(OBJECT(pnv), chip_name, chip); 1024 object_property_set_int(chip, "chip-id", i, &error_fatal); 1025 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1026 &error_fatal); 1027 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1028 &error_fatal); 1029 /* 1030 * The POWER8 machine use the XICS interrupt interface. 1031 * Propagate the XICS fabric to the chip and its controllers. 1032 */ 1033 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1034 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1035 } 1036 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1037 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1038 &error_abort); 1039 } 1040 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1041 } 1042 g_free(chip_typename); 1043 1044 /* Instantiate ISA bus on chip 0 */ 1045 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1046 1047 /* Create serial port */ 1048 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1049 1050 /* Create an RTC ISA device too */ 1051 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1052 1053 /* 1054 * Create the machine BMC simulator and the IPMI BT device for 1055 * communication with the BMC 1056 */ 1057 if (defaults_enabled()) { 1058 pnv->bmc = pnv_bmc_create(pnv->pnor); 1059 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1060 } 1061 1062 /* 1063 * The PNOR is mapped on the LPC FW address space by the BMC. 1064 * Since we can not reach the remote BMC machine with LPC memops, 1065 * map it always for now. 1066 */ 1067 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1068 &pnv->pnor->mmio); 1069 1070 /* 1071 * OpenPOWER systems use a IPMI SEL Event message to notify the 1072 * host to powerdown 1073 */ 1074 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1075 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1076 1077 /* 1078 * Create/Connect any machine-specific I2C devices 1079 */ 1080 if (pmc->i2c_init) { 1081 pmc->i2c_init(pnv); 1082 } 1083 } 1084 1085 /* 1086 * 0:21 Reserved - Read as zeros 1087 * 22:24 Chip ID 1088 * 25:28 Core number 1089 * 29:31 Thread ID 1090 */ 1091 static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, 1092 uint32_t thread_id) 1093 { 1094 return (chip->chip_id << 7) | (core_id << 3) | thread_id; 1095 } 1096 1097 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1098 Error **errp) 1099 { 1100 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1101 Error *local_err = NULL; 1102 Object *obj; 1103 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1104 1105 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1106 if (local_err) { 1107 error_propagate(errp, local_err); 1108 return; 1109 } 1110 1111 pnv_cpu->intc = obj; 1112 } 1113 1114 1115 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1116 { 1117 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1118 1119 icp_reset(ICP(pnv_cpu->intc)); 1120 } 1121 1122 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1123 { 1124 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1125 1126 icp_destroy(ICP(pnv_cpu->intc)); 1127 pnv_cpu->intc = NULL; 1128 } 1129 1130 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1131 Monitor *mon) 1132 { 1133 g_autoptr(GString) buf = g_string_new(""); 1134 g_autoptr(HumanReadableText) info = NULL; 1135 1136 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1137 1138 info = human_readable_text_from_str(buf); 1139 monitor_puts(mon, info->human_readable_text); 1140 } 1141 1142 /* 1143 * 0:48 Reserved - Read as zeroes 1144 * 49:52 Node ID 1145 * 53:55 Chip ID 1146 * 56 Reserved - Read as zero 1147 * 57:61 Core number 1148 * 62:63 Thread ID 1149 * 1150 * We only care about the lower bits. uint32_t is fine for the moment. 1151 */ 1152 static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, 1153 uint32_t thread_id) 1154 { 1155 if (chip->nr_threads == 8) { 1156 return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) | 1157 (thread_id >> 1); 1158 } else { 1159 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1160 } 1161 } 1162 1163 /* 1164 * 0:48 Reserved - Read as zeroes 1165 * 49:52 Node ID 1166 * 53:55 Chip ID 1167 * 56 Reserved - Read as zero 1168 * 57:59 Quad ID 1169 * 60 Core Chiplet Pair ID 1170 * 61:63 Thread/Core Chiplet ID t0-t2 1171 * 1172 * We only care about the lower bits. uint32_t is fine for the moment. 1173 */ 1174 static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, 1175 uint32_t thread_id) 1176 { 1177 if (chip->nr_threads == 8) { 1178 return (chip->chip_id << 8) | ((core_id / 4) << 4) | 1179 ((core_id % 2) << 3) | thread_id; 1180 } else { 1181 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1182 } 1183 } 1184 1185 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1186 Error **errp) 1187 { 1188 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1189 Error *local_err = NULL; 1190 Object *obj; 1191 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1192 1193 /* 1194 * The core creates its interrupt presenter but the XIVE interrupt 1195 * controller object is initialized afterwards. Hopefully, it's 1196 * only used at runtime. 1197 */ 1198 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1199 &local_err); 1200 if (local_err) { 1201 error_propagate(errp, local_err); 1202 return; 1203 } 1204 1205 pnv_cpu->intc = obj; 1206 } 1207 1208 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1209 { 1210 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1211 1212 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1213 } 1214 1215 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1216 { 1217 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1218 1219 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1220 pnv_cpu->intc = NULL; 1221 } 1222 1223 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1224 Monitor *mon) 1225 { 1226 g_autoptr(GString) buf = g_string_new(""); 1227 g_autoptr(HumanReadableText) info = NULL; 1228 1229 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1230 1231 info = human_readable_text_from_str(buf); 1232 monitor_puts(mon, info->human_readable_text); 1233 } 1234 1235 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1236 Error **errp) 1237 { 1238 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1239 Error *local_err = NULL; 1240 Object *obj; 1241 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1242 1243 /* 1244 * The core creates its interrupt presenter but the XIVE2 interrupt 1245 * controller object is initialized afterwards. Hopefully, it's 1246 * only used at runtime. 1247 */ 1248 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1249 &local_err); 1250 if (local_err) { 1251 error_propagate(errp, local_err); 1252 return; 1253 } 1254 1255 pnv_cpu->intc = obj; 1256 } 1257 1258 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1259 { 1260 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1261 1262 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1263 } 1264 1265 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1266 { 1267 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1268 1269 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1270 pnv_cpu->intc = NULL; 1271 } 1272 1273 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1274 Monitor *mon) 1275 { 1276 g_autoptr(GString) buf = g_string_new(""); 1277 g_autoptr(HumanReadableText) info = NULL; 1278 1279 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1280 1281 info = human_readable_text_from_str(buf); 1282 monitor_puts(mon, info->human_readable_text); 1283 } 1284 1285 /* 1286 * Allowed core identifiers on a POWER8 Processor Chip : 1287 * 1288 * <EX0 reserved> 1289 * EX1 - Venice only 1290 * EX2 - Venice only 1291 * EX3 - Venice only 1292 * EX4 1293 * EX5 1294 * EX6 1295 * <EX7,8 reserved> <reserved> 1296 * EX9 - Venice only 1297 * EX10 - Venice only 1298 * EX11 - Venice only 1299 * EX12 1300 * EX13 1301 * EX14 1302 * <EX15 reserved> 1303 */ 1304 #define POWER8E_CORE_MASK (0x7070ull) 1305 #define POWER8_CORE_MASK (0x7e7eull) 1306 1307 /* 1308 * POWER9 has 24 cores, ids starting at 0x0 1309 */ 1310 #define POWER9_CORE_MASK (0xffffffffffffffull) 1311 1312 1313 #define POWER10_CORE_MASK (0xffffffffffffffull) 1314 1315 static void pnv_chip_power8_instance_init(Object *obj) 1316 { 1317 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1318 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1319 int i; 1320 1321 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1322 (Object **)&chip8->xics, 1323 object_property_allow_set_link, 1324 OBJ_PROP_LINK_STRONG); 1325 1326 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1327 1328 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1329 1330 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1331 1332 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1333 1334 if (defaults_enabled()) { 1335 chip8->num_phbs = pcc->num_phbs; 1336 1337 for (i = 0; i < chip8->num_phbs; i++) { 1338 Object *phb = object_new(TYPE_PNV_PHB); 1339 1340 /* 1341 * We need the chip to parent the PHB to allow the DT 1342 * to build correctly (via pnv_xscom_dt()). 1343 * 1344 * TODO: the PHB should be parented by a PEC device that, at 1345 * this moment, is not modelled powernv8/phb3. 1346 */ 1347 object_property_add_child(obj, "phb[*]", phb); 1348 chip8->phbs[i] = PNV_PHB(phb); 1349 } 1350 } 1351 1352 } 1353 1354 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1355 { 1356 PnvChip *chip = PNV_CHIP(chip8); 1357 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1358 int i, j; 1359 char *name; 1360 1361 name = g_strdup_printf("icp-%x", chip->chip_id); 1362 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1363 g_free(name); 1364 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1365 &chip8->icp_mmio); 1366 1367 /* Map the ICP registers for each thread */ 1368 for (i = 0; i < chip->nr_cores; i++) { 1369 PnvCore *pnv_core = chip->cores[i]; 1370 int core_hwid = CPU_CORE(pnv_core)->core_id; 1371 1372 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1373 uint32_t pir = pcc->chip_pir(chip, core_hwid, j); 1374 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1375 1376 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1377 &icp->mmio); 1378 } 1379 } 1380 } 1381 1382 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1383 { 1384 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1385 PnvChip *chip = PNV_CHIP(dev); 1386 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1387 Pnv8Psi *psi8 = &chip8->psi; 1388 Error *local_err = NULL; 1389 int i; 1390 1391 assert(chip8->xics); 1392 1393 /* XSCOM bridge is first */ 1394 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1395 1396 pcc->parent_realize(dev, &local_err); 1397 if (local_err) { 1398 error_propagate(errp, local_err); 1399 return; 1400 } 1401 1402 /* Processor Service Interface (PSI) Host Bridge */ 1403 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1404 &error_fatal); 1405 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1406 OBJECT(chip8->xics), &error_abort); 1407 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1408 return; 1409 } 1410 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1411 &PNV_PSI(psi8)->xscom_regs); 1412 1413 /* Create LPC controller */ 1414 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1415 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1416 1417 chip->fw_mr = &chip8->lpc.isa_fw; 1418 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1419 (uint64_t) PNV_XSCOM_BASE(chip), 1420 PNV_XSCOM_LPC_BASE); 1421 1422 /* 1423 * Interrupt Management Area. This is the memory region holding 1424 * all the Interrupt Control Presenter (ICP) registers 1425 */ 1426 pnv_chip_icp_realize(chip8, &local_err); 1427 if (local_err) { 1428 error_propagate(errp, local_err); 1429 return; 1430 } 1431 1432 /* Create the simplified OCC model */ 1433 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1434 return; 1435 } 1436 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1437 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1438 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1439 1440 /* OCC SRAM model */ 1441 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1442 &chip8->occ.sram_regs); 1443 1444 /* HOMER */ 1445 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1446 &error_abort); 1447 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1448 return; 1449 } 1450 /* Homer Xscom region */ 1451 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1452 1453 /* Homer mmio region */ 1454 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1455 &chip8->homer.regs); 1456 1457 /* PHB controllers */ 1458 for (i = 0; i < chip8->num_phbs; i++) { 1459 PnvPHB *phb = chip8->phbs[i]; 1460 1461 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1462 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1463 &error_fatal); 1464 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1465 &error_fatal); 1466 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1467 return; 1468 } 1469 } 1470 } 1471 1472 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1473 { 1474 addr &= (PNV_XSCOM_SIZE - 1); 1475 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1476 } 1477 1478 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1479 { 1480 DeviceClass *dc = DEVICE_CLASS(klass); 1481 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1482 1483 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1484 k->cores_mask = POWER8E_CORE_MASK; 1485 k->num_phbs = 3; 1486 k->chip_pir = pnv_chip_pir_p8; 1487 k->intc_create = pnv_chip_power8_intc_create; 1488 k->intc_reset = pnv_chip_power8_intc_reset; 1489 k->intc_destroy = pnv_chip_power8_intc_destroy; 1490 k->intc_print_info = pnv_chip_power8_intc_print_info; 1491 k->isa_create = pnv_chip_power8_isa_create; 1492 k->dt_populate = pnv_chip_power8_dt_populate; 1493 k->pic_print_info = pnv_chip_power8_pic_print_info; 1494 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1495 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1496 dc->desc = "PowerNV Chip POWER8E"; 1497 1498 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1499 &k->parent_realize); 1500 } 1501 1502 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1503 { 1504 DeviceClass *dc = DEVICE_CLASS(klass); 1505 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1506 1507 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1508 k->cores_mask = POWER8_CORE_MASK; 1509 k->num_phbs = 3; 1510 k->chip_pir = pnv_chip_pir_p8; 1511 k->intc_create = pnv_chip_power8_intc_create; 1512 k->intc_reset = pnv_chip_power8_intc_reset; 1513 k->intc_destroy = pnv_chip_power8_intc_destroy; 1514 k->intc_print_info = pnv_chip_power8_intc_print_info; 1515 k->isa_create = pnv_chip_power8_isa_create; 1516 k->dt_populate = pnv_chip_power8_dt_populate; 1517 k->pic_print_info = pnv_chip_power8_pic_print_info; 1518 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1519 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1520 dc->desc = "PowerNV Chip POWER8"; 1521 1522 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1523 &k->parent_realize); 1524 } 1525 1526 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1527 { 1528 DeviceClass *dc = DEVICE_CLASS(klass); 1529 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1530 1531 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1532 k->cores_mask = POWER8_CORE_MASK; 1533 k->num_phbs = 4; 1534 k->chip_pir = pnv_chip_pir_p8; 1535 k->intc_create = pnv_chip_power8_intc_create; 1536 k->intc_reset = pnv_chip_power8_intc_reset; 1537 k->intc_destroy = pnv_chip_power8_intc_destroy; 1538 k->intc_print_info = pnv_chip_power8_intc_print_info; 1539 k->isa_create = pnv_chip_power8nvl_isa_create; 1540 k->dt_populate = pnv_chip_power8_dt_populate; 1541 k->pic_print_info = pnv_chip_power8_pic_print_info; 1542 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1543 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1544 dc->desc = "PowerNV Chip POWER8NVL"; 1545 1546 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1547 &k->parent_realize); 1548 } 1549 1550 static void pnv_chip_power9_instance_init(Object *obj) 1551 { 1552 PnvChip *chip = PNV_CHIP(obj); 1553 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1554 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1555 int i; 1556 1557 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1558 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1559 "xive-fabric"); 1560 1561 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1562 1563 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1564 1565 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1566 1567 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1568 1569 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1570 1571 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1572 1573 /* Number of PECs is the chip default */ 1574 chip->num_pecs = pcc->num_pecs; 1575 1576 for (i = 0; i < chip->num_pecs; i++) { 1577 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1578 TYPE_PNV_PHB4_PEC); 1579 } 1580 1581 for (i = 0; i < pcc->i2c_num_engines; i++) { 1582 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1583 } 1584 } 1585 1586 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1587 PnvCore *pnv_core, 1588 const char *type) 1589 { 1590 char eq_name[32]; 1591 int core_id = CPU_CORE(pnv_core)->core_id; 1592 1593 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1594 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1595 sizeof(*eq), type, 1596 &error_fatal, NULL); 1597 1598 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1599 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1600 } 1601 1602 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1603 { 1604 PnvChip *chip = PNV_CHIP(chip9); 1605 int i; 1606 1607 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1608 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1609 1610 for (i = 0; i < chip9->nr_quads; i++) { 1611 PnvQuad *eq = &chip9->quads[i]; 1612 1613 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1614 PNV_QUAD_TYPE_NAME("power9")); 1615 1616 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1617 &eq->xscom_regs); 1618 } 1619 } 1620 1621 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1622 { 1623 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1624 int i; 1625 1626 for (i = 0; i < chip->num_pecs; i++) { 1627 PnvPhb4PecState *pec = &chip9->pecs[i]; 1628 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1629 uint32_t pec_nest_base; 1630 uint32_t pec_pci_base; 1631 1632 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1633 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1634 &error_fatal); 1635 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1636 &error_fatal); 1637 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1638 return; 1639 } 1640 1641 pec_nest_base = pecc->xscom_nest_base(pec); 1642 pec_pci_base = pecc->xscom_pci_base(pec); 1643 1644 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1645 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1646 } 1647 } 1648 1649 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1650 { 1651 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1652 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1653 PnvChip *chip = PNV_CHIP(dev); 1654 Pnv9Psi *psi9 = &chip9->psi; 1655 Error *local_err = NULL; 1656 int i; 1657 1658 /* XSCOM bridge is first */ 1659 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1660 1661 pcc->parent_realize(dev, &local_err); 1662 if (local_err) { 1663 error_propagate(errp, local_err); 1664 return; 1665 } 1666 1667 pnv_chip_quad_realize(chip9, &local_err); 1668 if (local_err) { 1669 error_propagate(errp, local_err); 1670 return; 1671 } 1672 1673 /* XIVE interrupt controller (POWER9) */ 1674 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1675 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1676 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1677 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1678 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1679 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1680 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1681 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1682 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1683 &error_abort); 1684 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1685 return; 1686 } 1687 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1688 &chip9->xive.xscom_regs); 1689 1690 /* Processor Service Interface (PSI) Host Bridge */ 1691 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1692 &error_fatal); 1693 /* This is the only device with 4k ESB pages */ 1694 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1695 &error_fatal); 1696 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1697 return; 1698 } 1699 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1700 &PNV_PSI(psi9)->xscom_regs); 1701 1702 /* LPC */ 1703 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1704 return; 1705 } 1706 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1707 &chip9->lpc.xscom_regs); 1708 1709 chip->fw_mr = &chip9->lpc.isa_fw; 1710 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1711 (uint64_t) PNV9_LPCM_BASE(chip)); 1712 1713 /* ChipTOD */ 1714 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1715 chip->chip_id == 0, &error_abort); 1716 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1717 chip->chip_id == 1, &error_abort); 1718 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1719 &error_abort); 1720 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1721 return; 1722 } 1723 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1724 &chip9->chiptod.xscom_regs); 1725 1726 /* Create the simplified OCC model */ 1727 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1728 return; 1729 } 1730 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1731 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1732 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1733 1734 /* OCC SRAM model */ 1735 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1736 &chip9->occ.sram_regs); 1737 1738 /* SBE */ 1739 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1740 return; 1741 } 1742 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1743 &chip9->sbe.xscom_ctrl_regs); 1744 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1745 &chip9->sbe.xscom_mbox_regs); 1746 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1747 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1748 1749 /* HOMER */ 1750 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1751 &error_abort); 1752 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1753 return; 1754 } 1755 /* Homer Xscom region */ 1756 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1757 1758 /* Homer mmio region */ 1759 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1760 &chip9->homer.regs); 1761 1762 /* PEC PHBs */ 1763 pnv_chip_power9_pec_realize(chip, &local_err); 1764 if (local_err) { 1765 error_propagate(errp, local_err); 1766 return; 1767 } 1768 1769 /* 1770 * I2C 1771 */ 1772 for (i = 0; i < pcc->i2c_num_engines; i++) { 1773 Object *obj = OBJECT(&chip9->i2c[i]); 1774 1775 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1776 object_property_set_int(obj, "num-busses", 1777 pcc->i2c_ports_per_engine[i], 1778 &error_fatal); 1779 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1780 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1781 return; 1782 } 1783 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1784 (chip9->i2c[i].engine - 1) * 1785 PNV9_XSCOM_I2CM_SIZE, 1786 &chip9->i2c[i].xscom_regs); 1787 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1788 qdev_get_gpio_in(DEVICE(psi9), 1789 PSIHB9_IRQ_SBE_I2C)); 1790 } 1791 } 1792 1793 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1794 { 1795 addr &= (PNV9_XSCOM_SIZE - 1); 1796 return addr >> 3; 1797 } 1798 1799 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1800 { 1801 DeviceClass *dc = DEVICE_CLASS(klass); 1802 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1803 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1804 1805 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1806 k->cores_mask = POWER9_CORE_MASK; 1807 k->chip_pir = pnv_chip_pir_p9; 1808 k->intc_create = pnv_chip_power9_intc_create; 1809 k->intc_reset = pnv_chip_power9_intc_reset; 1810 k->intc_destroy = pnv_chip_power9_intc_destroy; 1811 k->intc_print_info = pnv_chip_power9_intc_print_info; 1812 k->isa_create = pnv_chip_power9_isa_create; 1813 k->dt_populate = pnv_chip_power9_dt_populate; 1814 k->pic_print_info = pnv_chip_power9_pic_print_info; 1815 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1816 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1817 dc->desc = "PowerNV Chip POWER9"; 1818 k->num_pecs = PNV9_CHIP_MAX_PEC; 1819 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1820 k->i2c_ports_per_engine = i2c_ports_per_engine; 1821 1822 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1823 &k->parent_realize); 1824 } 1825 1826 static void pnv_chip_power10_instance_init(Object *obj) 1827 { 1828 PnvChip *chip = PNV_CHIP(obj); 1829 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1830 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1831 int i; 1832 1833 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1834 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1835 "xive-fabric"); 1836 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1837 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1838 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1839 TYPE_PNV10_CHIPTOD); 1840 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1841 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1842 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1843 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1844 TYPE_PNV_N1_CHIPLET); 1845 1846 chip->num_pecs = pcc->num_pecs; 1847 1848 for (i = 0; i < chip->num_pecs; i++) { 1849 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1850 TYPE_PNV_PHB5_PEC); 1851 } 1852 1853 for (i = 0; i < pcc->i2c_num_engines; i++) { 1854 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1855 } 1856 } 1857 1858 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1859 { 1860 PnvChip *chip = PNV_CHIP(chip10); 1861 int i; 1862 1863 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1864 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1865 1866 for (i = 0; i < chip10->nr_quads; i++) { 1867 PnvQuad *eq = &chip10->quads[i]; 1868 1869 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1870 PNV_QUAD_TYPE_NAME("power10")); 1871 1872 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1873 &eq->xscom_regs); 1874 1875 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1876 &eq->xscom_qme_regs); 1877 } 1878 } 1879 1880 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1881 { 1882 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1883 int i; 1884 1885 for (i = 0; i < chip->num_pecs; i++) { 1886 PnvPhb4PecState *pec = &chip10->pecs[i]; 1887 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1888 uint32_t pec_nest_base; 1889 uint32_t pec_pci_base; 1890 1891 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1892 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1893 &error_fatal); 1894 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1895 &error_fatal); 1896 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1897 return; 1898 } 1899 1900 pec_nest_base = pecc->xscom_nest_base(pec); 1901 pec_pci_base = pecc->xscom_pci_base(pec); 1902 1903 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1904 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1905 } 1906 } 1907 1908 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1909 { 1910 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1911 PnvChip *chip = PNV_CHIP(dev); 1912 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1913 Error *local_err = NULL; 1914 int i; 1915 1916 /* XSCOM bridge is first */ 1917 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1918 1919 pcc->parent_realize(dev, &local_err); 1920 if (local_err) { 1921 error_propagate(errp, local_err); 1922 return; 1923 } 1924 1925 pnv_chip_power10_quad_realize(chip10, &local_err); 1926 if (local_err) { 1927 error_propagate(errp, local_err); 1928 return; 1929 } 1930 1931 /* XIVE2 interrupt controller (POWER10) */ 1932 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1933 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1934 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1935 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1936 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1937 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1938 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1939 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1940 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1941 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1942 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1943 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1944 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1945 &error_abort); 1946 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1947 return; 1948 } 1949 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1950 &chip10->xive.xscom_regs); 1951 1952 /* Processor Service Interface (PSI) Host Bridge */ 1953 object_property_set_int(OBJECT(&chip10->psi), "bar", 1954 PNV10_PSIHB_BASE(chip), &error_fatal); 1955 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1956 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1957 &error_fatal); 1958 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1959 return; 1960 } 1961 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1962 &PNV_PSI(&chip10->psi)->xscom_regs); 1963 1964 /* LPC */ 1965 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1966 return; 1967 } 1968 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1969 &chip10->lpc.xscom_regs); 1970 1971 chip->fw_mr = &chip10->lpc.isa_fw; 1972 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1973 (uint64_t) PNV10_LPCM_BASE(chip)); 1974 1975 /* ChipTOD */ 1976 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1977 chip->chip_id == 0, &error_abort); 1978 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1979 chip->chip_id == 1, &error_abort); 1980 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 1981 &error_abort); 1982 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 1983 return; 1984 } 1985 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 1986 &chip10->chiptod.xscom_regs); 1987 1988 /* Create the simplified OCC model */ 1989 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1990 return; 1991 } 1992 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1993 &chip10->occ.xscom_regs); 1994 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1995 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1996 1997 /* OCC SRAM model */ 1998 memory_region_add_subregion(get_system_memory(), 1999 PNV10_OCC_SENSOR_BASE(chip), 2000 &chip10->occ.sram_regs); 2001 2002 /* SBE */ 2003 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2004 return; 2005 } 2006 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2007 &chip10->sbe.xscom_ctrl_regs); 2008 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2009 &chip10->sbe.xscom_mbox_regs); 2010 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2011 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2012 2013 /* HOMER */ 2014 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2015 &error_abort); 2016 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2017 return; 2018 } 2019 /* Homer Xscom region */ 2020 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2021 &chip10->homer.pba_regs); 2022 2023 /* Homer mmio region */ 2024 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2025 &chip10->homer.regs); 2026 2027 /* N1 chiplet */ 2028 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2029 return; 2030 } 2031 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2032 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2033 2034 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2035 &chip10->n1_chiplet.xscom_pb_eq_mr); 2036 2037 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2038 &chip10->n1_chiplet.xscom_pb_es_mr); 2039 2040 /* PHBs */ 2041 pnv_chip_power10_phb_realize(chip, &local_err); 2042 if (local_err) { 2043 error_propagate(errp, local_err); 2044 return; 2045 } 2046 2047 2048 /* 2049 * I2C 2050 */ 2051 for (i = 0; i < pcc->i2c_num_engines; i++) { 2052 Object *obj = OBJECT(&chip10->i2c[i]); 2053 2054 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2055 object_property_set_int(obj, "num-busses", 2056 pcc->i2c_ports_per_engine[i], 2057 &error_fatal); 2058 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2059 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2060 return; 2061 } 2062 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2063 (chip10->i2c[i].engine - 1) * 2064 PNV10_XSCOM_I2CM_SIZE, 2065 &chip10->i2c[i].xscom_regs); 2066 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2067 qdev_get_gpio_in(DEVICE(&chip10->psi), 2068 PSIHB9_IRQ_SBE_I2C)); 2069 } 2070 2071 } 2072 2073 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2074 { 2075 int i; 2076 for (i = 0; i < pnv->num_chips; i++) { 2077 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2078 2079 /* 2080 * Add a PCA9552 I2C device for PCIe hotplug control 2081 * to engine 2, bus 1, address 0x63 2082 */ 2083 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2084 "pca9552", 0x63); 2085 2086 /* 2087 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2088 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2089 * after hypervisor code sets a SLOTx_EN pin high. 2090 */ 2091 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2092 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2093 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2094 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2095 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2096 2097 /* 2098 * Add a PCA9554 I2C device for cable card presence detection 2099 * to engine 2, bus 1, address 0x25 2100 */ 2101 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2102 } 2103 } 2104 2105 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2106 { 2107 addr &= (PNV10_XSCOM_SIZE - 1); 2108 return addr >> 3; 2109 } 2110 2111 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2112 { 2113 DeviceClass *dc = DEVICE_CLASS(klass); 2114 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2115 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2116 2117 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 2118 k->cores_mask = POWER10_CORE_MASK; 2119 k->chip_pir = pnv_chip_pir_p10; 2120 k->intc_create = pnv_chip_power10_intc_create; 2121 k->intc_reset = pnv_chip_power10_intc_reset; 2122 k->intc_destroy = pnv_chip_power10_intc_destroy; 2123 k->intc_print_info = pnv_chip_power10_intc_print_info; 2124 k->isa_create = pnv_chip_power10_isa_create; 2125 k->dt_populate = pnv_chip_power10_dt_populate; 2126 k->pic_print_info = pnv_chip_power10_pic_print_info; 2127 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2128 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2129 dc->desc = "PowerNV Chip POWER10"; 2130 k->num_pecs = PNV10_CHIP_MAX_PEC; 2131 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2132 k->i2c_ports_per_engine = i2c_ports_per_engine; 2133 2134 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2135 &k->parent_realize); 2136 } 2137 2138 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2139 { 2140 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2141 int cores_max; 2142 2143 /* 2144 * No custom mask for this chip, let's use the default one from * 2145 * the chip class 2146 */ 2147 if (!chip->cores_mask) { 2148 chip->cores_mask = pcc->cores_mask; 2149 } 2150 2151 /* filter alien core ids ! some are reserved */ 2152 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2153 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2154 chip->cores_mask); 2155 return; 2156 } 2157 chip->cores_mask &= pcc->cores_mask; 2158 2159 /* now that we have a sane layout, let check the number of cores */ 2160 cores_max = ctpop64(chip->cores_mask); 2161 if (chip->nr_cores > cores_max) { 2162 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2163 cores_max); 2164 return; 2165 } 2166 } 2167 2168 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2169 { 2170 Error *error = NULL; 2171 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2172 const char *typename = pnv_chip_core_typename(chip); 2173 int i, core_hwid; 2174 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2175 2176 if (!object_class_by_name(typename)) { 2177 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2178 return; 2179 } 2180 2181 /* Cores */ 2182 pnv_chip_core_sanitize(chip, &error); 2183 if (error) { 2184 error_propagate(errp, error); 2185 return; 2186 } 2187 2188 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2189 2190 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2191 && (i < chip->nr_cores); core_hwid++) { 2192 char core_name[32]; 2193 PnvCore *pnv_core; 2194 uint64_t xscom_core_base; 2195 2196 if (!(chip->cores_mask & (1ull << core_hwid))) { 2197 continue; 2198 } 2199 2200 pnv_core = PNV_CORE(object_new(typename)); 2201 2202 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2203 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2204 chip->cores[i] = pnv_core; 2205 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2206 chip->nr_threads, &error_fatal); 2207 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2208 core_hwid, &error_fatal); 2209 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2210 &error_fatal); 2211 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2212 &error_fatal); 2213 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2214 &error_abort); 2215 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2216 2217 /* Each core has an XSCOM MMIO region */ 2218 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2219 2220 pnv_xscom_add_subregion(chip, xscom_core_base, 2221 &pnv_core->xscom_regs); 2222 i++; 2223 } 2224 } 2225 2226 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2227 { 2228 PnvChip *chip = PNV_CHIP(dev); 2229 Error *error = NULL; 2230 2231 /* Cores */ 2232 pnv_chip_core_realize(chip, &error); 2233 if (error) { 2234 error_propagate(errp, error); 2235 return; 2236 } 2237 } 2238 2239 static Property pnv_chip_properties[] = { 2240 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2241 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2242 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2243 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2244 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2245 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2246 DEFINE_PROP_END_OF_LIST(), 2247 }; 2248 2249 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2250 { 2251 DeviceClass *dc = DEVICE_CLASS(klass); 2252 2253 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2254 dc->realize = pnv_chip_realize; 2255 device_class_set_props(dc, pnv_chip_properties); 2256 dc->desc = "PowerNV Chip"; 2257 } 2258 2259 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2260 { 2261 int i; 2262 2263 for (i = 0; i < chip->nr_cores; i++) { 2264 PnvCore *pc = chip->cores[i]; 2265 CPUCore *cc = CPU_CORE(pc); 2266 2267 if (cc->core_id == core_id) { 2268 return pc; 2269 } 2270 } 2271 return NULL; 2272 } 2273 2274 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2275 { 2276 int i, j; 2277 2278 for (i = 0; i < chip->nr_cores; i++) { 2279 PnvCore *pc = chip->cores[i]; 2280 CPUCore *cc = CPU_CORE(pc); 2281 2282 for (j = 0; j < cc->nr_threads; j++) { 2283 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2284 return pc->threads[j]; 2285 } 2286 } 2287 } 2288 return NULL; 2289 } 2290 2291 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2292 { 2293 PnvMachineState *pnv = PNV_MACHINE(xi); 2294 int i, j; 2295 2296 for (i = 0; i < pnv->num_chips; i++) { 2297 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2298 2299 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2300 return &chip8->psi.ics; 2301 } 2302 2303 for (j = 0; j < chip8->num_phbs; j++) { 2304 PnvPHB *phb = chip8->phbs[j]; 2305 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2306 2307 if (ics_valid_irq(&phb3->lsis, irq)) { 2308 return &phb3->lsis; 2309 } 2310 2311 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2312 return ICS(&phb3->msis); 2313 } 2314 } 2315 } 2316 return NULL; 2317 } 2318 2319 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2320 { 2321 int i; 2322 2323 for (i = 0; i < pnv->num_chips; i++) { 2324 PnvChip *chip = pnv->chips[i]; 2325 if (chip->chip_id == chip_id) { 2326 return chip; 2327 } 2328 } 2329 return NULL; 2330 } 2331 2332 static void pnv_ics_resend(XICSFabric *xi) 2333 { 2334 PnvMachineState *pnv = PNV_MACHINE(xi); 2335 int i, j; 2336 2337 for (i = 0; i < pnv->num_chips; i++) { 2338 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2339 2340 ics_resend(&chip8->psi.ics); 2341 2342 for (j = 0; j < chip8->num_phbs; j++) { 2343 PnvPHB *phb = chip8->phbs[j]; 2344 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2345 2346 ics_resend(&phb3->lsis); 2347 ics_resend(ICS(&phb3->msis)); 2348 } 2349 } 2350 } 2351 2352 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2353 { 2354 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2355 2356 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2357 } 2358 2359 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2360 Monitor *mon) 2361 { 2362 PnvMachineState *pnv = PNV_MACHINE(obj); 2363 int i; 2364 CPUState *cs; 2365 2366 CPU_FOREACH(cs) { 2367 PowerPCCPU *cpu = POWERPC_CPU(cs); 2368 2369 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2370 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2371 mon); 2372 } 2373 2374 for (i = 0; i < pnv->num_chips; i++) { 2375 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2376 } 2377 } 2378 2379 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2380 uint8_t nvt_blk, uint32_t nvt_idx, 2381 bool cam_ignore, uint8_t priority, 2382 uint32_t logic_serv, 2383 XiveTCTXMatch *match) 2384 { 2385 PnvMachineState *pnv = PNV_MACHINE(xfb); 2386 int total_count = 0; 2387 int i; 2388 2389 for (i = 0; i < pnv->num_chips; i++) { 2390 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2391 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2392 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2393 int count; 2394 2395 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2396 priority, logic_serv, match); 2397 2398 if (count < 0) { 2399 return count; 2400 } 2401 2402 total_count += count; 2403 } 2404 2405 return total_count; 2406 } 2407 2408 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2409 uint8_t nvt_blk, uint32_t nvt_idx, 2410 bool cam_ignore, uint8_t priority, 2411 uint32_t logic_serv, 2412 XiveTCTXMatch *match) 2413 { 2414 PnvMachineState *pnv = PNV_MACHINE(xfb); 2415 int total_count = 0; 2416 int i; 2417 2418 for (i = 0; i < pnv->num_chips; i++) { 2419 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2420 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2421 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2422 int count; 2423 2424 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2425 priority, logic_serv, match); 2426 2427 if (count < 0) { 2428 return count; 2429 } 2430 2431 total_count += count; 2432 } 2433 2434 return total_count; 2435 } 2436 2437 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2438 { 2439 MachineClass *mc = MACHINE_CLASS(oc); 2440 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2441 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2442 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2443 2444 static GlobalProperty phb_compat[] = { 2445 { TYPE_PNV_PHB, "version", "3" }, 2446 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2447 }; 2448 2449 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2450 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2451 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2452 2453 xic->icp_get = pnv_icp_get; 2454 xic->ics_get = pnv_ics_get; 2455 xic->ics_resend = pnv_ics_resend; 2456 2457 pmc->compat = compat; 2458 pmc->compat_size = sizeof(compat); 2459 2460 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2461 } 2462 2463 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2464 { 2465 MachineClass *mc = MACHINE_CLASS(oc); 2466 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2467 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2468 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2469 2470 static GlobalProperty phb_compat[] = { 2471 { TYPE_PNV_PHB, "version", "4" }, 2472 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2473 }; 2474 2475 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2476 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2477 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2478 2479 xfc->match_nvt = pnv_match_nvt; 2480 2481 pmc->compat = compat; 2482 pmc->compat_size = sizeof(compat); 2483 pmc->dt_power_mgt = pnv_dt_power_mgt; 2484 2485 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2486 } 2487 2488 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2489 { 2490 MachineClass *mc = MACHINE_CLASS(oc); 2491 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2492 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2493 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2494 2495 static GlobalProperty phb_compat[] = { 2496 { TYPE_PNV_PHB, "version", "5" }, 2497 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2498 }; 2499 2500 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2501 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2502 2503 mc->alias = "powernv"; 2504 2505 pmc->compat = compat; 2506 pmc->compat_size = sizeof(compat); 2507 pmc->dt_power_mgt = pnv_dt_power_mgt; 2508 2509 xfc->match_nvt = pnv10_xive_match_nvt; 2510 2511 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2512 } 2513 2514 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2515 { 2516 MachineClass *mc = MACHINE_CLASS(oc); 2517 2518 pnv_machine_p10_common_class_init(oc, data); 2519 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2520 } 2521 2522 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2523 { 2524 MachineClass *mc = MACHINE_CLASS(oc); 2525 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2526 2527 pnv_machine_p10_common_class_init(oc, data); 2528 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2529 pmc->i2c_init = pnv_rainier_i2c_init; 2530 } 2531 2532 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2533 { 2534 PnvMachineState *pnv = PNV_MACHINE(obj); 2535 2536 return !!pnv->fw_load_addr; 2537 } 2538 2539 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2540 { 2541 PnvMachineState *pnv = PNV_MACHINE(obj); 2542 2543 if (value) { 2544 pnv->fw_load_addr = 0x8000000; 2545 } 2546 } 2547 2548 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2549 { 2550 CPUPPCState *env = cpu_env(cs); 2551 2552 cpu_synchronize_state(cs); 2553 ppc_cpu_do_system_reset(cs); 2554 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2555 /* 2556 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2557 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2558 * (PPC_BIT(43)). 2559 */ 2560 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2561 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2562 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2563 } 2564 } else { 2565 /* 2566 * For non-powersave system resets, SRR1[42:45] are defined to be 2567 * implementation-dependent. The POWER9 User Manual specifies that 2568 * an external (SCOM driven, which may come from a BMC nmi command or 2569 * another CPU requesting a NMI IPI) system reset exception should be 2570 * 0b0010 (PPC_BIT(44)). 2571 */ 2572 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2573 } 2574 } 2575 2576 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2577 { 2578 CPUState *cs; 2579 2580 CPU_FOREACH(cs) { 2581 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2582 } 2583 } 2584 2585 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2586 { 2587 MachineClass *mc = MACHINE_CLASS(oc); 2588 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2589 NMIClass *nc = NMI_CLASS(oc); 2590 2591 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2592 mc->init = pnv_init; 2593 mc->reset = pnv_reset; 2594 mc->max_cpus = MAX_CPUS; 2595 /* Pnv provides a AHCI device for storage */ 2596 mc->block_default_type = IF_IDE; 2597 mc->no_parallel = 1; 2598 mc->default_boot_order = NULL; 2599 /* 2600 * RAM defaults to less than 2048 for 32-bit hosts, and large 2601 * enough to fit the maximum initrd size at it's load address 2602 */ 2603 mc->default_ram_size = 1 * GiB; 2604 mc->default_ram_id = "pnv.ram"; 2605 ispc->print_info = pnv_pic_print_info; 2606 nc->nmi_monitor_handler = pnv_nmi; 2607 2608 object_class_property_add_bool(oc, "hb-mode", 2609 pnv_machine_get_hb, pnv_machine_set_hb); 2610 object_class_property_set_description(oc, "hb-mode", 2611 "Use a hostboot like boot loader"); 2612 } 2613 2614 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2615 { \ 2616 .name = type, \ 2617 .class_init = class_initfn, \ 2618 .parent = TYPE_PNV8_CHIP, \ 2619 } 2620 2621 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2622 { \ 2623 .name = type, \ 2624 .class_init = class_initfn, \ 2625 .parent = TYPE_PNV9_CHIP, \ 2626 } 2627 2628 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2629 { \ 2630 .name = type, \ 2631 .class_init = class_initfn, \ 2632 .parent = TYPE_PNV10_CHIP, \ 2633 } 2634 2635 static const TypeInfo types[] = { 2636 { 2637 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2638 .parent = MACHINE_TYPE_NAME("powernv10"), 2639 .class_init = pnv_machine_p10_rainier_class_init, 2640 }, 2641 { 2642 .name = MACHINE_TYPE_NAME("powernv10"), 2643 .parent = TYPE_PNV_MACHINE, 2644 .class_init = pnv_machine_power10_class_init, 2645 .interfaces = (InterfaceInfo[]) { 2646 { TYPE_XIVE_FABRIC }, 2647 { }, 2648 }, 2649 }, 2650 { 2651 .name = MACHINE_TYPE_NAME("powernv9"), 2652 .parent = TYPE_PNV_MACHINE, 2653 .class_init = pnv_machine_power9_class_init, 2654 .interfaces = (InterfaceInfo[]) { 2655 { TYPE_XIVE_FABRIC }, 2656 { }, 2657 }, 2658 }, 2659 { 2660 .name = MACHINE_TYPE_NAME("powernv8"), 2661 .parent = TYPE_PNV_MACHINE, 2662 .class_init = pnv_machine_power8_class_init, 2663 .interfaces = (InterfaceInfo[]) { 2664 { TYPE_XICS_FABRIC }, 2665 { }, 2666 }, 2667 }, 2668 { 2669 .name = TYPE_PNV_MACHINE, 2670 .parent = TYPE_MACHINE, 2671 .abstract = true, 2672 .instance_size = sizeof(PnvMachineState), 2673 .class_init = pnv_machine_class_init, 2674 .class_size = sizeof(PnvMachineClass), 2675 .interfaces = (InterfaceInfo[]) { 2676 { TYPE_INTERRUPT_STATS_PROVIDER }, 2677 { TYPE_NMI }, 2678 { }, 2679 }, 2680 }, 2681 { 2682 .name = TYPE_PNV_CHIP, 2683 .parent = TYPE_SYS_BUS_DEVICE, 2684 .class_init = pnv_chip_class_init, 2685 .instance_size = sizeof(PnvChip), 2686 .class_size = sizeof(PnvChipClass), 2687 .abstract = true, 2688 }, 2689 2690 /* 2691 * P10 chip and variants 2692 */ 2693 { 2694 .name = TYPE_PNV10_CHIP, 2695 .parent = TYPE_PNV_CHIP, 2696 .instance_init = pnv_chip_power10_instance_init, 2697 .instance_size = sizeof(Pnv10Chip), 2698 }, 2699 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2700 2701 /* 2702 * P9 chip and variants 2703 */ 2704 { 2705 .name = TYPE_PNV9_CHIP, 2706 .parent = TYPE_PNV_CHIP, 2707 .instance_init = pnv_chip_power9_instance_init, 2708 .instance_size = sizeof(Pnv9Chip), 2709 }, 2710 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2711 2712 /* 2713 * P8 chip and variants 2714 */ 2715 { 2716 .name = TYPE_PNV8_CHIP, 2717 .parent = TYPE_PNV_CHIP, 2718 .instance_init = pnv_chip_power8_instance_init, 2719 .instance_size = sizeof(Pnv8Chip), 2720 }, 2721 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2722 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2723 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2724 pnv_chip_power8nvl_class_init), 2725 }; 2726 2727 DEFINE_TYPES(types) 2728