1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/cutils.h" 25 #include "qapi/error.h" 26 #include "sysemu/qtest.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/runstate.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/device_tree.h" 33 #include "sysemu/hw_accel.h" 34 #include "target/ppc/cpu.h" 35 #include "hw/ppc/fdt.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/ppc/pnv.h" 38 #include "hw/ppc/pnv_core.h" 39 #include "hw/loader.h" 40 #include "hw/nmi.h" 41 #include "exec/address-spaces.h" 42 #include "qapi/visitor.h" 43 #include "monitor/monitor.h" 44 #include "hw/intc/intc.h" 45 #include "hw/ipmi/ipmi.h" 46 #include "target/ppc/mmu-hash64.h" 47 #include "hw/pci/msi.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_xscom.h" 52 #include "hw/ppc/pnv_pnor.h" 53 54 #include "hw/isa/isa.h" 55 #include "hw/char/serial.h" 56 #include "hw/rtc/mc146818rtc.h" 57 58 #include <libfdt.h> 59 60 #define FDT_MAX_SIZE (1 * MiB) 61 62 #define FW_FILE_NAME "skiboot.lid" 63 #define FW_LOAD_ADDR 0x0 64 #define FW_MAX_SIZE (16 * MiB) 65 66 #define KERNEL_LOAD_ADDR 0x20000000 67 #define KERNEL_MAX_SIZE (128 * MiB) 68 #define INITRD_LOAD_ADDR 0x28000000 69 #define INITRD_MAX_SIZE (128 * MiB) 70 71 static const char *pnv_chip_core_typename(const PnvChip *o) 72 { 73 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 74 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 75 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 76 const char *core_type = object_class_get_name(object_class_by_name(s)); 77 g_free(s); 78 return core_type; 79 } 80 81 /* 82 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 83 * 4 * 4 sockets * 12 cores * 8 threads = 1536 84 * Let's make it 2^11 85 */ 86 #define MAX_CPUS 2048 87 88 /* 89 * Memory nodes are created by hostboot, one for each range of memory 90 * that has a different "affinity". In practice, it means one range 91 * per chip. 92 */ 93 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 94 { 95 char *mem_name; 96 uint64_t mem_reg_property[2]; 97 int off; 98 99 mem_reg_property[0] = cpu_to_be64(start); 100 mem_reg_property[1] = cpu_to_be64(size); 101 102 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 103 off = fdt_add_subnode(fdt, 0, mem_name); 104 g_free(mem_name); 105 106 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 107 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 108 sizeof(mem_reg_property)))); 109 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 110 } 111 112 static int get_cpus_node(void *fdt) 113 { 114 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 115 116 if (cpus_offset < 0) { 117 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 118 if (cpus_offset) { 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 121 } 122 } 123 _FDT(cpus_offset); 124 return cpus_offset; 125 } 126 127 /* 128 * The PowerNV cores (and threads) need to use real HW ids and not an 129 * incremental index like it has been done on other platforms. This HW 130 * id is stored in the CPU PIR, it is used to create cpu nodes in the 131 * device tree, used in XSCOM to address cores and in interrupt 132 * servers. 133 */ 134 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 135 { 136 PowerPCCPU *cpu = pc->threads[0]; 137 CPUState *cs = CPU(cpu); 138 DeviceClass *dc = DEVICE_GET_CLASS(cs); 139 int smt_threads = CPU_CORE(pc)->nr_threads; 140 CPUPPCState *env = &cpu->env; 141 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 142 uint32_t servers_prop[smt_threads]; 143 int i; 144 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 145 0xffffffff, 0xffffffff}; 146 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 147 uint32_t cpufreq = 1000000000; 148 uint32_t page_sizes_prop[64]; 149 size_t page_sizes_prop_size; 150 const uint8_t pa_features[] = { 24, 0, 151 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 152 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 153 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 154 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 160 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 161 _FDT(offset); 162 g_free(nodename); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 168 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 169 170 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 176 env->icache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 178 env->icache_line_size))); 179 180 if (pcc->l1_dcache_size) { 181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 182 pcc->l1_dcache_size))); 183 } else { 184 warn_report("Unknown L1 dcache size for cpu"); 185 } 186 if (pcc->l1_icache_size) { 187 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 188 pcc->l1_icache_size))); 189 } else { 190 warn_report("Unknown L1 icache size for cpu"); 191 } 192 193 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 195 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 196 cpu->hash64_opts->slb_size))); 197 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 198 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 199 200 if (env->spr_cb[SPR_PURR].oea_read) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 202 } 203 204 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 205 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 206 segs, sizeof(segs)))); 207 } 208 209 /* 210 * Advertise VMX/VSX (vector extensions) if available 211 * 0 / no property == no vector extensions 212 * 1 == VMX / Altivec available 213 * 2 == VSX available 214 */ 215 if (env->insns_flags & PPC_ALTIVEC) { 216 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 217 218 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 219 } 220 221 /* 222 * Advertise DFP (Decimal Floating Point) if available 223 * 0 / no property == no DFP 224 * 1 == DFP available 225 */ 226 if (env->insns_flags2 & PPC2_DFP) { 227 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 228 } 229 230 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 231 sizeof(page_sizes_prop)); 232 if (page_sizes_prop_size) { 233 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 234 page_sizes_prop, page_sizes_prop_size))); 235 } 236 237 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 238 pa_features, sizeof(pa_features)))); 239 240 /* Build interrupt servers properties */ 241 for (i = 0; i < smt_threads; i++) { 242 servers_prop[i] = cpu_to_be32(pc->pir + i); 243 } 244 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 245 servers_prop, sizeof(servers_prop)))); 246 } 247 248 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 249 uint32_t nr_threads) 250 { 251 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 252 char *name; 253 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 254 uint32_t irange[2], i, rsize; 255 uint64_t *reg; 256 int offset; 257 258 irange[0] = cpu_to_be32(pir); 259 irange[1] = cpu_to_be32(nr_threads); 260 261 rsize = sizeof(uint64_t) * 2 * nr_threads; 262 reg = g_malloc(rsize); 263 for (i = 0; i < nr_threads; i++) { 264 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 265 reg[i * 2 + 1] = cpu_to_be64(0x1000); 266 } 267 268 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 269 offset = fdt_add_subnode(fdt, 0, name); 270 _FDT(offset); 271 g_free(name); 272 273 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 274 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 275 _FDT((fdt_setprop_string(fdt, offset, "device_type", 276 "PowerPC-External-Interrupt-Presentation"))); 277 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 278 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 279 irange, sizeof(irange)))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 281 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 282 g_free(reg); 283 } 284 285 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 286 { 287 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 288 int i; 289 290 pnv_dt_xscom(chip, fdt, 0, 291 cpu_to_be64(PNV_XSCOM_BASE(chip)), 292 cpu_to_be64(PNV_XSCOM_SIZE), 293 compat, sizeof(compat)); 294 295 for (i = 0; i < chip->nr_cores; i++) { 296 PnvCore *pnv_core = chip->cores[i]; 297 298 pnv_dt_core(chip, pnv_core, fdt); 299 300 /* Interrupt Control Presenters (ICP). One per core. */ 301 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 302 } 303 304 if (chip->ram_size) { 305 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 306 } 307 } 308 309 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 310 { 311 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 312 int i; 313 314 pnv_dt_xscom(chip, fdt, 0, 315 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 316 cpu_to_be64(PNV9_XSCOM_SIZE), 317 compat, sizeof(compat)); 318 319 for (i = 0; i < chip->nr_cores; i++) { 320 PnvCore *pnv_core = chip->cores[i]; 321 322 pnv_dt_core(chip, pnv_core, fdt); 323 } 324 325 if (chip->ram_size) { 326 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 327 } 328 329 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 330 } 331 332 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 333 { 334 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 335 int i; 336 337 pnv_dt_xscom(chip, fdt, 0, 338 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 339 cpu_to_be64(PNV10_XSCOM_SIZE), 340 compat, sizeof(compat)); 341 342 for (i = 0; i < chip->nr_cores; i++) { 343 PnvCore *pnv_core = chip->cores[i]; 344 345 pnv_dt_core(chip, pnv_core, fdt); 346 } 347 348 if (chip->ram_size) { 349 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 350 } 351 352 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 353 } 354 355 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 356 { 357 uint32_t io_base = d->ioport_id; 358 uint32_t io_regs[] = { 359 cpu_to_be32(1), 360 cpu_to_be32(io_base), 361 cpu_to_be32(2) 362 }; 363 char *name; 364 int node; 365 366 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 367 node = fdt_add_subnode(fdt, lpc_off, name); 368 _FDT(node); 369 g_free(name); 370 371 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 372 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 373 } 374 375 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 376 { 377 const char compatible[] = "ns16550\0pnpPNP,501"; 378 uint32_t io_base = d->ioport_id; 379 uint32_t io_regs[] = { 380 cpu_to_be32(1), 381 cpu_to_be32(io_base), 382 cpu_to_be32(8) 383 }; 384 char *name; 385 int node; 386 387 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 388 node = fdt_add_subnode(fdt, lpc_off, name); 389 _FDT(node); 390 g_free(name); 391 392 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 393 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 394 sizeof(compatible)))); 395 396 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 397 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 399 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 400 fdt_get_phandle(fdt, lpc_off)))); 401 402 /* This is needed by Linux */ 403 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 404 } 405 406 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 407 { 408 const char compatible[] = "bt\0ipmi-bt"; 409 uint32_t io_base; 410 uint32_t io_regs[] = { 411 cpu_to_be32(1), 412 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 413 cpu_to_be32(3) 414 }; 415 uint32_t irq; 416 char *name; 417 int node; 418 419 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 420 io_regs[1] = cpu_to_be32(io_base); 421 422 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 423 424 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 425 node = fdt_add_subnode(fdt, lpc_off, name); 426 _FDT(node); 427 g_free(name); 428 429 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 430 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 431 sizeof(compatible)))); 432 433 /* Mark it as reserved to avoid Linux trying to claim it */ 434 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 436 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 437 fdt_get_phandle(fdt, lpc_off)))); 438 } 439 440 typedef struct ForeachPopulateArgs { 441 void *fdt; 442 int offset; 443 } ForeachPopulateArgs; 444 445 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 446 { 447 ForeachPopulateArgs *args = opaque; 448 ISADevice *d = ISA_DEVICE(dev); 449 450 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 451 pnv_dt_rtc(d, args->fdt, args->offset); 452 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 453 pnv_dt_serial(d, args->fdt, args->offset); 454 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 455 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 456 } else { 457 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 458 d->ioport_id); 459 } 460 461 return 0; 462 } 463 464 /* 465 * The default LPC bus of a multichip system is on chip 0. It's 466 * recognized by the firmware (skiboot) using a "primary" property. 467 */ 468 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 469 { 470 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 471 ForeachPopulateArgs args = { 472 .fdt = fdt, 473 .offset = isa_offset, 474 }; 475 uint32_t phandle; 476 477 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 478 479 phandle = qemu_fdt_alloc_phandle(fdt); 480 assert(phandle > 0); 481 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 482 483 /* 484 * ISA devices are not necessarily parented to the ISA bus so we 485 * can not use object_child_foreach() 486 */ 487 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 488 &args); 489 } 490 491 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 492 { 493 int off; 494 495 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 496 off = fdt_add_subnode(fdt, off, "power-mgt"); 497 498 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 499 } 500 501 static void *pnv_dt_create(MachineState *machine) 502 { 503 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 504 PnvMachineState *pnv = PNV_MACHINE(machine); 505 void *fdt; 506 char *buf; 507 int off; 508 int i; 509 510 fdt = g_malloc0(FDT_MAX_SIZE); 511 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 512 513 /* /qemu node */ 514 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 515 516 /* Root node */ 517 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 518 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 519 _FDT((fdt_setprop_string(fdt, 0, "model", 520 "IBM PowerNV (emulated by qemu)"))); 521 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 522 523 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 524 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 525 if (qemu_uuid_set) { 526 _FDT((fdt_property_string(fdt, "system-id", buf))); 527 } 528 g_free(buf); 529 530 off = fdt_add_subnode(fdt, 0, "chosen"); 531 if (machine->kernel_cmdline) { 532 _FDT((fdt_setprop_string(fdt, off, "bootargs", 533 machine->kernel_cmdline))); 534 } 535 536 if (pnv->initrd_size) { 537 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 538 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 539 540 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 541 &start_prop, sizeof(start_prop)))); 542 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 543 &end_prop, sizeof(end_prop)))); 544 } 545 546 /* Populate device tree for each chip */ 547 for (i = 0; i < pnv->num_chips; i++) { 548 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 549 } 550 551 /* Populate ISA devices on chip 0 */ 552 pnv_dt_isa(pnv, fdt); 553 554 if (pnv->bmc) { 555 pnv_dt_bmc_sensors(pnv->bmc, fdt); 556 } 557 558 /* Create an extra node for power management on machines that support it */ 559 if (pmc->dt_power_mgt) { 560 pmc->dt_power_mgt(pnv, fdt); 561 } 562 563 return fdt; 564 } 565 566 static void pnv_powerdown_notify(Notifier *n, void *opaque) 567 { 568 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 569 570 if (pnv->bmc) { 571 pnv_bmc_powerdown(pnv->bmc); 572 } 573 } 574 575 static void pnv_reset(MachineState *machine) 576 { 577 PnvMachineState *pnv = PNV_MACHINE(machine); 578 IPMIBmc *bmc; 579 void *fdt; 580 581 qemu_devices_reset(); 582 583 /* 584 * The machine should provide by default an internal BMC simulator. 585 * If not, try to use the BMC device that was provided on the command 586 * line. 587 */ 588 bmc = pnv_bmc_find(&error_fatal); 589 if (!pnv->bmc) { 590 if (!bmc) { 591 if (!qtest_enabled()) { 592 warn_report("machine has no BMC device. Use '-device " 593 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 594 "to define one"); 595 } 596 } else { 597 pnv_bmc_set_pnor(bmc, pnv->pnor); 598 pnv->bmc = bmc; 599 } 600 } 601 602 fdt = pnv_dt_create(machine); 603 604 /* Pack resulting tree */ 605 _FDT((fdt_pack(fdt))); 606 607 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 608 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 609 610 g_free(fdt); 611 } 612 613 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 614 { 615 Pnv8Chip *chip8 = PNV8_CHIP(chip); 616 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 617 } 618 619 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 620 { 621 Pnv8Chip *chip8 = PNV8_CHIP(chip); 622 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 623 } 624 625 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 626 { 627 Pnv9Chip *chip9 = PNV9_CHIP(chip); 628 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 629 } 630 631 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 632 { 633 Pnv10Chip *chip10 = PNV10_CHIP(chip); 634 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 635 } 636 637 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 638 { 639 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 640 } 641 642 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 643 { 644 Pnv8Chip *chip8 = PNV8_CHIP(chip); 645 int i; 646 647 ics_pic_print_info(&chip8->psi.ics, mon); 648 for (i = 0; i < chip->num_phbs; i++) { 649 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 650 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 651 } 652 } 653 654 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 655 { 656 Pnv9Chip *chip9 = PNV9_CHIP(chip); 657 int i, j; 658 659 pnv_xive_pic_print_info(&chip9->xive, mon); 660 pnv_psi_pic_print_info(&chip9->psi, mon); 661 662 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 663 PnvPhb4PecState *pec = &chip9->pecs[i]; 664 for (j = 0; j < pec->num_stacks; j++) { 665 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 666 } 667 } 668 } 669 670 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 671 uint32_t core_id) 672 { 673 return PNV_XSCOM_EX_BASE(core_id); 674 } 675 676 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 677 uint32_t core_id) 678 { 679 return PNV9_XSCOM_EC_BASE(core_id); 680 } 681 682 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 683 uint32_t core_id) 684 { 685 return PNV10_XSCOM_EC_BASE(core_id); 686 } 687 688 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 689 { 690 PowerPCCPUClass *ppc_default = 691 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 692 PowerPCCPUClass *ppc = 693 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 694 695 return ppc_default->pvr_match(ppc_default, ppc->pvr); 696 } 697 698 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 699 { 700 ISADevice *dev = isa_new("isa-ipmi-bt"); 701 702 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 703 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 704 isa_realize_and_unref(dev, bus, &error_fatal); 705 } 706 707 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 708 { 709 Pnv10Chip *chip10 = PNV10_CHIP(chip); 710 711 pnv_psi_pic_print_info(&chip10->psi, mon); 712 } 713 714 static void pnv_init(MachineState *machine) 715 { 716 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 717 PnvMachineState *pnv = PNV_MACHINE(machine); 718 MachineClass *mc = MACHINE_GET_CLASS(machine); 719 char *fw_filename; 720 long fw_size; 721 int i; 722 char *chip_typename; 723 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 724 DeviceState *dev; 725 726 /* allocate RAM */ 727 if (machine->ram_size < mc->default_ram_size) { 728 char *sz = size_to_str(mc->default_ram_size); 729 error_report("Invalid RAM size, should be bigger than %s", sz); 730 g_free(sz); 731 exit(EXIT_FAILURE); 732 } 733 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 734 735 /* 736 * Create our simple PNOR device 737 */ 738 dev = qdev_new(TYPE_PNV_PNOR); 739 if (pnor) { 740 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 741 } 742 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 743 pnv->pnor = PNV_PNOR(dev); 744 745 /* load skiboot firmware */ 746 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 747 if (!fw_filename) { 748 error_report("Could not find OPAL firmware '%s'", bios_name); 749 exit(1); 750 } 751 752 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 753 if (fw_size < 0) { 754 error_report("Could not load OPAL firmware '%s'", fw_filename); 755 exit(1); 756 } 757 g_free(fw_filename); 758 759 /* load kernel */ 760 if (machine->kernel_filename) { 761 long kernel_size; 762 763 kernel_size = load_image_targphys(machine->kernel_filename, 764 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 765 if (kernel_size < 0) { 766 error_report("Could not load kernel '%s'", 767 machine->kernel_filename); 768 exit(1); 769 } 770 } 771 772 /* load initrd */ 773 if (machine->initrd_filename) { 774 pnv->initrd_base = INITRD_LOAD_ADDR; 775 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 776 pnv->initrd_base, INITRD_MAX_SIZE); 777 if (pnv->initrd_size < 0) { 778 error_report("Could not load initial ram disk '%s'", 779 machine->initrd_filename); 780 exit(1); 781 } 782 } 783 784 /* MSIs are supported on this platform */ 785 msi_nonbroken = true; 786 787 /* 788 * Check compatibility of the specified CPU with the machine 789 * default. 790 */ 791 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 792 error_report("invalid CPU model '%s' for %s machine", 793 machine->cpu_type, mc->name); 794 exit(1); 795 } 796 797 /* Create the processor chips */ 798 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 799 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 800 i, machine->cpu_type); 801 if (!object_class_by_name(chip_typename)) { 802 error_report("invalid chip model '%.*s' for %s machine", 803 i, machine->cpu_type, mc->name); 804 exit(1); 805 } 806 807 pnv->num_chips = 808 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 809 /* 810 * TODO: should we decide on how many chips we can create based 811 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 812 */ 813 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 814 error_report("invalid number of chips: '%d'", pnv->num_chips); 815 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 816 exit(1); 817 } 818 819 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 820 for (i = 0; i < pnv->num_chips; i++) { 821 char chip_name[32]; 822 Object *chip = OBJECT(qdev_new(chip_typename)); 823 824 pnv->chips[i] = PNV_CHIP(chip); 825 826 /* 827 * TODO: put all the memory in one node on chip 0 until we find a 828 * way to specify different ranges for each chip 829 */ 830 if (i == 0) { 831 object_property_set_int(chip, "ram-size", machine->ram_size, 832 &error_fatal); 833 } 834 835 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 836 object_property_add_child(OBJECT(pnv), chip_name, chip); 837 object_property_set_int(chip, "chip-id", PNV_CHIP_HWID(i), 838 &error_fatal); 839 object_property_set_int(chip, "nr-cores", machine->smp.cores, 840 &error_fatal); 841 object_property_set_int(chip, "nr-threads", machine->smp.threads, 842 &error_fatal); 843 /* 844 * The POWER8 machine use the XICS interrupt interface. 845 * Propagate the XICS fabric to the chip and its controllers. 846 */ 847 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 848 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 849 } 850 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 851 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 852 &error_abort); 853 } 854 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 855 } 856 g_free(chip_typename); 857 858 /* Instantiate ISA bus on chip 0 */ 859 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 860 861 /* Create serial port */ 862 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 863 864 /* Create an RTC ISA device too */ 865 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 866 867 /* 868 * Create the machine BMC simulator and the IPMI BT device for 869 * communication with the BMC 870 */ 871 if (defaults_enabled()) { 872 pnv->bmc = pnv_bmc_create(pnv->pnor); 873 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 874 } 875 876 /* 877 * The PNOR is mapped on the LPC FW address space by the BMC. 878 * Since we can not reach the remote BMC machine with LPC memops, 879 * map it always for now. 880 */ 881 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 882 &pnv->pnor->mmio); 883 884 /* 885 * OpenPOWER systems use a IPMI SEL Event message to notify the 886 * host to powerdown 887 */ 888 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 889 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 890 } 891 892 /* 893 * 0:21 Reserved - Read as zeros 894 * 22:24 Chip ID 895 * 25:28 Core number 896 * 29:31 Thread ID 897 */ 898 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 899 { 900 return (chip->chip_id << 7) | (core_id << 3); 901 } 902 903 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 904 Error **errp) 905 { 906 Pnv8Chip *chip8 = PNV8_CHIP(chip); 907 Error *local_err = NULL; 908 Object *obj; 909 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 910 911 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 912 if (local_err) { 913 error_propagate(errp, local_err); 914 return; 915 } 916 917 pnv_cpu->intc = obj; 918 } 919 920 921 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 922 { 923 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 924 925 icp_reset(ICP(pnv_cpu->intc)); 926 } 927 928 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 929 { 930 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 931 932 icp_destroy(ICP(pnv_cpu->intc)); 933 pnv_cpu->intc = NULL; 934 } 935 936 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 937 Monitor *mon) 938 { 939 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 940 } 941 942 /* 943 * 0:48 Reserved - Read as zeroes 944 * 49:52 Node ID 945 * 53:55 Chip ID 946 * 56 Reserved - Read as zero 947 * 57:61 Core number 948 * 62:63 Thread ID 949 * 950 * We only care about the lower bits. uint32_t is fine for the moment. 951 */ 952 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 953 { 954 return (chip->chip_id << 8) | (core_id << 2); 955 } 956 957 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 958 { 959 return (chip->chip_id << 8) | (core_id << 2); 960 } 961 962 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 963 Error **errp) 964 { 965 Pnv9Chip *chip9 = PNV9_CHIP(chip); 966 Error *local_err = NULL; 967 Object *obj; 968 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 969 970 /* 971 * The core creates its interrupt presenter but the XIVE interrupt 972 * controller object is initialized afterwards. Hopefully, it's 973 * only used at runtime. 974 */ 975 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 976 &local_err); 977 if (local_err) { 978 error_propagate(errp, local_err); 979 return; 980 } 981 982 pnv_cpu->intc = obj; 983 } 984 985 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 986 { 987 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 988 989 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 990 } 991 992 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 993 { 994 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 995 996 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 997 pnv_cpu->intc = NULL; 998 } 999 1000 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1001 Monitor *mon) 1002 { 1003 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1004 } 1005 1006 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1007 Error **errp) 1008 { 1009 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1010 1011 /* Will be defined when the interrupt controller is */ 1012 pnv_cpu->intc = NULL; 1013 } 1014 1015 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1016 { 1017 ; 1018 } 1019 1020 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1021 { 1022 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1023 1024 pnv_cpu->intc = NULL; 1025 } 1026 1027 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1028 Monitor *mon) 1029 { 1030 } 1031 1032 /* 1033 * Allowed core identifiers on a POWER8 Processor Chip : 1034 * 1035 * <EX0 reserved> 1036 * EX1 - Venice only 1037 * EX2 - Venice only 1038 * EX3 - Venice only 1039 * EX4 1040 * EX5 1041 * EX6 1042 * <EX7,8 reserved> <reserved> 1043 * EX9 - Venice only 1044 * EX10 - Venice only 1045 * EX11 - Venice only 1046 * EX12 1047 * EX13 1048 * EX14 1049 * <EX15 reserved> 1050 */ 1051 #define POWER8E_CORE_MASK (0x7070ull) 1052 #define POWER8_CORE_MASK (0x7e7eull) 1053 1054 /* 1055 * POWER9 has 24 cores, ids starting at 0x0 1056 */ 1057 #define POWER9_CORE_MASK (0xffffffffffffffull) 1058 1059 1060 #define POWER10_CORE_MASK (0xffffffffffffffull) 1061 1062 static void pnv_chip_power8_instance_init(Object *obj) 1063 { 1064 PnvChip *chip = PNV_CHIP(obj); 1065 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1066 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1067 int i; 1068 1069 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1070 (Object **)&chip8->xics, 1071 object_property_allow_set_link, 1072 OBJ_PROP_LINK_STRONG); 1073 1074 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1075 1076 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1077 1078 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1079 1080 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1081 1082 for (i = 0; i < pcc->num_phbs; i++) { 1083 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1084 } 1085 1086 /* 1087 * Number of PHBs is the chip default 1088 */ 1089 chip->num_phbs = pcc->num_phbs; 1090 } 1091 1092 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1093 { 1094 PnvChip *chip = PNV_CHIP(chip8); 1095 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1096 int i, j; 1097 char *name; 1098 1099 name = g_strdup_printf("icp-%x", chip->chip_id); 1100 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1101 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1102 g_free(name); 1103 1104 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1105 1106 /* Map the ICP registers for each thread */ 1107 for (i = 0; i < chip->nr_cores; i++) { 1108 PnvCore *pnv_core = chip->cores[i]; 1109 int core_hwid = CPU_CORE(pnv_core)->core_id; 1110 1111 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1112 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1113 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1114 1115 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1116 &icp->mmio); 1117 } 1118 } 1119 } 1120 1121 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1122 { 1123 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1124 PnvChip *chip = PNV_CHIP(dev); 1125 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1126 Pnv8Psi *psi8 = &chip8->psi; 1127 Error *local_err = NULL; 1128 int i; 1129 1130 assert(chip8->xics); 1131 1132 /* XSCOM bridge is first */ 1133 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1134 if (local_err) { 1135 error_propagate(errp, local_err); 1136 return; 1137 } 1138 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1139 1140 pcc->parent_realize(dev, &local_err); 1141 if (local_err) { 1142 error_propagate(errp, local_err); 1143 return; 1144 } 1145 1146 /* Processor Service Interface (PSI) Host Bridge */ 1147 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1148 &error_fatal); 1149 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1150 OBJECT(chip8->xics), &error_abort); 1151 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1152 return; 1153 } 1154 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1155 &PNV_PSI(psi8)->xscom_regs); 1156 1157 /* Create LPC controller */ 1158 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1159 &error_abort); 1160 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1161 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1162 1163 chip->fw_mr = &chip8->lpc.isa_fw; 1164 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1165 (uint64_t) PNV_XSCOM_BASE(chip), 1166 PNV_XSCOM_LPC_BASE); 1167 1168 /* 1169 * Interrupt Management Area. This is the memory region holding 1170 * all the Interrupt Control Presenter (ICP) registers 1171 */ 1172 pnv_chip_icp_realize(chip8, &local_err); 1173 if (local_err) { 1174 error_propagate(errp, local_err); 1175 return; 1176 } 1177 1178 /* Create the simplified OCC model */ 1179 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1180 &error_abort); 1181 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1182 return; 1183 } 1184 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1185 1186 /* OCC SRAM model */ 1187 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1188 &chip8->occ.sram_regs); 1189 1190 /* HOMER */ 1191 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1192 &error_abort); 1193 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1194 return; 1195 } 1196 /* Homer Xscom region */ 1197 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1198 1199 /* Homer mmio region */ 1200 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1201 &chip8->homer.regs); 1202 1203 /* PHB3 controllers */ 1204 for (i = 0; i < chip->num_phbs; i++) { 1205 PnvPHB3 *phb = &chip8->phbs[i]; 1206 PnvPBCQState *pbcq = &phb->pbcq; 1207 1208 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1209 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1210 &error_fatal); 1211 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1212 return; 1213 } 1214 1215 /* Populate the XSCOM address space. */ 1216 pnv_xscom_add_subregion(chip, 1217 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1218 &pbcq->xscom_nest_regs); 1219 pnv_xscom_add_subregion(chip, 1220 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1221 &pbcq->xscom_pci_regs); 1222 pnv_xscom_add_subregion(chip, 1223 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1224 &pbcq->xscom_spci_regs); 1225 } 1226 } 1227 1228 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1229 { 1230 addr &= (PNV_XSCOM_SIZE - 1); 1231 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1232 } 1233 1234 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1235 { 1236 DeviceClass *dc = DEVICE_CLASS(klass); 1237 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1238 1239 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1240 k->cores_mask = POWER8E_CORE_MASK; 1241 k->num_phbs = 3; 1242 k->core_pir = pnv_chip_core_pir_p8; 1243 k->intc_create = pnv_chip_power8_intc_create; 1244 k->intc_reset = pnv_chip_power8_intc_reset; 1245 k->intc_destroy = pnv_chip_power8_intc_destroy; 1246 k->intc_print_info = pnv_chip_power8_intc_print_info; 1247 k->isa_create = pnv_chip_power8_isa_create; 1248 k->dt_populate = pnv_chip_power8_dt_populate; 1249 k->pic_print_info = pnv_chip_power8_pic_print_info; 1250 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1251 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1252 dc->desc = "PowerNV Chip POWER8E"; 1253 1254 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1255 &k->parent_realize); 1256 } 1257 1258 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1259 { 1260 DeviceClass *dc = DEVICE_CLASS(klass); 1261 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1262 1263 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1264 k->cores_mask = POWER8_CORE_MASK; 1265 k->num_phbs = 3; 1266 k->core_pir = pnv_chip_core_pir_p8; 1267 k->intc_create = pnv_chip_power8_intc_create; 1268 k->intc_reset = pnv_chip_power8_intc_reset; 1269 k->intc_destroy = pnv_chip_power8_intc_destroy; 1270 k->intc_print_info = pnv_chip_power8_intc_print_info; 1271 k->isa_create = pnv_chip_power8_isa_create; 1272 k->dt_populate = pnv_chip_power8_dt_populate; 1273 k->pic_print_info = pnv_chip_power8_pic_print_info; 1274 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1275 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1276 dc->desc = "PowerNV Chip POWER8"; 1277 1278 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1279 &k->parent_realize); 1280 } 1281 1282 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1283 { 1284 DeviceClass *dc = DEVICE_CLASS(klass); 1285 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1286 1287 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1288 k->cores_mask = POWER8_CORE_MASK; 1289 k->num_phbs = 3; 1290 k->core_pir = pnv_chip_core_pir_p8; 1291 k->intc_create = pnv_chip_power8_intc_create; 1292 k->intc_reset = pnv_chip_power8_intc_reset; 1293 k->intc_destroy = pnv_chip_power8_intc_destroy; 1294 k->intc_print_info = pnv_chip_power8_intc_print_info; 1295 k->isa_create = pnv_chip_power8nvl_isa_create; 1296 k->dt_populate = pnv_chip_power8_dt_populate; 1297 k->pic_print_info = pnv_chip_power8_pic_print_info; 1298 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1299 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1300 dc->desc = "PowerNV Chip POWER8NVL"; 1301 1302 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1303 &k->parent_realize); 1304 } 1305 1306 static void pnv_chip_power9_instance_init(Object *obj) 1307 { 1308 PnvChip *chip = PNV_CHIP(obj); 1309 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1310 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1311 int i; 1312 1313 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1314 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1315 "xive-fabric"); 1316 1317 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1318 1319 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1320 1321 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1322 1323 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1324 1325 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1326 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1327 TYPE_PNV_PHB4_PEC); 1328 } 1329 1330 /* 1331 * Number of PHBs is the chip default 1332 */ 1333 chip->num_phbs = pcc->num_phbs; 1334 } 1335 1336 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1337 { 1338 PnvChip *chip = PNV_CHIP(chip9); 1339 int i; 1340 1341 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1342 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1343 1344 for (i = 0; i < chip9->nr_quads; i++) { 1345 char eq_name[32]; 1346 PnvQuad *eq = &chip9->quads[i]; 1347 PnvCore *pnv_core = chip->cores[i * 4]; 1348 int core_id = CPU_CORE(pnv_core)->core_id; 1349 1350 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1351 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1352 sizeof(*eq), TYPE_PNV_QUAD, 1353 &error_fatal, NULL); 1354 1355 object_property_set_int(OBJECT(eq), "id", core_id, &error_fatal); 1356 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1357 1358 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1359 &eq->xscom_regs); 1360 } 1361 } 1362 1363 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1364 { 1365 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1366 int i, j; 1367 int phb_id = 0; 1368 1369 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1370 PnvPhb4PecState *pec = &chip9->pecs[i]; 1371 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1372 uint32_t pec_nest_base; 1373 uint32_t pec_pci_base; 1374 1375 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1376 /* 1377 * PEC0 -> 1 stack 1378 * PEC1 -> 2 stacks 1379 * PEC2 -> 3 stacks 1380 */ 1381 object_property_set_int(OBJECT(pec), "num-stacks", i + 1, 1382 &error_fatal); 1383 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1384 &error_fatal); 1385 object_property_set_link(OBJECT(pec), "system-memory", 1386 OBJECT(get_system_memory()), &error_abort); 1387 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1388 return; 1389 } 1390 1391 pec_nest_base = pecc->xscom_nest_base(pec); 1392 pec_pci_base = pecc->xscom_pci_base(pec); 1393 1394 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1395 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1396 1397 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1398 j++, phb_id++) { 1399 PnvPhb4PecStack *stack = &pec->stacks[j]; 1400 Object *obj = OBJECT(&stack->phb); 1401 1402 object_property_set_int(obj, "index", phb_id, &error_fatal); 1403 object_property_set_int(obj, "chip-id", chip->chip_id, 1404 &error_fatal); 1405 object_property_set_int(obj, "version", PNV_PHB4_VERSION, 1406 &error_fatal); 1407 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, 1408 &error_fatal); 1409 object_property_set_link(obj, "stack", OBJECT(stack), 1410 &error_abort); 1411 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { 1412 return; 1413 } 1414 1415 /* Populate the XSCOM address space. */ 1416 pnv_xscom_add_subregion(chip, 1417 pec_nest_base + 0x40 * (stack->stack_no + 1), 1418 &stack->nest_regs_mr); 1419 pnv_xscom_add_subregion(chip, 1420 pec_pci_base + 0x40 * (stack->stack_no + 1), 1421 &stack->pci_regs_mr); 1422 pnv_xscom_add_subregion(chip, 1423 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1424 0x40 * stack->stack_no, 1425 &stack->phb_regs_mr); 1426 } 1427 } 1428 } 1429 1430 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1431 { 1432 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1433 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1434 PnvChip *chip = PNV_CHIP(dev); 1435 Pnv9Psi *psi9 = &chip9->psi; 1436 Error *local_err = NULL; 1437 1438 /* XSCOM bridge is first */ 1439 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1440 if (local_err) { 1441 error_propagate(errp, local_err); 1442 return; 1443 } 1444 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1445 1446 pcc->parent_realize(dev, &local_err); 1447 if (local_err) { 1448 error_propagate(errp, local_err); 1449 return; 1450 } 1451 1452 pnv_chip_quad_realize(chip9, &local_err); 1453 if (local_err) { 1454 error_propagate(errp, local_err); 1455 return; 1456 } 1457 1458 /* XIVE interrupt controller (POWER9) */ 1459 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1460 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1461 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1462 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1463 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1464 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1465 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1466 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1467 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1468 &error_abort); 1469 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1470 return; 1471 } 1472 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1473 &chip9->xive.xscom_regs); 1474 1475 /* Processor Service Interface (PSI) Host Bridge */ 1476 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1477 &error_fatal); 1478 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1479 return; 1480 } 1481 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1482 &PNV_PSI(psi9)->xscom_regs); 1483 1484 /* LPC */ 1485 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1486 &error_abort); 1487 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1488 return; 1489 } 1490 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1491 &chip9->lpc.xscom_regs); 1492 1493 chip->fw_mr = &chip9->lpc.isa_fw; 1494 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1495 (uint64_t) PNV9_LPCM_BASE(chip)); 1496 1497 /* Create the simplified OCC model */ 1498 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1499 &error_abort); 1500 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1501 return; 1502 } 1503 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1504 1505 /* OCC SRAM model */ 1506 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1507 &chip9->occ.sram_regs); 1508 1509 /* HOMER */ 1510 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1511 &error_abort); 1512 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1513 return; 1514 } 1515 /* Homer Xscom region */ 1516 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1517 1518 /* Homer mmio region */ 1519 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1520 &chip9->homer.regs); 1521 1522 /* PHBs */ 1523 pnv_chip_power9_phb_realize(chip, &local_err); 1524 if (local_err) { 1525 error_propagate(errp, local_err); 1526 return; 1527 } 1528 } 1529 1530 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1531 { 1532 addr &= (PNV9_XSCOM_SIZE - 1); 1533 return addr >> 3; 1534 } 1535 1536 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1537 { 1538 DeviceClass *dc = DEVICE_CLASS(klass); 1539 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1540 1541 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1542 k->cores_mask = POWER9_CORE_MASK; 1543 k->core_pir = pnv_chip_core_pir_p9; 1544 k->intc_create = pnv_chip_power9_intc_create; 1545 k->intc_reset = pnv_chip_power9_intc_reset; 1546 k->intc_destroy = pnv_chip_power9_intc_destroy; 1547 k->intc_print_info = pnv_chip_power9_intc_print_info; 1548 k->isa_create = pnv_chip_power9_isa_create; 1549 k->dt_populate = pnv_chip_power9_dt_populate; 1550 k->pic_print_info = pnv_chip_power9_pic_print_info; 1551 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1552 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1553 dc->desc = "PowerNV Chip POWER9"; 1554 k->num_phbs = 6; 1555 1556 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1557 &k->parent_realize); 1558 } 1559 1560 static void pnv_chip_power10_instance_init(Object *obj) 1561 { 1562 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1563 1564 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1565 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1566 } 1567 1568 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1569 { 1570 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1571 PnvChip *chip = PNV_CHIP(dev); 1572 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1573 Error *local_err = NULL; 1574 1575 /* XSCOM bridge is first */ 1576 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1577 if (local_err) { 1578 error_propagate(errp, local_err); 1579 return; 1580 } 1581 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1582 1583 pcc->parent_realize(dev, &local_err); 1584 if (local_err) { 1585 error_propagate(errp, local_err); 1586 return; 1587 } 1588 1589 /* Processor Service Interface (PSI) Host Bridge */ 1590 object_property_set_int(OBJECT(&chip10->psi), "bar", 1591 PNV10_PSIHB_BASE(chip), &error_fatal); 1592 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1593 return; 1594 } 1595 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1596 &PNV_PSI(&chip10->psi)->xscom_regs); 1597 1598 /* LPC */ 1599 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1600 OBJECT(&chip10->psi), &error_abort); 1601 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1602 return; 1603 } 1604 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1605 &chip10->lpc.xscom_regs); 1606 1607 chip->fw_mr = &chip10->lpc.isa_fw; 1608 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1609 (uint64_t) PNV10_LPCM_BASE(chip)); 1610 } 1611 1612 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1613 { 1614 addr &= (PNV10_XSCOM_SIZE - 1); 1615 return addr >> 3; 1616 } 1617 1618 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1619 { 1620 DeviceClass *dc = DEVICE_CLASS(klass); 1621 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1622 1623 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1624 k->cores_mask = POWER10_CORE_MASK; 1625 k->core_pir = pnv_chip_core_pir_p10; 1626 k->intc_create = pnv_chip_power10_intc_create; 1627 k->intc_reset = pnv_chip_power10_intc_reset; 1628 k->intc_destroy = pnv_chip_power10_intc_destroy; 1629 k->intc_print_info = pnv_chip_power10_intc_print_info; 1630 k->isa_create = pnv_chip_power10_isa_create; 1631 k->dt_populate = pnv_chip_power10_dt_populate; 1632 k->pic_print_info = pnv_chip_power10_pic_print_info; 1633 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1634 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1635 dc->desc = "PowerNV Chip POWER10"; 1636 1637 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1638 &k->parent_realize); 1639 } 1640 1641 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1642 { 1643 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1644 int cores_max; 1645 1646 /* 1647 * No custom mask for this chip, let's use the default one from * 1648 * the chip class 1649 */ 1650 if (!chip->cores_mask) { 1651 chip->cores_mask = pcc->cores_mask; 1652 } 1653 1654 /* filter alien core ids ! some are reserved */ 1655 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1656 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1657 chip->cores_mask); 1658 return; 1659 } 1660 chip->cores_mask &= pcc->cores_mask; 1661 1662 /* now that we have a sane layout, let check the number of cores */ 1663 cores_max = ctpop64(chip->cores_mask); 1664 if (chip->nr_cores > cores_max) { 1665 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1666 cores_max); 1667 return; 1668 } 1669 } 1670 1671 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1672 { 1673 Error *error = NULL; 1674 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1675 const char *typename = pnv_chip_core_typename(chip); 1676 int i, core_hwid; 1677 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1678 1679 if (!object_class_by_name(typename)) { 1680 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1681 return; 1682 } 1683 1684 /* Cores */ 1685 pnv_chip_core_sanitize(chip, &error); 1686 if (error) { 1687 error_propagate(errp, error); 1688 return; 1689 } 1690 1691 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1692 1693 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1694 && (i < chip->nr_cores); core_hwid++) { 1695 char core_name[32]; 1696 PnvCore *pnv_core; 1697 uint64_t xscom_core_base; 1698 1699 if (!(chip->cores_mask & (1ull << core_hwid))) { 1700 continue; 1701 } 1702 1703 pnv_core = PNV_CORE(object_new(typename)); 1704 1705 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1706 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1707 chip->cores[i] = pnv_core; 1708 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1709 chip->nr_threads, &error_fatal); 1710 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1711 core_hwid, &error_fatal); 1712 object_property_set_int(OBJECT(pnv_core), "pir", 1713 pcc->core_pir(chip, core_hwid), &error_fatal); 1714 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1715 &error_fatal); 1716 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1717 &error_abort); 1718 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1719 1720 /* Each core has an XSCOM MMIO region */ 1721 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1722 1723 pnv_xscom_add_subregion(chip, xscom_core_base, 1724 &pnv_core->xscom_regs); 1725 i++; 1726 } 1727 } 1728 1729 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1730 { 1731 PnvChip *chip = PNV_CHIP(dev); 1732 Error *error = NULL; 1733 1734 /* Cores */ 1735 pnv_chip_core_realize(chip, &error); 1736 if (error) { 1737 error_propagate(errp, error); 1738 return; 1739 } 1740 } 1741 1742 static Property pnv_chip_properties[] = { 1743 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1744 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1745 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1746 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1747 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1748 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1749 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1750 DEFINE_PROP_END_OF_LIST(), 1751 }; 1752 1753 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1754 { 1755 DeviceClass *dc = DEVICE_CLASS(klass); 1756 1757 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1758 dc->realize = pnv_chip_realize; 1759 device_class_set_props(dc, pnv_chip_properties); 1760 dc->desc = "PowerNV Chip"; 1761 } 1762 1763 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1764 { 1765 int i, j; 1766 1767 for (i = 0; i < chip->nr_cores; i++) { 1768 PnvCore *pc = chip->cores[i]; 1769 CPUCore *cc = CPU_CORE(pc); 1770 1771 for (j = 0; j < cc->nr_threads; j++) { 1772 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1773 return pc->threads[j]; 1774 } 1775 } 1776 } 1777 return NULL; 1778 } 1779 1780 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1781 { 1782 PnvMachineState *pnv = PNV_MACHINE(xi); 1783 int i, j; 1784 1785 for (i = 0; i < pnv->num_chips; i++) { 1786 PnvChip *chip = pnv->chips[i]; 1787 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1788 1789 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1790 return &chip8->psi.ics; 1791 } 1792 for (j = 0; j < chip->num_phbs; j++) { 1793 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1794 return &chip8->phbs[j].lsis; 1795 } 1796 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1797 return ICS(&chip8->phbs[j].msis); 1798 } 1799 } 1800 } 1801 return NULL; 1802 } 1803 1804 static void pnv_ics_resend(XICSFabric *xi) 1805 { 1806 PnvMachineState *pnv = PNV_MACHINE(xi); 1807 int i, j; 1808 1809 for (i = 0; i < pnv->num_chips; i++) { 1810 PnvChip *chip = pnv->chips[i]; 1811 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1812 1813 ics_resend(&chip8->psi.ics); 1814 for (j = 0; j < chip->num_phbs; j++) { 1815 ics_resend(&chip8->phbs[j].lsis); 1816 ics_resend(ICS(&chip8->phbs[j].msis)); 1817 } 1818 } 1819 } 1820 1821 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1822 { 1823 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1824 1825 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1826 } 1827 1828 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1829 Monitor *mon) 1830 { 1831 PnvMachineState *pnv = PNV_MACHINE(obj); 1832 int i; 1833 CPUState *cs; 1834 1835 CPU_FOREACH(cs) { 1836 PowerPCCPU *cpu = POWERPC_CPU(cs); 1837 1838 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1839 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1840 mon); 1841 } 1842 1843 for (i = 0; i < pnv->num_chips; i++) { 1844 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1845 } 1846 } 1847 1848 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1849 uint8_t nvt_blk, uint32_t nvt_idx, 1850 bool cam_ignore, uint8_t priority, 1851 uint32_t logic_serv, 1852 XiveTCTXMatch *match) 1853 { 1854 PnvMachineState *pnv = PNV_MACHINE(xfb); 1855 int total_count = 0; 1856 int i; 1857 1858 for (i = 0; i < pnv->num_chips; i++) { 1859 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1860 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1861 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1862 int count; 1863 1864 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1865 priority, logic_serv, match); 1866 1867 if (count < 0) { 1868 return count; 1869 } 1870 1871 total_count += count; 1872 } 1873 1874 return total_count; 1875 } 1876 1877 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1878 { 1879 MachineClass *mc = MACHINE_CLASS(oc); 1880 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1881 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1882 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1883 1884 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1885 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1886 1887 xic->icp_get = pnv_icp_get; 1888 xic->ics_get = pnv_ics_get; 1889 xic->ics_resend = pnv_ics_resend; 1890 1891 pmc->compat = compat; 1892 pmc->compat_size = sizeof(compat); 1893 } 1894 1895 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1896 { 1897 MachineClass *mc = MACHINE_CLASS(oc); 1898 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1899 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1900 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1901 1902 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1903 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1904 xfc->match_nvt = pnv_match_nvt; 1905 1906 mc->alias = "powernv"; 1907 1908 pmc->compat = compat; 1909 pmc->compat_size = sizeof(compat); 1910 pmc->dt_power_mgt = pnv_dt_power_mgt; 1911 } 1912 1913 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1914 { 1915 MachineClass *mc = MACHINE_CLASS(oc); 1916 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1917 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1918 1919 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1920 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1921 1922 pmc->compat = compat; 1923 pmc->compat_size = sizeof(compat); 1924 pmc->dt_power_mgt = pnv_dt_power_mgt; 1925 } 1926 1927 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1928 { 1929 PnvMachineState *pnv = PNV_MACHINE(obj); 1930 1931 return !!pnv->fw_load_addr; 1932 } 1933 1934 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1935 { 1936 PnvMachineState *pnv = PNV_MACHINE(obj); 1937 1938 if (value) { 1939 pnv->fw_load_addr = 0x8000000; 1940 } 1941 } 1942 1943 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1944 { 1945 PowerPCCPU *cpu = POWERPC_CPU(cs); 1946 CPUPPCState *env = &cpu->env; 1947 1948 cpu_synchronize_state(cs); 1949 ppc_cpu_do_system_reset(cs); 1950 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1951 /* 1952 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1953 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1954 * (PPC_BIT(43)). 1955 */ 1956 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1957 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1958 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1959 } 1960 } else { 1961 /* 1962 * For non-powersave system resets, SRR1[42:45] are defined to be 1963 * implementation-dependent. The POWER9 User Manual specifies that 1964 * an external (SCOM driven, which may come from a BMC nmi command or 1965 * another CPU requesting a NMI IPI) system reset exception should be 1966 * 0b0010 (PPC_BIT(44)). 1967 */ 1968 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1969 } 1970 } 1971 1972 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1973 { 1974 CPUState *cs; 1975 1976 CPU_FOREACH(cs) { 1977 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 1978 } 1979 } 1980 1981 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1982 { 1983 MachineClass *mc = MACHINE_CLASS(oc); 1984 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1985 NMIClass *nc = NMI_CLASS(oc); 1986 1987 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1988 mc->init = pnv_init; 1989 mc->reset = pnv_reset; 1990 mc->max_cpus = MAX_CPUS; 1991 /* Pnv provides a AHCI device for storage */ 1992 mc->block_default_type = IF_IDE; 1993 mc->no_parallel = 1; 1994 mc->default_boot_order = NULL; 1995 /* 1996 * RAM defaults to less than 2048 for 32-bit hosts, and large 1997 * enough to fit the maximum initrd size at it's load address 1998 */ 1999 mc->default_ram_size = 1 * GiB; 2000 mc->default_ram_id = "pnv.ram"; 2001 ispc->print_info = pnv_pic_print_info; 2002 nc->nmi_monitor_handler = pnv_nmi; 2003 2004 object_class_property_add_bool(oc, "hb-mode", 2005 pnv_machine_get_hb, pnv_machine_set_hb); 2006 object_class_property_set_description(oc, "hb-mode", 2007 "Use a hostboot like boot loader"); 2008 } 2009 2010 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2011 { \ 2012 .name = type, \ 2013 .class_init = class_initfn, \ 2014 .parent = TYPE_PNV8_CHIP, \ 2015 } 2016 2017 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2018 { \ 2019 .name = type, \ 2020 .class_init = class_initfn, \ 2021 .parent = TYPE_PNV9_CHIP, \ 2022 } 2023 2024 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2025 { \ 2026 .name = type, \ 2027 .class_init = class_initfn, \ 2028 .parent = TYPE_PNV10_CHIP, \ 2029 } 2030 2031 static const TypeInfo types[] = { 2032 { 2033 .name = MACHINE_TYPE_NAME("powernv10"), 2034 .parent = TYPE_PNV_MACHINE, 2035 .class_init = pnv_machine_power10_class_init, 2036 }, 2037 { 2038 .name = MACHINE_TYPE_NAME("powernv9"), 2039 .parent = TYPE_PNV_MACHINE, 2040 .class_init = pnv_machine_power9_class_init, 2041 .interfaces = (InterfaceInfo[]) { 2042 { TYPE_XIVE_FABRIC }, 2043 { }, 2044 }, 2045 }, 2046 { 2047 .name = MACHINE_TYPE_NAME("powernv8"), 2048 .parent = TYPE_PNV_MACHINE, 2049 .class_init = pnv_machine_power8_class_init, 2050 .interfaces = (InterfaceInfo[]) { 2051 { TYPE_XICS_FABRIC }, 2052 { }, 2053 }, 2054 }, 2055 { 2056 .name = TYPE_PNV_MACHINE, 2057 .parent = TYPE_MACHINE, 2058 .abstract = true, 2059 .instance_size = sizeof(PnvMachineState), 2060 .class_init = pnv_machine_class_init, 2061 .class_size = sizeof(PnvMachineClass), 2062 .interfaces = (InterfaceInfo[]) { 2063 { TYPE_INTERRUPT_STATS_PROVIDER }, 2064 { TYPE_NMI }, 2065 { }, 2066 }, 2067 }, 2068 { 2069 .name = TYPE_PNV_CHIP, 2070 .parent = TYPE_SYS_BUS_DEVICE, 2071 .class_init = pnv_chip_class_init, 2072 .instance_size = sizeof(PnvChip), 2073 .class_size = sizeof(PnvChipClass), 2074 .abstract = true, 2075 }, 2076 2077 /* 2078 * P10 chip and variants 2079 */ 2080 { 2081 .name = TYPE_PNV10_CHIP, 2082 .parent = TYPE_PNV_CHIP, 2083 .instance_init = pnv_chip_power10_instance_init, 2084 .instance_size = sizeof(Pnv10Chip), 2085 }, 2086 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2087 2088 /* 2089 * P9 chip and variants 2090 */ 2091 { 2092 .name = TYPE_PNV9_CHIP, 2093 .parent = TYPE_PNV_CHIP, 2094 .instance_init = pnv_chip_power9_instance_init, 2095 .instance_size = sizeof(Pnv9Chip), 2096 }, 2097 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2098 2099 /* 2100 * P8 chip and variants 2101 */ 2102 { 2103 .name = TYPE_PNV8_CHIP, 2104 .parent = TYPE_PNV_CHIP, 2105 .instance_init = pnv_chip_power8_instance_init, 2106 .instance_size = sizeof(Pnv8Chip), 2107 }, 2108 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2109 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2110 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2111 pnv_chip_power8nvl_class_init), 2112 }; 2113 2114 DEFINE_TYPES(types) 2115