1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (16 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (128 * MiB) 67 #define INITRD_LOAD_ADDR 0x28000000 68 #define INITRD_MAX_SIZE (128 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (ppc_has_spr(cpu, SPR_PURR)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 uint32_t irq; 384 char *name; 385 int node; 386 387 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 388 389 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 390 node = fdt_add_subnode(fdt, lpc_off, name); 391 _FDT(node); 392 g_free(name); 393 394 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 395 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 396 sizeof(compatible)))); 397 398 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 399 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 400 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 401 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 402 fdt_get_phandle(fdt, lpc_off)))); 403 404 /* This is needed by Linux */ 405 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 406 } 407 408 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 409 { 410 const char compatible[] = "bt\0ipmi-bt"; 411 uint32_t io_base; 412 uint32_t io_regs[] = { 413 cpu_to_be32(1), 414 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 415 cpu_to_be32(3) 416 }; 417 uint32_t irq; 418 char *name; 419 int node; 420 421 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 422 io_regs[1] = cpu_to_be32(io_base); 423 424 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 425 426 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 427 node = fdt_add_subnode(fdt, lpc_off, name); 428 _FDT(node); 429 g_free(name); 430 431 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 432 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 433 sizeof(compatible)))); 434 435 /* Mark it as reserved to avoid Linux trying to claim it */ 436 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 437 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 438 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 439 fdt_get_phandle(fdt, lpc_off)))); 440 } 441 442 typedef struct ForeachPopulateArgs { 443 void *fdt; 444 int offset; 445 } ForeachPopulateArgs; 446 447 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 448 { 449 ForeachPopulateArgs *args = opaque; 450 ISADevice *d = ISA_DEVICE(dev); 451 452 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 453 pnv_dt_rtc(d, args->fdt, args->offset); 454 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 455 pnv_dt_serial(d, args->fdt, args->offset); 456 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 457 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 458 } else { 459 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 460 d->ioport_id); 461 } 462 463 return 0; 464 } 465 466 /* 467 * The default LPC bus of a multichip system is on chip 0. It's 468 * recognized by the firmware (skiboot) using a "primary" property. 469 */ 470 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 471 { 472 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 473 ForeachPopulateArgs args = { 474 .fdt = fdt, 475 .offset = isa_offset, 476 }; 477 uint32_t phandle; 478 479 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 480 481 phandle = qemu_fdt_alloc_phandle(fdt); 482 assert(phandle > 0); 483 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 484 485 /* 486 * ISA devices are not necessarily parented to the ISA bus so we 487 * can not use object_child_foreach() 488 */ 489 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 490 &args); 491 } 492 493 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 494 { 495 int off; 496 497 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 498 off = fdt_add_subnode(fdt, off, "power-mgt"); 499 500 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 501 } 502 503 static void *pnv_dt_create(MachineState *machine) 504 { 505 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 506 PnvMachineState *pnv = PNV_MACHINE(machine); 507 void *fdt; 508 char *buf; 509 int off; 510 int i; 511 512 fdt = g_malloc0(FDT_MAX_SIZE); 513 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 514 515 /* /qemu node */ 516 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 517 518 /* Root node */ 519 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 520 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 521 _FDT((fdt_setprop_string(fdt, 0, "model", 522 "IBM PowerNV (emulated by qemu)"))); 523 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 524 525 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 526 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 527 if (qemu_uuid_set) { 528 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 529 } 530 g_free(buf); 531 532 off = fdt_add_subnode(fdt, 0, "chosen"); 533 if (machine->kernel_cmdline) { 534 _FDT((fdt_setprop_string(fdt, off, "bootargs", 535 machine->kernel_cmdline))); 536 } 537 538 if (pnv->initrd_size) { 539 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 540 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 541 542 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 543 &start_prop, sizeof(start_prop)))); 544 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 545 &end_prop, sizeof(end_prop)))); 546 } 547 548 /* Populate device tree for each chip */ 549 for (i = 0; i < pnv->num_chips; i++) { 550 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 551 } 552 553 /* Populate ISA devices on chip 0 */ 554 pnv_dt_isa(pnv, fdt); 555 556 if (pnv->bmc) { 557 pnv_dt_bmc_sensors(pnv->bmc, fdt); 558 } 559 560 /* Create an extra node for power management on machines that support it */ 561 if (pmc->dt_power_mgt) { 562 pmc->dt_power_mgt(pnv, fdt); 563 } 564 565 return fdt; 566 } 567 568 static void pnv_powerdown_notify(Notifier *n, void *opaque) 569 { 570 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 571 572 if (pnv->bmc) { 573 pnv_bmc_powerdown(pnv->bmc); 574 } 575 } 576 577 static void pnv_reset(MachineState *machine) 578 { 579 PnvMachineState *pnv = PNV_MACHINE(machine); 580 IPMIBmc *bmc; 581 void *fdt; 582 583 qemu_devices_reset(); 584 585 /* 586 * The machine should provide by default an internal BMC simulator. 587 * If not, try to use the BMC device that was provided on the command 588 * line. 589 */ 590 bmc = pnv_bmc_find(&error_fatal); 591 if (!pnv->bmc) { 592 if (!bmc) { 593 if (!qtest_enabled()) { 594 warn_report("machine has no BMC device. Use '-device " 595 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 596 "to define one"); 597 } 598 } else { 599 pnv_bmc_set_pnor(bmc, pnv->pnor); 600 pnv->bmc = bmc; 601 } 602 } 603 604 fdt = pnv_dt_create(machine); 605 606 /* Pack resulting tree */ 607 _FDT((fdt_pack(fdt))); 608 609 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 610 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 611 612 g_free(fdt); 613 } 614 615 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 616 { 617 Pnv8Chip *chip8 = PNV8_CHIP(chip); 618 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 619 620 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 621 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 622 } 623 624 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 625 { 626 Pnv8Chip *chip8 = PNV8_CHIP(chip); 627 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 628 629 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 630 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 631 } 632 633 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 634 { 635 Pnv9Chip *chip9 = PNV9_CHIP(chip); 636 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 637 638 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 639 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 640 } 641 642 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 643 { 644 Pnv10Chip *chip10 = PNV10_CHIP(chip); 645 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 646 647 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 648 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 649 } 650 651 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 652 { 653 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 654 } 655 656 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 657 { 658 Pnv8Chip *chip8 = PNV8_CHIP(chip); 659 int i; 660 661 ics_pic_print_info(&chip8->psi.ics, mon); 662 663 for (i = 0; i < chip8->num_phbs; i++) { 664 PnvPHB *phb = &chip8->phbs[i]; 665 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 666 667 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 668 ics_pic_print_info(&phb3->lsis, mon); 669 } 670 } 671 672 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 673 { 674 Monitor *mon = opaque; 675 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 676 677 if (!phb) { 678 return 0; 679 } 680 681 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 682 683 return 0; 684 } 685 686 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 687 { 688 Pnv9Chip *chip9 = PNV9_CHIP(chip); 689 690 pnv_xive_pic_print_info(&chip9->xive, mon); 691 pnv_psi_pic_print_info(&chip9->psi, mon); 692 693 object_child_foreach_recursive(OBJECT(chip), 694 pnv_chip_power9_pic_print_info_child, mon); 695 } 696 697 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 698 uint32_t core_id) 699 { 700 return PNV_XSCOM_EX_BASE(core_id); 701 } 702 703 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 704 uint32_t core_id) 705 { 706 return PNV9_XSCOM_EC_BASE(core_id); 707 } 708 709 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 710 uint32_t core_id) 711 { 712 return PNV10_XSCOM_EC_BASE(core_id); 713 } 714 715 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 716 { 717 PowerPCCPUClass *ppc_default = 718 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 719 PowerPCCPUClass *ppc = 720 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 721 722 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 723 } 724 725 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 726 { 727 ISADevice *dev = isa_new("isa-ipmi-bt"); 728 729 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 730 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 731 isa_realize_and_unref(dev, bus, &error_fatal); 732 } 733 734 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 735 { 736 Pnv10Chip *chip10 = PNV10_CHIP(chip); 737 738 pnv_xive2_pic_print_info(&chip10->xive, mon); 739 pnv_psi_pic_print_info(&chip10->psi, mon); 740 741 object_child_foreach_recursive(OBJECT(chip), 742 pnv_chip_power9_pic_print_info_child, mon); 743 } 744 745 /* Always give the first 1GB to chip 0 else we won't boot */ 746 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 747 { 748 MachineState *machine = MACHINE(pnv); 749 uint64_t ram_per_chip; 750 751 assert(machine->ram_size >= 1 * GiB); 752 753 ram_per_chip = machine->ram_size / pnv->num_chips; 754 if (ram_per_chip >= 1 * GiB) { 755 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 756 } 757 758 assert(pnv->num_chips > 1); 759 760 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 761 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 762 } 763 764 static void pnv_init(MachineState *machine) 765 { 766 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 767 PnvMachineState *pnv = PNV_MACHINE(machine); 768 MachineClass *mc = MACHINE_GET_CLASS(machine); 769 char *fw_filename; 770 long fw_size; 771 uint64_t chip_ram_start = 0; 772 int i; 773 char *chip_typename; 774 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 775 DeviceState *dev; 776 777 if (kvm_enabled()) { 778 error_report("The powernv machine does not work with KVM acceleration"); 779 exit(EXIT_FAILURE); 780 } 781 782 /* allocate RAM */ 783 if (machine->ram_size < mc->default_ram_size) { 784 char *sz = size_to_str(mc->default_ram_size); 785 error_report("Invalid RAM size, should be bigger than %s", sz); 786 g_free(sz); 787 exit(EXIT_FAILURE); 788 } 789 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 790 791 /* 792 * Create our simple PNOR device 793 */ 794 dev = qdev_new(TYPE_PNV_PNOR); 795 if (pnor) { 796 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 797 } 798 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 799 pnv->pnor = PNV_PNOR(dev); 800 801 /* load skiboot firmware */ 802 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 803 if (!fw_filename) { 804 error_report("Could not find OPAL firmware '%s'", bios_name); 805 exit(1); 806 } 807 808 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 809 if (fw_size < 0) { 810 error_report("Could not load OPAL firmware '%s'", fw_filename); 811 exit(1); 812 } 813 g_free(fw_filename); 814 815 /* load kernel */ 816 if (machine->kernel_filename) { 817 long kernel_size; 818 819 kernel_size = load_image_targphys(machine->kernel_filename, 820 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 821 if (kernel_size < 0) { 822 error_report("Could not load kernel '%s'", 823 machine->kernel_filename); 824 exit(1); 825 } 826 } 827 828 /* load initrd */ 829 if (machine->initrd_filename) { 830 pnv->initrd_base = INITRD_LOAD_ADDR; 831 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 832 pnv->initrd_base, INITRD_MAX_SIZE); 833 if (pnv->initrd_size < 0) { 834 error_report("Could not load initial ram disk '%s'", 835 machine->initrd_filename); 836 exit(1); 837 } 838 } 839 840 /* MSIs are supported on this platform */ 841 msi_nonbroken = true; 842 843 /* 844 * Check compatibility of the specified CPU with the machine 845 * default. 846 */ 847 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 848 error_report("invalid CPU model '%s' for %s machine", 849 machine->cpu_type, mc->name); 850 exit(1); 851 } 852 853 /* Create the processor chips */ 854 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 855 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 856 i, machine->cpu_type); 857 if (!object_class_by_name(chip_typename)) { 858 error_report("invalid chip model '%.*s' for %s machine", 859 i, machine->cpu_type, mc->name); 860 exit(1); 861 } 862 863 pnv->num_chips = 864 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 865 /* 866 * TODO: should we decide on how many chips we can create based 867 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 868 */ 869 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 870 error_report("invalid number of chips: '%d'", pnv->num_chips); 871 error_printf( 872 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 873 exit(1); 874 } 875 876 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 877 for (i = 0; i < pnv->num_chips; i++) { 878 char chip_name[32]; 879 Object *chip = OBJECT(qdev_new(chip_typename)); 880 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 881 882 pnv->chips[i] = PNV_CHIP(chip); 883 884 /* Distribute RAM among the chips */ 885 object_property_set_int(chip, "ram-start", chip_ram_start, 886 &error_fatal); 887 object_property_set_int(chip, "ram-size", chip_ram_size, 888 &error_fatal); 889 chip_ram_start += chip_ram_size; 890 891 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 892 object_property_add_child(OBJECT(pnv), chip_name, chip); 893 object_property_set_int(chip, "chip-id", i, &error_fatal); 894 object_property_set_int(chip, "nr-cores", machine->smp.cores, 895 &error_fatal); 896 object_property_set_int(chip, "nr-threads", machine->smp.threads, 897 &error_fatal); 898 /* 899 * The POWER8 machine use the XICS interrupt interface. 900 * Propagate the XICS fabric to the chip and its controllers. 901 */ 902 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 903 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 904 } 905 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 906 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 907 &error_abort); 908 } 909 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 910 } 911 g_free(chip_typename); 912 913 /* Instantiate ISA bus on chip 0 */ 914 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 915 916 /* Create serial port */ 917 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 918 919 /* Create an RTC ISA device too */ 920 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 921 922 /* 923 * Create the machine BMC simulator and the IPMI BT device for 924 * communication with the BMC 925 */ 926 if (defaults_enabled()) { 927 pnv->bmc = pnv_bmc_create(pnv->pnor); 928 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 929 } 930 931 /* 932 * The PNOR is mapped on the LPC FW address space by the BMC. 933 * Since we can not reach the remote BMC machine with LPC memops, 934 * map it always for now. 935 */ 936 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 937 &pnv->pnor->mmio); 938 939 /* 940 * OpenPOWER systems use a IPMI SEL Event message to notify the 941 * host to powerdown 942 */ 943 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 944 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 945 } 946 947 /* 948 * 0:21 Reserved - Read as zeros 949 * 22:24 Chip ID 950 * 25:28 Core number 951 * 29:31 Thread ID 952 */ 953 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 954 { 955 return (chip->chip_id << 7) | (core_id << 3); 956 } 957 958 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 959 Error **errp) 960 { 961 Pnv8Chip *chip8 = PNV8_CHIP(chip); 962 Error *local_err = NULL; 963 Object *obj; 964 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 965 966 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 967 if (local_err) { 968 error_propagate(errp, local_err); 969 return; 970 } 971 972 pnv_cpu->intc = obj; 973 } 974 975 976 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 977 { 978 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 979 980 icp_reset(ICP(pnv_cpu->intc)); 981 } 982 983 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 984 { 985 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 986 987 icp_destroy(ICP(pnv_cpu->intc)); 988 pnv_cpu->intc = NULL; 989 } 990 991 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 992 Monitor *mon) 993 { 994 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 995 } 996 997 /* 998 * 0:48 Reserved - Read as zeroes 999 * 49:52 Node ID 1000 * 53:55 Chip ID 1001 * 56 Reserved - Read as zero 1002 * 57:61 Core number 1003 * 62:63 Thread ID 1004 * 1005 * We only care about the lower bits. uint32_t is fine for the moment. 1006 */ 1007 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1008 { 1009 return (chip->chip_id << 8) | (core_id << 2); 1010 } 1011 1012 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1013 { 1014 return (chip->chip_id << 8) | (core_id << 2); 1015 } 1016 1017 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1018 Error **errp) 1019 { 1020 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1021 Error *local_err = NULL; 1022 Object *obj; 1023 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1024 1025 /* 1026 * The core creates its interrupt presenter but the XIVE interrupt 1027 * controller object is initialized afterwards. Hopefully, it's 1028 * only used at runtime. 1029 */ 1030 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1031 &local_err); 1032 if (local_err) { 1033 error_propagate(errp, local_err); 1034 return; 1035 } 1036 1037 pnv_cpu->intc = obj; 1038 } 1039 1040 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1041 { 1042 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1043 1044 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1045 } 1046 1047 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1048 { 1049 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1050 1051 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1052 pnv_cpu->intc = NULL; 1053 } 1054 1055 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1056 Monitor *mon) 1057 { 1058 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1059 } 1060 1061 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1062 Error **errp) 1063 { 1064 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1065 Error *local_err = NULL; 1066 Object *obj; 1067 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1068 1069 /* 1070 * The core creates its interrupt presenter but the XIVE2 interrupt 1071 * controller object is initialized afterwards. Hopefully, it's 1072 * only used at runtime. 1073 */ 1074 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1075 &local_err); 1076 if (local_err) { 1077 error_propagate(errp, local_err); 1078 return; 1079 } 1080 1081 pnv_cpu->intc = obj; 1082 } 1083 1084 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1085 { 1086 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1087 1088 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1089 } 1090 1091 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1092 { 1093 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1094 1095 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1096 pnv_cpu->intc = NULL; 1097 } 1098 1099 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1100 Monitor *mon) 1101 { 1102 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1103 } 1104 1105 /* 1106 * Allowed core identifiers on a POWER8 Processor Chip : 1107 * 1108 * <EX0 reserved> 1109 * EX1 - Venice only 1110 * EX2 - Venice only 1111 * EX3 - Venice only 1112 * EX4 1113 * EX5 1114 * EX6 1115 * <EX7,8 reserved> <reserved> 1116 * EX9 - Venice only 1117 * EX10 - Venice only 1118 * EX11 - Venice only 1119 * EX12 1120 * EX13 1121 * EX14 1122 * <EX15 reserved> 1123 */ 1124 #define POWER8E_CORE_MASK (0x7070ull) 1125 #define POWER8_CORE_MASK (0x7e7eull) 1126 1127 /* 1128 * POWER9 has 24 cores, ids starting at 0x0 1129 */ 1130 #define POWER9_CORE_MASK (0xffffffffffffffull) 1131 1132 1133 #define POWER10_CORE_MASK (0xffffffffffffffull) 1134 1135 static void pnv_chip_power8_instance_init(Object *obj) 1136 { 1137 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1138 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1139 int i; 1140 1141 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1142 (Object **)&chip8->xics, 1143 object_property_allow_set_link, 1144 OBJ_PROP_LINK_STRONG); 1145 1146 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1147 1148 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1149 1150 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1151 1152 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1153 1154 chip8->num_phbs = pcc->num_phbs; 1155 1156 for (i = 0; i < chip8->num_phbs; i++) { 1157 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB); 1158 } 1159 1160 } 1161 1162 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1163 { 1164 PnvChip *chip = PNV_CHIP(chip8); 1165 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1166 int i, j; 1167 char *name; 1168 1169 name = g_strdup_printf("icp-%x", chip->chip_id); 1170 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1171 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1172 g_free(name); 1173 1174 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1175 1176 /* Map the ICP registers for each thread */ 1177 for (i = 0; i < chip->nr_cores; i++) { 1178 PnvCore *pnv_core = chip->cores[i]; 1179 int core_hwid = CPU_CORE(pnv_core)->core_id; 1180 1181 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1182 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1183 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1184 1185 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1186 &icp->mmio); 1187 } 1188 } 1189 } 1190 1191 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1192 { 1193 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1194 PnvChip *chip = PNV_CHIP(dev); 1195 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1196 Pnv8Psi *psi8 = &chip8->psi; 1197 Error *local_err = NULL; 1198 int i; 1199 1200 assert(chip8->xics); 1201 1202 /* XSCOM bridge is first */ 1203 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1204 if (local_err) { 1205 error_propagate(errp, local_err); 1206 return; 1207 } 1208 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1209 1210 pcc->parent_realize(dev, &local_err); 1211 if (local_err) { 1212 error_propagate(errp, local_err); 1213 return; 1214 } 1215 1216 /* Processor Service Interface (PSI) Host Bridge */ 1217 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1218 &error_fatal); 1219 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1220 OBJECT(chip8->xics), &error_abort); 1221 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1222 return; 1223 } 1224 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1225 &PNV_PSI(psi8)->xscom_regs); 1226 1227 /* Create LPC controller */ 1228 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1229 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1230 1231 chip->fw_mr = &chip8->lpc.isa_fw; 1232 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1233 (uint64_t) PNV_XSCOM_BASE(chip), 1234 PNV_XSCOM_LPC_BASE); 1235 1236 /* 1237 * Interrupt Management Area. This is the memory region holding 1238 * all the Interrupt Control Presenter (ICP) registers 1239 */ 1240 pnv_chip_icp_realize(chip8, &local_err); 1241 if (local_err) { 1242 error_propagate(errp, local_err); 1243 return; 1244 } 1245 1246 /* Create the simplified OCC model */ 1247 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1248 return; 1249 } 1250 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1251 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1252 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1253 1254 /* OCC SRAM model */ 1255 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1256 &chip8->occ.sram_regs); 1257 1258 /* HOMER */ 1259 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1260 &error_abort); 1261 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1262 return; 1263 } 1264 /* Homer Xscom region */ 1265 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1266 1267 /* Homer mmio region */ 1268 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1269 &chip8->homer.regs); 1270 1271 /* PHB controllers */ 1272 for (i = 0; i < chip8->num_phbs; i++) { 1273 PnvPHB *phb = &chip8->phbs[i]; 1274 1275 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1276 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1277 &error_fatal); 1278 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1279 &error_fatal); 1280 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1281 return; 1282 } 1283 } 1284 } 1285 1286 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1287 { 1288 addr &= (PNV_XSCOM_SIZE - 1); 1289 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1290 } 1291 1292 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1293 { 1294 DeviceClass *dc = DEVICE_CLASS(klass); 1295 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1296 1297 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1298 k->cores_mask = POWER8E_CORE_MASK; 1299 k->num_phbs = 3; 1300 k->core_pir = pnv_chip_core_pir_p8; 1301 k->intc_create = pnv_chip_power8_intc_create; 1302 k->intc_reset = pnv_chip_power8_intc_reset; 1303 k->intc_destroy = pnv_chip_power8_intc_destroy; 1304 k->intc_print_info = pnv_chip_power8_intc_print_info; 1305 k->isa_create = pnv_chip_power8_isa_create; 1306 k->dt_populate = pnv_chip_power8_dt_populate; 1307 k->pic_print_info = pnv_chip_power8_pic_print_info; 1308 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1309 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1310 dc->desc = "PowerNV Chip POWER8E"; 1311 1312 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1313 &k->parent_realize); 1314 } 1315 1316 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1317 { 1318 DeviceClass *dc = DEVICE_CLASS(klass); 1319 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1320 1321 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1322 k->cores_mask = POWER8_CORE_MASK; 1323 k->num_phbs = 3; 1324 k->core_pir = pnv_chip_core_pir_p8; 1325 k->intc_create = pnv_chip_power8_intc_create; 1326 k->intc_reset = pnv_chip_power8_intc_reset; 1327 k->intc_destroy = pnv_chip_power8_intc_destroy; 1328 k->intc_print_info = pnv_chip_power8_intc_print_info; 1329 k->isa_create = pnv_chip_power8_isa_create; 1330 k->dt_populate = pnv_chip_power8_dt_populate; 1331 k->pic_print_info = pnv_chip_power8_pic_print_info; 1332 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1333 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1334 dc->desc = "PowerNV Chip POWER8"; 1335 1336 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1337 &k->parent_realize); 1338 } 1339 1340 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1341 { 1342 DeviceClass *dc = DEVICE_CLASS(klass); 1343 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1344 1345 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1346 k->cores_mask = POWER8_CORE_MASK; 1347 k->num_phbs = 4; 1348 k->core_pir = pnv_chip_core_pir_p8; 1349 k->intc_create = pnv_chip_power8_intc_create; 1350 k->intc_reset = pnv_chip_power8_intc_reset; 1351 k->intc_destroy = pnv_chip_power8_intc_destroy; 1352 k->intc_print_info = pnv_chip_power8_intc_print_info; 1353 k->isa_create = pnv_chip_power8nvl_isa_create; 1354 k->dt_populate = pnv_chip_power8_dt_populate; 1355 k->pic_print_info = pnv_chip_power8_pic_print_info; 1356 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1357 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1358 dc->desc = "PowerNV Chip POWER8NVL"; 1359 1360 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1361 &k->parent_realize); 1362 } 1363 1364 static void pnv_chip_power9_instance_init(Object *obj) 1365 { 1366 PnvChip *chip = PNV_CHIP(obj); 1367 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1368 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1369 int i; 1370 1371 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1372 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1373 "xive-fabric"); 1374 1375 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1376 1377 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1378 1379 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1380 1381 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1382 1383 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1384 1385 /* Number of PECs is the chip default */ 1386 chip->num_pecs = pcc->num_pecs; 1387 1388 for (i = 0; i < chip->num_pecs; i++) { 1389 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1390 TYPE_PNV_PHB4_PEC); 1391 } 1392 } 1393 1394 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1395 PnvCore *pnv_core) 1396 { 1397 char eq_name[32]; 1398 int core_id = CPU_CORE(pnv_core)->core_id; 1399 1400 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1401 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1402 sizeof(*eq), TYPE_PNV_QUAD, 1403 &error_fatal, NULL); 1404 1405 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1406 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1407 } 1408 1409 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1410 { 1411 PnvChip *chip = PNV_CHIP(chip9); 1412 int i; 1413 1414 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1415 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1416 1417 for (i = 0; i < chip9->nr_quads; i++) { 1418 PnvQuad *eq = &chip9->quads[i]; 1419 1420 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1421 1422 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1423 &eq->xscom_regs); 1424 } 1425 } 1426 1427 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1428 { 1429 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1430 int i; 1431 1432 for (i = 0; i < chip->num_pecs; i++) { 1433 PnvPhb4PecState *pec = &chip9->pecs[i]; 1434 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1435 uint32_t pec_nest_base; 1436 uint32_t pec_pci_base; 1437 1438 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1439 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1440 &error_fatal); 1441 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1442 &error_fatal); 1443 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1444 return; 1445 } 1446 1447 pec_nest_base = pecc->xscom_nest_base(pec); 1448 pec_pci_base = pecc->xscom_pci_base(pec); 1449 1450 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1451 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1452 } 1453 } 1454 1455 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1456 { 1457 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1458 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1459 PnvChip *chip = PNV_CHIP(dev); 1460 Pnv9Psi *psi9 = &chip9->psi; 1461 Error *local_err = NULL; 1462 1463 /* XSCOM bridge is first */ 1464 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1465 if (local_err) { 1466 error_propagate(errp, local_err); 1467 return; 1468 } 1469 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1470 1471 pcc->parent_realize(dev, &local_err); 1472 if (local_err) { 1473 error_propagate(errp, local_err); 1474 return; 1475 } 1476 1477 pnv_chip_quad_realize(chip9, &local_err); 1478 if (local_err) { 1479 error_propagate(errp, local_err); 1480 return; 1481 } 1482 1483 /* XIVE interrupt controller (POWER9) */ 1484 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1485 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1486 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1487 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1488 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1489 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1490 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1491 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1492 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1493 &error_abort); 1494 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1495 return; 1496 } 1497 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1498 &chip9->xive.xscom_regs); 1499 1500 /* Processor Service Interface (PSI) Host Bridge */ 1501 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1502 &error_fatal); 1503 /* This is the only device with 4k ESB pages */ 1504 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1505 &error_fatal); 1506 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1507 return; 1508 } 1509 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1510 &PNV_PSI(psi9)->xscom_regs); 1511 1512 /* LPC */ 1513 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1514 return; 1515 } 1516 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1517 &chip9->lpc.xscom_regs); 1518 1519 chip->fw_mr = &chip9->lpc.isa_fw; 1520 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1521 (uint64_t) PNV9_LPCM_BASE(chip)); 1522 1523 /* Create the simplified OCC model */ 1524 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1525 return; 1526 } 1527 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1528 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1529 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1530 1531 /* OCC SRAM model */ 1532 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1533 &chip9->occ.sram_regs); 1534 1535 /* SBE */ 1536 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1537 return; 1538 } 1539 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1540 &chip9->sbe.xscom_ctrl_regs); 1541 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1542 &chip9->sbe.xscom_mbox_regs); 1543 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1544 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1545 1546 /* HOMER */ 1547 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1548 &error_abort); 1549 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1550 return; 1551 } 1552 /* Homer Xscom region */ 1553 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1554 1555 /* Homer mmio region */ 1556 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1557 &chip9->homer.regs); 1558 1559 /* PEC PHBs */ 1560 pnv_chip_power9_pec_realize(chip, &local_err); 1561 if (local_err) { 1562 error_propagate(errp, local_err); 1563 return; 1564 } 1565 } 1566 1567 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1568 { 1569 addr &= (PNV9_XSCOM_SIZE - 1); 1570 return addr >> 3; 1571 } 1572 1573 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1574 { 1575 DeviceClass *dc = DEVICE_CLASS(klass); 1576 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1577 1578 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1579 k->cores_mask = POWER9_CORE_MASK; 1580 k->core_pir = pnv_chip_core_pir_p9; 1581 k->intc_create = pnv_chip_power9_intc_create; 1582 k->intc_reset = pnv_chip_power9_intc_reset; 1583 k->intc_destroy = pnv_chip_power9_intc_destroy; 1584 k->intc_print_info = pnv_chip_power9_intc_print_info; 1585 k->isa_create = pnv_chip_power9_isa_create; 1586 k->dt_populate = pnv_chip_power9_dt_populate; 1587 k->pic_print_info = pnv_chip_power9_pic_print_info; 1588 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1589 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1590 dc->desc = "PowerNV Chip POWER9"; 1591 k->num_pecs = PNV9_CHIP_MAX_PEC; 1592 1593 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1594 &k->parent_realize); 1595 } 1596 1597 static void pnv_chip_power10_instance_init(Object *obj) 1598 { 1599 PnvChip *chip = PNV_CHIP(obj); 1600 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1601 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1602 int i; 1603 1604 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1605 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1606 "xive-fabric"); 1607 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1608 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1609 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1610 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1611 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1612 1613 chip->num_pecs = pcc->num_pecs; 1614 1615 for (i = 0; i < chip->num_pecs; i++) { 1616 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1617 TYPE_PNV_PHB5_PEC); 1618 } 1619 } 1620 1621 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1622 { 1623 PnvChip *chip = PNV_CHIP(chip10); 1624 int i; 1625 1626 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1627 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1628 1629 for (i = 0; i < chip10->nr_quads; i++) { 1630 PnvQuad *eq = &chip10->quads[i]; 1631 1632 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1633 1634 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1635 &eq->xscom_regs); 1636 } 1637 } 1638 1639 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1640 { 1641 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1642 int i; 1643 1644 for (i = 0; i < chip->num_pecs; i++) { 1645 PnvPhb4PecState *pec = &chip10->pecs[i]; 1646 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1647 uint32_t pec_nest_base; 1648 uint32_t pec_pci_base; 1649 1650 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1651 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1652 &error_fatal); 1653 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1654 &error_fatal); 1655 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1656 return; 1657 } 1658 1659 pec_nest_base = pecc->xscom_nest_base(pec); 1660 pec_pci_base = pecc->xscom_pci_base(pec); 1661 1662 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1663 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1664 } 1665 } 1666 1667 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1668 { 1669 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1670 PnvChip *chip = PNV_CHIP(dev); 1671 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1672 Error *local_err = NULL; 1673 1674 /* XSCOM bridge is first */ 1675 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1676 if (local_err) { 1677 error_propagate(errp, local_err); 1678 return; 1679 } 1680 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1681 1682 pcc->parent_realize(dev, &local_err); 1683 if (local_err) { 1684 error_propagate(errp, local_err); 1685 return; 1686 } 1687 1688 pnv_chip_power10_quad_realize(chip10, &local_err); 1689 if (local_err) { 1690 error_propagate(errp, local_err); 1691 return; 1692 } 1693 1694 /* XIVE2 interrupt controller (POWER10) */ 1695 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1696 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1697 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1698 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1699 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1700 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1701 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1702 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1703 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1704 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1705 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1706 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1707 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1708 &error_abort); 1709 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1710 return; 1711 } 1712 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1713 &chip10->xive.xscom_regs); 1714 1715 /* Processor Service Interface (PSI) Host Bridge */ 1716 object_property_set_int(OBJECT(&chip10->psi), "bar", 1717 PNV10_PSIHB_BASE(chip), &error_fatal); 1718 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1719 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1720 &error_fatal); 1721 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1722 return; 1723 } 1724 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1725 &PNV_PSI(&chip10->psi)->xscom_regs); 1726 1727 /* LPC */ 1728 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1729 return; 1730 } 1731 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1732 &chip10->lpc.xscom_regs); 1733 1734 chip->fw_mr = &chip10->lpc.isa_fw; 1735 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1736 (uint64_t) PNV10_LPCM_BASE(chip)); 1737 1738 /* Create the simplified OCC model */ 1739 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1740 return; 1741 } 1742 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1743 &chip10->occ.xscom_regs); 1744 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1745 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1746 1747 /* OCC SRAM model */ 1748 memory_region_add_subregion(get_system_memory(), 1749 PNV10_OCC_SENSOR_BASE(chip), 1750 &chip10->occ.sram_regs); 1751 1752 /* SBE */ 1753 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1754 return; 1755 } 1756 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1757 &chip10->sbe.xscom_ctrl_regs); 1758 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1759 &chip10->sbe.xscom_mbox_regs); 1760 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1761 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1762 1763 /* HOMER */ 1764 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1765 &error_abort); 1766 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1767 return; 1768 } 1769 /* Homer Xscom region */ 1770 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1771 &chip10->homer.pba_regs); 1772 1773 /* Homer mmio region */ 1774 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1775 &chip10->homer.regs); 1776 1777 /* PHBs */ 1778 pnv_chip_power10_phb_realize(chip, &local_err); 1779 if (local_err) { 1780 error_propagate(errp, local_err); 1781 return; 1782 } 1783 } 1784 1785 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1786 { 1787 addr &= (PNV10_XSCOM_SIZE - 1); 1788 return addr >> 3; 1789 } 1790 1791 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1792 { 1793 DeviceClass *dc = DEVICE_CLASS(klass); 1794 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1795 1796 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1797 k->cores_mask = POWER10_CORE_MASK; 1798 k->core_pir = pnv_chip_core_pir_p10; 1799 k->intc_create = pnv_chip_power10_intc_create; 1800 k->intc_reset = pnv_chip_power10_intc_reset; 1801 k->intc_destroy = pnv_chip_power10_intc_destroy; 1802 k->intc_print_info = pnv_chip_power10_intc_print_info; 1803 k->isa_create = pnv_chip_power10_isa_create; 1804 k->dt_populate = pnv_chip_power10_dt_populate; 1805 k->pic_print_info = pnv_chip_power10_pic_print_info; 1806 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1807 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1808 dc->desc = "PowerNV Chip POWER10"; 1809 k->num_pecs = PNV10_CHIP_MAX_PEC; 1810 1811 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1812 &k->parent_realize); 1813 } 1814 1815 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1816 { 1817 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1818 int cores_max; 1819 1820 /* 1821 * No custom mask for this chip, let's use the default one from * 1822 * the chip class 1823 */ 1824 if (!chip->cores_mask) { 1825 chip->cores_mask = pcc->cores_mask; 1826 } 1827 1828 /* filter alien core ids ! some are reserved */ 1829 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1830 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1831 chip->cores_mask); 1832 return; 1833 } 1834 chip->cores_mask &= pcc->cores_mask; 1835 1836 /* now that we have a sane layout, let check the number of cores */ 1837 cores_max = ctpop64(chip->cores_mask); 1838 if (chip->nr_cores > cores_max) { 1839 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1840 cores_max); 1841 return; 1842 } 1843 } 1844 1845 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1846 { 1847 Error *error = NULL; 1848 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1849 const char *typename = pnv_chip_core_typename(chip); 1850 int i, core_hwid; 1851 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1852 1853 if (!object_class_by_name(typename)) { 1854 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1855 return; 1856 } 1857 1858 /* Cores */ 1859 pnv_chip_core_sanitize(chip, &error); 1860 if (error) { 1861 error_propagate(errp, error); 1862 return; 1863 } 1864 1865 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1866 1867 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1868 && (i < chip->nr_cores); core_hwid++) { 1869 char core_name[32]; 1870 PnvCore *pnv_core; 1871 uint64_t xscom_core_base; 1872 1873 if (!(chip->cores_mask & (1ull << core_hwid))) { 1874 continue; 1875 } 1876 1877 pnv_core = PNV_CORE(object_new(typename)); 1878 1879 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1880 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1881 chip->cores[i] = pnv_core; 1882 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1883 chip->nr_threads, &error_fatal); 1884 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1885 core_hwid, &error_fatal); 1886 object_property_set_int(OBJECT(pnv_core), "pir", 1887 pcc->core_pir(chip, core_hwid), &error_fatal); 1888 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1889 &error_fatal); 1890 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1891 &error_abort); 1892 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1893 1894 /* Each core has an XSCOM MMIO region */ 1895 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1896 1897 pnv_xscom_add_subregion(chip, xscom_core_base, 1898 &pnv_core->xscom_regs); 1899 i++; 1900 } 1901 } 1902 1903 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1904 { 1905 PnvChip *chip = PNV_CHIP(dev); 1906 Error *error = NULL; 1907 1908 /* Cores */ 1909 pnv_chip_core_realize(chip, &error); 1910 if (error) { 1911 error_propagate(errp, error); 1912 return; 1913 } 1914 } 1915 1916 static Property pnv_chip_properties[] = { 1917 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1918 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1919 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1920 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1921 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1922 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1923 DEFINE_PROP_END_OF_LIST(), 1924 }; 1925 1926 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1927 { 1928 DeviceClass *dc = DEVICE_CLASS(klass); 1929 1930 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1931 dc->realize = pnv_chip_realize; 1932 device_class_set_props(dc, pnv_chip_properties); 1933 dc->desc = "PowerNV Chip"; 1934 } 1935 1936 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1937 { 1938 int i, j; 1939 1940 for (i = 0; i < chip->nr_cores; i++) { 1941 PnvCore *pc = chip->cores[i]; 1942 CPUCore *cc = CPU_CORE(pc); 1943 1944 for (j = 0; j < cc->nr_threads; j++) { 1945 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1946 return pc->threads[j]; 1947 } 1948 } 1949 } 1950 return NULL; 1951 } 1952 1953 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1954 { 1955 PnvMachineState *pnv = PNV_MACHINE(xi); 1956 int i, j; 1957 1958 for (i = 0; i < pnv->num_chips; i++) { 1959 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1960 1961 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1962 return &chip8->psi.ics; 1963 } 1964 1965 for (j = 0; j < chip8->num_phbs; j++) { 1966 PnvPHB *phb = &chip8->phbs[j]; 1967 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 1968 1969 if (ics_valid_irq(&phb3->lsis, irq)) { 1970 return &phb3->lsis; 1971 } 1972 1973 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 1974 return ICS(&phb3->msis); 1975 } 1976 } 1977 } 1978 return NULL; 1979 } 1980 1981 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 1982 { 1983 int i; 1984 1985 for (i = 0; i < pnv->num_chips; i++) { 1986 PnvChip *chip = pnv->chips[i]; 1987 if (chip->chip_id == chip_id) { 1988 return chip; 1989 } 1990 } 1991 return NULL; 1992 } 1993 1994 static void pnv_ics_resend(XICSFabric *xi) 1995 { 1996 PnvMachineState *pnv = PNV_MACHINE(xi); 1997 int i, j; 1998 1999 for (i = 0; i < pnv->num_chips; i++) { 2000 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2001 2002 ics_resend(&chip8->psi.ics); 2003 2004 for (j = 0; j < chip8->num_phbs; j++) { 2005 PnvPHB *phb = &chip8->phbs[j]; 2006 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2007 2008 ics_resend(&phb3->lsis); 2009 ics_resend(ICS(&phb3->msis)); 2010 } 2011 } 2012 } 2013 2014 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2015 { 2016 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2017 2018 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2019 } 2020 2021 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2022 Monitor *mon) 2023 { 2024 PnvMachineState *pnv = PNV_MACHINE(obj); 2025 int i; 2026 CPUState *cs; 2027 2028 CPU_FOREACH(cs) { 2029 PowerPCCPU *cpu = POWERPC_CPU(cs); 2030 2031 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2032 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2033 mon); 2034 } 2035 2036 for (i = 0; i < pnv->num_chips; i++) { 2037 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2038 } 2039 } 2040 2041 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2042 uint8_t nvt_blk, uint32_t nvt_idx, 2043 bool cam_ignore, uint8_t priority, 2044 uint32_t logic_serv, 2045 XiveTCTXMatch *match) 2046 { 2047 PnvMachineState *pnv = PNV_MACHINE(xfb); 2048 int total_count = 0; 2049 int i; 2050 2051 for (i = 0; i < pnv->num_chips; i++) { 2052 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2053 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2054 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2055 int count; 2056 2057 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2058 priority, logic_serv, match); 2059 2060 if (count < 0) { 2061 return count; 2062 } 2063 2064 total_count += count; 2065 } 2066 2067 return total_count; 2068 } 2069 2070 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2071 uint8_t nvt_blk, uint32_t nvt_idx, 2072 bool cam_ignore, uint8_t priority, 2073 uint32_t logic_serv, 2074 XiveTCTXMatch *match) 2075 { 2076 PnvMachineState *pnv = PNV_MACHINE(xfb); 2077 int total_count = 0; 2078 int i; 2079 2080 for (i = 0; i < pnv->num_chips; i++) { 2081 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2082 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2083 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2084 int count; 2085 2086 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2087 priority, logic_serv, match); 2088 2089 if (count < 0) { 2090 return count; 2091 } 2092 2093 total_count += count; 2094 } 2095 2096 return total_count; 2097 } 2098 2099 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2100 { 2101 MachineClass *mc = MACHINE_CLASS(oc); 2102 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2103 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2104 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2105 2106 static GlobalProperty phb_compat[] = { 2107 { TYPE_PNV_PHB, "version", "3" }, 2108 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2109 }; 2110 2111 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2112 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2113 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2114 2115 xic->icp_get = pnv_icp_get; 2116 xic->ics_get = pnv_ics_get; 2117 xic->ics_resend = pnv_ics_resend; 2118 2119 pmc->compat = compat; 2120 pmc->compat_size = sizeof(compat); 2121 } 2122 2123 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2124 { 2125 MachineClass *mc = MACHINE_CLASS(oc); 2126 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2127 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2128 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2129 2130 static GlobalProperty phb_compat[] = { 2131 { TYPE_PNV_PHB, "version", "4" }, 2132 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2133 }; 2134 2135 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2136 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2137 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2138 2139 xfc->match_nvt = pnv_match_nvt; 2140 2141 mc->alias = "powernv"; 2142 2143 pmc->compat = compat; 2144 pmc->compat_size = sizeof(compat); 2145 pmc->dt_power_mgt = pnv_dt_power_mgt; 2146 } 2147 2148 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2149 { 2150 MachineClass *mc = MACHINE_CLASS(oc); 2151 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2152 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2153 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2154 2155 static GlobalProperty phb_compat[] = { 2156 { TYPE_PNV_PHB, "version", "5" }, 2157 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2158 }; 2159 2160 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2161 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2162 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2163 2164 pmc->compat = compat; 2165 pmc->compat_size = sizeof(compat); 2166 pmc->dt_power_mgt = pnv_dt_power_mgt; 2167 2168 xfc->match_nvt = pnv10_xive_match_nvt; 2169 } 2170 2171 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2172 { 2173 PnvMachineState *pnv = PNV_MACHINE(obj); 2174 2175 return !!pnv->fw_load_addr; 2176 } 2177 2178 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2179 { 2180 PnvMachineState *pnv = PNV_MACHINE(obj); 2181 2182 if (value) { 2183 pnv->fw_load_addr = 0x8000000; 2184 } 2185 } 2186 2187 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2188 { 2189 PowerPCCPU *cpu = POWERPC_CPU(cs); 2190 CPUPPCState *env = &cpu->env; 2191 2192 cpu_synchronize_state(cs); 2193 ppc_cpu_do_system_reset(cs); 2194 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2195 /* 2196 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2197 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2198 * (PPC_BIT(43)). 2199 */ 2200 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2201 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2202 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2203 } 2204 } else { 2205 /* 2206 * For non-powersave system resets, SRR1[42:45] are defined to be 2207 * implementation-dependent. The POWER9 User Manual specifies that 2208 * an external (SCOM driven, which may come from a BMC nmi command or 2209 * another CPU requesting a NMI IPI) system reset exception should be 2210 * 0b0010 (PPC_BIT(44)). 2211 */ 2212 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2213 } 2214 } 2215 2216 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2217 { 2218 CPUState *cs; 2219 2220 CPU_FOREACH(cs) { 2221 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2222 } 2223 } 2224 2225 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2226 { 2227 MachineClass *mc = MACHINE_CLASS(oc); 2228 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2229 NMIClass *nc = NMI_CLASS(oc); 2230 2231 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2232 mc->init = pnv_init; 2233 mc->reset = pnv_reset; 2234 mc->max_cpus = MAX_CPUS; 2235 /* Pnv provides a AHCI device for storage */ 2236 mc->block_default_type = IF_IDE; 2237 mc->no_parallel = 1; 2238 mc->default_boot_order = NULL; 2239 /* 2240 * RAM defaults to less than 2048 for 32-bit hosts, and large 2241 * enough to fit the maximum initrd size at it's load address 2242 */ 2243 mc->default_ram_size = 1 * GiB; 2244 mc->default_ram_id = "pnv.ram"; 2245 ispc->print_info = pnv_pic_print_info; 2246 nc->nmi_monitor_handler = pnv_nmi; 2247 2248 object_class_property_add_bool(oc, "hb-mode", 2249 pnv_machine_get_hb, pnv_machine_set_hb); 2250 object_class_property_set_description(oc, "hb-mode", 2251 "Use a hostboot like boot loader"); 2252 } 2253 2254 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2255 { \ 2256 .name = type, \ 2257 .class_init = class_initfn, \ 2258 .parent = TYPE_PNV8_CHIP, \ 2259 } 2260 2261 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2262 { \ 2263 .name = type, \ 2264 .class_init = class_initfn, \ 2265 .parent = TYPE_PNV9_CHIP, \ 2266 } 2267 2268 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2269 { \ 2270 .name = type, \ 2271 .class_init = class_initfn, \ 2272 .parent = TYPE_PNV10_CHIP, \ 2273 } 2274 2275 static const TypeInfo types[] = { 2276 { 2277 .name = MACHINE_TYPE_NAME("powernv10"), 2278 .parent = TYPE_PNV_MACHINE, 2279 .class_init = pnv_machine_power10_class_init, 2280 .interfaces = (InterfaceInfo[]) { 2281 { TYPE_XIVE_FABRIC }, 2282 { }, 2283 }, 2284 }, 2285 { 2286 .name = MACHINE_TYPE_NAME("powernv9"), 2287 .parent = TYPE_PNV_MACHINE, 2288 .class_init = pnv_machine_power9_class_init, 2289 .interfaces = (InterfaceInfo[]) { 2290 { TYPE_XIVE_FABRIC }, 2291 { }, 2292 }, 2293 }, 2294 { 2295 .name = MACHINE_TYPE_NAME("powernv8"), 2296 .parent = TYPE_PNV_MACHINE, 2297 .class_init = pnv_machine_power8_class_init, 2298 .interfaces = (InterfaceInfo[]) { 2299 { TYPE_XICS_FABRIC }, 2300 { }, 2301 }, 2302 }, 2303 { 2304 .name = TYPE_PNV_MACHINE, 2305 .parent = TYPE_MACHINE, 2306 .abstract = true, 2307 .instance_size = sizeof(PnvMachineState), 2308 .class_init = pnv_machine_class_init, 2309 .class_size = sizeof(PnvMachineClass), 2310 .interfaces = (InterfaceInfo[]) { 2311 { TYPE_INTERRUPT_STATS_PROVIDER }, 2312 { TYPE_NMI }, 2313 { }, 2314 }, 2315 }, 2316 { 2317 .name = TYPE_PNV_CHIP, 2318 .parent = TYPE_SYS_BUS_DEVICE, 2319 .class_init = pnv_chip_class_init, 2320 .instance_size = sizeof(PnvChip), 2321 .class_size = sizeof(PnvChipClass), 2322 .abstract = true, 2323 }, 2324 2325 /* 2326 * P10 chip and variants 2327 */ 2328 { 2329 .name = TYPE_PNV10_CHIP, 2330 .parent = TYPE_PNV_CHIP, 2331 .instance_init = pnv_chip_power10_instance_init, 2332 .instance_size = sizeof(Pnv10Chip), 2333 }, 2334 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2335 2336 /* 2337 * P9 chip and variants 2338 */ 2339 { 2340 .name = TYPE_PNV9_CHIP, 2341 .parent = TYPE_PNV_CHIP, 2342 .instance_init = pnv_chip_power9_instance_init, 2343 .instance_size = sizeof(Pnv9Chip), 2344 }, 2345 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2346 2347 /* 2348 * P8 chip and variants 2349 */ 2350 { 2351 .name = TYPE_PNV8_CHIP, 2352 .parent = TYPE_PNV_CHIP, 2353 .instance_init = pnv_chip_power8_instance_init, 2354 .instance_size = sizeof(Pnv8Chip), 2355 }, 2356 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2357 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2358 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2359 pnv_chip_power8nvl_class_init), 2360 }; 2361 2362 DEFINE_TYPES(types) 2363