1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 48 #include "hw/isa/isa.h" 49 #include "hw/boards.h" 50 #include "hw/char/serial.h" 51 #include "hw/timer/mc146818rtc.h" 52 53 #include <libfdt.h> 54 55 #define FDT_MAX_SIZE (1 * MiB) 56 57 #define FW_FILE_NAME "skiboot.lid" 58 #define FW_LOAD_ADDR 0x0 59 #define FW_MAX_SIZE (4 * MiB) 60 61 #define KERNEL_LOAD_ADDR 0x20000000 62 #define KERNEL_MAX_SIZE (256 * MiB) 63 #define INITRD_LOAD_ADDR 0x60000000 64 #define INITRD_MAX_SIZE (256 * MiB) 65 66 static const char *pnv_chip_core_typename(const PnvChip *o) 67 { 68 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 69 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 70 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 71 const char *core_type = object_class_get_name(object_class_by_name(s)); 72 g_free(s); 73 return core_type; 74 } 75 76 /* 77 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 78 * 4 * 4 sockets * 12 cores * 8 threads = 1536 79 * Let's make it 2^11 80 */ 81 #define MAX_CPUS 2048 82 83 /* 84 * Memory nodes are created by hostboot, one for each range of memory 85 * that has a different "affinity". In practice, it means one range 86 * per chip. 87 */ 88 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 89 { 90 char *mem_name; 91 uint64_t mem_reg_property[2]; 92 int off; 93 94 mem_reg_property[0] = cpu_to_be64(start); 95 mem_reg_property[1] = cpu_to_be64(size); 96 97 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 98 off = fdt_add_subnode(fdt, 0, mem_name); 99 g_free(mem_name); 100 101 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 102 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 103 sizeof(mem_reg_property)))); 104 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 105 } 106 107 static int get_cpus_node(void *fdt) 108 { 109 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 110 111 if (cpus_offset < 0) { 112 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 113 if (cpus_offset) { 114 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 116 } 117 } 118 _FDT(cpus_offset); 119 return cpus_offset; 120 } 121 122 /* 123 * The PowerNV cores (and threads) need to use real HW ids and not an 124 * incremental index like it has been done on other platforms. This HW 125 * id is stored in the CPU PIR, it is used to create cpu nodes in the 126 * device tree, used in XSCOM to address cores and in interrupt 127 * servers. 128 */ 129 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 130 { 131 PowerPCCPU *cpu = pc->threads[0]; 132 CPUState *cs = CPU(cpu); 133 DeviceClass *dc = DEVICE_GET_CLASS(cs); 134 int smt_threads = CPU_CORE(pc)->nr_threads; 135 CPUPPCState *env = &cpu->env; 136 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 137 uint32_t servers_prop[smt_threads]; 138 int i; 139 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 140 0xffffffff, 0xffffffff}; 141 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 142 uint32_t cpufreq = 1000000000; 143 uint32_t page_sizes_prop[64]; 144 size_t page_sizes_prop_size; 145 const uint8_t pa_features[] = { 24, 0, 146 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 147 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 148 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 149 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 150 int offset; 151 char *nodename; 152 int cpus_offset = get_cpus_node(fdt); 153 154 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 155 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 156 _FDT(offset); 157 g_free(nodename); 158 159 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 160 161 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 162 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 163 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 166 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 167 env->dcache_line_size))); 168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 169 env->dcache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 171 env->icache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 173 env->icache_line_size))); 174 175 if (pcc->l1_dcache_size) { 176 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 177 pcc->l1_dcache_size))); 178 } else { 179 warn_report("Unknown L1 dcache size for cpu"); 180 } 181 if (pcc->l1_icache_size) { 182 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 183 pcc->l1_icache_size))); 184 } else { 185 warn_report("Unknown L1 icache size for cpu"); 186 } 187 188 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 189 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 191 cpu->hash64_opts->slb_size))); 192 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 193 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 194 195 if (env->spr_cb[SPR_PURR].oea_read) { 196 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 197 } 198 199 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 201 segs, sizeof(segs)))); 202 } 203 204 /* 205 * Advertise VMX/VSX (vector extensions) if available 206 * 0 / no property == no vector extensions 207 * 1 == VMX / Altivec available 208 * 2 == VSX available 209 */ 210 if (env->insns_flags & PPC_ALTIVEC) { 211 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 212 213 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 214 } 215 216 /* 217 * Advertise DFP (Decimal Floating Point) if available 218 * 0 / no property == no DFP 219 * 1 == DFP available 220 */ 221 if (env->insns_flags2 & PPC2_DFP) { 222 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 223 } 224 225 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 226 sizeof(page_sizes_prop)); 227 if (page_sizes_prop_size) { 228 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 229 page_sizes_prop, page_sizes_prop_size))); 230 } 231 232 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 233 pa_features, sizeof(pa_features)))); 234 235 /* Build interrupt servers properties */ 236 for (i = 0; i < smt_threads; i++) { 237 servers_prop[i] = cpu_to_be32(pc->pir + i); 238 } 239 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 240 servers_prop, sizeof(servers_prop)))); 241 } 242 243 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 244 uint32_t nr_threads) 245 { 246 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 247 char *name; 248 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 249 uint32_t irange[2], i, rsize; 250 uint64_t *reg; 251 int offset; 252 253 irange[0] = cpu_to_be32(pir); 254 irange[1] = cpu_to_be32(nr_threads); 255 256 rsize = sizeof(uint64_t) * 2 * nr_threads; 257 reg = g_malloc(rsize); 258 for (i = 0; i < nr_threads; i++) { 259 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 260 reg[i * 2 + 1] = cpu_to_be64(0x1000); 261 } 262 263 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 264 offset = fdt_add_subnode(fdt, 0, name); 265 _FDT(offset); 266 g_free(name); 267 268 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 269 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 270 _FDT((fdt_setprop_string(fdt, offset, "device_type", 271 "PowerPC-External-Interrupt-Presentation"))); 272 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 273 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 274 irange, sizeof(irange)))); 275 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 277 g_free(reg); 278 } 279 280 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 281 { 282 const char *typename = pnv_chip_core_typename(chip); 283 size_t typesize = object_type_get_instance_size(typename); 284 int i; 285 286 pnv_dt_xscom(chip, fdt, 0); 287 288 for (i = 0; i < chip->nr_cores; i++) { 289 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 290 291 pnv_dt_core(chip, pnv_core, fdt); 292 293 /* Interrupt Control Presenters (ICP). One per core. */ 294 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 295 } 296 297 if (chip->ram_size) { 298 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 299 } 300 } 301 302 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 303 { 304 const char *typename = pnv_chip_core_typename(chip); 305 size_t typesize = object_type_get_instance_size(typename); 306 int i; 307 308 pnv_dt_xscom(chip, fdt, 0); 309 310 for (i = 0; i < chip->nr_cores; i++) { 311 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 312 313 pnv_dt_core(chip, pnv_core, fdt); 314 } 315 316 if (chip->ram_size) { 317 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 318 } 319 320 pnv_dt_lpc(chip, fdt, 0); 321 } 322 323 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 324 { 325 uint32_t io_base = d->ioport_id; 326 uint32_t io_regs[] = { 327 cpu_to_be32(1), 328 cpu_to_be32(io_base), 329 cpu_to_be32(2) 330 }; 331 char *name; 332 int node; 333 334 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 335 node = fdt_add_subnode(fdt, lpc_off, name); 336 _FDT(node); 337 g_free(name); 338 339 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 340 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 341 } 342 343 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 344 { 345 const char compatible[] = "ns16550\0pnpPNP,501"; 346 uint32_t io_base = d->ioport_id; 347 uint32_t io_regs[] = { 348 cpu_to_be32(1), 349 cpu_to_be32(io_base), 350 cpu_to_be32(8) 351 }; 352 char *name; 353 int node; 354 355 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 356 node = fdt_add_subnode(fdt, lpc_off, name); 357 _FDT(node); 358 g_free(name); 359 360 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 361 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 362 sizeof(compatible)))); 363 364 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 365 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 366 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 367 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 368 fdt_get_phandle(fdt, lpc_off)))); 369 370 /* This is needed by Linux */ 371 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 372 } 373 374 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "bt\0ipmi-bt"; 377 uint32_t io_base; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 381 cpu_to_be32(3) 382 }; 383 uint32_t irq; 384 char *name; 385 int node; 386 387 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 388 io_regs[1] = cpu_to_be32(io_base); 389 390 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 391 392 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 393 node = fdt_add_subnode(fdt, lpc_off, name); 394 _FDT(node); 395 g_free(name); 396 397 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 398 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 399 sizeof(compatible)))); 400 401 /* Mark it as reserved to avoid Linux trying to claim it */ 402 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 403 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 404 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 405 fdt_get_phandle(fdt, lpc_off)))); 406 } 407 408 typedef struct ForeachPopulateArgs { 409 void *fdt; 410 int offset; 411 } ForeachPopulateArgs; 412 413 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 414 { 415 ForeachPopulateArgs *args = opaque; 416 ISADevice *d = ISA_DEVICE(dev); 417 418 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 419 pnv_dt_rtc(d, args->fdt, args->offset); 420 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 421 pnv_dt_serial(d, args->fdt, args->offset); 422 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 423 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 424 } else { 425 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 426 d->ioport_id); 427 } 428 429 return 0; 430 } 431 432 /* 433 * The default LPC bus of a multichip system is on chip 0. It's 434 * recognized by the firmware (skiboot) using a "primary" property. 435 */ 436 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 437 { 438 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 439 ForeachPopulateArgs args = { 440 .fdt = fdt, 441 .offset = isa_offset, 442 }; 443 uint32_t phandle; 444 445 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 446 447 phandle = qemu_fdt_alloc_phandle(fdt); 448 assert(phandle > 0); 449 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 450 451 /* 452 * ISA devices are not necessarily parented to the ISA bus so we 453 * can not use object_child_foreach() 454 */ 455 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 456 &args); 457 } 458 459 static void pnv_dt_power_mgt(void *fdt) 460 { 461 int off; 462 463 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 464 off = fdt_add_subnode(fdt, off, "power-mgt"); 465 466 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 467 } 468 469 static void *pnv_dt_create(MachineState *machine) 470 { 471 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 472 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; 473 PnvMachineState *pnv = PNV_MACHINE(machine); 474 void *fdt; 475 char *buf; 476 int off; 477 int i; 478 479 fdt = g_malloc0(FDT_MAX_SIZE); 480 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 481 482 /* Root node */ 483 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 484 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 485 _FDT((fdt_setprop_string(fdt, 0, "model", 486 "IBM PowerNV (emulated by qemu)"))); 487 if (pnv_is_power9(pnv)) { 488 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, 489 sizeof(plat_compat9)))); 490 } else { 491 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, 492 sizeof(plat_compat8)))); 493 } 494 495 496 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 497 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 498 if (qemu_uuid_set) { 499 _FDT((fdt_property_string(fdt, "system-id", buf))); 500 } 501 g_free(buf); 502 503 off = fdt_add_subnode(fdt, 0, "chosen"); 504 if (machine->kernel_cmdline) { 505 _FDT((fdt_setprop_string(fdt, off, "bootargs", 506 machine->kernel_cmdline))); 507 } 508 509 if (pnv->initrd_size) { 510 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 511 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 512 513 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 514 &start_prop, sizeof(start_prop)))); 515 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 516 &end_prop, sizeof(end_prop)))); 517 } 518 519 /* Populate device tree for each chip */ 520 for (i = 0; i < pnv->num_chips; i++) { 521 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 522 } 523 524 /* Populate ISA devices on chip 0 */ 525 pnv_dt_isa(pnv, fdt); 526 527 if (pnv->bmc) { 528 pnv_dt_bmc_sensors(pnv->bmc, fdt); 529 } 530 531 /* Create an extra node for power management on Power9 */ 532 if (pnv_is_power9(pnv)) { 533 pnv_dt_power_mgt(fdt); 534 } 535 536 return fdt; 537 } 538 539 static void pnv_powerdown_notify(Notifier *n, void *opaque) 540 { 541 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 542 543 if (pnv->bmc) { 544 pnv_bmc_powerdown(pnv->bmc); 545 } 546 } 547 548 static void pnv_reset(MachineState *machine) 549 { 550 PnvMachineState *pnv = PNV_MACHINE(machine); 551 void *fdt; 552 Object *obj; 553 554 qemu_devices_reset(); 555 556 /* 557 * OpenPOWER systems have a BMC, which can be defined on the 558 * command line with: 559 * 560 * -device ipmi-bmc-sim,id=bmc0 561 * 562 * This is the internal simulator but it could also be an external 563 * BMC. 564 */ 565 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 566 if (obj) { 567 pnv->bmc = IPMI_BMC(obj); 568 } 569 570 fdt = pnv_dt_create(machine); 571 572 /* Pack resulting tree */ 573 _FDT((fdt_pack(fdt))); 574 575 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 576 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 577 } 578 579 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 580 { 581 Pnv8Chip *chip8 = PNV8_CHIP(chip); 582 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 583 } 584 585 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 586 { 587 Pnv8Chip *chip8 = PNV8_CHIP(chip); 588 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 589 } 590 591 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 592 { 593 Pnv9Chip *chip9 = PNV9_CHIP(chip); 594 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 595 } 596 597 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 598 { 599 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 600 } 601 602 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 603 { 604 Pnv8Chip *chip8 = PNV8_CHIP(chip); 605 606 ics_pic_print_info(&chip8->psi.ics, mon); 607 } 608 609 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 610 { 611 Pnv9Chip *chip9 = PNV9_CHIP(chip); 612 613 pnv_xive_pic_print_info(&chip9->xive, mon); 614 pnv_psi_pic_print_info(&chip9->psi, mon); 615 } 616 617 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 618 { 619 PowerPCCPUClass *ppc_default = 620 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 621 PowerPCCPUClass *ppc = 622 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 623 624 return ppc_default->pvr_match(ppc_default, ppc->pvr); 625 } 626 627 static void pnv_init(MachineState *machine) 628 { 629 PnvMachineState *pnv = PNV_MACHINE(machine); 630 MachineClass *mc = MACHINE_GET_CLASS(machine); 631 MemoryRegion *ram; 632 char *fw_filename; 633 long fw_size; 634 int i; 635 char *chip_typename; 636 637 /* allocate RAM */ 638 if (machine->ram_size < (1 * GiB)) { 639 warn_report("skiboot may not work with < 1GB of RAM"); 640 } 641 642 ram = g_new(MemoryRegion, 1); 643 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 644 machine->ram_size); 645 memory_region_add_subregion(get_system_memory(), 0, ram); 646 647 /* load skiboot firmware */ 648 if (bios_name == NULL) { 649 bios_name = FW_FILE_NAME; 650 } 651 652 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 653 if (!fw_filename) { 654 error_report("Could not find OPAL firmware '%s'", bios_name); 655 exit(1); 656 } 657 658 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 659 if (fw_size < 0) { 660 error_report("Could not load OPAL firmware '%s'", fw_filename); 661 exit(1); 662 } 663 g_free(fw_filename); 664 665 /* load kernel */ 666 if (machine->kernel_filename) { 667 long kernel_size; 668 669 kernel_size = load_image_targphys(machine->kernel_filename, 670 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 671 if (kernel_size < 0) { 672 error_report("Could not load kernel '%s'", 673 machine->kernel_filename); 674 exit(1); 675 } 676 } 677 678 /* load initrd */ 679 if (machine->initrd_filename) { 680 pnv->initrd_base = INITRD_LOAD_ADDR; 681 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 682 pnv->initrd_base, INITRD_MAX_SIZE); 683 if (pnv->initrd_size < 0) { 684 error_report("Could not load initial ram disk '%s'", 685 machine->initrd_filename); 686 exit(1); 687 } 688 } 689 690 /* 691 * Check compatibility of the specified CPU with the machine 692 * default. 693 */ 694 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 695 error_report("invalid CPU model '%s' for %s machine", 696 machine->cpu_type, mc->name); 697 exit(1); 698 } 699 700 /* Create the processor chips */ 701 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 702 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 703 i, machine->cpu_type); 704 if (!object_class_by_name(chip_typename)) { 705 error_report("invalid chip model '%.*s' for %s machine", 706 i, machine->cpu_type, mc->name); 707 exit(1); 708 } 709 710 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 711 for (i = 0; i < pnv->num_chips; i++) { 712 char chip_name[32]; 713 Object *chip = object_new(chip_typename); 714 715 pnv->chips[i] = PNV_CHIP(chip); 716 717 /* 718 * TODO: put all the memory in one node on chip 0 until we find a 719 * way to specify different ranges for each chip 720 */ 721 if (i == 0) { 722 object_property_set_int(chip, machine->ram_size, "ram-size", 723 &error_fatal); 724 } 725 726 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 727 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 728 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 729 &error_fatal); 730 object_property_set_int(chip, machine->smp.cores, 731 "nr-cores", &error_fatal); 732 object_property_set_bool(chip, true, "realized", &error_fatal); 733 } 734 g_free(chip_typename); 735 736 /* Instantiate ISA bus on chip 0 */ 737 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 738 739 /* Create serial port */ 740 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 741 742 /* Create an RTC ISA device too */ 743 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 744 745 /* 746 * OpenPOWER systems use a IPMI SEL Event message to notify the 747 * host to powerdown 748 */ 749 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 750 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 751 } 752 753 /* 754 * 0:21 Reserved - Read as zeros 755 * 22:24 Chip ID 756 * 25:28 Core number 757 * 29:31 Thread ID 758 */ 759 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 760 { 761 return (chip->chip_id << 7) | (core_id << 3); 762 } 763 764 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 765 Error **errp) 766 { 767 Error *local_err = NULL; 768 Object *obj; 769 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 770 771 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 772 &local_err); 773 if (local_err) { 774 error_propagate(errp, local_err); 775 return; 776 } 777 778 pnv_cpu->intc = obj; 779 } 780 781 /* 782 * 0:48 Reserved - Read as zeroes 783 * 49:52 Node ID 784 * 53:55 Chip ID 785 * 56 Reserved - Read as zero 786 * 57:61 Core number 787 * 62:63 Thread ID 788 * 789 * We only care about the lower bits. uint32_t is fine for the moment. 790 */ 791 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 792 { 793 return (chip->chip_id << 8) | (core_id << 2); 794 } 795 796 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 797 Error **errp) 798 { 799 Pnv9Chip *chip9 = PNV9_CHIP(chip); 800 Error *local_err = NULL; 801 Object *obj; 802 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 803 804 /* 805 * The core creates its interrupt presenter but the XIVE interrupt 806 * controller object is initialized afterwards. Hopefully, it's 807 * only used at runtime. 808 */ 809 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 810 if (local_err) { 811 error_propagate(errp, local_err); 812 return; 813 } 814 815 pnv_cpu->intc = obj; 816 } 817 818 /* 819 * Allowed core identifiers on a POWER8 Processor Chip : 820 * 821 * <EX0 reserved> 822 * EX1 - Venice only 823 * EX2 - Venice only 824 * EX3 - Venice only 825 * EX4 826 * EX5 827 * EX6 828 * <EX7,8 reserved> <reserved> 829 * EX9 - Venice only 830 * EX10 - Venice only 831 * EX11 - Venice only 832 * EX12 833 * EX13 834 * EX14 835 * <EX15 reserved> 836 */ 837 #define POWER8E_CORE_MASK (0x7070ull) 838 #define POWER8_CORE_MASK (0x7e7eull) 839 840 /* 841 * POWER9 has 24 cores, ids starting at 0x0 842 */ 843 #define POWER9_CORE_MASK (0xffffffffffffffull) 844 845 static void pnv_chip_power8_instance_init(Object *obj) 846 { 847 Pnv8Chip *chip8 = PNV8_CHIP(obj); 848 849 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 850 TYPE_PNV8_PSI, &error_abort, NULL); 851 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 852 OBJECT(qdev_get_machine()), &error_abort); 853 854 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 855 TYPE_PNV8_LPC, &error_abort, NULL); 856 object_property_add_const_link(OBJECT(&chip8->lpc), "psi", 857 OBJECT(&chip8->psi), &error_abort); 858 859 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 860 TYPE_PNV8_OCC, &error_abort, NULL); 861 object_property_add_const_link(OBJECT(&chip8->occ), "psi", 862 OBJECT(&chip8->psi), &error_abort); 863 864 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 865 TYPE_PNV8_HOMER, &error_abort, NULL); 866 object_property_add_const_link(OBJECT(&chip8->homer), "chip", obj, 867 &error_abort); 868 } 869 870 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 871 { 872 PnvChip *chip = PNV_CHIP(chip8); 873 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 874 const char *typename = pnv_chip_core_typename(chip); 875 size_t typesize = object_type_get_instance_size(typename); 876 int i, j; 877 char *name; 878 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 879 880 name = g_strdup_printf("icp-%x", chip->chip_id); 881 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 882 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 883 g_free(name); 884 885 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 886 887 /* Map the ICP registers for each thread */ 888 for (i = 0; i < chip->nr_cores; i++) { 889 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 890 int core_hwid = CPU_CORE(pnv_core)->core_id; 891 892 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 893 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 894 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 895 896 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 897 &icp->mmio); 898 } 899 } 900 } 901 902 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 903 { 904 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 905 PnvChip *chip = PNV_CHIP(dev); 906 Pnv8Chip *chip8 = PNV8_CHIP(dev); 907 Pnv8Psi *psi8 = &chip8->psi; 908 Error *local_err = NULL; 909 910 /* XSCOM bridge is first */ 911 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 912 if (local_err) { 913 error_propagate(errp, local_err); 914 return; 915 } 916 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 917 918 pcc->parent_realize(dev, &local_err); 919 if (local_err) { 920 error_propagate(errp, local_err); 921 return; 922 } 923 924 /* Processor Service Interface (PSI) Host Bridge */ 925 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 926 "bar", &error_fatal); 927 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 928 if (local_err) { 929 error_propagate(errp, local_err); 930 return; 931 } 932 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 933 &PNV_PSI(psi8)->xscom_regs); 934 935 /* Create LPC controller */ 936 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 937 &error_fatal); 938 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 939 940 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 941 (uint64_t) PNV_XSCOM_BASE(chip), 942 PNV_XSCOM_LPC_BASE); 943 944 /* 945 * Interrupt Management Area. This is the memory region holding 946 * all the Interrupt Control Presenter (ICP) registers 947 */ 948 pnv_chip_icp_realize(chip8, &local_err); 949 if (local_err) { 950 error_propagate(errp, local_err); 951 return; 952 } 953 954 /* Create the simplified OCC model */ 955 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 956 if (local_err) { 957 error_propagate(errp, local_err); 958 return; 959 } 960 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 961 962 /* OCC SRAM model */ 963 memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip), 964 &chip8->occ.sram_regs); 965 966 /* HOMER */ 967 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 968 &local_err); 969 if (local_err) { 970 error_propagate(errp, local_err); 971 return; 972 } 973 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 974 &chip8->homer.regs); 975 } 976 977 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 978 { 979 DeviceClass *dc = DEVICE_CLASS(klass); 980 PnvChipClass *k = PNV_CHIP_CLASS(klass); 981 982 k->chip_type = PNV_CHIP_POWER8E; 983 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 984 k->cores_mask = POWER8E_CORE_MASK; 985 k->core_pir = pnv_chip_core_pir_p8; 986 k->intc_create = pnv_chip_power8_intc_create; 987 k->isa_create = pnv_chip_power8_isa_create; 988 k->dt_populate = pnv_chip_power8_dt_populate; 989 k->pic_print_info = pnv_chip_power8_pic_print_info; 990 dc->desc = "PowerNV Chip POWER8E"; 991 992 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 993 &k->parent_realize); 994 } 995 996 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 997 { 998 DeviceClass *dc = DEVICE_CLASS(klass); 999 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1000 1001 k->chip_type = PNV_CHIP_POWER8; 1002 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1003 k->cores_mask = POWER8_CORE_MASK; 1004 k->core_pir = pnv_chip_core_pir_p8; 1005 k->intc_create = pnv_chip_power8_intc_create; 1006 k->isa_create = pnv_chip_power8_isa_create; 1007 k->dt_populate = pnv_chip_power8_dt_populate; 1008 k->pic_print_info = pnv_chip_power8_pic_print_info; 1009 dc->desc = "PowerNV Chip POWER8"; 1010 1011 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1012 &k->parent_realize); 1013 } 1014 1015 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1016 { 1017 DeviceClass *dc = DEVICE_CLASS(klass); 1018 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1019 1020 k->chip_type = PNV_CHIP_POWER8NVL; 1021 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1022 k->cores_mask = POWER8_CORE_MASK; 1023 k->core_pir = pnv_chip_core_pir_p8; 1024 k->intc_create = pnv_chip_power8_intc_create; 1025 k->isa_create = pnv_chip_power8nvl_isa_create; 1026 k->dt_populate = pnv_chip_power8_dt_populate; 1027 k->pic_print_info = pnv_chip_power8_pic_print_info; 1028 dc->desc = "PowerNV Chip POWER8NVL"; 1029 1030 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1031 &k->parent_realize); 1032 } 1033 1034 static void pnv_chip_power9_instance_init(Object *obj) 1035 { 1036 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1037 1038 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1039 TYPE_PNV_XIVE, &error_abort, NULL); 1040 object_property_add_const_link(OBJECT(&chip9->xive), "chip", obj, 1041 &error_abort); 1042 1043 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1044 TYPE_PNV9_PSI, &error_abort, NULL); 1045 object_property_add_const_link(OBJECT(&chip9->psi), "chip", obj, 1046 &error_abort); 1047 1048 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1049 TYPE_PNV9_LPC, &error_abort, NULL); 1050 object_property_add_const_link(OBJECT(&chip9->lpc), "psi", 1051 OBJECT(&chip9->psi), &error_abort); 1052 1053 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1054 TYPE_PNV9_OCC, &error_abort, NULL); 1055 object_property_add_const_link(OBJECT(&chip9->occ), "psi", 1056 OBJECT(&chip9->psi), &error_abort); 1057 1058 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1059 TYPE_PNV9_HOMER, &error_abort, NULL); 1060 object_property_add_const_link(OBJECT(&chip9->homer), "chip", obj, 1061 &error_abort); 1062 } 1063 1064 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1065 { 1066 PnvChip *chip = PNV_CHIP(chip9); 1067 const char *typename = pnv_chip_core_typename(chip); 1068 size_t typesize = object_type_get_instance_size(typename); 1069 int i; 1070 1071 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1072 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1073 1074 for (i = 0; i < chip9->nr_quads; i++) { 1075 char eq_name[32]; 1076 PnvQuad *eq = &chip9->quads[i]; 1077 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); 1078 int core_id = CPU_CORE(pnv_core)->core_id; 1079 1080 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1081 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1082 TYPE_PNV_QUAD, &error_fatal, NULL); 1083 1084 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1085 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1086 1087 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1088 &eq->xscom_regs); 1089 } 1090 } 1091 1092 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1093 { 1094 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1095 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1096 PnvChip *chip = PNV_CHIP(dev); 1097 Pnv9Psi *psi9 = &chip9->psi; 1098 Error *local_err = NULL; 1099 1100 /* XSCOM bridge is first */ 1101 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1102 if (local_err) { 1103 error_propagate(errp, local_err); 1104 return; 1105 } 1106 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1107 1108 pcc->parent_realize(dev, &local_err); 1109 if (local_err) { 1110 error_propagate(errp, local_err); 1111 return; 1112 } 1113 1114 pnv_chip_quad_realize(chip9, &local_err); 1115 if (local_err) { 1116 error_propagate(errp, local_err); 1117 return; 1118 } 1119 1120 /* XIVE interrupt controller (POWER9) */ 1121 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1122 "ic-bar", &error_fatal); 1123 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1124 "vc-bar", &error_fatal); 1125 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1126 "pc-bar", &error_fatal); 1127 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1128 "tm-bar", &error_fatal); 1129 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1130 &local_err); 1131 if (local_err) { 1132 error_propagate(errp, local_err); 1133 return; 1134 } 1135 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1136 &chip9->xive.xscom_regs); 1137 1138 /* Processor Service Interface (PSI) Host Bridge */ 1139 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1140 "bar", &error_fatal); 1141 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1142 if (local_err) { 1143 error_propagate(errp, local_err); 1144 return; 1145 } 1146 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1147 &PNV_PSI(psi9)->xscom_regs); 1148 1149 /* LPC */ 1150 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1151 if (local_err) { 1152 error_propagate(errp, local_err); 1153 return; 1154 } 1155 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1156 &chip9->lpc.xscom_regs); 1157 1158 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1159 (uint64_t) PNV9_LPCM_BASE(chip)); 1160 1161 /* Create the simplified OCC model */ 1162 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1163 if (local_err) { 1164 error_propagate(errp, local_err); 1165 return; 1166 } 1167 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1168 1169 /* OCC SRAM model */ 1170 memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip), 1171 &chip9->occ.sram_regs); 1172 1173 /* HOMER */ 1174 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1175 &local_err); 1176 if (local_err) { 1177 error_propagate(errp, local_err); 1178 return; 1179 } 1180 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1181 &chip9->homer.regs); 1182 } 1183 1184 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1185 { 1186 DeviceClass *dc = DEVICE_CLASS(klass); 1187 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1188 1189 k->chip_type = PNV_CHIP_POWER9; 1190 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1191 k->cores_mask = POWER9_CORE_MASK; 1192 k->core_pir = pnv_chip_core_pir_p9; 1193 k->intc_create = pnv_chip_power9_intc_create; 1194 k->isa_create = pnv_chip_power9_isa_create; 1195 k->dt_populate = pnv_chip_power9_dt_populate; 1196 k->pic_print_info = pnv_chip_power9_pic_print_info; 1197 dc->desc = "PowerNV Chip POWER9"; 1198 1199 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1200 &k->parent_realize); 1201 } 1202 1203 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1204 { 1205 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1206 int cores_max; 1207 1208 /* 1209 * No custom mask for this chip, let's use the default one from * 1210 * the chip class 1211 */ 1212 if (!chip->cores_mask) { 1213 chip->cores_mask = pcc->cores_mask; 1214 } 1215 1216 /* filter alien core ids ! some are reserved */ 1217 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1218 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1219 chip->cores_mask); 1220 return; 1221 } 1222 chip->cores_mask &= pcc->cores_mask; 1223 1224 /* now that we have a sane layout, let check the number of cores */ 1225 cores_max = ctpop64(chip->cores_mask); 1226 if (chip->nr_cores > cores_max) { 1227 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1228 cores_max); 1229 return; 1230 } 1231 } 1232 1233 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1234 { 1235 MachineState *ms = MACHINE(qdev_get_machine()); 1236 Error *error = NULL; 1237 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1238 const char *typename = pnv_chip_core_typename(chip); 1239 size_t typesize = object_type_get_instance_size(typename); 1240 int i, core_hwid; 1241 1242 if (!object_class_by_name(typename)) { 1243 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1244 return; 1245 } 1246 1247 /* Cores */ 1248 pnv_chip_core_sanitize(chip, &error); 1249 if (error) { 1250 error_propagate(errp, error); 1251 return; 1252 } 1253 1254 chip->cores = g_malloc0(typesize * chip->nr_cores); 1255 1256 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1257 && (i < chip->nr_cores); core_hwid++) { 1258 char core_name[32]; 1259 void *pnv_core = chip->cores + i * typesize; 1260 uint64_t xscom_core_base; 1261 1262 if (!(chip->cores_mask & (1ull << core_hwid))) { 1263 continue; 1264 } 1265 1266 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1267 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, 1268 typename, &error_fatal, NULL); 1269 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1270 &error_fatal); 1271 object_property_set_int(OBJECT(pnv_core), core_hwid, 1272 CPU_CORE_PROP_CORE_ID, &error_fatal); 1273 object_property_set_int(OBJECT(pnv_core), 1274 pcc->core_pir(chip, core_hwid), 1275 "pir", &error_fatal); 1276 object_property_add_const_link(OBJECT(pnv_core), "chip", 1277 OBJECT(chip), &error_fatal); 1278 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1279 &error_fatal); 1280 1281 /* Each core has an XSCOM MMIO region */ 1282 if (!pnv_chip_is_power9(chip)) { 1283 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1284 } else { 1285 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1286 } 1287 1288 pnv_xscom_add_subregion(chip, xscom_core_base, 1289 &PNV_CORE(pnv_core)->xscom_regs); 1290 i++; 1291 } 1292 } 1293 1294 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1295 { 1296 PnvChip *chip = PNV_CHIP(dev); 1297 Error *error = NULL; 1298 1299 /* Cores */ 1300 pnv_chip_core_realize(chip, &error); 1301 if (error) { 1302 error_propagate(errp, error); 1303 return; 1304 } 1305 } 1306 1307 static Property pnv_chip_properties[] = { 1308 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1309 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1310 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1311 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1312 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1313 DEFINE_PROP_END_OF_LIST(), 1314 }; 1315 1316 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1317 { 1318 DeviceClass *dc = DEVICE_CLASS(klass); 1319 1320 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1321 dc->realize = pnv_chip_realize; 1322 dc->props = pnv_chip_properties; 1323 dc->desc = "PowerNV Chip"; 1324 } 1325 1326 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1327 { 1328 PnvMachineState *pnv = PNV_MACHINE(xi); 1329 int i; 1330 1331 for (i = 0; i < pnv->num_chips; i++) { 1332 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1333 1334 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1335 return &chip8->psi.ics; 1336 } 1337 } 1338 return NULL; 1339 } 1340 1341 static void pnv_ics_resend(XICSFabric *xi) 1342 { 1343 PnvMachineState *pnv = PNV_MACHINE(xi); 1344 int i; 1345 1346 for (i = 0; i < pnv->num_chips; i++) { 1347 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1348 ics_resend(&chip8->psi.ics); 1349 } 1350 } 1351 1352 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1353 { 1354 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1355 1356 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1357 } 1358 1359 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1360 Monitor *mon) 1361 { 1362 PnvMachineState *pnv = PNV_MACHINE(obj); 1363 int i; 1364 CPUState *cs; 1365 1366 CPU_FOREACH(cs) { 1367 PowerPCCPU *cpu = POWERPC_CPU(cs); 1368 1369 if (pnv_chip_is_power9(pnv->chips[0])) { 1370 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1371 } else { 1372 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1373 } 1374 } 1375 1376 for (i = 0; i < pnv->num_chips; i++) { 1377 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1378 } 1379 } 1380 1381 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1382 void *opaque, Error **errp) 1383 { 1384 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1385 } 1386 1387 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1388 void *opaque, Error **errp) 1389 { 1390 PnvMachineState *pnv = PNV_MACHINE(obj); 1391 uint32_t num_chips; 1392 Error *local_err = NULL; 1393 1394 visit_type_uint32(v, name, &num_chips, &local_err); 1395 if (local_err) { 1396 error_propagate(errp, local_err); 1397 return; 1398 } 1399 1400 /* 1401 * TODO: should we decide on how many chips we can create based 1402 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1403 */ 1404 if (!is_power_of_2(num_chips) || num_chips > 4) { 1405 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1406 return; 1407 } 1408 1409 pnv->num_chips = num_chips; 1410 } 1411 1412 static void pnv_machine_instance_init(Object *obj) 1413 { 1414 PnvMachineState *pnv = PNV_MACHINE(obj); 1415 pnv->num_chips = 1; 1416 } 1417 1418 static void pnv_machine_class_props_init(ObjectClass *oc) 1419 { 1420 object_class_property_add(oc, "num-chips", "uint32", 1421 pnv_get_num_chips, pnv_set_num_chips, 1422 NULL, NULL, NULL); 1423 object_class_property_set_description(oc, "num-chips", 1424 "Specifies the number of processor chips", 1425 NULL); 1426 } 1427 1428 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1429 { 1430 MachineClass *mc = MACHINE_CLASS(oc); 1431 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1432 1433 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1434 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1435 1436 xic->icp_get = pnv_icp_get; 1437 xic->ics_get = pnv_ics_get; 1438 xic->ics_resend = pnv_ics_resend; 1439 } 1440 1441 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1442 { 1443 MachineClass *mc = MACHINE_CLASS(oc); 1444 1445 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1446 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1447 1448 mc->alias = "powernv"; 1449 } 1450 1451 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1452 { 1453 MachineClass *mc = MACHINE_CLASS(oc); 1454 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1455 1456 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1457 mc->init = pnv_init; 1458 mc->reset = pnv_reset; 1459 mc->max_cpus = MAX_CPUS; 1460 /* Pnv provides a AHCI device for storage */ 1461 mc->block_default_type = IF_IDE; 1462 mc->no_parallel = 1; 1463 mc->default_boot_order = NULL; 1464 /* 1465 * RAM defaults to less than 2048 for 32-bit hosts, and large 1466 * enough to fit the maximum initrd size at it's load address 1467 */ 1468 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1469 ispc->print_info = pnv_pic_print_info; 1470 1471 pnv_machine_class_props_init(oc); 1472 } 1473 1474 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1475 { \ 1476 .name = type, \ 1477 .class_init = class_initfn, \ 1478 .parent = TYPE_PNV8_CHIP, \ 1479 } 1480 1481 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1482 { \ 1483 .name = type, \ 1484 .class_init = class_initfn, \ 1485 .parent = TYPE_PNV9_CHIP, \ 1486 } 1487 1488 static const TypeInfo types[] = { 1489 { 1490 .name = MACHINE_TYPE_NAME("powernv9"), 1491 .parent = TYPE_PNV_MACHINE, 1492 .class_init = pnv_machine_power9_class_init, 1493 }, 1494 { 1495 .name = MACHINE_TYPE_NAME("powernv8"), 1496 .parent = TYPE_PNV_MACHINE, 1497 .class_init = pnv_machine_power8_class_init, 1498 .interfaces = (InterfaceInfo[]) { 1499 { TYPE_XICS_FABRIC }, 1500 { }, 1501 }, 1502 }, 1503 { 1504 .name = TYPE_PNV_MACHINE, 1505 .parent = TYPE_MACHINE, 1506 .abstract = true, 1507 .instance_size = sizeof(PnvMachineState), 1508 .instance_init = pnv_machine_instance_init, 1509 .class_init = pnv_machine_class_init, 1510 .interfaces = (InterfaceInfo[]) { 1511 { TYPE_INTERRUPT_STATS_PROVIDER }, 1512 { }, 1513 }, 1514 }, 1515 { 1516 .name = TYPE_PNV_CHIP, 1517 .parent = TYPE_SYS_BUS_DEVICE, 1518 .class_init = pnv_chip_class_init, 1519 .instance_size = sizeof(PnvChip), 1520 .class_size = sizeof(PnvChipClass), 1521 .abstract = true, 1522 }, 1523 1524 /* 1525 * P9 chip and variants 1526 */ 1527 { 1528 .name = TYPE_PNV9_CHIP, 1529 .parent = TYPE_PNV_CHIP, 1530 .instance_init = pnv_chip_power9_instance_init, 1531 .instance_size = sizeof(Pnv9Chip), 1532 }, 1533 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1534 1535 /* 1536 * P8 chip and variants 1537 */ 1538 { 1539 .name = TYPE_PNV8_CHIP, 1540 .parent = TYPE_PNV_CHIP, 1541 .instance_init = pnv_chip_power8_instance_init, 1542 .instance_size = sizeof(Pnv8Chip), 1543 }, 1544 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1545 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1546 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1547 pnv_chip_power8nvl_class_init), 1548 }; 1549 1550 DEFINE_TYPES(types) 1551