1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 #include "hw/pci/msi.h" 44 45 #include "hw/ppc/xics.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/ppc/pnv_xscom.h" 48 #include "hw/ppc/pnv_pnor.h" 49 50 #include "hw/isa/isa.h" 51 #include "hw/boards.h" 52 #include "hw/char/serial.h" 53 #include "hw/rtc/mc146818rtc.h" 54 55 #include <libfdt.h> 56 57 #define FDT_MAX_SIZE (1 * MiB) 58 59 #define FW_FILE_NAME "skiboot.lid" 60 #define FW_LOAD_ADDR 0x0 61 #define FW_MAX_SIZE (4 * MiB) 62 63 #define KERNEL_LOAD_ADDR 0x20000000 64 #define KERNEL_MAX_SIZE (256 * MiB) 65 #define INITRD_LOAD_ADDR 0x60000000 66 #define INITRD_MAX_SIZE (256 * MiB) 67 68 static const char *pnv_chip_core_typename(const PnvChip *o) 69 { 70 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 71 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 72 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 73 const char *core_type = object_class_get_name(object_class_by_name(s)); 74 g_free(s); 75 return core_type; 76 } 77 78 /* 79 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 80 * 4 * 4 sockets * 12 cores * 8 threads = 1536 81 * Let's make it 2^11 82 */ 83 #define MAX_CPUS 2048 84 85 /* 86 * Memory nodes are created by hostboot, one for each range of memory 87 * that has a different "affinity". In practice, it means one range 88 * per chip. 89 */ 90 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 91 { 92 char *mem_name; 93 uint64_t mem_reg_property[2]; 94 int off; 95 96 mem_reg_property[0] = cpu_to_be64(start); 97 mem_reg_property[1] = cpu_to_be64(size); 98 99 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 100 off = fdt_add_subnode(fdt, 0, mem_name); 101 g_free(mem_name); 102 103 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 104 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 105 sizeof(mem_reg_property)))); 106 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 107 } 108 109 static int get_cpus_node(void *fdt) 110 { 111 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 112 113 if (cpus_offset < 0) { 114 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 115 if (cpus_offset) { 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 117 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 118 } 119 } 120 _FDT(cpus_offset); 121 return cpus_offset; 122 } 123 124 /* 125 * The PowerNV cores (and threads) need to use real HW ids and not an 126 * incremental index like it has been done on other platforms. This HW 127 * id is stored in the CPU PIR, it is used to create cpu nodes in the 128 * device tree, used in XSCOM to address cores and in interrupt 129 * servers. 130 */ 131 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 132 { 133 PowerPCCPU *cpu = pc->threads[0]; 134 CPUState *cs = CPU(cpu); 135 DeviceClass *dc = DEVICE_GET_CLASS(cs); 136 int smt_threads = CPU_CORE(pc)->nr_threads; 137 CPUPPCState *env = &cpu->env; 138 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 139 uint32_t servers_prop[smt_threads]; 140 int i; 141 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 142 0xffffffff, 0xffffffff}; 143 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 144 uint32_t cpufreq = 1000000000; 145 uint32_t page_sizes_prop[64]; 146 size_t page_sizes_prop_size; 147 const uint8_t pa_features[] = { 24, 0, 148 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 149 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 150 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 151 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 152 int offset; 153 char *nodename; 154 int cpus_offset = get_cpus_node(fdt); 155 156 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 157 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 158 _FDT(offset); 159 g_free(nodename); 160 161 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 165 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 169 env->dcache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 173 env->icache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 175 env->icache_line_size))); 176 177 if (pcc->l1_dcache_size) { 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 179 pcc->l1_dcache_size))); 180 } else { 181 warn_report("Unknown L1 dcache size for cpu"); 182 } 183 if (pcc->l1_icache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 185 pcc->l1_icache_size))); 186 } else { 187 warn_report("Unknown L1 icache size for cpu"); 188 } 189 190 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 193 cpu->hash64_opts->slb_size))); 194 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 195 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 196 197 if (env->spr_cb[SPR_PURR].oea_read) { 198 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 199 } 200 201 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 203 segs, sizeof(segs)))); 204 } 205 206 /* 207 * Advertise VMX/VSX (vector extensions) if available 208 * 0 / no property == no vector extensions 209 * 1 == VMX / Altivec available 210 * 2 == VSX available 211 */ 212 if (env->insns_flags & PPC_ALTIVEC) { 213 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 214 215 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 216 } 217 218 /* 219 * Advertise DFP (Decimal Floating Point) if available 220 * 0 / no property == no DFP 221 * 1 == DFP available 222 */ 223 if (env->insns_flags2 & PPC2_DFP) { 224 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 225 } 226 227 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 228 sizeof(page_sizes_prop)); 229 if (page_sizes_prop_size) { 230 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 231 page_sizes_prop, page_sizes_prop_size))); 232 } 233 234 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 235 pa_features, sizeof(pa_features)))); 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 servers_prop[i] = cpu_to_be32(pc->pir + i); 240 } 241 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 242 servers_prop, sizeof(servers_prop)))); 243 } 244 245 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 246 uint32_t nr_threads) 247 { 248 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 249 char *name; 250 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 251 uint32_t irange[2], i, rsize; 252 uint64_t *reg; 253 int offset; 254 255 irange[0] = cpu_to_be32(pir); 256 irange[1] = cpu_to_be32(nr_threads); 257 258 rsize = sizeof(uint64_t) * 2 * nr_threads; 259 reg = g_malloc(rsize); 260 for (i = 0; i < nr_threads; i++) { 261 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 262 reg[i * 2 + 1] = cpu_to_be64(0x1000); 263 } 264 265 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 266 offset = fdt_add_subnode(fdt, 0, name); 267 _FDT(offset); 268 g_free(name); 269 270 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 271 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 272 _FDT((fdt_setprop_string(fdt, offset, "device_type", 273 "PowerPC-External-Interrupt-Presentation"))); 274 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 275 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 276 irange, sizeof(irange)))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 278 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 279 g_free(reg); 280 } 281 282 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 283 { 284 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 285 int i; 286 287 pnv_dt_xscom(chip, fdt, 0, 288 cpu_to_be64(PNV_XSCOM_BASE(chip)), 289 cpu_to_be64(PNV_XSCOM_SIZE), 290 compat, sizeof(compat)); 291 292 for (i = 0; i < chip->nr_cores; i++) { 293 PnvCore *pnv_core = chip->cores[i]; 294 295 pnv_dt_core(chip, pnv_core, fdt); 296 297 /* Interrupt Control Presenters (ICP). One per core. */ 298 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 299 } 300 301 if (chip->ram_size) { 302 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 303 } 304 } 305 306 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 307 { 308 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 309 int i; 310 311 pnv_dt_xscom(chip, fdt, 0, 312 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 313 cpu_to_be64(PNV9_XSCOM_SIZE), 314 compat, sizeof(compat)); 315 316 for (i = 0; i < chip->nr_cores; i++) { 317 PnvCore *pnv_core = chip->cores[i]; 318 319 pnv_dt_core(chip, pnv_core, fdt); 320 } 321 322 if (chip->ram_size) { 323 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 324 } 325 326 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 327 } 328 329 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 330 { 331 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 332 int i; 333 334 pnv_dt_xscom(chip, fdt, 0, 335 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 336 cpu_to_be64(PNV10_XSCOM_SIZE), 337 compat, sizeof(compat)); 338 339 for (i = 0; i < chip->nr_cores; i++) { 340 PnvCore *pnv_core = chip->cores[i]; 341 342 pnv_dt_core(chip, pnv_core, fdt); 343 } 344 345 if (chip->ram_size) { 346 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 347 } 348 349 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 350 } 351 352 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 353 { 354 uint32_t io_base = d->ioport_id; 355 uint32_t io_regs[] = { 356 cpu_to_be32(1), 357 cpu_to_be32(io_base), 358 cpu_to_be32(2) 359 }; 360 char *name; 361 int node; 362 363 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 364 node = fdt_add_subnode(fdt, lpc_off, name); 365 _FDT(node); 366 g_free(name); 367 368 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 369 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 370 } 371 372 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 373 { 374 const char compatible[] = "ns16550\0pnpPNP,501"; 375 uint32_t io_base = d->ioport_id; 376 uint32_t io_regs[] = { 377 cpu_to_be32(1), 378 cpu_to_be32(io_base), 379 cpu_to_be32(8) 380 }; 381 char *name; 382 int node; 383 384 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 385 node = fdt_add_subnode(fdt, lpc_off, name); 386 _FDT(node); 387 g_free(name); 388 389 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 390 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 391 sizeof(compatible)))); 392 393 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 394 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 395 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 396 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 397 fdt_get_phandle(fdt, lpc_off)))); 398 399 /* This is needed by Linux */ 400 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 401 } 402 403 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 404 { 405 const char compatible[] = "bt\0ipmi-bt"; 406 uint32_t io_base; 407 uint32_t io_regs[] = { 408 cpu_to_be32(1), 409 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 410 cpu_to_be32(3) 411 }; 412 uint32_t irq; 413 char *name; 414 int node; 415 416 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 417 io_regs[1] = cpu_to_be32(io_base); 418 419 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 420 421 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 422 node = fdt_add_subnode(fdt, lpc_off, name); 423 _FDT(node); 424 g_free(name); 425 426 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 427 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 428 sizeof(compatible)))); 429 430 /* Mark it as reserved to avoid Linux trying to claim it */ 431 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 432 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 433 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 434 fdt_get_phandle(fdt, lpc_off)))); 435 } 436 437 typedef struct ForeachPopulateArgs { 438 void *fdt; 439 int offset; 440 } ForeachPopulateArgs; 441 442 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 443 { 444 ForeachPopulateArgs *args = opaque; 445 ISADevice *d = ISA_DEVICE(dev); 446 447 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 448 pnv_dt_rtc(d, args->fdt, args->offset); 449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 450 pnv_dt_serial(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 452 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 453 } else { 454 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 455 d->ioport_id); 456 } 457 458 return 0; 459 } 460 461 /* 462 * The default LPC bus of a multichip system is on chip 0. It's 463 * recognized by the firmware (skiboot) using a "primary" property. 464 */ 465 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 466 { 467 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 468 ForeachPopulateArgs args = { 469 .fdt = fdt, 470 .offset = isa_offset, 471 }; 472 uint32_t phandle; 473 474 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 475 476 phandle = qemu_fdt_alloc_phandle(fdt); 477 assert(phandle > 0); 478 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 479 480 /* 481 * ISA devices are not necessarily parented to the ISA bus so we 482 * can not use object_child_foreach() 483 */ 484 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 485 &args); 486 } 487 488 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 489 { 490 int off; 491 492 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 493 off = fdt_add_subnode(fdt, off, "power-mgt"); 494 495 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 496 } 497 498 static void *pnv_dt_create(MachineState *machine) 499 { 500 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 501 PnvMachineState *pnv = PNV_MACHINE(machine); 502 void *fdt; 503 char *buf; 504 int off; 505 int i; 506 507 fdt = g_malloc0(FDT_MAX_SIZE); 508 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 509 510 /* /qemu node */ 511 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 512 513 /* Root node */ 514 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 515 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 516 _FDT((fdt_setprop_string(fdt, 0, "model", 517 "IBM PowerNV (emulated by qemu)"))); 518 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 519 520 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 521 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 522 if (qemu_uuid_set) { 523 _FDT((fdt_property_string(fdt, "system-id", buf))); 524 } 525 g_free(buf); 526 527 off = fdt_add_subnode(fdt, 0, "chosen"); 528 if (machine->kernel_cmdline) { 529 _FDT((fdt_setprop_string(fdt, off, "bootargs", 530 machine->kernel_cmdline))); 531 } 532 533 if (pnv->initrd_size) { 534 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 535 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 536 537 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 538 &start_prop, sizeof(start_prop)))); 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 540 &end_prop, sizeof(end_prop)))); 541 } 542 543 /* Populate device tree for each chip */ 544 for (i = 0; i < pnv->num_chips; i++) { 545 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 546 } 547 548 /* Populate ISA devices on chip 0 */ 549 pnv_dt_isa(pnv, fdt); 550 551 if (pnv->bmc) { 552 pnv_dt_bmc_sensors(pnv->bmc, fdt); 553 } 554 555 /* Create an extra node for power management on machines that support it */ 556 if (pmc->dt_power_mgt) { 557 pmc->dt_power_mgt(pnv, fdt); 558 } 559 560 return fdt; 561 } 562 563 static void pnv_powerdown_notify(Notifier *n, void *opaque) 564 { 565 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 566 567 if (pnv->bmc) { 568 pnv_bmc_powerdown(pnv->bmc); 569 } 570 } 571 572 static void pnv_reset(MachineState *machine) 573 { 574 void *fdt; 575 576 qemu_devices_reset(); 577 578 fdt = pnv_dt_create(machine); 579 580 /* Pack resulting tree */ 581 _FDT((fdt_pack(fdt))); 582 583 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 584 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 585 586 g_free(fdt); 587 } 588 589 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 590 { 591 Pnv8Chip *chip8 = PNV8_CHIP(chip); 592 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 593 } 594 595 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 596 { 597 Pnv8Chip *chip8 = PNV8_CHIP(chip); 598 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 599 } 600 601 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 602 { 603 Pnv9Chip *chip9 = PNV9_CHIP(chip); 604 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 605 } 606 607 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 608 { 609 Pnv10Chip *chip10 = PNV10_CHIP(chip); 610 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 611 } 612 613 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 614 { 615 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 616 } 617 618 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 619 { 620 Pnv8Chip *chip8 = PNV8_CHIP(chip); 621 int i; 622 623 ics_pic_print_info(&chip8->psi.ics, mon); 624 for (i = 0; i < chip->num_phbs; i++) { 625 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 626 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 627 } 628 } 629 630 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 631 { 632 Pnv9Chip *chip9 = PNV9_CHIP(chip); 633 int i, j; 634 635 pnv_xive_pic_print_info(&chip9->xive, mon); 636 pnv_psi_pic_print_info(&chip9->psi, mon); 637 638 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 639 PnvPhb4PecState *pec = &chip9->pecs[i]; 640 for (j = 0; j < pec->num_stacks; j++) { 641 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 642 } 643 } 644 } 645 646 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 647 uint32_t core_id) 648 { 649 return PNV_XSCOM_EX_BASE(core_id); 650 } 651 652 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 653 uint32_t core_id) 654 { 655 return PNV9_XSCOM_EC_BASE(core_id); 656 } 657 658 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 659 uint32_t core_id) 660 { 661 return PNV10_XSCOM_EC_BASE(core_id); 662 } 663 664 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 665 { 666 PowerPCCPUClass *ppc_default = 667 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 668 PowerPCCPUClass *ppc = 669 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 670 671 return ppc_default->pvr_match(ppc_default, ppc->pvr); 672 } 673 674 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 675 { 676 Object *obj; 677 678 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 679 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 680 object_property_set_int(obj, irq, "irq", &error_fatal); 681 object_property_set_bool(obj, true, "realized", &error_fatal); 682 } 683 684 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 685 { 686 Pnv10Chip *chip10 = PNV10_CHIP(chip); 687 688 pnv_psi_pic_print_info(&chip10->psi, mon); 689 } 690 691 static void pnv_init(MachineState *machine) 692 { 693 PnvMachineState *pnv = PNV_MACHINE(machine); 694 MachineClass *mc = MACHINE_GET_CLASS(machine); 695 char *fw_filename; 696 long fw_size; 697 int i; 698 char *chip_typename; 699 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 700 DeviceState *dev; 701 702 /* allocate RAM */ 703 if (machine->ram_size < (1 * GiB)) { 704 warn_report("skiboot may not work with < 1GB of RAM"); 705 } 706 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 707 708 /* 709 * Create our simple PNOR device 710 */ 711 dev = qdev_create(NULL, TYPE_PNV_PNOR); 712 if (pnor) { 713 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 714 &error_abort); 715 } 716 qdev_init_nofail(dev); 717 pnv->pnor = PNV_PNOR(dev); 718 719 /* load skiboot firmware */ 720 if (bios_name == NULL) { 721 bios_name = FW_FILE_NAME; 722 } 723 724 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 725 if (!fw_filename) { 726 error_report("Could not find OPAL firmware '%s'", bios_name); 727 exit(1); 728 } 729 730 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 731 if (fw_size < 0) { 732 error_report("Could not load OPAL firmware '%s'", fw_filename); 733 exit(1); 734 } 735 g_free(fw_filename); 736 737 /* load kernel */ 738 if (machine->kernel_filename) { 739 long kernel_size; 740 741 kernel_size = load_image_targphys(machine->kernel_filename, 742 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 743 if (kernel_size < 0) { 744 error_report("Could not load kernel '%s'", 745 machine->kernel_filename); 746 exit(1); 747 } 748 } 749 750 /* load initrd */ 751 if (machine->initrd_filename) { 752 pnv->initrd_base = INITRD_LOAD_ADDR; 753 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 754 pnv->initrd_base, INITRD_MAX_SIZE); 755 if (pnv->initrd_size < 0) { 756 error_report("Could not load initial ram disk '%s'", 757 machine->initrd_filename); 758 exit(1); 759 } 760 } 761 762 /* MSIs are supported on this platform */ 763 msi_nonbroken = true; 764 765 /* 766 * Check compatibility of the specified CPU with the machine 767 * default. 768 */ 769 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 770 error_report("invalid CPU model '%s' for %s machine", 771 machine->cpu_type, mc->name); 772 exit(1); 773 } 774 775 /* Create the processor chips */ 776 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 777 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 778 i, machine->cpu_type); 779 if (!object_class_by_name(chip_typename)) { 780 error_report("invalid chip model '%.*s' for %s machine", 781 i, machine->cpu_type, mc->name); 782 exit(1); 783 } 784 785 pnv->num_chips = 786 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 787 /* 788 * TODO: should we decide on how many chips we can create based 789 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 790 */ 791 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 792 error_report("invalid number of chips: '%d'", pnv->num_chips); 793 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 794 exit(1); 795 } 796 797 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 798 for (i = 0; i < pnv->num_chips; i++) { 799 char chip_name[32]; 800 Object *chip = object_new(chip_typename); 801 802 pnv->chips[i] = PNV_CHIP(chip); 803 804 /* 805 * TODO: put all the memory in one node on chip 0 until we find a 806 * way to specify different ranges for each chip 807 */ 808 if (i == 0) { 809 object_property_set_int(chip, machine->ram_size, "ram-size", 810 &error_fatal); 811 } 812 813 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 814 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 815 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 816 &error_fatal); 817 object_property_set_int(chip, machine->smp.cores, 818 "nr-cores", &error_fatal); 819 object_property_set_int(chip, machine->smp.threads, 820 "nr-threads", &error_fatal); 821 /* 822 * The POWER8 machine use the XICS interrupt interface. 823 * Propagate the XICS fabric to the chip and its controllers. 824 */ 825 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 826 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 827 } 828 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 829 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 830 &error_abort); 831 } 832 object_property_set_bool(chip, true, "realized", &error_fatal); 833 } 834 g_free(chip_typename); 835 836 /* Create the machine BMC simulator */ 837 pnv->bmc = pnv_bmc_create(pnv->pnor); 838 839 /* Instantiate ISA bus on chip 0 */ 840 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 841 842 /* Create serial port */ 843 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 844 845 /* Create an RTC ISA device too */ 846 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 847 848 /* Create the IPMI BT device for communication with the BMC */ 849 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 850 851 /* 852 * OpenPOWER systems use a IPMI SEL Event message to notify the 853 * host to powerdown 854 */ 855 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 856 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 857 } 858 859 /* 860 * 0:21 Reserved - Read as zeros 861 * 22:24 Chip ID 862 * 25:28 Core number 863 * 29:31 Thread ID 864 */ 865 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 866 { 867 return (chip->chip_id << 7) | (core_id << 3); 868 } 869 870 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 871 Error **errp) 872 { 873 Pnv8Chip *chip8 = PNV8_CHIP(chip); 874 Error *local_err = NULL; 875 Object *obj; 876 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 877 878 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 879 if (local_err) { 880 error_propagate(errp, local_err); 881 return; 882 } 883 884 pnv_cpu->intc = obj; 885 } 886 887 888 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 889 { 890 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 891 892 icp_reset(ICP(pnv_cpu->intc)); 893 } 894 895 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 896 { 897 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 898 899 icp_destroy(ICP(pnv_cpu->intc)); 900 pnv_cpu->intc = NULL; 901 } 902 903 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 904 Monitor *mon) 905 { 906 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 907 } 908 909 /* 910 * 0:48 Reserved - Read as zeroes 911 * 49:52 Node ID 912 * 53:55 Chip ID 913 * 56 Reserved - Read as zero 914 * 57:61 Core number 915 * 62:63 Thread ID 916 * 917 * We only care about the lower bits. uint32_t is fine for the moment. 918 */ 919 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 920 { 921 return (chip->chip_id << 8) | (core_id << 2); 922 } 923 924 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 925 { 926 return (chip->chip_id << 8) | (core_id << 2); 927 } 928 929 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 930 Error **errp) 931 { 932 Pnv9Chip *chip9 = PNV9_CHIP(chip); 933 Error *local_err = NULL; 934 Object *obj; 935 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 936 937 /* 938 * The core creates its interrupt presenter but the XIVE interrupt 939 * controller object is initialized afterwards. Hopefully, it's 940 * only used at runtime. 941 */ 942 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 943 &local_err); 944 if (local_err) { 945 error_propagate(errp, local_err); 946 return; 947 } 948 949 pnv_cpu->intc = obj; 950 } 951 952 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 953 { 954 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 955 956 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 957 } 958 959 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 960 { 961 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 962 963 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 964 pnv_cpu->intc = NULL; 965 } 966 967 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 968 Monitor *mon) 969 { 970 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 971 } 972 973 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 974 Error **errp) 975 { 976 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 977 978 /* Will be defined when the interrupt controller is */ 979 pnv_cpu->intc = NULL; 980 } 981 982 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 983 { 984 ; 985 } 986 987 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 988 { 989 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 990 991 pnv_cpu->intc = NULL; 992 } 993 994 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 995 Monitor *mon) 996 { 997 } 998 999 /* 1000 * Allowed core identifiers on a POWER8 Processor Chip : 1001 * 1002 * <EX0 reserved> 1003 * EX1 - Venice only 1004 * EX2 - Venice only 1005 * EX3 - Venice only 1006 * EX4 1007 * EX5 1008 * EX6 1009 * <EX7,8 reserved> <reserved> 1010 * EX9 - Venice only 1011 * EX10 - Venice only 1012 * EX11 - Venice only 1013 * EX12 1014 * EX13 1015 * EX14 1016 * <EX15 reserved> 1017 */ 1018 #define POWER8E_CORE_MASK (0x7070ull) 1019 #define POWER8_CORE_MASK (0x7e7eull) 1020 1021 /* 1022 * POWER9 has 24 cores, ids starting at 0x0 1023 */ 1024 #define POWER9_CORE_MASK (0xffffffffffffffull) 1025 1026 1027 #define POWER10_CORE_MASK (0xffffffffffffffull) 1028 1029 static void pnv_chip_power8_instance_init(Object *obj) 1030 { 1031 PnvChip *chip = PNV_CHIP(obj); 1032 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1033 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1034 int i; 1035 1036 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1037 (Object **)&chip8->xics, 1038 object_property_allow_set_link, 1039 OBJ_PROP_LINK_STRONG, 1040 &error_abort); 1041 1042 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 1043 TYPE_PNV8_PSI, &error_abort, NULL); 1044 1045 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 1046 TYPE_PNV8_LPC, &error_abort, NULL); 1047 1048 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 1049 TYPE_PNV8_OCC, &error_abort, NULL); 1050 1051 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 1052 TYPE_PNV8_HOMER, &error_abort, NULL); 1053 1054 for (i = 0; i < pcc->num_phbs; i++) { 1055 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], 1056 sizeof(chip8->phbs[i]), TYPE_PNV_PHB3, 1057 &error_abort, NULL); 1058 } 1059 1060 /* 1061 * Number of PHBs is the chip default 1062 */ 1063 chip->num_phbs = pcc->num_phbs; 1064 } 1065 1066 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1067 { 1068 PnvChip *chip = PNV_CHIP(chip8); 1069 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1070 int i, j; 1071 char *name; 1072 1073 name = g_strdup_printf("icp-%x", chip->chip_id); 1074 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1075 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1076 g_free(name); 1077 1078 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1079 1080 /* Map the ICP registers for each thread */ 1081 for (i = 0; i < chip->nr_cores; i++) { 1082 PnvCore *pnv_core = chip->cores[i]; 1083 int core_hwid = CPU_CORE(pnv_core)->core_id; 1084 1085 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1086 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1087 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1088 1089 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1090 &icp->mmio); 1091 } 1092 } 1093 } 1094 1095 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1096 { 1097 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1098 PnvChip *chip = PNV_CHIP(dev); 1099 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1100 Pnv8Psi *psi8 = &chip8->psi; 1101 Error *local_err = NULL; 1102 int i; 1103 1104 assert(chip8->xics); 1105 1106 /* XSCOM bridge is first */ 1107 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1108 if (local_err) { 1109 error_propagate(errp, local_err); 1110 return; 1111 } 1112 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1113 1114 pcc->parent_realize(dev, &local_err); 1115 if (local_err) { 1116 error_propagate(errp, local_err); 1117 return; 1118 } 1119 1120 /* Processor Service Interface (PSI) Host Bridge */ 1121 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1122 "bar", &error_fatal); 1123 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1124 ICS_PROP_XICS, &error_abort); 1125 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1126 if (local_err) { 1127 error_propagate(errp, local_err); 1128 return; 1129 } 1130 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1131 &PNV_PSI(psi8)->xscom_regs); 1132 1133 /* Create LPC controller */ 1134 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1135 &error_abort); 1136 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1137 &error_fatal); 1138 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1139 1140 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1141 (uint64_t) PNV_XSCOM_BASE(chip), 1142 PNV_XSCOM_LPC_BASE); 1143 1144 /* 1145 * Interrupt Management Area. This is the memory region holding 1146 * all the Interrupt Control Presenter (ICP) registers 1147 */ 1148 pnv_chip_icp_realize(chip8, &local_err); 1149 if (local_err) { 1150 error_propagate(errp, local_err); 1151 return; 1152 } 1153 1154 /* Create the simplified OCC model */ 1155 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1156 &error_abort); 1157 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1158 if (local_err) { 1159 error_propagate(errp, local_err); 1160 return; 1161 } 1162 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1163 1164 /* OCC SRAM model */ 1165 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1166 &chip8->occ.sram_regs); 1167 1168 /* HOMER */ 1169 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1170 &error_abort); 1171 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1172 &local_err); 1173 if (local_err) { 1174 error_propagate(errp, local_err); 1175 return; 1176 } 1177 /* Homer Xscom region */ 1178 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1179 1180 /* Homer mmio region */ 1181 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1182 &chip8->homer.regs); 1183 1184 /* PHB3 controllers */ 1185 for (i = 0; i < chip->num_phbs; i++) { 1186 PnvPHB3 *phb = &chip8->phbs[i]; 1187 PnvPBCQState *pbcq = &phb->pbcq; 1188 1189 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1190 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1191 &error_fatal); 1192 object_property_set_bool(OBJECT(phb), true, "realized", &local_err); 1193 if (local_err) { 1194 error_propagate(errp, local_err); 1195 return; 1196 } 1197 qdev_set_parent_bus(DEVICE(phb), sysbus_get_default()); 1198 1199 /* Populate the XSCOM address space. */ 1200 pnv_xscom_add_subregion(chip, 1201 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1202 &pbcq->xscom_nest_regs); 1203 pnv_xscom_add_subregion(chip, 1204 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1205 &pbcq->xscom_pci_regs); 1206 pnv_xscom_add_subregion(chip, 1207 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1208 &pbcq->xscom_spci_regs); 1209 } 1210 } 1211 1212 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1213 { 1214 addr &= (PNV_XSCOM_SIZE - 1); 1215 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1216 } 1217 1218 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1219 { 1220 DeviceClass *dc = DEVICE_CLASS(klass); 1221 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1222 1223 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1224 k->cores_mask = POWER8E_CORE_MASK; 1225 k->num_phbs = 3; 1226 k->core_pir = pnv_chip_core_pir_p8; 1227 k->intc_create = pnv_chip_power8_intc_create; 1228 k->intc_reset = pnv_chip_power8_intc_reset; 1229 k->intc_destroy = pnv_chip_power8_intc_destroy; 1230 k->intc_print_info = pnv_chip_power8_intc_print_info; 1231 k->isa_create = pnv_chip_power8_isa_create; 1232 k->dt_populate = pnv_chip_power8_dt_populate; 1233 k->pic_print_info = pnv_chip_power8_pic_print_info; 1234 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1235 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1236 dc->desc = "PowerNV Chip POWER8E"; 1237 1238 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1239 &k->parent_realize); 1240 } 1241 1242 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1243 { 1244 DeviceClass *dc = DEVICE_CLASS(klass); 1245 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1246 1247 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1248 k->cores_mask = POWER8_CORE_MASK; 1249 k->num_phbs = 3; 1250 k->core_pir = pnv_chip_core_pir_p8; 1251 k->intc_create = pnv_chip_power8_intc_create; 1252 k->intc_reset = pnv_chip_power8_intc_reset; 1253 k->intc_destroy = pnv_chip_power8_intc_destroy; 1254 k->intc_print_info = pnv_chip_power8_intc_print_info; 1255 k->isa_create = pnv_chip_power8_isa_create; 1256 k->dt_populate = pnv_chip_power8_dt_populate; 1257 k->pic_print_info = pnv_chip_power8_pic_print_info; 1258 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1259 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1260 dc->desc = "PowerNV Chip POWER8"; 1261 1262 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1263 &k->parent_realize); 1264 } 1265 1266 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1267 { 1268 DeviceClass *dc = DEVICE_CLASS(klass); 1269 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1270 1271 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1272 k->cores_mask = POWER8_CORE_MASK; 1273 k->num_phbs = 3; 1274 k->core_pir = pnv_chip_core_pir_p8; 1275 k->intc_create = pnv_chip_power8_intc_create; 1276 k->intc_reset = pnv_chip_power8_intc_reset; 1277 k->intc_destroy = pnv_chip_power8_intc_destroy; 1278 k->intc_print_info = pnv_chip_power8_intc_print_info; 1279 k->isa_create = pnv_chip_power8nvl_isa_create; 1280 k->dt_populate = pnv_chip_power8_dt_populate; 1281 k->pic_print_info = pnv_chip_power8_pic_print_info; 1282 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1283 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1284 dc->desc = "PowerNV Chip POWER8NVL"; 1285 1286 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1287 &k->parent_realize); 1288 } 1289 1290 static void pnv_chip_power9_instance_init(Object *obj) 1291 { 1292 PnvChip *chip = PNV_CHIP(obj); 1293 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1294 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1295 int i; 1296 1297 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1298 TYPE_PNV_XIVE, &error_abort, NULL); 1299 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1300 "xive-fabric", &error_abort); 1301 1302 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1303 TYPE_PNV9_PSI, &error_abort, NULL); 1304 1305 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1306 TYPE_PNV9_LPC, &error_abort, NULL); 1307 1308 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1309 TYPE_PNV9_OCC, &error_abort, NULL); 1310 1311 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1312 TYPE_PNV9_HOMER, &error_abort, NULL); 1313 1314 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1315 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1316 sizeof(chip9->pecs[i]), TYPE_PNV_PHB4_PEC, 1317 &error_abort, NULL); 1318 } 1319 1320 /* 1321 * Number of PHBs is the chip default 1322 */ 1323 chip->num_phbs = pcc->num_phbs; 1324 } 1325 1326 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1327 { 1328 PnvChip *chip = PNV_CHIP(chip9); 1329 int i; 1330 1331 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1332 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1333 1334 for (i = 0; i < chip9->nr_quads; i++) { 1335 char eq_name[32]; 1336 PnvQuad *eq = &chip9->quads[i]; 1337 PnvCore *pnv_core = chip->cores[i * 4]; 1338 int core_id = CPU_CORE(pnv_core)->core_id; 1339 1340 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1341 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1342 TYPE_PNV_QUAD, &error_fatal, NULL); 1343 1344 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1345 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1346 1347 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1348 &eq->xscom_regs); 1349 } 1350 } 1351 1352 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1353 { 1354 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1355 Error *local_err = NULL; 1356 int i, j; 1357 int phb_id = 0; 1358 1359 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1360 PnvPhb4PecState *pec = &chip9->pecs[i]; 1361 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1362 uint32_t pec_nest_base; 1363 uint32_t pec_pci_base; 1364 1365 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1366 /* 1367 * PEC0 -> 1 stack 1368 * PEC1 -> 2 stacks 1369 * PEC2 -> 3 stacks 1370 */ 1371 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1372 &error_fatal); 1373 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1374 &error_fatal); 1375 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1376 "system-memory", &error_abort); 1377 object_property_set_bool(OBJECT(pec), true, "realized", &local_err); 1378 if (local_err) { 1379 error_propagate(errp, local_err); 1380 return; 1381 } 1382 1383 pec_nest_base = pecc->xscom_nest_base(pec); 1384 pec_pci_base = pecc->xscom_pci_base(pec); 1385 1386 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1387 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1388 1389 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1390 j++, phb_id++) { 1391 PnvPhb4PecStack *stack = &pec->stacks[j]; 1392 Object *obj = OBJECT(&stack->phb); 1393 1394 object_property_set_int(obj, phb_id, "index", &error_fatal); 1395 object_property_set_int(obj, chip->chip_id, "chip-id", 1396 &error_fatal); 1397 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1398 &error_fatal); 1399 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1400 &error_fatal); 1401 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1402 object_property_set_bool(obj, true, "realized", &local_err); 1403 if (local_err) { 1404 error_propagate(errp, local_err); 1405 return; 1406 } 1407 qdev_set_parent_bus(DEVICE(obj), sysbus_get_default()); 1408 1409 /* Populate the XSCOM address space. */ 1410 pnv_xscom_add_subregion(chip, 1411 pec_nest_base + 0x40 * (stack->stack_no + 1), 1412 &stack->nest_regs_mr); 1413 pnv_xscom_add_subregion(chip, 1414 pec_pci_base + 0x40 * (stack->stack_no + 1), 1415 &stack->pci_regs_mr); 1416 pnv_xscom_add_subregion(chip, 1417 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1418 0x40 * stack->stack_no, 1419 &stack->phb_regs_mr); 1420 } 1421 } 1422 } 1423 1424 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1425 { 1426 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1427 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1428 PnvChip *chip = PNV_CHIP(dev); 1429 Pnv9Psi *psi9 = &chip9->psi; 1430 Error *local_err = NULL; 1431 1432 /* XSCOM bridge is first */ 1433 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1434 if (local_err) { 1435 error_propagate(errp, local_err); 1436 return; 1437 } 1438 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1439 1440 pcc->parent_realize(dev, &local_err); 1441 if (local_err) { 1442 error_propagate(errp, local_err); 1443 return; 1444 } 1445 1446 pnv_chip_quad_realize(chip9, &local_err); 1447 if (local_err) { 1448 error_propagate(errp, local_err); 1449 return; 1450 } 1451 1452 /* XIVE interrupt controller (POWER9) */ 1453 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1454 "ic-bar", &error_fatal); 1455 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1456 "vc-bar", &error_fatal); 1457 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1458 "pc-bar", &error_fatal); 1459 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1460 "tm-bar", &error_fatal); 1461 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1462 &error_abort); 1463 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1464 &local_err); 1465 if (local_err) { 1466 error_propagate(errp, local_err); 1467 return; 1468 } 1469 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1470 &chip9->xive.xscom_regs); 1471 1472 /* Processor Service Interface (PSI) Host Bridge */ 1473 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1474 "bar", &error_fatal); 1475 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1476 if (local_err) { 1477 error_propagate(errp, local_err); 1478 return; 1479 } 1480 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1481 &PNV_PSI(psi9)->xscom_regs); 1482 1483 /* LPC */ 1484 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1485 &error_abort); 1486 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1487 if (local_err) { 1488 error_propagate(errp, local_err); 1489 return; 1490 } 1491 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1492 &chip9->lpc.xscom_regs); 1493 1494 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1495 (uint64_t) PNV9_LPCM_BASE(chip)); 1496 1497 /* Create the simplified OCC model */ 1498 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1499 &error_abort); 1500 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1501 if (local_err) { 1502 error_propagate(errp, local_err); 1503 return; 1504 } 1505 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1506 1507 /* OCC SRAM model */ 1508 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1509 &chip9->occ.sram_regs); 1510 1511 /* HOMER */ 1512 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1513 &error_abort); 1514 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1515 &local_err); 1516 if (local_err) { 1517 error_propagate(errp, local_err); 1518 return; 1519 } 1520 /* Homer Xscom region */ 1521 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1522 1523 /* Homer mmio region */ 1524 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1525 &chip9->homer.regs); 1526 1527 /* PHBs */ 1528 pnv_chip_power9_phb_realize(chip, &local_err); 1529 if (local_err) { 1530 error_propagate(errp, local_err); 1531 return; 1532 } 1533 } 1534 1535 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1536 { 1537 addr &= (PNV9_XSCOM_SIZE - 1); 1538 return addr >> 3; 1539 } 1540 1541 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1542 { 1543 DeviceClass *dc = DEVICE_CLASS(klass); 1544 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1545 1546 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1547 k->cores_mask = POWER9_CORE_MASK; 1548 k->core_pir = pnv_chip_core_pir_p9; 1549 k->intc_create = pnv_chip_power9_intc_create; 1550 k->intc_reset = pnv_chip_power9_intc_reset; 1551 k->intc_destroy = pnv_chip_power9_intc_destroy; 1552 k->intc_print_info = pnv_chip_power9_intc_print_info; 1553 k->isa_create = pnv_chip_power9_isa_create; 1554 k->dt_populate = pnv_chip_power9_dt_populate; 1555 k->pic_print_info = pnv_chip_power9_pic_print_info; 1556 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1557 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1558 dc->desc = "PowerNV Chip POWER9"; 1559 k->num_phbs = 6; 1560 1561 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1562 &k->parent_realize); 1563 } 1564 1565 static void pnv_chip_power10_instance_init(Object *obj) 1566 { 1567 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1568 1569 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1570 TYPE_PNV10_PSI, &error_abort, NULL); 1571 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1572 TYPE_PNV10_LPC, &error_abort, NULL); 1573 } 1574 1575 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1576 { 1577 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1578 PnvChip *chip = PNV_CHIP(dev); 1579 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1580 Error *local_err = NULL; 1581 1582 /* XSCOM bridge is first */ 1583 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1584 if (local_err) { 1585 error_propagate(errp, local_err); 1586 return; 1587 } 1588 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1589 1590 pcc->parent_realize(dev, &local_err); 1591 if (local_err) { 1592 error_propagate(errp, local_err); 1593 return; 1594 } 1595 1596 /* Processor Service Interface (PSI) Host Bridge */ 1597 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1598 "bar", &error_fatal); 1599 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1600 &local_err); 1601 if (local_err) { 1602 error_propagate(errp, local_err); 1603 return; 1604 } 1605 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1606 &PNV_PSI(&chip10->psi)->xscom_regs); 1607 1608 /* LPC */ 1609 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1610 &error_abort); 1611 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1612 &local_err); 1613 if (local_err) { 1614 error_propagate(errp, local_err); 1615 return; 1616 } 1617 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1618 &chip10->lpc.xscom_regs); 1619 1620 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1621 (uint64_t) PNV10_LPCM_BASE(chip)); 1622 } 1623 1624 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1625 { 1626 addr &= (PNV10_XSCOM_SIZE - 1); 1627 return addr >> 3; 1628 } 1629 1630 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1631 { 1632 DeviceClass *dc = DEVICE_CLASS(klass); 1633 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1634 1635 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1636 k->cores_mask = POWER10_CORE_MASK; 1637 k->core_pir = pnv_chip_core_pir_p10; 1638 k->intc_create = pnv_chip_power10_intc_create; 1639 k->intc_reset = pnv_chip_power10_intc_reset; 1640 k->intc_destroy = pnv_chip_power10_intc_destroy; 1641 k->intc_print_info = pnv_chip_power10_intc_print_info; 1642 k->isa_create = pnv_chip_power10_isa_create; 1643 k->dt_populate = pnv_chip_power10_dt_populate; 1644 k->pic_print_info = pnv_chip_power10_pic_print_info; 1645 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1646 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1647 dc->desc = "PowerNV Chip POWER10"; 1648 1649 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1650 &k->parent_realize); 1651 } 1652 1653 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1654 { 1655 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1656 int cores_max; 1657 1658 /* 1659 * No custom mask for this chip, let's use the default one from * 1660 * the chip class 1661 */ 1662 if (!chip->cores_mask) { 1663 chip->cores_mask = pcc->cores_mask; 1664 } 1665 1666 /* filter alien core ids ! some are reserved */ 1667 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1668 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1669 chip->cores_mask); 1670 return; 1671 } 1672 chip->cores_mask &= pcc->cores_mask; 1673 1674 /* now that we have a sane layout, let check the number of cores */ 1675 cores_max = ctpop64(chip->cores_mask); 1676 if (chip->nr_cores > cores_max) { 1677 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1678 cores_max); 1679 return; 1680 } 1681 } 1682 1683 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1684 { 1685 Error *error = NULL; 1686 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1687 const char *typename = pnv_chip_core_typename(chip); 1688 int i, core_hwid; 1689 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1690 1691 if (!object_class_by_name(typename)) { 1692 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1693 return; 1694 } 1695 1696 /* Cores */ 1697 pnv_chip_core_sanitize(chip, &error); 1698 if (error) { 1699 error_propagate(errp, error); 1700 return; 1701 } 1702 1703 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1704 1705 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1706 && (i < chip->nr_cores); core_hwid++) { 1707 char core_name[32]; 1708 PnvCore *pnv_core; 1709 uint64_t xscom_core_base; 1710 1711 if (!(chip->cores_mask & (1ull << core_hwid))) { 1712 continue; 1713 } 1714 1715 pnv_core = PNV_CORE(object_new(typename)); 1716 1717 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1718 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1719 &error_abort); 1720 chip->cores[i] = pnv_core; 1721 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1722 "nr-threads", &error_fatal); 1723 object_property_set_int(OBJECT(pnv_core), core_hwid, 1724 CPU_CORE_PROP_CORE_ID, &error_fatal); 1725 object_property_set_int(OBJECT(pnv_core), 1726 pcc->core_pir(chip, core_hwid), 1727 "pir", &error_fatal); 1728 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1729 "hrmor", &error_fatal); 1730 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1731 &error_abort); 1732 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1733 &error_fatal); 1734 1735 /* Each core has an XSCOM MMIO region */ 1736 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1737 1738 pnv_xscom_add_subregion(chip, xscom_core_base, 1739 &pnv_core->xscom_regs); 1740 i++; 1741 } 1742 } 1743 1744 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1745 { 1746 PnvChip *chip = PNV_CHIP(dev); 1747 Error *error = NULL; 1748 1749 /* Cores */ 1750 pnv_chip_core_realize(chip, &error); 1751 if (error) { 1752 error_propagate(errp, error); 1753 return; 1754 } 1755 } 1756 1757 static Property pnv_chip_properties[] = { 1758 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1759 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1760 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1761 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1762 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1763 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1764 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1765 DEFINE_PROP_END_OF_LIST(), 1766 }; 1767 1768 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1769 { 1770 DeviceClass *dc = DEVICE_CLASS(klass); 1771 1772 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1773 dc->realize = pnv_chip_realize; 1774 device_class_set_props(dc, pnv_chip_properties); 1775 dc->desc = "PowerNV Chip"; 1776 } 1777 1778 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1779 { 1780 int i, j; 1781 1782 for (i = 0; i < chip->nr_cores; i++) { 1783 PnvCore *pc = chip->cores[i]; 1784 CPUCore *cc = CPU_CORE(pc); 1785 1786 for (j = 0; j < cc->nr_threads; j++) { 1787 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1788 return pc->threads[j]; 1789 } 1790 } 1791 } 1792 return NULL; 1793 } 1794 1795 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1796 { 1797 PnvMachineState *pnv = PNV_MACHINE(xi); 1798 int i, j; 1799 1800 for (i = 0; i < pnv->num_chips; i++) { 1801 PnvChip *chip = pnv->chips[i]; 1802 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1803 1804 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1805 return &chip8->psi.ics; 1806 } 1807 for (j = 0; j < chip->num_phbs; j++) { 1808 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1809 return &chip8->phbs[j].lsis; 1810 } 1811 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1812 return ICS(&chip8->phbs[j].msis); 1813 } 1814 } 1815 } 1816 return NULL; 1817 } 1818 1819 static void pnv_ics_resend(XICSFabric *xi) 1820 { 1821 PnvMachineState *pnv = PNV_MACHINE(xi); 1822 int i, j; 1823 1824 for (i = 0; i < pnv->num_chips; i++) { 1825 PnvChip *chip = pnv->chips[i]; 1826 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1827 1828 ics_resend(&chip8->psi.ics); 1829 for (j = 0; j < chip->num_phbs; j++) { 1830 ics_resend(&chip8->phbs[j].lsis); 1831 ics_resend(ICS(&chip8->phbs[j].msis)); 1832 } 1833 } 1834 } 1835 1836 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1837 { 1838 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1839 1840 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1841 } 1842 1843 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1844 Monitor *mon) 1845 { 1846 PnvMachineState *pnv = PNV_MACHINE(obj); 1847 int i; 1848 CPUState *cs; 1849 1850 CPU_FOREACH(cs) { 1851 PowerPCCPU *cpu = POWERPC_CPU(cs); 1852 1853 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1854 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1855 mon); 1856 } 1857 1858 for (i = 0; i < pnv->num_chips; i++) { 1859 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1860 } 1861 } 1862 1863 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1864 uint8_t nvt_blk, uint32_t nvt_idx, 1865 bool cam_ignore, uint8_t priority, 1866 uint32_t logic_serv, 1867 XiveTCTXMatch *match) 1868 { 1869 PnvMachineState *pnv = PNV_MACHINE(xfb); 1870 int total_count = 0; 1871 int i; 1872 1873 for (i = 0; i < pnv->num_chips; i++) { 1874 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1875 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1876 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1877 int count; 1878 1879 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1880 priority, logic_serv, match); 1881 1882 if (count < 0) { 1883 return count; 1884 } 1885 1886 total_count += count; 1887 } 1888 1889 return total_count; 1890 } 1891 1892 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1893 { 1894 MachineClass *mc = MACHINE_CLASS(oc); 1895 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1896 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1897 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1898 1899 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1900 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1901 1902 xic->icp_get = pnv_icp_get; 1903 xic->ics_get = pnv_ics_get; 1904 xic->ics_resend = pnv_ics_resend; 1905 1906 pmc->compat = compat; 1907 pmc->compat_size = sizeof(compat); 1908 } 1909 1910 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1911 { 1912 MachineClass *mc = MACHINE_CLASS(oc); 1913 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1914 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1915 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1916 1917 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1918 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1919 xfc->match_nvt = pnv_match_nvt; 1920 1921 mc->alias = "powernv"; 1922 1923 pmc->compat = compat; 1924 pmc->compat_size = sizeof(compat); 1925 pmc->dt_power_mgt = pnv_dt_power_mgt; 1926 } 1927 1928 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1929 { 1930 MachineClass *mc = MACHINE_CLASS(oc); 1931 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1932 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1933 1934 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1935 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1936 1937 pmc->compat = compat; 1938 pmc->compat_size = sizeof(compat); 1939 pmc->dt_power_mgt = pnv_dt_power_mgt; 1940 } 1941 1942 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1943 { 1944 PnvMachineState *pnv = PNV_MACHINE(obj); 1945 1946 return !!pnv->fw_load_addr; 1947 } 1948 1949 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1950 { 1951 PnvMachineState *pnv = PNV_MACHINE(obj); 1952 1953 if (value) { 1954 pnv->fw_load_addr = 0x8000000; 1955 } 1956 } 1957 1958 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1959 { 1960 MachineClass *mc = MACHINE_CLASS(oc); 1961 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1962 1963 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1964 mc->init = pnv_init; 1965 mc->reset = pnv_reset; 1966 mc->max_cpus = MAX_CPUS; 1967 /* Pnv provides a AHCI device for storage */ 1968 mc->block_default_type = IF_IDE; 1969 mc->no_parallel = 1; 1970 mc->default_boot_order = NULL; 1971 /* 1972 * RAM defaults to less than 2048 for 32-bit hosts, and large 1973 * enough to fit the maximum initrd size at it's load address 1974 */ 1975 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1976 mc->default_ram_id = "pnv.ram"; 1977 ispc->print_info = pnv_pic_print_info; 1978 1979 object_class_property_add_bool(oc, "hb-mode", 1980 pnv_machine_get_hb, pnv_machine_set_hb, 1981 &error_abort); 1982 object_class_property_set_description(oc, "hb-mode", 1983 "Use a hostboot like boot loader", 1984 NULL); 1985 } 1986 1987 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1988 { \ 1989 .name = type, \ 1990 .class_init = class_initfn, \ 1991 .parent = TYPE_PNV8_CHIP, \ 1992 } 1993 1994 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1995 { \ 1996 .name = type, \ 1997 .class_init = class_initfn, \ 1998 .parent = TYPE_PNV9_CHIP, \ 1999 } 2000 2001 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2002 { \ 2003 .name = type, \ 2004 .class_init = class_initfn, \ 2005 .parent = TYPE_PNV10_CHIP, \ 2006 } 2007 2008 static const TypeInfo types[] = { 2009 { 2010 .name = MACHINE_TYPE_NAME("powernv10"), 2011 .parent = TYPE_PNV_MACHINE, 2012 .class_init = pnv_machine_power10_class_init, 2013 }, 2014 { 2015 .name = MACHINE_TYPE_NAME("powernv9"), 2016 .parent = TYPE_PNV_MACHINE, 2017 .class_init = pnv_machine_power9_class_init, 2018 .interfaces = (InterfaceInfo[]) { 2019 { TYPE_XIVE_FABRIC }, 2020 { }, 2021 }, 2022 }, 2023 { 2024 .name = MACHINE_TYPE_NAME("powernv8"), 2025 .parent = TYPE_PNV_MACHINE, 2026 .class_init = pnv_machine_power8_class_init, 2027 .interfaces = (InterfaceInfo[]) { 2028 { TYPE_XICS_FABRIC }, 2029 { }, 2030 }, 2031 }, 2032 { 2033 .name = TYPE_PNV_MACHINE, 2034 .parent = TYPE_MACHINE, 2035 .abstract = true, 2036 .instance_size = sizeof(PnvMachineState), 2037 .class_init = pnv_machine_class_init, 2038 .class_size = sizeof(PnvMachineClass), 2039 .interfaces = (InterfaceInfo[]) { 2040 { TYPE_INTERRUPT_STATS_PROVIDER }, 2041 { }, 2042 }, 2043 }, 2044 { 2045 .name = TYPE_PNV_CHIP, 2046 .parent = TYPE_SYS_BUS_DEVICE, 2047 .class_init = pnv_chip_class_init, 2048 .instance_size = sizeof(PnvChip), 2049 .class_size = sizeof(PnvChipClass), 2050 .abstract = true, 2051 }, 2052 2053 /* 2054 * P10 chip and variants 2055 */ 2056 { 2057 .name = TYPE_PNV10_CHIP, 2058 .parent = TYPE_PNV_CHIP, 2059 .instance_init = pnv_chip_power10_instance_init, 2060 .instance_size = sizeof(Pnv10Chip), 2061 }, 2062 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2063 2064 /* 2065 * P9 chip and variants 2066 */ 2067 { 2068 .name = TYPE_PNV9_CHIP, 2069 .parent = TYPE_PNV_CHIP, 2070 .instance_init = pnv_chip_power9_instance_init, 2071 .instance_size = sizeof(Pnv9Chip), 2072 }, 2073 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2074 2075 /* 2076 * P8 chip and variants 2077 */ 2078 { 2079 .name = TYPE_PNV8_CHIP, 2080 .parent = TYPE_PNV_CHIP, 2081 .instance_init = pnv_chip_power8_instance_init, 2082 .instance_size = sizeof(Pnv8Chip), 2083 }, 2084 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2085 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2086 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2087 pnv_chip_power8nvl_class_init), 2088 }; 2089 2090 DEFINE_TYPES(types) 2091