1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 #include "hw/ppc/pnv_pnor.h" 48 49 #include "hw/isa/isa.h" 50 #include "hw/boards.h" 51 #include "hw/char/serial.h" 52 #include "hw/rtc/mc146818rtc.h" 53 54 #include <libfdt.h> 55 56 #define FDT_MAX_SIZE (1 * MiB) 57 58 #define FW_FILE_NAME "skiboot.lid" 59 #define FW_LOAD_ADDR 0x0 60 #define FW_MAX_SIZE (4 * MiB) 61 62 #define KERNEL_LOAD_ADDR 0x20000000 63 #define KERNEL_MAX_SIZE (256 * MiB) 64 #define INITRD_LOAD_ADDR 0x60000000 65 #define INITRD_MAX_SIZE (256 * MiB) 66 67 static const char *pnv_chip_core_typename(const PnvChip *o) 68 { 69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 72 const char *core_type = object_class_get_name(object_class_by_name(s)); 73 g_free(s); 74 return core_type; 75 } 76 77 /* 78 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 79 * 4 * 4 sockets * 12 cores * 8 threads = 1536 80 * Let's make it 2^11 81 */ 82 #define MAX_CPUS 2048 83 84 /* 85 * Memory nodes are created by hostboot, one for each range of memory 86 * that has a different "affinity". In practice, it means one range 87 * per chip. 88 */ 89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 90 { 91 char *mem_name; 92 uint64_t mem_reg_property[2]; 93 int off; 94 95 mem_reg_property[0] = cpu_to_be64(start); 96 mem_reg_property[1] = cpu_to_be64(size); 97 98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 99 off = fdt_add_subnode(fdt, 0, mem_name); 100 g_free(mem_name); 101 102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 104 sizeof(mem_reg_property)))); 105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 106 } 107 108 static int get_cpus_node(void *fdt) 109 { 110 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 111 112 if (cpus_offset < 0) { 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 114 if (cpus_offset) { 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 117 } 118 } 119 _FDT(cpus_offset); 120 return cpus_offset; 121 } 122 123 /* 124 * The PowerNV cores (and threads) need to use real HW ids and not an 125 * incremental index like it has been done on other platforms. This HW 126 * id is stored in the CPU PIR, it is used to create cpu nodes in the 127 * device tree, used in XSCOM to address cores and in interrupt 128 * servers. 129 */ 130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 131 { 132 PowerPCCPU *cpu = pc->threads[0]; 133 CPUState *cs = CPU(cpu); 134 DeviceClass *dc = DEVICE_GET_CLASS(cs); 135 int smt_threads = CPU_CORE(pc)->nr_threads; 136 CPUPPCState *env = &cpu->env; 137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 138 uint32_t servers_prop[smt_threads]; 139 int i; 140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 141 0xffffffff, 0xffffffff}; 142 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 143 uint32_t cpufreq = 1000000000; 144 uint32_t page_sizes_prop[64]; 145 size_t page_sizes_prop_size; 146 const uint8_t pa_features[] = { 24, 0, 147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 151 int offset; 152 char *nodename; 153 int cpus_offset = get_cpus_node(fdt); 154 155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 156 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 157 _FDT(offset); 158 g_free(nodename); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 172 env->icache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 174 env->icache_line_size))); 175 176 if (pcc->l1_dcache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 178 pcc->l1_dcache_size))); 179 } else { 180 warn_report("Unknown L1 dcache size for cpu"); 181 } 182 if (pcc->l1_icache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 184 pcc->l1_icache_size))); 185 } else { 186 warn_report("Unknown L1 icache size for cpu"); 187 } 188 189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 192 cpu->hash64_opts->slb_size))); 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 195 196 if (env->spr_cb[SPR_PURR].oea_read) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 198 } 199 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 202 segs, sizeof(segs)))); 203 } 204 205 /* 206 * Advertise VMX/VSX (vector extensions) if available 207 * 0 / no property == no vector extensions 208 * 1 == VMX / Altivec available 209 * 2 == VSX available 210 */ 211 if (env->insns_flags & PPC_ALTIVEC) { 212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 213 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 215 } 216 217 /* 218 * Advertise DFP (Decimal Floating Point) if available 219 * 0 / no property == no DFP 220 * 1 == DFP available 221 */ 222 if (env->insns_flags2 & PPC2_DFP) { 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 224 } 225 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 227 sizeof(page_sizes_prop)); 228 if (page_sizes_prop_size) { 229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 230 page_sizes_prop, page_sizes_prop_size))); 231 } 232 233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 234 pa_features, sizeof(pa_features)))); 235 236 /* Build interrupt servers properties */ 237 for (i = 0; i < smt_threads; i++) { 238 servers_prop[i] = cpu_to_be32(pc->pir + i); 239 } 240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 241 servers_prop, sizeof(servers_prop)))); 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 282 { 283 int i; 284 285 pnv_dt_xscom(chip, fdt, 0); 286 287 for (i = 0; i < chip->nr_cores; i++) { 288 PnvCore *pnv_core = chip->cores[i]; 289 290 pnv_dt_core(chip, pnv_core, fdt); 291 292 /* Interrupt Control Presenters (ICP). One per core. */ 293 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 294 } 295 296 if (chip->ram_size) { 297 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 298 } 299 } 300 301 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 302 { 303 int i; 304 305 pnv_dt_xscom(chip, fdt, 0); 306 307 for (i = 0; i < chip->nr_cores; i++) { 308 PnvCore *pnv_core = chip->cores[i]; 309 310 pnv_dt_core(chip, pnv_core, fdt); 311 } 312 313 if (chip->ram_size) { 314 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 315 } 316 317 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 318 } 319 320 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 321 { 322 int i; 323 324 pnv_dt_xscom(chip, fdt, 0); 325 326 for (i = 0; i < chip->nr_cores; i++) { 327 PnvCore *pnv_core = chip->cores[i]; 328 329 pnv_dt_core(chip, pnv_core, fdt); 330 } 331 332 if (chip->ram_size) { 333 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 334 } 335 336 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 337 } 338 339 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 340 { 341 uint32_t io_base = d->ioport_id; 342 uint32_t io_regs[] = { 343 cpu_to_be32(1), 344 cpu_to_be32(io_base), 345 cpu_to_be32(2) 346 }; 347 char *name; 348 int node; 349 350 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 351 node = fdt_add_subnode(fdt, lpc_off, name); 352 _FDT(node); 353 g_free(name); 354 355 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 356 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 357 } 358 359 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 360 { 361 const char compatible[] = "ns16550\0pnpPNP,501"; 362 uint32_t io_base = d->ioport_id; 363 uint32_t io_regs[] = { 364 cpu_to_be32(1), 365 cpu_to_be32(io_base), 366 cpu_to_be32(8) 367 }; 368 char *name; 369 int node; 370 371 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 372 node = fdt_add_subnode(fdt, lpc_off, name); 373 _FDT(node); 374 g_free(name); 375 376 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 377 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 378 sizeof(compatible)))); 379 380 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 381 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 382 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 383 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 384 fdt_get_phandle(fdt, lpc_off)))); 385 386 /* This is needed by Linux */ 387 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 388 } 389 390 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 391 { 392 const char compatible[] = "bt\0ipmi-bt"; 393 uint32_t io_base; 394 uint32_t io_regs[] = { 395 cpu_to_be32(1), 396 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 397 cpu_to_be32(3) 398 }; 399 uint32_t irq; 400 char *name; 401 int node; 402 403 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 404 io_regs[1] = cpu_to_be32(io_base); 405 406 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 407 408 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 409 node = fdt_add_subnode(fdt, lpc_off, name); 410 _FDT(node); 411 g_free(name); 412 413 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 414 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 415 sizeof(compatible)))); 416 417 /* Mark it as reserved to avoid Linux trying to claim it */ 418 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 419 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 420 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 421 fdt_get_phandle(fdt, lpc_off)))); 422 } 423 424 typedef struct ForeachPopulateArgs { 425 void *fdt; 426 int offset; 427 } ForeachPopulateArgs; 428 429 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 430 { 431 ForeachPopulateArgs *args = opaque; 432 ISADevice *d = ISA_DEVICE(dev); 433 434 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 435 pnv_dt_rtc(d, args->fdt, args->offset); 436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 437 pnv_dt_serial(d, args->fdt, args->offset); 438 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 439 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 440 } else { 441 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 442 d->ioport_id); 443 } 444 445 return 0; 446 } 447 448 /* 449 * The default LPC bus of a multichip system is on chip 0. It's 450 * recognized by the firmware (skiboot) using a "primary" property. 451 */ 452 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 453 { 454 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 455 ForeachPopulateArgs args = { 456 .fdt = fdt, 457 .offset = isa_offset, 458 }; 459 uint32_t phandle; 460 461 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 462 463 phandle = qemu_fdt_alloc_phandle(fdt); 464 assert(phandle > 0); 465 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 466 467 /* 468 * ISA devices are not necessarily parented to the ISA bus so we 469 * can not use object_child_foreach() 470 */ 471 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 472 &args); 473 } 474 475 static void pnv_dt_power_mgt(void *fdt) 476 { 477 int off; 478 479 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 480 off = fdt_add_subnode(fdt, off, "power-mgt"); 481 482 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 483 } 484 485 static void *pnv_dt_create(MachineState *machine) 486 { 487 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 488 PnvMachineState *pnv = PNV_MACHINE(machine); 489 void *fdt; 490 char *buf; 491 int off; 492 int i; 493 494 fdt = g_malloc0(FDT_MAX_SIZE); 495 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 496 497 /* /qemu node */ 498 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 499 500 /* Root node */ 501 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 502 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 503 _FDT((fdt_setprop_string(fdt, 0, "model", 504 "IBM PowerNV (emulated by qemu)"))); 505 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 506 507 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 508 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 509 if (qemu_uuid_set) { 510 _FDT((fdt_property_string(fdt, "system-id", buf))); 511 } 512 g_free(buf); 513 514 off = fdt_add_subnode(fdt, 0, "chosen"); 515 if (machine->kernel_cmdline) { 516 _FDT((fdt_setprop_string(fdt, off, "bootargs", 517 machine->kernel_cmdline))); 518 } 519 520 if (pnv->initrd_size) { 521 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 522 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 523 524 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 525 &start_prop, sizeof(start_prop)))); 526 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 527 &end_prop, sizeof(end_prop)))); 528 } 529 530 /* Populate device tree for each chip */ 531 for (i = 0; i < pnv->num_chips; i++) { 532 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 533 } 534 535 /* Populate ISA devices on chip 0 */ 536 pnv_dt_isa(pnv, fdt); 537 538 if (pnv->bmc) { 539 pnv_dt_bmc_sensors(pnv->bmc, fdt); 540 } 541 542 /* Create an extra node for power management on Power9 and Power10 */ 543 if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) { 544 pnv_dt_power_mgt(fdt); 545 } 546 547 return fdt; 548 } 549 550 static void pnv_powerdown_notify(Notifier *n, void *opaque) 551 { 552 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 553 554 if (pnv->bmc) { 555 pnv_bmc_powerdown(pnv->bmc); 556 } 557 } 558 559 static void pnv_reset(MachineState *machine) 560 { 561 void *fdt; 562 563 qemu_devices_reset(); 564 565 fdt = pnv_dt_create(machine); 566 567 /* Pack resulting tree */ 568 _FDT((fdt_pack(fdt))); 569 570 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 571 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 572 } 573 574 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 575 { 576 Pnv8Chip *chip8 = PNV8_CHIP(chip); 577 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 578 } 579 580 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 581 { 582 Pnv8Chip *chip8 = PNV8_CHIP(chip); 583 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 584 } 585 586 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 587 { 588 Pnv9Chip *chip9 = PNV9_CHIP(chip); 589 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 590 } 591 592 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 593 { 594 Pnv10Chip *chip10 = PNV10_CHIP(chip); 595 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 596 } 597 598 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 599 { 600 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 601 } 602 603 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 604 { 605 Pnv8Chip *chip8 = PNV8_CHIP(chip); 606 607 ics_pic_print_info(&chip8->psi.ics, mon); 608 } 609 610 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 611 { 612 Pnv9Chip *chip9 = PNV9_CHIP(chip); 613 614 pnv_xive_pic_print_info(&chip9->xive, mon); 615 pnv_psi_pic_print_info(&chip9->psi, mon); 616 } 617 618 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 619 { 620 PowerPCCPUClass *ppc_default = 621 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 622 PowerPCCPUClass *ppc = 623 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 624 625 return ppc_default->pvr_match(ppc_default, ppc->pvr); 626 } 627 628 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 629 { 630 Object *obj; 631 632 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 633 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 634 object_property_set_int(obj, irq, "irq", &error_fatal); 635 object_property_set_bool(obj, true, "realized", &error_fatal); 636 } 637 638 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 639 { 640 Pnv10Chip *chip10 = PNV10_CHIP(chip); 641 642 pnv_psi_pic_print_info(&chip10->psi, mon); 643 } 644 645 static void pnv_init(MachineState *machine) 646 { 647 PnvMachineState *pnv = PNV_MACHINE(machine); 648 MachineClass *mc = MACHINE_GET_CLASS(machine); 649 MemoryRegion *ram; 650 char *fw_filename; 651 long fw_size; 652 int i; 653 char *chip_typename; 654 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 655 DeviceState *dev; 656 657 /* allocate RAM */ 658 if (machine->ram_size < (1 * GiB)) { 659 warn_report("skiboot may not work with < 1GB of RAM"); 660 } 661 662 ram = g_new(MemoryRegion, 1); 663 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 664 machine->ram_size); 665 memory_region_add_subregion(get_system_memory(), 0, ram); 666 667 /* 668 * Create our simple PNOR device 669 */ 670 dev = qdev_create(NULL, TYPE_PNV_PNOR); 671 if (pnor) { 672 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 673 &error_abort); 674 } 675 qdev_init_nofail(dev); 676 pnv->pnor = PNV_PNOR(dev); 677 678 /* load skiboot firmware */ 679 if (bios_name == NULL) { 680 bios_name = FW_FILE_NAME; 681 } 682 683 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 684 if (!fw_filename) { 685 error_report("Could not find OPAL firmware '%s'", bios_name); 686 exit(1); 687 } 688 689 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 690 if (fw_size < 0) { 691 error_report("Could not load OPAL firmware '%s'", fw_filename); 692 exit(1); 693 } 694 g_free(fw_filename); 695 696 /* load kernel */ 697 if (machine->kernel_filename) { 698 long kernel_size; 699 700 kernel_size = load_image_targphys(machine->kernel_filename, 701 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 702 if (kernel_size < 0) { 703 error_report("Could not load kernel '%s'", 704 machine->kernel_filename); 705 exit(1); 706 } 707 } 708 709 /* load initrd */ 710 if (machine->initrd_filename) { 711 pnv->initrd_base = INITRD_LOAD_ADDR; 712 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 713 pnv->initrd_base, INITRD_MAX_SIZE); 714 if (pnv->initrd_size < 0) { 715 error_report("Could not load initial ram disk '%s'", 716 machine->initrd_filename); 717 exit(1); 718 } 719 } 720 721 /* 722 * Check compatibility of the specified CPU with the machine 723 * default. 724 */ 725 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 726 error_report("invalid CPU model '%s' for %s machine", 727 machine->cpu_type, mc->name); 728 exit(1); 729 } 730 731 /* Create the processor chips */ 732 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 733 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 734 i, machine->cpu_type); 735 if (!object_class_by_name(chip_typename)) { 736 error_report("invalid chip model '%.*s' for %s machine", 737 i, machine->cpu_type, mc->name); 738 exit(1); 739 } 740 741 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 742 for (i = 0; i < pnv->num_chips; i++) { 743 char chip_name[32]; 744 Object *chip = object_new(chip_typename); 745 746 pnv->chips[i] = PNV_CHIP(chip); 747 748 /* 749 * TODO: put all the memory in one node on chip 0 until we find a 750 * way to specify different ranges for each chip 751 */ 752 if (i == 0) { 753 object_property_set_int(chip, machine->ram_size, "ram-size", 754 &error_fatal); 755 } 756 757 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 758 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 759 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 760 &error_fatal); 761 object_property_set_int(chip, machine->smp.cores, 762 "nr-cores", &error_fatal); 763 object_property_set_bool(chip, true, "realized", &error_fatal); 764 } 765 g_free(chip_typename); 766 767 /* Create the machine BMC simulator */ 768 pnv->bmc = pnv_bmc_create(); 769 770 /* Instantiate ISA bus on chip 0 */ 771 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 772 773 /* Create serial port */ 774 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 775 776 /* Create an RTC ISA device too */ 777 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 778 779 /* Create the IPMI BT device for communication with the BMC */ 780 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 781 782 /* 783 * OpenPOWER systems use a IPMI SEL Event message to notify the 784 * host to powerdown 785 */ 786 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 787 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 788 } 789 790 /* 791 * 0:21 Reserved - Read as zeros 792 * 22:24 Chip ID 793 * 25:28 Core number 794 * 29:31 Thread ID 795 */ 796 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 797 { 798 return (chip->chip_id << 7) | (core_id << 3); 799 } 800 801 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 802 Error **errp) 803 { 804 Error *local_err = NULL; 805 Object *obj; 806 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 807 808 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 809 &local_err); 810 if (local_err) { 811 error_propagate(errp, local_err); 812 return; 813 } 814 815 pnv_cpu->intc = obj; 816 } 817 818 819 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 820 { 821 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 822 823 icp_reset(ICP(pnv_cpu->intc)); 824 } 825 826 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 827 { 828 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 829 830 icp_destroy(ICP(pnv_cpu->intc)); 831 pnv_cpu->intc = NULL; 832 } 833 834 /* 835 * 0:48 Reserved - Read as zeroes 836 * 49:52 Node ID 837 * 53:55 Chip ID 838 * 56 Reserved - Read as zero 839 * 57:61 Core number 840 * 62:63 Thread ID 841 * 842 * We only care about the lower bits. uint32_t is fine for the moment. 843 */ 844 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 845 { 846 return (chip->chip_id << 8) | (core_id << 2); 847 } 848 849 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 850 { 851 return (chip->chip_id << 8) | (core_id << 2); 852 } 853 854 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 855 Error **errp) 856 { 857 Pnv9Chip *chip9 = PNV9_CHIP(chip); 858 Error *local_err = NULL; 859 Object *obj; 860 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 861 862 /* 863 * The core creates its interrupt presenter but the XIVE interrupt 864 * controller object is initialized afterwards. Hopefully, it's 865 * only used at runtime. 866 */ 867 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 868 if (local_err) { 869 error_propagate(errp, local_err); 870 return; 871 } 872 873 pnv_cpu->intc = obj; 874 } 875 876 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 877 { 878 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 879 880 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 881 } 882 883 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 884 { 885 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 886 887 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 888 pnv_cpu->intc = NULL; 889 } 890 891 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 892 Error **errp) 893 { 894 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 895 896 /* Will be defined when the interrupt controller is */ 897 pnv_cpu->intc = NULL; 898 } 899 900 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 901 { 902 ; 903 } 904 905 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 906 { 907 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 908 909 pnv_cpu->intc = NULL; 910 } 911 912 /* 913 * Allowed core identifiers on a POWER8 Processor Chip : 914 * 915 * <EX0 reserved> 916 * EX1 - Venice only 917 * EX2 - Venice only 918 * EX3 - Venice only 919 * EX4 920 * EX5 921 * EX6 922 * <EX7,8 reserved> <reserved> 923 * EX9 - Venice only 924 * EX10 - Venice only 925 * EX11 - Venice only 926 * EX12 927 * EX13 928 * EX14 929 * <EX15 reserved> 930 */ 931 #define POWER8E_CORE_MASK (0x7070ull) 932 #define POWER8_CORE_MASK (0x7e7eull) 933 934 /* 935 * POWER9 has 24 cores, ids starting at 0x0 936 */ 937 #define POWER9_CORE_MASK (0xffffffffffffffull) 938 939 940 #define POWER10_CORE_MASK (0xffffffffffffffull) 941 942 static void pnv_chip_power8_instance_init(Object *obj) 943 { 944 Pnv8Chip *chip8 = PNV8_CHIP(obj); 945 946 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 947 TYPE_PNV8_PSI, &error_abort, NULL); 948 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 949 OBJECT(qdev_get_machine()), &error_abort); 950 951 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 952 TYPE_PNV8_LPC, &error_abort, NULL); 953 954 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 955 TYPE_PNV8_OCC, &error_abort, NULL); 956 957 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 958 TYPE_PNV8_HOMER, &error_abort, NULL); 959 } 960 961 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 962 { 963 PnvChip *chip = PNV_CHIP(chip8); 964 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 965 int i, j; 966 char *name; 967 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 968 969 name = g_strdup_printf("icp-%x", chip->chip_id); 970 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 971 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 972 g_free(name); 973 974 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 975 976 /* Map the ICP registers for each thread */ 977 for (i = 0; i < chip->nr_cores; i++) { 978 PnvCore *pnv_core = chip->cores[i]; 979 int core_hwid = CPU_CORE(pnv_core)->core_id; 980 981 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 982 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 983 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 984 985 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 986 &icp->mmio); 987 } 988 } 989 } 990 991 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 992 { 993 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 994 PnvChip *chip = PNV_CHIP(dev); 995 Pnv8Chip *chip8 = PNV8_CHIP(dev); 996 Pnv8Psi *psi8 = &chip8->psi; 997 Error *local_err = NULL; 998 999 /* XSCOM bridge is first */ 1000 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1001 if (local_err) { 1002 error_propagate(errp, local_err); 1003 return; 1004 } 1005 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1006 1007 pcc->parent_realize(dev, &local_err); 1008 if (local_err) { 1009 error_propagate(errp, local_err); 1010 return; 1011 } 1012 1013 /* Processor Service Interface (PSI) Host Bridge */ 1014 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1015 "bar", &error_fatal); 1016 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1017 if (local_err) { 1018 error_propagate(errp, local_err); 1019 return; 1020 } 1021 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1022 &PNV_PSI(psi8)->xscom_regs); 1023 1024 /* Create LPC controller */ 1025 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1026 &error_abort); 1027 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1028 &error_fatal); 1029 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1030 1031 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1032 (uint64_t) PNV_XSCOM_BASE(chip), 1033 PNV_XSCOM_LPC_BASE); 1034 1035 /* 1036 * Interrupt Management Area. This is the memory region holding 1037 * all the Interrupt Control Presenter (ICP) registers 1038 */ 1039 pnv_chip_icp_realize(chip8, &local_err); 1040 if (local_err) { 1041 error_propagate(errp, local_err); 1042 return; 1043 } 1044 1045 /* Create the simplified OCC model */ 1046 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1047 &error_abort); 1048 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1049 if (local_err) { 1050 error_propagate(errp, local_err); 1051 return; 1052 } 1053 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1054 1055 /* OCC SRAM model */ 1056 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1057 &chip8->occ.sram_regs); 1058 1059 /* HOMER */ 1060 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1061 &error_abort); 1062 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1063 &local_err); 1064 if (local_err) { 1065 error_propagate(errp, local_err); 1066 return; 1067 } 1068 /* Homer Xscom region */ 1069 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1070 1071 /* Homer mmio region */ 1072 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1073 &chip8->homer.regs); 1074 } 1075 1076 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1077 { 1078 DeviceClass *dc = DEVICE_CLASS(klass); 1079 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1080 1081 k->chip_type = PNV_CHIP_POWER8E; 1082 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1083 k->cores_mask = POWER8E_CORE_MASK; 1084 k->core_pir = pnv_chip_core_pir_p8; 1085 k->intc_create = pnv_chip_power8_intc_create; 1086 k->intc_reset = pnv_chip_power8_intc_reset; 1087 k->intc_destroy = pnv_chip_power8_intc_destroy; 1088 k->isa_create = pnv_chip_power8_isa_create; 1089 k->dt_populate = pnv_chip_power8_dt_populate; 1090 k->pic_print_info = pnv_chip_power8_pic_print_info; 1091 dc->desc = "PowerNV Chip POWER8E"; 1092 1093 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1094 &k->parent_realize); 1095 } 1096 1097 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1098 { 1099 DeviceClass *dc = DEVICE_CLASS(klass); 1100 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1101 1102 k->chip_type = PNV_CHIP_POWER8; 1103 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1104 k->cores_mask = POWER8_CORE_MASK; 1105 k->core_pir = pnv_chip_core_pir_p8; 1106 k->intc_create = pnv_chip_power8_intc_create; 1107 k->intc_reset = pnv_chip_power8_intc_reset; 1108 k->intc_destroy = pnv_chip_power8_intc_destroy; 1109 k->isa_create = pnv_chip_power8_isa_create; 1110 k->dt_populate = pnv_chip_power8_dt_populate; 1111 k->pic_print_info = pnv_chip_power8_pic_print_info; 1112 dc->desc = "PowerNV Chip POWER8"; 1113 1114 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1115 &k->parent_realize); 1116 } 1117 1118 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1119 { 1120 DeviceClass *dc = DEVICE_CLASS(klass); 1121 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1122 1123 k->chip_type = PNV_CHIP_POWER8NVL; 1124 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1125 k->cores_mask = POWER8_CORE_MASK; 1126 k->core_pir = pnv_chip_core_pir_p8; 1127 k->intc_create = pnv_chip_power8_intc_create; 1128 k->intc_reset = pnv_chip_power8_intc_reset; 1129 k->intc_destroy = pnv_chip_power8_intc_destroy; 1130 k->isa_create = pnv_chip_power8nvl_isa_create; 1131 k->dt_populate = pnv_chip_power8_dt_populate; 1132 k->pic_print_info = pnv_chip_power8_pic_print_info; 1133 dc->desc = "PowerNV Chip POWER8NVL"; 1134 1135 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1136 &k->parent_realize); 1137 } 1138 1139 static void pnv_chip_power9_instance_init(Object *obj) 1140 { 1141 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1142 1143 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1144 TYPE_PNV_XIVE, &error_abort, NULL); 1145 1146 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1147 TYPE_PNV9_PSI, &error_abort, NULL); 1148 1149 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1150 TYPE_PNV9_LPC, &error_abort, NULL); 1151 1152 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1153 TYPE_PNV9_OCC, &error_abort, NULL); 1154 1155 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1156 TYPE_PNV9_HOMER, &error_abort, NULL); 1157 } 1158 1159 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1160 { 1161 PnvChip *chip = PNV_CHIP(chip9); 1162 int i; 1163 1164 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1165 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1166 1167 for (i = 0; i < chip9->nr_quads; i++) { 1168 char eq_name[32]; 1169 PnvQuad *eq = &chip9->quads[i]; 1170 PnvCore *pnv_core = chip->cores[i * 4]; 1171 int core_id = CPU_CORE(pnv_core)->core_id; 1172 1173 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1174 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1175 TYPE_PNV_QUAD, &error_fatal, NULL); 1176 1177 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1178 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1179 1180 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1181 &eq->xscom_regs); 1182 } 1183 } 1184 1185 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1186 { 1187 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1188 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1189 PnvChip *chip = PNV_CHIP(dev); 1190 Pnv9Psi *psi9 = &chip9->psi; 1191 Error *local_err = NULL; 1192 1193 /* XSCOM bridge is first */ 1194 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1195 if (local_err) { 1196 error_propagate(errp, local_err); 1197 return; 1198 } 1199 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1200 1201 pcc->parent_realize(dev, &local_err); 1202 if (local_err) { 1203 error_propagate(errp, local_err); 1204 return; 1205 } 1206 1207 pnv_chip_quad_realize(chip9, &local_err); 1208 if (local_err) { 1209 error_propagate(errp, local_err); 1210 return; 1211 } 1212 1213 /* XIVE interrupt controller (POWER9) */ 1214 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1215 "ic-bar", &error_fatal); 1216 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1217 "vc-bar", &error_fatal); 1218 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1219 "pc-bar", &error_fatal); 1220 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1221 "tm-bar", &error_fatal); 1222 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1223 &error_abort); 1224 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1225 &local_err); 1226 if (local_err) { 1227 error_propagate(errp, local_err); 1228 return; 1229 } 1230 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1231 &chip9->xive.xscom_regs); 1232 1233 /* Processor Service Interface (PSI) Host Bridge */ 1234 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1235 "bar", &error_fatal); 1236 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1237 if (local_err) { 1238 error_propagate(errp, local_err); 1239 return; 1240 } 1241 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1242 &PNV_PSI(psi9)->xscom_regs); 1243 1244 /* LPC */ 1245 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1246 &error_abort); 1247 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1248 if (local_err) { 1249 error_propagate(errp, local_err); 1250 return; 1251 } 1252 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1253 &chip9->lpc.xscom_regs); 1254 1255 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1256 (uint64_t) PNV9_LPCM_BASE(chip)); 1257 1258 /* Create the simplified OCC model */ 1259 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1260 &error_abort); 1261 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1262 if (local_err) { 1263 error_propagate(errp, local_err); 1264 return; 1265 } 1266 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1267 1268 /* OCC SRAM model */ 1269 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1270 &chip9->occ.sram_regs); 1271 1272 /* HOMER */ 1273 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1274 &error_abort); 1275 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1276 &local_err); 1277 if (local_err) { 1278 error_propagate(errp, local_err); 1279 return; 1280 } 1281 /* Homer Xscom region */ 1282 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1283 1284 /* Homer mmio region */ 1285 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1286 &chip9->homer.regs); 1287 } 1288 1289 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1290 { 1291 DeviceClass *dc = DEVICE_CLASS(klass); 1292 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1293 1294 k->chip_type = PNV_CHIP_POWER9; 1295 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1296 k->cores_mask = POWER9_CORE_MASK; 1297 k->core_pir = pnv_chip_core_pir_p9; 1298 k->intc_create = pnv_chip_power9_intc_create; 1299 k->intc_reset = pnv_chip_power9_intc_reset; 1300 k->intc_destroy = pnv_chip_power9_intc_destroy; 1301 k->isa_create = pnv_chip_power9_isa_create; 1302 k->dt_populate = pnv_chip_power9_dt_populate; 1303 k->pic_print_info = pnv_chip_power9_pic_print_info; 1304 dc->desc = "PowerNV Chip POWER9"; 1305 1306 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1307 &k->parent_realize); 1308 } 1309 1310 static void pnv_chip_power10_instance_init(Object *obj) 1311 { 1312 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1313 1314 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1315 TYPE_PNV10_PSI, &error_abort, NULL); 1316 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1317 TYPE_PNV10_LPC, &error_abort, NULL); 1318 } 1319 1320 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1321 { 1322 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1323 PnvChip *chip = PNV_CHIP(dev); 1324 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1325 Error *local_err = NULL; 1326 1327 /* XSCOM bridge is first */ 1328 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1329 if (local_err) { 1330 error_propagate(errp, local_err); 1331 return; 1332 } 1333 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1334 1335 pcc->parent_realize(dev, &local_err); 1336 if (local_err) { 1337 error_propagate(errp, local_err); 1338 return; 1339 } 1340 1341 /* Processor Service Interface (PSI) Host Bridge */ 1342 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1343 "bar", &error_fatal); 1344 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1345 &local_err); 1346 if (local_err) { 1347 error_propagate(errp, local_err); 1348 return; 1349 } 1350 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1351 &PNV_PSI(&chip10->psi)->xscom_regs); 1352 1353 /* LPC */ 1354 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1355 &error_abort); 1356 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1357 &local_err); 1358 if (local_err) { 1359 error_propagate(errp, local_err); 1360 return; 1361 } 1362 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1363 &chip10->lpc.xscom_regs); 1364 1365 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1366 (uint64_t) PNV10_LPCM_BASE(chip)); 1367 } 1368 1369 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1370 { 1371 DeviceClass *dc = DEVICE_CLASS(klass); 1372 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1373 1374 k->chip_type = PNV_CHIP_POWER10; 1375 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1376 k->cores_mask = POWER10_CORE_MASK; 1377 k->core_pir = pnv_chip_core_pir_p10; 1378 k->intc_create = pnv_chip_power10_intc_create; 1379 k->intc_reset = pnv_chip_power10_intc_reset; 1380 k->intc_destroy = pnv_chip_power10_intc_destroy; 1381 k->isa_create = pnv_chip_power10_isa_create; 1382 k->dt_populate = pnv_chip_power10_dt_populate; 1383 k->pic_print_info = pnv_chip_power10_pic_print_info; 1384 dc->desc = "PowerNV Chip POWER10"; 1385 1386 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1387 &k->parent_realize); 1388 } 1389 1390 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1391 { 1392 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1393 int cores_max; 1394 1395 /* 1396 * No custom mask for this chip, let's use the default one from * 1397 * the chip class 1398 */ 1399 if (!chip->cores_mask) { 1400 chip->cores_mask = pcc->cores_mask; 1401 } 1402 1403 /* filter alien core ids ! some are reserved */ 1404 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1405 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1406 chip->cores_mask); 1407 return; 1408 } 1409 chip->cores_mask &= pcc->cores_mask; 1410 1411 /* now that we have a sane layout, let check the number of cores */ 1412 cores_max = ctpop64(chip->cores_mask); 1413 if (chip->nr_cores > cores_max) { 1414 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1415 cores_max); 1416 return; 1417 } 1418 } 1419 1420 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1421 { 1422 MachineState *ms = MACHINE(qdev_get_machine()); 1423 Error *error = NULL; 1424 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1425 const char *typename = pnv_chip_core_typename(chip); 1426 int i, core_hwid; 1427 1428 if (!object_class_by_name(typename)) { 1429 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1430 return; 1431 } 1432 1433 /* Cores */ 1434 pnv_chip_core_sanitize(chip, &error); 1435 if (error) { 1436 error_propagate(errp, error); 1437 return; 1438 } 1439 1440 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1441 1442 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1443 && (i < chip->nr_cores); core_hwid++) { 1444 char core_name[32]; 1445 PnvCore *pnv_core; 1446 uint64_t xscom_core_base; 1447 1448 if (!(chip->cores_mask & (1ull << core_hwid))) { 1449 continue; 1450 } 1451 1452 pnv_core = PNV_CORE(object_new(typename)); 1453 1454 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1455 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1456 &error_abort); 1457 chip->cores[i] = pnv_core; 1458 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1459 &error_fatal); 1460 object_property_set_int(OBJECT(pnv_core), core_hwid, 1461 CPU_CORE_PROP_CORE_ID, &error_fatal); 1462 object_property_set_int(OBJECT(pnv_core), 1463 pcc->core_pir(chip, core_hwid), 1464 "pir", &error_fatal); 1465 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1466 &error_abort); 1467 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1468 &error_fatal); 1469 1470 /* Each core has an XSCOM MMIO region */ 1471 if (pnv_chip_is_power10(chip)) { 1472 xscom_core_base = PNV10_XSCOM_EC_BASE(core_hwid); 1473 } else if (pnv_chip_is_power9(chip)) { 1474 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1475 } else { 1476 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1477 } 1478 1479 pnv_xscom_add_subregion(chip, xscom_core_base, 1480 &pnv_core->xscom_regs); 1481 i++; 1482 } 1483 } 1484 1485 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1486 { 1487 PnvChip *chip = PNV_CHIP(dev); 1488 Error *error = NULL; 1489 1490 /* Cores */ 1491 pnv_chip_core_realize(chip, &error); 1492 if (error) { 1493 error_propagate(errp, error); 1494 return; 1495 } 1496 } 1497 1498 static Property pnv_chip_properties[] = { 1499 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1500 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1501 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1502 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1503 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1504 DEFINE_PROP_END_OF_LIST(), 1505 }; 1506 1507 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1508 { 1509 DeviceClass *dc = DEVICE_CLASS(klass); 1510 1511 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1512 dc->realize = pnv_chip_realize; 1513 dc->props = pnv_chip_properties; 1514 dc->desc = "PowerNV Chip"; 1515 } 1516 1517 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1518 { 1519 int i, j; 1520 1521 for (i = 0; i < chip->nr_cores; i++) { 1522 PnvCore *pc = chip->cores[i]; 1523 CPUCore *cc = CPU_CORE(pc); 1524 1525 for (j = 0; j < cc->nr_threads; j++) { 1526 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1527 return pc->threads[j]; 1528 } 1529 } 1530 } 1531 return NULL; 1532 } 1533 1534 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1535 { 1536 PnvMachineState *pnv = PNV_MACHINE(xi); 1537 int i; 1538 1539 for (i = 0; i < pnv->num_chips; i++) { 1540 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1541 1542 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1543 return &chip8->psi.ics; 1544 } 1545 } 1546 return NULL; 1547 } 1548 1549 static void pnv_ics_resend(XICSFabric *xi) 1550 { 1551 PnvMachineState *pnv = PNV_MACHINE(xi); 1552 int i; 1553 1554 for (i = 0; i < pnv->num_chips; i++) { 1555 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1556 ics_resend(&chip8->psi.ics); 1557 } 1558 } 1559 1560 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1561 { 1562 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1563 1564 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1565 } 1566 1567 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1568 Monitor *mon) 1569 { 1570 PnvMachineState *pnv = PNV_MACHINE(obj); 1571 int i; 1572 CPUState *cs; 1573 1574 CPU_FOREACH(cs) { 1575 PowerPCCPU *cpu = POWERPC_CPU(cs); 1576 1577 if (pnv_chip_is_power9(pnv->chips[0])) { 1578 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1579 } else { 1580 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1581 } 1582 } 1583 1584 for (i = 0; i < pnv->num_chips; i++) { 1585 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1586 } 1587 } 1588 1589 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1590 uint8_t nvt_blk, uint32_t nvt_idx, 1591 bool cam_ignore, uint8_t priority, 1592 uint32_t logic_serv, 1593 XiveTCTXMatch *match) 1594 { 1595 PnvMachineState *pnv = PNV_MACHINE(xfb); 1596 int total_count = 0; 1597 int i; 1598 1599 for (i = 0; i < pnv->num_chips; i++) { 1600 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1601 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1602 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1603 int count; 1604 1605 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1606 priority, logic_serv, match); 1607 1608 if (count < 0) { 1609 return count; 1610 } 1611 1612 total_count += count; 1613 } 1614 1615 return total_count; 1616 } 1617 1618 PnvChip *pnv_get_chip(uint32_t chip_id) 1619 { 1620 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1621 int i; 1622 1623 for (i = 0; i < pnv->num_chips; i++) { 1624 PnvChip *chip = pnv->chips[i]; 1625 if (chip->chip_id == chip_id) { 1626 return chip; 1627 } 1628 } 1629 return NULL; 1630 } 1631 1632 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1633 void *opaque, Error **errp) 1634 { 1635 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1636 } 1637 1638 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1639 void *opaque, Error **errp) 1640 { 1641 PnvMachineState *pnv = PNV_MACHINE(obj); 1642 uint32_t num_chips; 1643 Error *local_err = NULL; 1644 1645 visit_type_uint32(v, name, &num_chips, &local_err); 1646 if (local_err) { 1647 error_propagate(errp, local_err); 1648 return; 1649 } 1650 1651 /* 1652 * TODO: should we decide on how many chips we can create based 1653 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1654 */ 1655 if (!is_power_of_2(num_chips) || num_chips > 4) { 1656 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1657 return; 1658 } 1659 1660 pnv->num_chips = num_chips; 1661 } 1662 1663 static void pnv_machine_instance_init(Object *obj) 1664 { 1665 PnvMachineState *pnv = PNV_MACHINE(obj); 1666 pnv->num_chips = 1; 1667 } 1668 1669 static void pnv_machine_class_props_init(ObjectClass *oc) 1670 { 1671 object_class_property_add(oc, "num-chips", "uint32", 1672 pnv_get_num_chips, pnv_set_num_chips, 1673 NULL, NULL, NULL); 1674 object_class_property_set_description(oc, "num-chips", 1675 "Specifies the number of processor chips", 1676 NULL); 1677 } 1678 1679 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1680 { 1681 MachineClass *mc = MACHINE_CLASS(oc); 1682 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1683 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1684 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1685 1686 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1687 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1688 1689 xic->icp_get = pnv_icp_get; 1690 xic->ics_get = pnv_ics_get; 1691 xic->ics_resend = pnv_ics_resend; 1692 1693 pmc->compat = compat; 1694 pmc->compat_size = sizeof(compat); 1695 } 1696 1697 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1698 { 1699 MachineClass *mc = MACHINE_CLASS(oc); 1700 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1701 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1702 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1703 1704 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1705 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1706 xfc->match_nvt = pnv_match_nvt; 1707 1708 mc->alias = "powernv"; 1709 1710 pmc->compat = compat; 1711 pmc->compat_size = sizeof(compat); 1712 } 1713 1714 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1715 { 1716 MachineClass *mc = MACHINE_CLASS(oc); 1717 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1718 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1719 1720 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1721 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1722 1723 pmc->compat = compat; 1724 pmc->compat_size = sizeof(compat); 1725 } 1726 1727 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1728 { 1729 MachineClass *mc = MACHINE_CLASS(oc); 1730 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1731 1732 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1733 mc->init = pnv_init; 1734 mc->reset = pnv_reset; 1735 mc->max_cpus = MAX_CPUS; 1736 /* Pnv provides a AHCI device for storage */ 1737 mc->block_default_type = IF_IDE; 1738 mc->no_parallel = 1; 1739 mc->default_boot_order = NULL; 1740 /* 1741 * RAM defaults to less than 2048 for 32-bit hosts, and large 1742 * enough to fit the maximum initrd size at it's load address 1743 */ 1744 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1745 ispc->print_info = pnv_pic_print_info; 1746 1747 pnv_machine_class_props_init(oc); 1748 } 1749 1750 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1751 { \ 1752 .name = type, \ 1753 .class_init = class_initfn, \ 1754 .parent = TYPE_PNV8_CHIP, \ 1755 } 1756 1757 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1758 { \ 1759 .name = type, \ 1760 .class_init = class_initfn, \ 1761 .parent = TYPE_PNV9_CHIP, \ 1762 } 1763 1764 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 1765 { \ 1766 .name = type, \ 1767 .class_init = class_initfn, \ 1768 .parent = TYPE_PNV10_CHIP, \ 1769 } 1770 1771 static const TypeInfo types[] = { 1772 { 1773 .name = MACHINE_TYPE_NAME("powernv10"), 1774 .parent = TYPE_PNV_MACHINE, 1775 .class_init = pnv_machine_power10_class_init, 1776 }, 1777 { 1778 .name = MACHINE_TYPE_NAME("powernv9"), 1779 .parent = TYPE_PNV_MACHINE, 1780 .class_init = pnv_machine_power9_class_init, 1781 .interfaces = (InterfaceInfo[]) { 1782 { TYPE_XIVE_FABRIC }, 1783 { }, 1784 }, 1785 }, 1786 { 1787 .name = MACHINE_TYPE_NAME("powernv8"), 1788 .parent = TYPE_PNV_MACHINE, 1789 .class_init = pnv_machine_power8_class_init, 1790 .interfaces = (InterfaceInfo[]) { 1791 { TYPE_XICS_FABRIC }, 1792 { }, 1793 }, 1794 }, 1795 { 1796 .name = TYPE_PNV_MACHINE, 1797 .parent = TYPE_MACHINE, 1798 .abstract = true, 1799 .instance_size = sizeof(PnvMachineState), 1800 .instance_init = pnv_machine_instance_init, 1801 .class_init = pnv_machine_class_init, 1802 .class_size = sizeof(PnvMachineClass), 1803 .interfaces = (InterfaceInfo[]) { 1804 { TYPE_INTERRUPT_STATS_PROVIDER }, 1805 { }, 1806 }, 1807 }, 1808 { 1809 .name = TYPE_PNV_CHIP, 1810 .parent = TYPE_SYS_BUS_DEVICE, 1811 .class_init = pnv_chip_class_init, 1812 .instance_size = sizeof(PnvChip), 1813 .class_size = sizeof(PnvChipClass), 1814 .abstract = true, 1815 }, 1816 1817 /* 1818 * P10 chip and variants 1819 */ 1820 { 1821 .name = TYPE_PNV10_CHIP, 1822 .parent = TYPE_PNV_CHIP, 1823 .instance_init = pnv_chip_power10_instance_init, 1824 .instance_size = sizeof(Pnv10Chip), 1825 }, 1826 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 1827 1828 /* 1829 * P9 chip and variants 1830 */ 1831 { 1832 .name = TYPE_PNV9_CHIP, 1833 .parent = TYPE_PNV_CHIP, 1834 .instance_init = pnv_chip_power9_instance_init, 1835 .instance_size = sizeof(Pnv9Chip), 1836 }, 1837 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1838 1839 /* 1840 * P8 chip and variants 1841 */ 1842 { 1843 .name = TYPE_PNV8_CHIP, 1844 .parent = TYPE_PNV_CHIP, 1845 .instance_init = pnv_chip_power8_instance_init, 1846 .instance_size = sizeof(Pnv8Chip), 1847 }, 1848 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1849 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1850 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1851 pnv_chip_power8nvl_class_init), 1852 }; 1853 1854 DEFINE_TYPES(types) 1855