1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "hw/intc/intc.h" 42 #include "hw/ipmi/ipmi.h" 43 #include "target/ppc/mmu-hash64.h" 44 #include "hw/pci/msi.h" 45 #include "hw/pci-host/pnv_phb.h" 46 #include "hw/pci-host/pnv_phb3.h" 47 #include "hw/pci-host/pnv_phb4.h" 48 49 #include "hw/ppc/xics.h" 50 #include "hw/qdev-properties.h" 51 #include "hw/ppc/pnv_chip.h" 52 #include "hw/ppc/pnv_xscom.h" 53 #include "hw/ppc/pnv_pnor.h" 54 55 #include "hw/isa/isa.h" 56 #include "hw/char/serial.h" 57 #include "hw/rtc/mc146818rtc.h" 58 59 #include <libfdt.h> 60 61 #define FDT_MAX_SIZE (1 * MiB) 62 63 #define FW_FILE_NAME "skiboot.lid" 64 #define FW_LOAD_ADDR 0x0 65 #define FW_MAX_SIZE (16 * MiB) 66 67 #define KERNEL_LOAD_ADDR 0x20000000 68 #define KERNEL_MAX_SIZE (128 * MiB) 69 #define INITRD_LOAD_ADDR 0x28000000 70 #define INITRD_MAX_SIZE (128 * MiB) 71 72 static const char *pnv_chip_core_typename(const PnvChip *o) 73 { 74 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 75 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 76 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 77 const char *core_type = object_class_get_name(object_class_by_name(s)); 78 g_free(s); 79 return core_type; 80 } 81 82 /* 83 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 84 * 4 * 4 sockets * 12 cores * 8 threads = 1536 85 * Let's make it 2^11 86 */ 87 #define MAX_CPUS 2048 88 89 /* 90 * Memory nodes are created by hostboot, one for each range of memory 91 * that has a different "affinity". In practice, it means one range 92 * per chip. 93 */ 94 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 95 { 96 char *mem_name; 97 uint64_t mem_reg_property[2]; 98 int off; 99 100 mem_reg_property[0] = cpu_to_be64(start); 101 mem_reg_property[1] = cpu_to_be64(size); 102 103 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 104 off = fdt_add_subnode(fdt, 0, mem_name); 105 g_free(mem_name); 106 107 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 108 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 109 sizeof(mem_reg_property)))); 110 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 111 } 112 113 static int get_cpus_node(void *fdt) 114 { 115 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 116 117 if (cpus_offset < 0) { 118 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 119 if (cpus_offset) { 120 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 122 } 123 } 124 _FDT(cpus_offset); 125 return cpus_offset; 126 } 127 128 /* 129 * The PowerNV cores (and threads) need to use real HW ids and not an 130 * incremental index like it has been done on other platforms. This HW 131 * id is stored in the CPU PIR, it is used to create cpu nodes in the 132 * device tree, used in XSCOM to address cores and in interrupt 133 * servers. 134 */ 135 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 136 { 137 PowerPCCPU *cpu = pc->threads[0]; 138 CPUState *cs = CPU(cpu); 139 DeviceClass *dc = DEVICE_GET_CLASS(cs); 140 int smt_threads = CPU_CORE(pc)->nr_threads; 141 CPUPPCState *env = &cpu->env; 142 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 143 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t pir; 147 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 148 0xffffffff, 0xffffffff}; 149 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 150 uint32_t cpufreq = 1000000000; 151 uint32_t page_sizes_prop[64]; 152 size_t page_sizes_prop_size; 153 int offset; 154 char *nodename; 155 int cpus_offset = get_cpus_node(fdt); 156 157 pir = pnv_cc->chip_pir(chip, pc->hwid, 0); 158 159 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 160 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 161 _FDT(offset); 162 g_free(nodename); 163 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 167 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 168 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 169 170 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 171 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 172 env->dcache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 176 env->icache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 178 env->icache_line_size))); 179 180 if (pcc->l1_dcache_size) { 181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 182 pcc->l1_dcache_size))); 183 } else { 184 warn_report("Unknown L1 dcache size for cpu"); 185 } 186 if (pcc->l1_icache_size) { 187 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 188 pcc->l1_icache_size))); 189 } else { 190 warn_report("Unknown L1 icache size for cpu"); 191 } 192 193 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 195 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 196 cpu->hash64_opts->slb_size))); 197 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 198 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 199 200 if (ppc_has_spr(cpu, SPR_PURR)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 202 } 203 204 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 205 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 206 segs, sizeof(segs)))); 207 } 208 209 /* 210 * Advertise VMX/VSX (vector extensions) if available 211 * 0 / no property == no vector extensions 212 * 1 == VMX / Altivec available 213 * 2 == VSX available 214 */ 215 if (env->insns_flags & PPC_ALTIVEC) { 216 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 217 218 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 219 } 220 221 /* 222 * Advertise DFP (Decimal Floating Point) if available 223 * 0 / no property == no DFP 224 * 1 == DFP available 225 */ 226 if (env->insns_flags2 & PPC2_DFP) { 227 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 228 } 229 230 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 231 sizeof(page_sizes_prop)); 232 if (page_sizes_prop_size) { 233 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 234 page_sizes_prop, page_sizes_prop_size))); 235 } 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i)); 240 } 241 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 242 servers_prop, sizeof(*servers_prop) * smt_threads))); 243 244 return offset; 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 248 uint32_t nr_threads) 249 { 250 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 251 uint32_t pir = pcc->chip_pir(chip, hwid, 0); 252 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 253 char *name; 254 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 255 uint32_t irange[2], i, rsize; 256 uint64_t *reg; 257 int offset; 258 259 irange[0] = cpu_to_be32(pir); 260 irange[1] = cpu_to_be32(nr_threads); 261 262 rsize = sizeof(uint64_t) * 2 * nr_threads; 263 reg = g_malloc(rsize); 264 for (i = 0; i < nr_threads; i++) { 265 /* We know P8 PIR is linear with thread id */ 266 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 267 reg[i * 2 + 1] = cpu_to_be64(0x1000); 268 } 269 270 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 271 offset = fdt_add_subnode(fdt, 0, name); 272 _FDT(offset); 273 g_free(name); 274 275 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 276 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 277 _FDT((fdt_setprop_string(fdt, offset, "device_type", 278 "PowerPC-External-Interrupt-Presentation"))); 279 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 280 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 281 irange, sizeof(irange)))); 282 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 283 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 284 g_free(reg); 285 } 286 287 /* 288 * Adds a PnvPHB to the chip on P8. 289 * Implemented here, like for defaults PHBs 290 */ 291 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 292 { 293 Pnv8Chip *chip8 = PNV8_CHIP(chip); 294 295 phb->chip = chip; 296 297 chip8->phbs[chip8->num_phbs] = phb; 298 chip8->num_phbs++; 299 return chip; 300 } 301 302 /* 303 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 304 * HTM is always enabled because TCG does implement HTM, it's just a 305 * degenerate implementation. 306 */ 307 static const uint8_t pa_features_207[] = { 24, 0, 308 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 309 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 310 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 311 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 312 313 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 314 { 315 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 316 int i; 317 318 pnv_dt_xscom(chip, fdt, 0, 319 cpu_to_be64(PNV_XSCOM_BASE(chip)), 320 cpu_to_be64(PNV_XSCOM_SIZE), 321 compat, sizeof(compat)); 322 323 for (i = 0; i < chip->nr_cores; i++) { 324 PnvCore *pnv_core = chip->cores[i]; 325 int offset; 326 327 offset = pnv_dt_core(chip, pnv_core, fdt); 328 329 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 330 pa_features_207, sizeof(pa_features_207)))); 331 332 /* Interrupt Control Presenters (ICP). One per core. */ 333 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 334 } 335 336 if (chip->ram_size) { 337 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 338 } 339 } 340 341 /* 342 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 343 */ 344 static const uint8_t pa_features_300[] = { 66, 0, 345 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 346 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 347 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 348 /* 6: DS207 */ 349 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 350 /* 16: Vector */ 351 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 352 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 353 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 354 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 356 /* 32: LE atomic, 34: EBB + ext EBB */ 357 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 358 /* 40: Radix MMU */ 359 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 360 /* 42: PM, 44: PC RA, 46: SC vec'd */ 361 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 362 /* 48: SIMD, 50: QP BFP, 52: String */ 363 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 364 /* 54: DecFP, 56: DecI, 58: SHA */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 366 /* 60: NM atomic, 62: RNG */ 367 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 368 }; 369 370 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 371 { 372 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 373 int i; 374 375 pnv_dt_xscom(chip, fdt, 0, 376 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 377 cpu_to_be64(PNV9_XSCOM_SIZE), 378 compat, sizeof(compat)); 379 380 for (i = 0; i < chip->nr_cores; i++) { 381 PnvCore *pnv_core = chip->cores[i]; 382 int offset; 383 384 offset = pnv_dt_core(chip, pnv_core, fdt); 385 386 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 387 pa_features_300, sizeof(pa_features_300)))); 388 } 389 390 if (chip->ram_size) { 391 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 392 } 393 394 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 395 } 396 397 /* 398 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 399 * always disables copy/paste. 400 */ 401 static const uint8_t pa_features_31[] = { 74, 0, 402 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 403 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 404 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 405 /* 6: DS207 */ 406 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 407 /* 16: Vector */ 408 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 409 /* 18: Vec. Scalar, 20: Vec. XOR */ 410 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 411 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 412 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 413 /* 32: LE atomic, 34: EBB + ext EBB */ 414 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 415 /* 40: Radix MMU */ 416 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 417 /* 42: PM, 44: PC RA, 46: SC vec'd */ 418 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 419 /* 48: SIMD, 50: QP BFP, 52: String */ 420 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 421 /* 54: DecFP, 56: DecI, 58: SHA */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 423 /* 60: NM atomic, 62: RNG */ 424 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 425 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 426 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 427 /* 72: [P]HASHST/[P]HASHCHK */ 428 0x80, 0x00, /* 72 - 73 */ 429 }; 430 431 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 432 { 433 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 434 int i; 435 436 pnv_dt_xscom(chip, fdt, 0, 437 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 438 cpu_to_be64(PNV10_XSCOM_SIZE), 439 compat, sizeof(compat)); 440 441 for (i = 0; i < chip->nr_cores; i++) { 442 PnvCore *pnv_core = chip->cores[i]; 443 int offset; 444 445 offset = pnv_dt_core(chip, pnv_core, fdt); 446 447 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 448 pa_features_31, sizeof(pa_features_31)))); 449 } 450 451 if (chip->ram_size) { 452 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 453 } 454 455 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 456 } 457 458 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 459 { 460 uint32_t io_base = d->ioport_id; 461 uint32_t io_regs[] = { 462 cpu_to_be32(1), 463 cpu_to_be32(io_base), 464 cpu_to_be32(2) 465 }; 466 char *name; 467 int node; 468 469 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 470 node = fdt_add_subnode(fdt, lpc_off, name); 471 _FDT(node); 472 g_free(name); 473 474 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 475 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 476 } 477 478 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 479 { 480 const char compatible[] = "ns16550\0pnpPNP,501"; 481 uint32_t io_base = d->ioport_id; 482 uint32_t io_regs[] = { 483 cpu_to_be32(1), 484 cpu_to_be32(io_base), 485 cpu_to_be32(8) 486 }; 487 uint32_t irq; 488 char *name; 489 int node; 490 491 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 492 493 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 494 node = fdt_add_subnode(fdt, lpc_off, name); 495 _FDT(node); 496 g_free(name); 497 498 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 499 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 500 sizeof(compatible)))); 501 502 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 503 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 504 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 505 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 506 fdt_get_phandle(fdt, lpc_off)))); 507 508 /* This is needed by Linux */ 509 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 510 } 511 512 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 513 { 514 const char compatible[] = "bt\0ipmi-bt"; 515 uint32_t io_base; 516 uint32_t io_regs[] = { 517 cpu_to_be32(1), 518 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 519 cpu_to_be32(3) 520 }; 521 uint32_t irq; 522 char *name; 523 int node; 524 525 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 526 io_regs[1] = cpu_to_be32(io_base); 527 528 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 529 530 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 531 node = fdt_add_subnode(fdt, lpc_off, name); 532 _FDT(node); 533 g_free(name); 534 535 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 536 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 537 sizeof(compatible)))); 538 539 /* Mark it as reserved to avoid Linux trying to claim it */ 540 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 541 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 542 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 543 fdt_get_phandle(fdt, lpc_off)))); 544 } 545 546 typedef struct ForeachPopulateArgs { 547 void *fdt; 548 int offset; 549 } ForeachPopulateArgs; 550 551 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 552 { 553 ForeachPopulateArgs *args = opaque; 554 ISADevice *d = ISA_DEVICE(dev); 555 556 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 557 pnv_dt_rtc(d, args->fdt, args->offset); 558 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 559 pnv_dt_serial(d, args->fdt, args->offset); 560 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 561 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 562 } else { 563 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 564 d->ioport_id); 565 } 566 567 return 0; 568 } 569 570 /* 571 * The default LPC bus of a multichip system is on chip 0. It's 572 * recognized by the firmware (skiboot) using a "primary" property. 573 */ 574 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 575 { 576 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 577 ForeachPopulateArgs args = { 578 .fdt = fdt, 579 .offset = isa_offset, 580 }; 581 uint32_t phandle; 582 583 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 584 585 phandle = qemu_fdt_alloc_phandle(fdt); 586 assert(phandle > 0); 587 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 588 589 /* 590 * ISA devices are not necessarily parented to the ISA bus so we 591 * can not use object_child_foreach() 592 */ 593 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 594 &args); 595 } 596 597 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 598 { 599 int off; 600 601 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 602 off = fdt_add_subnode(fdt, off, "power-mgt"); 603 604 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 605 } 606 607 static void *pnv_dt_create(MachineState *machine) 608 { 609 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 610 PnvMachineState *pnv = PNV_MACHINE(machine); 611 void *fdt; 612 char *buf; 613 int off; 614 int i; 615 616 fdt = g_malloc0(FDT_MAX_SIZE); 617 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 618 619 /* /qemu node */ 620 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 621 622 /* Root node */ 623 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 624 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 625 _FDT((fdt_setprop_string(fdt, 0, "model", 626 "IBM PowerNV (emulated by qemu)"))); 627 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 628 629 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 630 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 631 if (qemu_uuid_set) { 632 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 633 } 634 g_free(buf); 635 636 off = fdt_add_subnode(fdt, 0, "chosen"); 637 if (machine->kernel_cmdline) { 638 _FDT((fdt_setprop_string(fdt, off, "bootargs", 639 machine->kernel_cmdline))); 640 } 641 642 if (pnv->initrd_size) { 643 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 644 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 645 646 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 647 &start_prop, sizeof(start_prop)))); 648 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 649 &end_prop, sizeof(end_prop)))); 650 } 651 652 /* Populate device tree for each chip */ 653 for (i = 0; i < pnv->num_chips; i++) { 654 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 655 } 656 657 /* Populate ISA devices on chip 0 */ 658 pnv_dt_isa(pnv, fdt); 659 660 if (pnv->bmc) { 661 pnv_dt_bmc_sensors(pnv->bmc, fdt); 662 } 663 664 /* Create an extra node for power management on machines that support it */ 665 if (pmc->dt_power_mgt) { 666 pmc->dt_power_mgt(pnv, fdt); 667 } 668 669 return fdt; 670 } 671 672 static void pnv_powerdown_notify(Notifier *n, void *opaque) 673 { 674 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 675 676 if (pnv->bmc) { 677 pnv_bmc_powerdown(pnv->bmc); 678 } 679 } 680 681 static void pnv_reset(MachineState *machine, ShutdownCause reason) 682 { 683 PnvMachineState *pnv = PNV_MACHINE(machine); 684 IPMIBmc *bmc; 685 void *fdt; 686 687 qemu_devices_reset(reason); 688 689 /* 690 * The machine should provide by default an internal BMC simulator. 691 * If not, try to use the BMC device that was provided on the command 692 * line. 693 */ 694 bmc = pnv_bmc_find(&error_fatal); 695 if (!pnv->bmc) { 696 if (!bmc) { 697 if (!qtest_enabled()) { 698 warn_report("machine has no BMC device. Use '-device " 699 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 700 "to define one"); 701 } 702 } else { 703 pnv_bmc_set_pnor(bmc, pnv->pnor); 704 pnv->bmc = bmc; 705 } 706 } 707 708 fdt = pnv_dt_create(machine); 709 710 /* Pack resulting tree */ 711 _FDT((fdt_pack(fdt))); 712 713 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 714 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 715 716 /* 717 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 718 * the existing machine->fdt to avoid leaking it during 719 * a reset. 720 */ 721 g_free(machine->fdt); 722 machine->fdt = fdt; 723 } 724 725 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 726 { 727 Pnv8Chip *chip8 = PNV8_CHIP(chip); 728 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 729 730 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 731 732 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 733 } 734 735 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 736 { 737 Pnv8Chip *chip8 = PNV8_CHIP(chip); 738 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 739 740 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 741 742 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 743 } 744 745 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 746 { 747 Pnv9Chip *chip9 = PNV9_CHIP(chip); 748 qemu_irq irq; 749 750 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 751 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 752 753 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 754 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 755 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 756 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 757 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 758 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 759 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 760 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 761 762 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 763 } 764 765 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 766 { 767 Pnv10Chip *chip10 = PNV10_CHIP(chip); 768 qemu_irq irq; 769 770 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 771 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 772 773 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 774 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 775 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 776 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 777 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 778 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 779 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 780 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 781 782 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 783 } 784 785 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 786 { 787 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 788 } 789 790 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 791 { 792 Pnv8Chip *chip8 = PNV8_CHIP(chip); 793 int i; 794 795 ics_pic_print_info(&chip8->psi.ics, buf); 796 797 for (i = 0; i < chip8->num_phbs; i++) { 798 PnvPHB *phb = chip8->phbs[i]; 799 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 800 801 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 802 ics_pic_print_info(&phb3->lsis, buf); 803 } 804 } 805 806 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 807 { 808 GString *buf = opaque; 809 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 810 811 if (!phb) { 812 return 0; 813 } 814 815 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 816 817 return 0; 818 } 819 820 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 821 { 822 Pnv9Chip *chip9 = PNV9_CHIP(chip); 823 824 pnv_xive_pic_print_info(&chip9->xive, buf); 825 pnv_psi_pic_print_info(&chip9->psi, buf); 826 object_child_foreach_recursive(OBJECT(chip), 827 pnv_chip_power9_pic_print_info_child, buf); 828 } 829 830 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 831 uint32_t core_id) 832 { 833 return PNV_XSCOM_EX_BASE(core_id); 834 } 835 836 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 837 uint32_t core_id) 838 { 839 return PNV9_XSCOM_EC_BASE(core_id); 840 } 841 842 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 843 uint32_t core_id) 844 { 845 return PNV10_XSCOM_EC_BASE(core_id); 846 } 847 848 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 849 { 850 PowerPCCPUClass *ppc_default = 851 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 852 PowerPCCPUClass *ppc = 853 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 854 855 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 856 } 857 858 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 859 { 860 ISADevice *dev = isa_new("isa-ipmi-bt"); 861 862 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 863 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 864 isa_realize_and_unref(dev, bus, &error_fatal); 865 } 866 867 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 868 { 869 Pnv10Chip *chip10 = PNV10_CHIP(chip); 870 871 pnv_xive2_pic_print_info(&chip10->xive, buf); 872 pnv_psi_pic_print_info(&chip10->psi, buf); 873 object_child_foreach_recursive(OBJECT(chip), 874 pnv_chip_power9_pic_print_info_child, buf); 875 } 876 877 /* Always give the first 1GB to chip 0 else we won't boot */ 878 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 879 { 880 MachineState *machine = MACHINE(pnv); 881 uint64_t ram_per_chip; 882 883 assert(machine->ram_size >= 1 * GiB); 884 885 ram_per_chip = machine->ram_size / pnv->num_chips; 886 if (ram_per_chip >= 1 * GiB) { 887 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 888 } 889 890 assert(pnv->num_chips > 1); 891 892 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 893 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 894 } 895 896 static void pnv_init(MachineState *machine) 897 { 898 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 899 PnvMachineState *pnv = PNV_MACHINE(machine); 900 MachineClass *mc = MACHINE_GET_CLASS(machine); 901 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 902 int max_smt_threads = pmc->max_smt_threads; 903 char *fw_filename; 904 long fw_size; 905 uint64_t chip_ram_start = 0; 906 int i; 907 char *chip_typename; 908 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 909 DeviceState *dev; 910 911 if (kvm_enabled()) { 912 error_report("machine %s does not support the KVM accelerator", 913 mc->name); 914 exit(EXIT_FAILURE); 915 } 916 917 /* allocate RAM */ 918 if (machine->ram_size < mc->default_ram_size) { 919 char *sz = size_to_str(mc->default_ram_size); 920 error_report("Invalid RAM size, should be bigger than %s", sz); 921 g_free(sz); 922 exit(EXIT_FAILURE); 923 } 924 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 925 926 /* 927 * Create our simple PNOR device 928 */ 929 dev = qdev_new(TYPE_PNV_PNOR); 930 if (pnor) { 931 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 932 } 933 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 934 pnv->pnor = PNV_PNOR(dev); 935 936 /* load skiboot firmware */ 937 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 938 if (!fw_filename) { 939 error_report("Could not find OPAL firmware '%s'", bios_name); 940 exit(1); 941 } 942 943 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 944 if (fw_size < 0) { 945 error_report("Could not load OPAL firmware '%s'", fw_filename); 946 exit(1); 947 } 948 g_free(fw_filename); 949 950 /* load kernel */ 951 if (machine->kernel_filename) { 952 long kernel_size; 953 954 kernel_size = load_image_targphys(machine->kernel_filename, 955 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 956 if (kernel_size < 0) { 957 error_report("Could not load kernel '%s'", 958 machine->kernel_filename); 959 exit(1); 960 } 961 } 962 963 /* load initrd */ 964 if (machine->initrd_filename) { 965 pnv->initrd_base = INITRD_LOAD_ADDR; 966 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 967 pnv->initrd_base, INITRD_MAX_SIZE); 968 if (pnv->initrd_size < 0) { 969 error_report("Could not load initial ram disk '%s'", 970 machine->initrd_filename); 971 exit(1); 972 } 973 } 974 975 /* MSIs are supported on this platform */ 976 msi_nonbroken = true; 977 978 /* 979 * Check compatibility of the specified CPU with the machine 980 * default. 981 */ 982 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 983 error_report("invalid CPU model '%s' for %s machine", 984 machine->cpu_type, mc->name); 985 exit(1); 986 } 987 988 /* Create the processor chips */ 989 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 990 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 991 i, machine->cpu_type); 992 if (!object_class_by_name(chip_typename)) { 993 error_report("invalid chip model '%.*s' for %s machine", 994 i, machine->cpu_type, mc->name); 995 exit(1); 996 } 997 998 pnv->num_chips = 999 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1000 1001 if (machine->smp.threads > max_smt_threads) { 1002 error_report("Cannot support more than %d threads/core " 1003 "on %s machine", max_smt_threads, mc->desc); 1004 exit(1); 1005 } 1006 1007 if (!is_power_of_2(machine->smp.threads)) { 1008 error_report("Cannot support %d threads/core on a powernv" 1009 "machine because it must be a power of 2", 1010 machine->smp.threads); 1011 exit(1); 1012 } 1013 1014 /* 1015 * TODO: should we decide on how many chips we can create based 1016 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1017 */ 1018 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1019 error_report("invalid number of chips: '%d'", pnv->num_chips); 1020 error_printf( 1021 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1022 exit(1); 1023 } 1024 1025 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1026 for (i = 0; i < pnv->num_chips; i++) { 1027 char chip_name[32]; 1028 Object *chip = OBJECT(qdev_new(chip_typename)); 1029 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1030 1031 pnv->chips[i] = PNV_CHIP(chip); 1032 1033 /* Distribute RAM among the chips */ 1034 object_property_set_int(chip, "ram-start", chip_ram_start, 1035 &error_fatal); 1036 object_property_set_int(chip, "ram-size", chip_ram_size, 1037 &error_fatal); 1038 chip_ram_start += chip_ram_size; 1039 1040 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1041 object_property_add_child(OBJECT(pnv), chip_name, chip); 1042 object_property_set_int(chip, "chip-id", i, &error_fatal); 1043 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1044 &error_fatal); 1045 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1046 &error_fatal); 1047 /* 1048 * The POWER8 machine use the XICS interrupt interface. 1049 * Propagate the XICS fabric to the chip and its controllers. 1050 */ 1051 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1052 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1053 } 1054 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1055 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1056 &error_abort); 1057 } 1058 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1059 } 1060 g_free(chip_typename); 1061 1062 /* Instantiate ISA bus on chip 0 */ 1063 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1064 1065 /* Create serial port */ 1066 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1067 1068 /* Create an RTC ISA device too */ 1069 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1070 1071 /* 1072 * Create the machine BMC simulator and the IPMI BT device for 1073 * communication with the BMC 1074 */ 1075 if (defaults_enabled()) { 1076 pnv->bmc = pnv_bmc_create(pnv->pnor); 1077 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1078 } 1079 1080 /* 1081 * The PNOR is mapped on the LPC FW address space by the BMC. 1082 * Since we can not reach the remote BMC machine with LPC memops, 1083 * map it always for now. 1084 */ 1085 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1086 &pnv->pnor->mmio); 1087 1088 /* 1089 * OpenPOWER systems use a IPMI SEL Event message to notify the 1090 * host to powerdown 1091 */ 1092 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1093 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1094 1095 /* 1096 * Create/Connect any machine-specific I2C devices 1097 */ 1098 if (pmc->i2c_init) { 1099 pmc->i2c_init(pnv); 1100 } 1101 } 1102 1103 /* 1104 * 0:21 Reserved - Read as zeros 1105 * 22:24 Chip ID 1106 * 25:28 Core number 1107 * 29:31 Thread ID 1108 */ 1109 static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, 1110 uint32_t thread_id) 1111 { 1112 return (chip->chip_id << 7) | (core_id << 3) | thread_id; 1113 } 1114 1115 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1116 Error **errp) 1117 { 1118 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1119 Error *local_err = NULL; 1120 Object *obj; 1121 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1122 1123 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1124 if (local_err) { 1125 error_propagate(errp, local_err); 1126 return; 1127 } 1128 1129 pnv_cpu->intc = obj; 1130 } 1131 1132 1133 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1134 { 1135 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1136 1137 icp_reset(ICP(pnv_cpu->intc)); 1138 } 1139 1140 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1141 { 1142 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1143 1144 icp_destroy(ICP(pnv_cpu->intc)); 1145 pnv_cpu->intc = NULL; 1146 } 1147 1148 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1149 GString *buf) 1150 { 1151 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1152 } 1153 1154 /* 1155 * 0:48 Reserved - Read as zeroes 1156 * 49:52 Node ID 1157 * 53:55 Chip ID 1158 * 56 Reserved - Read as zero 1159 * 57:61 Core number 1160 * 62:63 Thread ID 1161 * 1162 * We only care about the lower bits. uint32_t is fine for the moment. 1163 */ 1164 static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, 1165 uint32_t thread_id) 1166 { 1167 if (chip->nr_threads == 8) { 1168 return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) | 1169 (thread_id >> 1); 1170 } else { 1171 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1172 } 1173 } 1174 1175 /* 1176 * 0:48 Reserved - Read as zeroes 1177 * 49:52 Node ID 1178 * 53:55 Chip ID 1179 * 56 Reserved - Read as zero 1180 * 57:59 Quad ID 1181 * 60 Core Chiplet Pair ID 1182 * 61:63 Thread/Core Chiplet ID t0-t2 1183 * 1184 * We only care about the lower bits. uint32_t is fine for the moment. 1185 */ 1186 static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, 1187 uint32_t thread_id) 1188 { 1189 if (chip->nr_threads == 8) { 1190 return (chip->chip_id << 8) | ((core_id / 4) << 4) | 1191 ((core_id % 2) << 3) | thread_id; 1192 } else { 1193 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1194 } 1195 } 1196 1197 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1198 Error **errp) 1199 { 1200 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1201 Error *local_err = NULL; 1202 Object *obj; 1203 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1204 1205 /* 1206 * The core creates its interrupt presenter but the XIVE interrupt 1207 * controller object is initialized afterwards. Hopefully, it's 1208 * only used at runtime. 1209 */ 1210 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1211 &local_err); 1212 if (local_err) { 1213 error_propagate(errp, local_err); 1214 return; 1215 } 1216 1217 pnv_cpu->intc = obj; 1218 } 1219 1220 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1221 { 1222 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1223 1224 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1225 } 1226 1227 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1228 { 1229 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1230 1231 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1232 pnv_cpu->intc = NULL; 1233 } 1234 1235 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1236 GString *buf) 1237 { 1238 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1239 } 1240 1241 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1242 Error **errp) 1243 { 1244 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1245 Error *local_err = NULL; 1246 Object *obj; 1247 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1248 1249 /* 1250 * The core creates its interrupt presenter but the XIVE2 interrupt 1251 * controller object is initialized afterwards. Hopefully, it's 1252 * only used at runtime. 1253 */ 1254 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1255 &local_err); 1256 if (local_err) { 1257 error_propagate(errp, local_err); 1258 return; 1259 } 1260 1261 pnv_cpu->intc = obj; 1262 } 1263 1264 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1265 { 1266 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1267 1268 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1269 } 1270 1271 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1272 { 1273 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1274 1275 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1276 pnv_cpu->intc = NULL; 1277 } 1278 1279 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1280 GString *buf) 1281 { 1282 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1283 } 1284 1285 /* 1286 * Allowed core identifiers on a POWER8 Processor Chip : 1287 * 1288 * <EX0 reserved> 1289 * EX1 - Venice only 1290 * EX2 - Venice only 1291 * EX3 - Venice only 1292 * EX4 1293 * EX5 1294 * EX6 1295 * <EX7,8 reserved> <reserved> 1296 * EX9 - Venice only 1297 * EX10 - Venice only 1298 * EX11 - Venice only 1299 * EX12 1300 * EX13 1301 * EX14 1302 * <EX15 reserved> 1303 */ 1304 #define POWER8E_CORE_MASK (0x7070ull) 1305 #define POWER8_CORE_MASK (0x7e7eull) 1306 1307 /* 1308 * POWER9 has 24 cores, ids starting at 0x0 1309 */ 1310 #define POWER9_CORE_MASK (0xffffffffffffffull) 1311 1312 1313 #define POWER10_CORE_MASK (0xffffffffffffffull) 1314 1315 static void pnv_chip_power8_instance_init(Object *obj) 1316 { 1317 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1318 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1319 int i; 1320 1321 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1322 (Object **)&chip8->xics, 1323 object_property_allow_set_link, 1324 OBJ_PROP_LINK_STRONG); 1325 1326 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1327 1328 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1329 1330 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1331 1332 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1333 1334 if (defaults_enabled()) { 1335 chip8->num_phbs = pcc->num_phbs; 1336 1337 for (i = 0; i < chip8->num_phbs; i++) { 1338 Object *phb = object_new(TYPE_PNV_PHB); 1339 1340 /* 1341 * We need the chip to parent the PHB to allow the DT 1342 * to build correctly (via pnv_xscom_dt()). 1343 * 1344 * TODO: the PHB should be parented by a PEC device that, at 1345 * this moment, is not modelled powernv8/phb3. 1346 */ 1347 object_property_add_child(obj, "phb[*]", phb); 1348 chip8->phbs[i] = PNV_PHB(phb); 1349 } 1350 } 1351 1352 } 1353 1354 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1355 { 1356 PnvChip *chip = PNV_CHIP(chip8); 1357 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1358 int i, j; 1359 char *name; 1360 1361 name = g_strdup_printf("icp-%x", chip->chip_id); 1362 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1363 g_free(name); 1364 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1365 &chip8->icp_mmio); 1366 1367 /* Map the ICP registers for each thread */ 1368 for (i = 0; i < chip->nr_cores; i++) { 1369 PnvCore *pnv_core = chip->cores[i]; 1370 int core_hwid = CPU_CORE(pnv_core)->core_id; 1371 1372 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1373 uint32_t pir = pcc->chip_pir(chip, core_hwid, j); 1374 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1375 1376 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1377 &icp->mmio); 1378 } 1379 } 1380 } 1381 1382 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1383 { 1384 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1385 PnvChip *chip = PNV_CHIP(dev); 1386 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1387 Pnv8Psi *psi8 = &chip8->psi; 1388 Error *local_err = NULL; 1389 int i; 1390 1391 assert(chip8->xics); 1392 1393 /* XSCOM bridge is first */ 1394 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1395 1396 pcc->parent_realize(dev, &local_err); 1397 if (local_err) { 1398 error_propagate(errp, local_err); 1399 return; 1400 } 1401 1402 /* Processor Service Interface (PSI) Host Bridge */ 1403 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1404 &error_fatal); 1405 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1406 OBJECT(chip8->xics), &error_abort); 1407 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1408 return; 1409 } 1410 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1411 &PNV_PSI(psi8)->xscom_regs); 1412 1413 /* Create LPC controller */ 1414 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1415 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1416 1417 chip->fw_mr = &chip8->lpc.isa_fw; 1418 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1419 (uint64_t) PNV_XSCOM_BASE(chip), 1420 PNV_XSCOM_LPC_BASE); 1421 1422 /* 1423 * Interrupt Management Area. This is the memory region holding 1424 * all the Interrupt Control Presenter (ICP) registers 1425 */ 1426 pnv_chip_icp_realize(chip8, &local_err); 1427 if (local_err) { 1428 error_propagate(errp, local_err); 1429 return; 1430 } 1431 1432 /* Create the simplified OCC model */ 1433 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1434 return; 1435 } 1436 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1437 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1438 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1439 1440 /* OCC SRAM model */ 1441 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1442 &chip8->occ.sram_regs); 1443 1444 /* HOMER */ 1445 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1446 &error_abort); 1447 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1448 return; 1449 } 1450 /* Homer Xscom region */ 1451 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1452 1453 /* Homer mmio region */ 1454 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1455 &chip8->homer.regs); 1456 1457 /* PHB controllers */ 1458 for (i = 0; i < chip8->num_phbs; i++) { 1459 PnvPHB *phb = chip8->phbs[i]; 1460 1461 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1462 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1463 &error_fatal); 1464 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1465 &error_fatal); 1466 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1467 return; 1468 } 1469 } 1470 } 1471 1472 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1473 { 1474 addr &= (PNV_XSCOM_SIZE - 1); 1475 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1476 } 1477 1478 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1479 { 1480 DeviceClass *dc = DEVICE_CLASS(klass); 1481 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1482 1483 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1484 k->cores_mask = POWER8E_CORE_MASK; 1485 k->num_phbs = 3; 1486 k->chip_pir = pnv_chip_pir_p8; 1487 k->intc_create = pnv_chip_power8_intc_create; 1488 k->intc_reset = pnv_chip_power8_intc_reset; 1489 k->intc_destroy = pnv_chip_power8_intc_destroy; 1490 k->intc_print_info = pnv_chip_power8_intc_print_info; 1491 k->isa_create = pnv_chip_power8_isa_create; 1492 k->dt_populate = pnv_chip_power8_dt_populate; 1493 k->pic_print_info = pnv_chip_power8_pic_print_info; 1494 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1495 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1496 dc->desc = "PowerNV Chip POWER8E"; 1497 1498 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1499 &k->parent_realize); 1500 } 1501 1502 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1503 { 1504 DeviceClass *dc = DEVICE_CLASS(klass); 1505 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1506 1507 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1508 k->cores_mask = POWER8_CORE_MASK; 1509 k->num_phbs = 3; 1510 k->chip_pir = pnv_chip_pir_p8; 1511 k->intc_create = pnv_chip_power8_intc_create; 1512 k->intc_reset = pnv_chip_power8_intc_reset; 1513 k->intc_destroy = pnv_chip_power8_intc_destroy; 1514 k->intc_print_info = pnv_chip_power8_intc_print_info; 1515 k->isa_create = pnv_chip_power8_isa_create; 1516 k->dt_populate = pnv_chip_power8_dt_populate; 1517 k->pic_print_info = pnv_chip_power8_pic_print_info; 1518 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1519 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1520 dc->desc = "PowerNV Chip POWER8"; 1521 1522 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1523 &k->parent_realize); 1524 } 1525 1526 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1527 { 1528 DeviceClass *dc = DEVICE_CLASS(klass); 1529 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1530 1531 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1532 k->cores_mask = POWER8_CORE_MASK; 1533 k->num_phbs = 4; 1534 k->chip_pir = pnv_chip_pir_p8; 1535 k->intc_create = pnv_chip_power8_intc_create; 1536 k->intc_reset = pnv_chip_power8_intc_reset; 1537 k->intc_destroy = pnv_chip_power8_intc_destroy; 1538 k->intc_print_info = pnv_chip_power8_intc_print_info; 1539 k->isa_create = pnv_chip_power8nvl_isa_create; 1540 k->dt_populate = pnv_chip_power8_dt_populate; 1541 k->pic_print_info = pnv_chip_power8_pic_print_info; 1542 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1543 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1544 dc->desc = "PowerNV Chip POWER8NVL"; 1545 1546 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1547 &k->parent_realize); 1548 } 1549 1550 static void pnv_chip_power9_instance_init(Object *obj) 1551 { 1552 PnvChip *chip = PNV_CHIP(obj); 1553 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1554 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1555 int i; 1556 1557 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1558 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1559 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1560 "xive-fabric"); 1561 1562 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1563 1564 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1565 1566 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1567 1568 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1569 1570 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1571 1572 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1573 1574 /* Number of PECs is the chip default */ 1575 chip->num_pecs = pcc->num_pecs; 1576 1577 for (i = 0; i < chip->num_pecs; i++) { 1578 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1579 TYPE_PNV_PHB4_PEC); 1580 } 1581 1582 for (i = 0; i < pcc->i2c_num_engines; i++) { 1583 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1584 } 1585 } 1586 1587 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1588 PnvCore *pnv_core, 1589 const char *type) 1590 { 1591 char eq_name[32]; 1592 int core_id = CPU_CORE(pnv_core)->core_id; 1593 1594 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1595 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1596 sizeof(*eq), type, 1597 &error_fatal, NULL); 1598 1599 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1600 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1601 } 1602 1603 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1604 { 1605 PnvChip *chip = PNV_CHIP(chip9); 1606 int i; 1607 1608 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1609 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1610 1611 for (i = 0; i < chip9->nr_quads; i++) { 1612 PnvQuad *eq = &chip9->quads[i]; 1613 1614 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1615 PNV_QUAD_TYPE_NAME("power9")); 1616 1617 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1618 &eq->xscom_regs); 1619 } 1620 } 1621 1622 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1623 { 1624 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1625 int i; 1626 1627 for (i = 0; i < chip->num_pecs; i++) { 1628 PnvPhb4PecState *pec = &chip9->pecs[i]; 1629 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1630 uint32_t pec_nest_base; 1631 uint32_t pec_pci_base; 1632 1633 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1634 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1635 &error_fatal); 1636 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1637 &error_fatal); 1638 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1639 return; 1640 } 1641 1642 pec_nest_base = pecc->xscom_nest_base(pec); 1643 pec_pci_base = pecc->xscom_pci_base(pec); 1644 1645 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1646 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1647 } 1648 } 1649 1650 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1651 { 1652 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1653 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1654 PnvChip *chip = PNV_CHIP(dev); 1655 Pnv9Psi *psi9 = &chip9->psi; 1656 Error *local_err = NULL; 1657 int i; 1658 1659 /* XSCOM bridge is first */ 1660 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1661 1662 pcc->parent_realize(dev, &local_err); 1663 if (local_err) { 1664 error_propagate(errp, local_err); 1665 return; 1666 } 1667 1668 /* ADU */ 1669 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1670 &error_abort); 1671 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1672 return; 1673 } 1674 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1675 &chip9->adu.xscom_regs); 1676 1677 pnv_chip_quad_realize(chip9, &local_err); 1678 if (local_err) { 1679 error_propagate(errp, local_err); 1680 return; 1681 } 1682 1683 /* XIVE interrupt controller (POWER9) */ 1684 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1685 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1686 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1687 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1688 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1689 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1690 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1691 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1692 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1693 &error_abort); 1694 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1695 return; 1696 } 1697 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1698 &chip9->xive.xscom_regs); 1699 1700 /* Processor Service Interface (PSI) Host Bridge */ 1701 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1702 &error_fatal); 1703 /* This is the only device with 4k ESB pages */ 1704 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1705 &error_fatal); 1706 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1707 return; 1708 } 1709 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1710 &PNV_PSI(psi9)->xscom_regs); 1711 1712 /* LPC */ 1713 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1714 return; 1715 } 1716 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1717 &chip9->lpc.xscom_regs); 1718 1719 chip->fw_mr = &chip9->lpc.isa_fw; 1720 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1721 (uint64_t) PNV9_LPCM_BASE(chip)); 1722 1723 /* ChipTOD */ 1724 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1725 chip->chip_id == 0, &error_abort); 1726 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1727 chip->chip_id == 1, &error_abort); 1728 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1729 &error_abort); 1730 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1731 return; 1732 } 1733 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1734 &chip9->chiptod.xscom_regs); 1735 1736 /* Create the simplified OCC model */ 1737 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1738 return; 1739 } 1740 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1741 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1742 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1743 1744 /* OCC SRAM model */ 1745 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1746 &chip9->occ.sram_regs); 1747 1748 /* SBE */ 1749 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1750 return; 1751 } 1752 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1753 &chip9->sbe.xscom_ctrl_regs); 1754 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1755 &chip9->sbe.xscom_mbox_regs); 1756 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1757 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1758 1759 /* HOMER */ 1760 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1761 &error_abort); 1762 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1763 return; 1764 } 1765 /* Homer Xscom region */ 1766 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1767 1768 /* Homer mmio region */ 1769 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1770 &chip9->homer.regs); 1771 1772 /* PEC PHBs */ 1773 pnv_chip_power9_pec_realize(chip, &local_err); 1774 if (local_err) { 1775 error_propagate(errp, local_err); 1776 return; 1777 } 1778 1779 /* 1780 * I2C 1781 */ 1782 for (i = 0; i < pcc->i2c_num_engines; i++) { 1783 Object *obj = OBJECT(&chip9->i2c[i]); 1784 1785 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1786 object_property_set_int(obj, "num-busses", 1787 pcc->i2c_ports_per_engine[i], 1788 &error_fatal); 1789 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1790 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1791 return; 1792 } 1793 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1794 (chip9->i2c[i].engine - 1) * 1795 PNV9_XSCOM_I2CM_SIZE, 1796 &chip9->i2c[i].xscom_regs); 1797 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1798 qdev_get_gpio_in(DEVICE(psi9), 1799 PSIHB9_IRQ_SBE_I2C)); 1800 } 1801 } 1802 1803 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1804 { 1805 addr &= (PNV9_XSCOM_SIZE - 1); 1806 return addr >> 3; 1807 } 1808 1809 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1810 { 1811 DeviceClass *dc = DEVICE_CLASS(klass); 1812 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1813 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1814 1815 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1816 k->cores_mask = POWER9_CORE_MASK; 1817 k->chip_pir = pnv_chip_pir_p9; 1818 k->intc_create = pnv_chip_power9_intc_create; 1819 k->intc_reset = pnv_chip_power9_intc_reset; 1820 k->intc_destroy = pnv_chip_power9_intc_destroy; 1821 k->intc_print_info = pnv_chip_power9_intc_print_info; 1822 k->isa_create = pnv_chip_power9_isa_create; 1823 k->dt_populate = pnv_chip_power9_dt_populate; 1824 k->pic_print_info = pnv_chip_power9_pic_print_info; 1825 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1826 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1827 dc->desc = "PowerNV Chip POWER9"; 1828 k->num_pecs = PNV9_CHIP_MAX_PEC; 1829 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1830 k->i2c_ports_per_engine = i2c_ports_per_engine; 1831 1832 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1833 &k->parent_realize); 1834 } 1835 1836 static void pnv_chip_power10_instance_init(Object *obj) 1837 { 1838 PnvChip *chip = PNV_CHIP(obj); 1839 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1840 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1841 int i; 1842 1843 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 1844 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1845 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1846 "xive-fabric"); 1847 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1848 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1849 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1850 TYPE_PNV10_CHIPTOD); 1851 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1852 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1853 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1854 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1855 TYPE_PNV_N1_CHIPLET); 1856 1857 chip->num_pecs = pcc->num_pecs; 1858 1859 for (i = 0; i < chip->num_pecs; i++) { 1860 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1861 TYPE_PNV_PHB5_PEC); 1862 } 1863 1864 for (i = 0; i < pcc->i2c_num_engines; i++) { 1865 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1866 } 1867 } 1868 1869 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1870 { 1871 PnvChip *chip = PNV_CHIP(chip10); 1872 int i; 1873 1874 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1875 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1876 1877 for (i = 0; i < chip10->nr_quads; i++) { 1878 PnvQuad *eq = &chip10->quads[i]; 1879 1880 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1881 PNV_QUAD_TYPE_NAME("power10")); 1882 1883 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1884 &eq->xscom_regs); 1885 1886 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1887 &eq->xscom_qme_regs); 1888 } 1889 } 1890 1891 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1892 { 1893 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1894 int i; 1895 1896 for (i = 0; i < chip->num_pecs; i++) { 1897 PnvPhb4PecState *pec = &chip10->pecs[i]; 1898 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1899 uint32_t pec_nest_base; 1900 uint32_t pec_pci_base; 1901 1902 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1903 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1904 &error_fatal); 1905 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1906 &error_fatal); 1907 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1908 return; 1909 } 1910 1911 pec_nest_base = pecc->xscom_nest_base(pec); 1912 pec_pci_base = pecc->xscom_pci_base(pec); 1913 1914 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1915 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1916 } 1917 } 1918 1919 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1920 { 1921 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1922 PnvChip *chip = PNV_CHIP(dev); 1923 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1924 Error *local_err = NULL; 1925 int i; 1926 1927 /* XSCOM bridge is first */ 1928 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1929 1930 pcc->parent_realize(dev, &local_err); 1931 if (local_err) { 1932 error_propagate(errp, local_err); 1933 return; 1934 } 1935 1936 /* ADU */ 1937 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 1938 &error_abort); 1939 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 1940 return; 1941 } 1942 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 1943 &chip10->adu.xscom_regs); 1944 1945 pnv_chip_power10_quad_realize(chip10, &local_err); 1946 if (local_err) { 1947 error_propagate(errp, local_err); 1948 return; 1949 } 1950 1951 /* XIVE2 interrupt controller (POWER10) */ 1952 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1953 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1954 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1955 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1956 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1957 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1958 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1959 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1960 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1961 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1962 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1963 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1964 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1965 &error_abort); 1966 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1967 return; 1968 } 1969 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1970 &chip10->xive.xscom_regs); 1971 1972 /* Processor Service Interface (PSI) Host Bridge */ 1973 object_property_set_int(OBJECT(&chip10->psi), "bar", 1974 PNV10_PSIHB_BASE(chip), &error_fatal); 1975 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1976 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1977 &error_fatal); 1978 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1979 return; 1980 } 1981 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1982 &PNV_PSI(&chip10->psi)->xscom_regs); 1983 1984 /* LPC */ 1985 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1986 return; 1987 } 1988 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1989 &chip10->lpc.xscom_regs); 1990 1991 chip->fw_mr = &chip10->lpc.isa_fw; 1992 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1993 (uint64_t) PNV10_LPCM_BASE(chip)); 1994 1995 /* ChipTOD */ 1996 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1997 chip->chip_id == 0, &error_abort); 1998 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1999 chip->chip_id == 1, &error_abort); 2000 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2001 &error_abort); 2002 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2003 return; 2004 } 2005 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2006 &chip10->chiptod.xscom_regs); 2007 2008 /* Create the simplified OCC model */ 2009 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2010 return; 2011 } 2012 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2013 &chip10->occ.xscom_regs); 2014 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2015 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2016 2017 /* OCC SRAM model */ 2018 memory_region_add_subregion(get_system_memory(), 2019 PNV10_OCC_SENSOR_BASE(chip), 2020 &chip10->occ.sram_regs); 2021 2022 /* SBE */ 2023 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2024 return; 2025 } 2026 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2027 &chip10->sbe.xscom_ctrl_regs); 2028 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2029 &chip10->sbe.xscom_mbox_regs); 2030 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2031 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2032 2033 /* HOMER */ 2034 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2035 &error_abort); 2036 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2037 return; 2038 } 2039 /* Homer Xscom region */ 2040 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2041 &chip10->homer.pba_regs); 2042 2043 /* Homer mmio region */ 2044 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2045 &chip10->homer.regs); 2046 2047 /* N1 chiplet */ 2048 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2049 return; 2050 } 2051 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2052 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2053 2054 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2055 &chip10->n1_chiplet.xscom_pb_eq_mr); 2056 2057 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2058 &chip10->n1_chiplet.xscom_pb_es_mr); 2059 2060 /* PHBs */ 2061 pnv_chip_power10_phb_realize(chip, &local_err); 2062 if (local_err) { 2063 error_propagate(errp, local_err); 2064 return; 2065 } 2066 2067 2068 /* 2069 * I2C 2070 */ 2071 for (i = 0; i < pcc->i2c_num_engines; i++) { 2072 Object *obj = OBJECT(&chip10->i2c[i]); 2073 2074 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2075 object_property_set_int(obj, "num-busses", 2076 pcc->i2c_ports_per_engine[i], 2077 &error_fatal); 2078 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2079 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2080 return; 2081 } 2082 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2083 (chip10->i2c[i].engine - 1) * 2084 PNV10_XSCOM_I2CM_SIZE, 2085 &chip10->i2c[i].xscom_regs); 2086 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2087 qdev_get_gpio_in(DEVICE(&chip10->psi), 2088 PSIHB9_IRQ_SBE_I2C)); 2089 } 2090 2091 } 2092 2093 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2094 { 2095 int i; 2096 for (i = 0; i < pnv->num_chips; i++) { 2097 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2098 2099 /* 2100 * Add a PCA9552 I2C device for PCIe hotplug control 2101 * to engine 2, bus 1, address 0x63 2102 */ 2103 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2104 "pca9552", 0x63); 2105 2106 /* 2107 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2108 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2109 * after hypervisor code sets a SLOTx_EN pin high. 2110 */ 2111 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2112 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2113 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2114 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2115 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2116 2117 /* 2118 * Add a PCA9554 I2C device for cable card presence detection 2119 * to engine 2, bus 1, address 0x25 2120 */ 2121 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2122 } 2123 } 2124 2125 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2126 { 2127 addr &= (PNV10_XSCOM_SIZE - 1); 2128 return addr >> 3; 2129 } 2130 2131 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2132 { 2133 DeviceClass *dc = DEVICE_CLASS(klass); 2134 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2135 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2136 2137 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2138 k->cores_mask = POWER10_CORE_MASK; 2139 k->chip_pir = pnv_chip_pir_p10; 2140 k->intc_create = pnv_chip_power10_intc_create; 2141 k->intc_reset = pnv_chip_power10_intc_reset; 2142 k->intc_destroy = pnv_chip_power10_intc_destroy; 2143 k->intc_print_info = pnv_chip_power10_intc_print_info; 2144 k->isa_create = pnv_chip_power10_isa_create; 2145 k->dt_populate = pnv_chip_power10_dt_populate; 2146 k->pic_print_info = pnv_chip_power10_pic_print_info; 2147 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2148 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2149 dc->desc = "PowerNV Chip POWER10"; 2150 k->num_pecs = PNV10_CHIP_MAX_PEC; 2151 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2152 k->i2c_ports_per_engine = i2c_ports_per_engine; 2153 2154 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2155 &k->parent_realize); 2156 } 2157 2158 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2159 { 2160 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2161 int cores_max; 2162 2163 /* 2164 * No custom mask for this chip, let's use the default one from * 2165 * the chip class 2166 */ 2167 if (!chip->cores_mask) { 2168 chip->cores_mask = pcc->cores_mask; 2169 } 2170 2171 /* filter alien core ids ! some are reserved */ 2172 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2173 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2174 chip->cores_mask); 2175 return; 2176 } 2177 chip->cores_mask &= pcc->cores_mask; 2178 2179 /* now that we have a sane layout, let check the number of cores */ 2180 cores_max = ctpop64(chip->cores_mask); 2181 if (chip->nr_cores > cores_max) { 2182 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2183 cores_max); 2184 return; 2185 } 2186 } 2187 2188 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2189 { 2190 Error *error = NULL; 2191 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2192 const char *typename = pnv_chip_core_typename(chip); 2193 int i, core_hwid; 2194 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2195 2196 if (!object_class_by_name(typename)) { 2197 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2198 return; 2199 } 2200 2201 /* Cores */ 2202 pnv_chip_core_sanitize(chip, &error); 2203 if (error) { 2204 error_propagate(errp, error); 2205 return; 2206 } 2207 2208 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2209 2210 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2211 && (i < chip->nr_cores); core_hwid++) { 2212 char core_name[32]; 2213 PnvCore *pnv_core; 2214 uint64_t xscom_core_base; 2215 2216 if (!(chip->cores_mask & (1ull << core_hwid))) { 2217 continue; 2218 } 2219 2220 pnv_core = PNV_CORE(object_new(typename)); 2221 2222 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2223 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2224 chip->cores[i] = pnv_core; 2225 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2226 chip->nr_threads, &error_fatal); 2227 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2228 core_hwid, &error_fatal); 2229 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2230 &error_fatal); 2231 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2232 &error_fatal); 2233 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2234 &error_abort); 2235 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2236 2237 /* Each core has an XSCOM MMIO region */ 2238 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2239 2240 pnv_xscom_add_subregion(chip, xscom_core_base, 2241 &pnv_core->xscom_regs); 2242 i++; 2243 } 2244 } 2245 2246 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2247 { 2248 PnvChip *chip = PNV_CHIP(dev); 2249 Error *error = NULL; 2250 2251 /* Cores */ 2252 pnv_chip_core_realize(chip, &error); 2253 if (error) { 2254 error_propagate(errp, error); 2255 return; 2256 } 2257 } 2258 2259 static Property pnv_chip_properties[] = { 2260 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2261 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2262 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2263 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2264 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2265 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2266 DEFINE_PROP_END_OF_LIST(), 2267 }; 2268 2269 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2270 { 2271 DeviceClass *dc = DEVICE_CLASS(klass); 2272 2273 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2274 dc->realize = pnv_chip_realize; 2275 device_class_set_props(dc, pnv_chip_properties); 2276 dc->desc = "PowerNV Chip"; 2277 } 2278 2279 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2280 { 2281 int i; 2282 2283 for (i = 0; i < chip->nr_cores; i++) { 2284 PnvCore *pc = chip->cores[i]; 2285 CPUCore *cc = CPU_CORE(pc); 2286 2287 if (cc->core_id == core_id) { 2288 return pc; 2289 } 2290 } 2291 return NULL; 2292 } 2293 2294 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2295 { 2296 int i, j; 2297 2298 for (i = 0; i < chip->nr_cores; i++) { 2299 PnvCore *pc = chip->cores[i]; 2300 CPUCore *cc = CPU_CORE(pc); 2301 2302 for (j = 0; j < cc->nr_threads; j++) { 2303 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2304 return pc->threads[j]; 2305 } 2306 } 2307 } 2308 return NULL; 2309 } 2310 2311 static void pnv_chip_foreach_cpu(PnvChip *chip, 2312 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2313 void *opaque) 2314 { 2315 int i, j; 2316 2317 for (i = 0; i < chip->nr_cores; i++) { 2318 PnvCore *pc = chip->cores[i]; 2319 2320 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2321 fn(chip, pc->threads[j], opaque); 2322 } 2323 } 2324 } 2325 2326 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2327 { 2328 PnvMachineState *pnv = PNV_MACHINE(xi); 2329 int i, j; 2330 2331 for (i = 0; i < pnv->num_chips; i++) { 2332 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2333 2334 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2335 return &chip8->psi.ics; 2336 } 2337 2338 for (j = 0; j < chip8->num_phbs; j++) { 2339 PnvPHB *phb = chip8->phbs[j]; 2340 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2341 2342 if (ics_valid_irq(&phb3->lsis, irq)) { 2343 return &phb3->lsis; 2344 } 2345 2346 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2347 return ICS(&phb3->msis); 2348 } 2349 } 2350 } 2351 return NULL; 2352 } 2353 2354 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2355 { 2356 int i; 2357 2358 for (i = 0; i < pnv->num_chips; i++) { 2359 PnvChip *chip = pnv->chips[i]; 2360 if (chip->chip_id == chip_id) { 2361 return chip; 2362 } 2363 } 2364 return NULL; 2365 } 2366 2367 static void pnv_ics_resend(XICSFabric *xi) 2368 { 2369 PnvMachineState *pnv = PNV_MACHINE(xi); 2370 int i, j; 2371 2372 for (i = 0; i < pnv->num_chips; i++) { 2373 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2374 2375 ics_resend(&chip8->psi.ics); 2376 2377 for (j = 0; j < chip8->num_phbs; j++) { 2378 PnvPHB *phb = chip8->phbs[j]; 2379 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2380 2381 ics_resend(&phb3->lsis); 2382 ics_resend(ICS(&phb3->msis)); 2383 } 2384 } 2385 } 2386 2387 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2388 { 2389 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2390 2391 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2392 } 2393 2394 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2395 void *opaque) 2396 { 2397 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2398 } 2399 2400 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2401 { 2402 PnvMachineState *pnv = PNV_MACHINE(obj); 2403 int i; 2404 2405 for (i = 0; i < pnv->num_chips; i++) { 2406 PnvChip *chip = pnv->chips[i]; 2407 2408 /* First CPU presenters */ 2409 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2410 2411 /* Then other devices, PHB, PSI, XIVE */ 2412 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2413 } 2414 } 2415 2416 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2417 uint8_t nvt_blk, uint32_t nvt_idx, 2418 bool cam_ignore, uint8_t priority, 2419 uint32_t logic_serv, 2420 XiveTCTXMatch *match) 2421 { 2422 PnvMachineState *pnv = PNV_MACHINE(xfb); 2423 int total_count = 0; 2424 int i; 2425 2426 for (i = 0; i < pnv->num_chips; i++) { 2427 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2428 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2429 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2430 int count; 2431 2432 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2433 priority, logic_serv, match); 2434 2435 if (count < 0) { 2436 return count; 2437 } 2438 2439 total_count += count; 2440 } 2441 2442 return total_count; 2443 } 2444 2445 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2446 uint8_t nvt_blk, uint32_t nvt_idx, 2447 bool cam_ignore, uint8_t priority, 2448 uint32_t logic_serv, 2449 XiveTCTXMatch *match) 2450 { 2451 PnvMachineState *pnv = PNV_MACHINE(xfb); 2452 int total_count = 0; 2453 int i; 2454 2455 for (i = 0; i < pnv->num_chips; i++) { 2456 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2457 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2458 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2459 int count; 2460 2461 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2462 priority, logic_serv, match); 2463 2464 if (count < 0) { 2465 return count; 2466 } 2467 2468 total_count += count; 2469 } 2470 2471 return total_count; 2472 } 2473 2474 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2475 { 2476 MachineClass *mc = MACHINE_CLASS(oc); 2477 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2478 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2479 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2480 2481 static GlobalProperty phb_compat[] = { 2482 { TYPE_PNV_PHB, "version", "3" }, 2483 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2484 }; 2485 2486 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2487 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2488 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2489 2490 xic->icp_get = pnv_icp_get; 2491 xic->ics_get = pnv_ics_get; 2492 xic->ics_resend = pnv_ics_resend; 2493 2494 pmc->compat = compat; 2495 pmc->compat_size = sizeof(compat); 2496 pmc->max_smt_threads = 8; 2497 2498 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2499 } 2500 2501 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2502 { 2503 MachineClass *mc = MACHINE_CLASS(oc); 2504 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2505 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2506 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2507 2508 static GlobalProperty phb_compat[] = { 2509 { TYPE_PNV_PHB, "version", "4" }, 2510 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2511 }; 2512 2513 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2514 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2515 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2516 2517 xfc->match_nvt = pnv_match_nvt; 2518 2519 pmc->compat = compat; 2520 pmc->compat_size = sizeof(compat); 2521 pmc->max_smt_threads = 4; 2522 pmc->dt_power_mgt = pnv_dt_power_mgt; 2523 2524 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2525 } 2526 2527 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2528 { 2529 MachineClass *mc = MACHINE_CLASS(oc); 2530 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2531 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2532 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2533 2534 static GlobalProperty phb_compat[] = { 2535 { TYPE_PNV_PHB, "version", "5" }, 2536 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2537 }; 2538 2539 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2540 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2541 2542 mc->alias = "powernv"; 2543 2544 pmc->compat = compat; 2545 pmc->compat_size = sizeof(compat); 2546 pmc->max_smt_threads = 4; 2547 pmc->dt_power_mgt = pnv_dt_power_mgt; 2548 2549 xfc->match_nvt = pnv10_xive_match_nvt; 2550 2551 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2552 } 2553 2554 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2555 { 2556 MachineClass *mc = MACHINE_CLASS(oc); 2557 2558 pnv_machine_p10_common_class_init(oc, data); 2559 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2560 } 2561 2562 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2563 { 2564 MachineClass *mc = MACHINE_CLASS(oc); 2565 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2566 2567 pnv_machine_p10_common_class_init(oc, data); 2568 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2569 pmc->i2c_init = pnv_rainier_i2c_init; 2570 } 2571 2572 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2573 { 2574 PnvMachineState *pnv = PNV_MACHINE(obj); 2575 2576 return !!pnv->fw_load_addr; 2577 } 2578 2579 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2580 { 2581 PnvMachineState *pnv = PNV_MACHINE(obj); 2582 2583 if (value) { 2584 pnv->fw_load_addr = 0x8000000; 2585 } 2586 } 2587 2588 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2589 { 2590 CPUPPCState *env = cpu_env(cs); 2591 2592 cpu_synchronize_state(cs); 2593 ppc_cpu_do_system_reset(cs); 2594 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2595 /* 2596 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2597 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2598 * (PPC_BIT(43)). 2599 */ 2600 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2601 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2602 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2603 } 2604 } else { 2605 /* 2606 * For non-powersave system resets, SRR1[42:45] are defined to be 2607 * implementation-dependent. The POWER9 User Manual specifies that 2608 * an external (SCOM driven, which may come from a BMC nmi command or 2609 * another CPU requesting a NMI IPI) system reset exception should be 2610 * 0b0010 (PPC_BIT(44)). 2611 */ 2612 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2613 } 2614 } 2615 2616 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2617 { 2618 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2619 } 2620 2621 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2622 { 2623 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2624 int i; 2625 2626 for (i = 0; i < pnv->num_chips; i++) { 2627 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2628 } 2629 } 2630 2631 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2632 { 2633 MachineClass *mc = MACHINE_CLASS(oc); 2634 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2635 NMIClass *nc = NMI_CLASS(oc); 2636 2637 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2638 mc->init = pnv_init; 2639 mc->reset = pnv_reset; 2640 mc->max_cpus = MAX_CPUS; 2641 /* Pnv provides a AHCI device for storage */ 2642 mc->block_default_type = IF_IDE; 2643 mc->no_parallel = 1; 2644 mc->default_boot_order = NULL; 2645 /* 2646 * RAM defaults to less than 2048 for 32-bit hosts, and large 2647 * enough to fit the maximum initrd size at it's load address 2648 */ 2649 mc->default_ram_size = 1 * GiB; 2650 mc->default_ram_id = "pnv.ram"; 2651 ispc->print_info = pnv_pic_print_info; 2652 nc->nmi_monitor_handler = pnv_nmi; 2653 2654 object_class_property_add_bool(oc, "hb-mode", 2655 pnv_machine_get_hb, pnv_machine_set_hb); 2656 object_class_property_set_description(oc, "hb-mode", 2657 "Use a hostboot like boot loader"); 2658 } 2659 2660 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2661 { \ 2662 .name = type, \ 2663 .class_init = class_initfn, \ 2664 .parent = TYPE_PNV8_CHIP, \ 2665 } 2666 2667 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2668 { \ 2669 .name = type, \ 2670 .class_init = class_initfn, \ 2671 .parent = TYPE_PNV9_CHIP, \ 2672 } 2673 2674 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2675 { \ 2676 .name = type, \ 2677 .class_init = class_initfn, \ 2678 .parent = TYPE_PNV10_CHIP, \ 2679 } 2680 2681 static const TypeInfo types[] = { 2682 { 2683 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2684 .parent = MACHINE_TYPE_NAME("powernv10"), 2685 .class_init = pnv_machine_p10_rainier_class_init, 2686 }, 2687 { 2688 .name = MACHINE_TYPE_NAME("powernv10"), 2689 .parent = TYPE_PNV_MACHINE, 2690 .class_init = pnv_machine_power10_class_init, 2691 .interfaces = (InterfaceInfo[]) { 2692 { TYPE_XIVE_FABRIC }, 2693 { }, 2694 }, 2695 }, 2696 { 2697 .name = MACHINE_TYPE_NAME("powernv9"), 2698 .parent = TYPE_PNV_MACHINE, 2699 .class_init = pnv_machine_power9_class_init, 2700 .interfaces = (InterfaceInfo[]) { 2701 { TYPE_XIVE_FABRIC }, 2702 { }, 2703 }, 2704 }, 2705 { 2706 .name = MACHINE_TYPE_NAME("powernv8"), 2707 .parent = TYPE_PNV_MACHINE, 2708 .class_init = pnv_machine_power8_class_init, 2709 .interfaces = (InterfaceInfo[]) { 2710 { TYPE_XICS_FABRIC }, 2711 { }, 2712 }, 2713 }, 2714 { 2715 .name = TYPE_PNV_MACHINE, 2716 .parent = TYPE_MACHINE, 2717 .abstract = true, 2718 .instance_size = sizeof(PnvMachineState), 2719 .class_init = pnv_machine_class_init, 2720 .class_size = sizeof(PnvMachineClass), 2721 .interfaces = (InterfaceInfo[]) { 2722 { TYPE_INTERRUPT_STATS_PROVIDER }, 2723 { TYPE_NMI }, 2724 { }, 2725 }, 2726 }, 2727 { 2728 .name = TYPE_PNV_CHIP, 2729 .parent = TYPE_SYS_BUS_DEVICE, 2730 .class_init = pnv_chip_class_init, 2731 .instance_size = sizeof(PnvChip), 2732 .class_size = sizeof(PnvChipClass), 2733 .abstract = true, 2734 }, 2735 2736 /* 2737 * P10 chip and variants 2738 */ 2739 { 2740 .name = TYPE_PNV10_CHIP, 2741 .parent = TYPE_PNV_CHIP, 2742 .instance_init = pnv_chip_power10_instance_init, 2743 .instance_size = sizeof(Pnv10Chip), 2744 }, 2745 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2746 2747 /* 2748 * P9 chip and variants 2749 */ 2750 { 2751 .name = TYPE_PNV9_CHIP, 2752 .parent = TYPE_PNV_CHIP, 2753 .instance_init = pnv_chip_power9_instance_init, 2754 .instance_size = sizeof(Pnv9Chip), 2755 }, 2756 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2757 2758 /* 2759 * P8 chip and variants 2760 */ 2761 { 2762 .name = TYPE_PNV8_CHIP, 2763 .parent = TYPE_PNV_CHIP, 2764 .instance_init = pnv_chip_power8_instance_init, 2765 .instance_size = sizeof(Pnv8Chip), 2766 }, 2767 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2768 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2769 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2770 pnv_chip_power8nvl_class_init), 2771 }; 2772 2773 DEFINE_TYPES(types) 2774