1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 #include "hw/pci-host/pnv_phb3.h" 48 #include "hw/pci-host/pnv_phb4.h" 49 50 #include "hw/ppc/xics.h" 51 #include "hw/qdev-properties.h" 52 #include "hw/ppc/pnv_chip.h" 53 #include "hw/ppc/pnv_xscom.h" 54 #include "hw/ppc/pnv_pnor.h" 55 56 #include "hw/isa/isa.h" 57 #include "hw/char/serial.h" 58 #include "hw/rtc/mc146818rtc.h" 59 60 #include <libfdt.h> 61 62 #define FDT_MAX_SIZE (1 * MiB) 63 64 #define FW_FILE_NAME "skiboot.lid" 65 #define FW_LOAD_ADDR 0x0 66 #define FW_MAX_SIZE (16 * MiB) 67 68 #define KERNEL_LOAD_ADDR 0x20000000 69 #define KERNEL_MAX_SIZE (128 * MiB) 70 #define INITRD_LOAD_ADDR 0x28000000 71 #define INITRD_MAX_SIZE (128 * MiB) 72 73 static const char *pnv_chip_core_typename(const PnvChip *o) 74 { 75 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 76 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 77 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 78 const char *core_type = object_class_get_name(object_class_by_name(s)); 79 g_free(s); 80 return core_type; 81 } 82 83 /* 84 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 85 * 4 * 4 sockets * 12 cores * 8 threads = 1536 86 * Let's make it 2^11 87 */ 88 #define MAX_CPUS 2048 89 90 /* 91 * Memory nodes are created by hostboot, one for each range of memory 92 * that has a different "affinity". In practice, it means one range 93 * per chip. 94 */ 95 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 96 { 97 char *mem_name; 98 uint64_t mem_reg_property[2]; 99 int off; 100 101 mem_reg_property[0] = cpu_to_be64(start); 102 mem_reg_property[1] = cpu_to_be64(size); 103 104 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 105 off = fdt_add_subnode(fdt, 0, mem_name); 106 g_free(mem_name); 107 108 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 109 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 110 sizeof(mem_reg_property)))); 111 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 112 } 113 114 static int get_cpus_node(void *fdt) 115 { 116 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 117 118 if (cpus_offset < 0) { 119 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 120 if (cpus_offset) { 121 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 123 } 124 } 125 _FDT(cpus_offset); 126 return cpus_offset; 127 } 128 129 /* 130 * The PowerNV cores (and threads) need to use real HW ids and not an 131 * incremental index like it has been done on other platforms. This HW 132 * id is stored in the CPU PIR, it is used to create cpu nodes in the 133 * device tree, used in XSCOM to address cores and in interrupt 134 * servers. 135 */ 136 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 137 { 138 PowerPCCPU *cpu = pc->threads[0]; 139 CPUState *cs = CPU(cpu); 140 DeviceClass *dc = DEVICE_GET_CLASS(cs); 141 int smt_threads = CPU_CORE(pc)->nr_threads; 142 CPUPPCState *env = &cpu->env; 143 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 144 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 145 int i; 146 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 147 0xffffffff, 0xffffffff}; 148 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 149 uint32_t cpufreq = 1000000000; 150 uint32_t page_sizes_prop[64]; 151 size_t page_sizes_prop_size; 152 int offset; 153 char *nodename; 154 int cpus_offset = get_cpus_node(fdt); 155 156 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 157 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 158 _FDT(offset); 159 g_free(nodename); 160 161 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 165 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 169 env->dcache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 173 env->icache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 175 env->icache_line_size))); 176 177 if (pcc->l1_dcache_size) { 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 179 pcc->l1_dcache_size))); 180 } else { 181 warn_report("Unknown L1 dcache size for cpu"); 182 } 183 if (pcc->l1_icache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 185 pcc->l1_icache_size))); 186 } else { 187 warn_report("Unknown L1 icache size for cpu"); 188 } 189 190 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 193 cpu->hash64_opts->slb_size))); 194 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 195 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 196 197 if (ppc_has_spr(cpu, SPR_PURR)) { 198 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 199 } 200 201 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 203 segs, sizeof(segs)))); 204 } 205 206 /* 207 * Advertise VMX/VSX (vector extensions) if available 208 * 0 / no property == no vector extensions 209 * 1 == VMX / Altivec available 210 * 2 == VSX available 211 */ 212 if (env->insns_flags & PPC_ALTIVEC) { 213 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 214 215 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 216 } 217 218 /* 219 * Advertise DFP (Decimal Floating Point) if available 220 * 0 / no property == no DFP 221 * 1 == DFP available 222 */ 223 if (env->insns_flags2 & PPC2_DFP) { 224 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 225 } 226 227 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 228 sizeof(page_sizes_prop)); 229 if (page_sizes_prop_size) { 230 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 231 page_sizes_prop, page_sizes_prop_size))); 232 } 233 234 /* Build interrupt servers properties */ 235 for (i = 0; i < smt_threads; i++) { 236 servers_prop[i] = cpu_to_be32(pc->pir + i); 237 } 238 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 239 servers_prop, sizeof(*servers_prop) * smt_threads))); 240 241 return offset; 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 /* 282 * Adds a PnvPHB to the chip on P8. 283 * Implemented here, like for defaults PHBs 284 */ 285 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 286 { 287 Pnv8Chip *chip8 = PNV8_CHIP(chip); 288 289 phb->chip = chip; 290 291 chip8->phbs[chip8->num_phbs] = phb; 292 chip8->num_phbs++; 293 return chip; 294 } 295 296 /* 297 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 298 * HTM is always enabled because TCG does implement HTM, it's just a 299 * degenerate implementation. 300 */ 301 static const uint8_t pa_features_207[] = { 24, 0, 302 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 303 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 304 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 305 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 306 307 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 308 { 309 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 310 int i; 311 312 pnv_dt_xscom(chip, fdt, 0, 313 cpu_to_be64(PNV_XSCOM_BASE(chip)), 314 cpu_to_be64(PNV_XSCOM_SIZE), 315 compat, sizeof(compat)); 316 317 for (i = 0; i < chip->nr_cores; i++) { 318 PnvCore *pnv_core = chip->cores[i]; 319 int offset; 320 321 offset = pnv_dt_core(chip, pnv_core, fdt); 322 323 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 324 pa_features_207, sizeof(pa_features_207)))); 325 326 /* Interrupt Control Presenters (ICP). One per core. */ 327 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 328 } 329 330 if (chip->ram_size) { 331 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 332 } 333 } 334 335 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 336 { 337 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 338 int i; 339 340 pnv_dt_xscom(chip, fdt, 0, 341 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 342 cpu_to_be64(PNV9_XSCOM_SIZE), 343 compat, sizeof(compat)); 344 345 for (i = 0; i < chip->nr_cores; i++) { 346 PnvCore *pnv_core = chip->cores[i]; 347 int offset; 348 349 offset = pnv_dt_core(chip, pnv_core, fdt); 350 351 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 352 pa_features_207, sizeof(pa_features_207)))); 353 } 354 355 if (chip->ram_size) { 356 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 357 } 358 359 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 360 } 361 362 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 363 { 364 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 365 int i; 366 367 pnv_dt_xscom(chip, fdt, 0, 368 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 369 cpu_to_be64(PNV10_XSCOM_SIZE), 370 compat, sizeof(compat)); 371 372 for (i = 0; i < chip->nr_cores; i++) { 373 PnvCore *pnv_core = chip->cores[i]; 374 int offset; 375 376 offset = pnv_dt_core(chip, pnv_core, fdt); 377 378 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 379 pa_features_207, sizeof(pa_features_207)))); 380 } 381 382 if (chip->ram_size) { 383 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 384 } 385 386 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 387 } 388 389 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 390 { 391 uint32_t io_base = d->ioport_id; 392 uint32_t io_regs[] = { 393 cpu_to_be32(1), 394 cpu_to_be32(io_base), 395 cpu_to_be32(2) 396 }; 397 char *name; 398 int node; 399 400 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 401 node = fdt_add_subnode(fdt, lpc_off, name); 402 _FDT(node); 403 g_free(name); 404 405 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 406 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 407 } 408 409 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 410 { 411 const char compatible[] = "ns16550\0pnpPNP,501"; 412 uint32_t io_base = d->ioport_id; 413 uint32_t io_regs[] = { 414 cpu_to_be32(1), 415 cpu_to_be32(io_base), 416 cpu_to_be32(8) 417 }; 418 uint32_t irq; 419 char *name; 420 int node; 421 422 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 423 424 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 425 node = fdt_add_subnode(fdt, lpc_off, name); 426 _FDT(node); 427 g_free(name); 428 429 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 430 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 431 sizeof(compatible)))); 432 433 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 434 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 436 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 437 fdt_get_phandle(fdt, lpc_off)))); 438 439 /* This is needed by Linux */ 440 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 441 } 442 443 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 444 { 445 const char compatible[] = "bt\0ipmi-bt"; 446 uint32_t io_base; 447 uint32_t io_regs[] = { 448 cpu_to_be32(1), 449 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 450 cpu_to_be32(3) 451 }; 452 uint32_t irq; 453 char *name; 454 int node; 455 456 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 457 io_regs[1] = cpu_to_be32(io_base); 458 459 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 460 461 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 462 node = fdt_add_subnode(fdt, lpc_off, name); 463 _FDT(node); 464 g_free(name); 465 466 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 467 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 468 sizeof(compatible)))); 469 470 /* Mark it as reserved to avoid Linux trying to claim it */ 471 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 472 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 473 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 474 fdt_get_phandle(fdt, lpc_off)))); 475 } 476 477 typedef struct ForeachPopulateArgs { 478 void *fdt; 479 int offset; 480 } ForeachPopulateArgs; 481 482 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 483 { 484 ForeachPopulateArgs *args = opaque; 485 ISADevice *d = ISA_DEVICE(dev); 486 487 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 488 pnv_dt_rtc(d, args->fdt, args->offset); 489 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 490 pnv_dt_serial(d, args->fdt, args->offset); 491 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 492 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 493 } else { 494 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 495 d->ioport_id); 496 } 497 498 return 0; 499 } 500 501 /* 502 * The default LPC bus of a multichip system is on chip 0. It's 503 * recognized by the firmware (skiboot) using a "primary" property. 504 */ 505 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 506 { 507 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 508 ForeachPopulateArgs args = { 509 .fdt = fdt, 510 .offset = isa_offset, 511 }; 512 uint32_t phandle; 513 514 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 515 516 phandle = qemu_fdt_alloc_phandle(fdt); 517 assert(phandle > 0); 518 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 519 520 /* 521 * ISA devices are not necessarily parented to the ISA bus so we 522 * can not use object_child_foreach() 523 */ 524 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 525 &args); 526 } 527 528 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 529 { 530 int off; 531 532 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 533 off = fdt_add_subnode(fdt, off, "power-mgt"); 534 535 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 536 } 537 538 static void *pnv_dt_create(MachineState *machine) 539 { 540 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 541 PnvMachineState *pnv = PNV_MACHINE(machine); 542 void *fdt; 543 char *buf; 544 int off; 545 int i; 546 547 fdt = g_malloc0(FDT_MAX_SIZE); 548 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 549 550 /* /qemu node */ 551 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 552 553 /* Root node */ 554 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 555 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 556 _FDT((fdt_setprop_string(fdt, 0, "model", 557 "IBM PowerNV (emulated by qemu)"))); 558 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 559 560 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 561 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 562 if (qemu_uuid_set) { 563 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 564 } 565 g_free(buf); 566 567 off = fdt_add_subnode(fdt, 0, "chosen"); 568 if (machine->kernel_cmdline) { 569 _FDT((fdt_setprop_string(fdt, off, "bootargs", 570 machine->kernel_cmdline))); 571 } 572 573 if (pnv->initrd_size) { 574 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 575 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 576 577 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 578 &start_prop, sizeof(start_prop)))); 579 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 580 &end_prop, sizeof(end_prop)))); 581 } 582 583 /* Populate device tree for each chip */ 584 for (i = 0; i < pnv->num_chips; i++) { 585 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 586 } 587 588 /* Populate ISA devices on chip 0 */ 589 pnv_dt_isa(pnv, fdt); 590 591 if (pnv->bmc) { 592 pnv_dt_bmc_sensors(pnv->bmc, fdt); 593 } 594 595 /* Create an extra node for power management on machines that support it */ 596 if (pmc->dt_power_mgt) { 597 pmc->dt_power_mgt(pnv, fdt); 598 } 599 600 return fdt; 601 } 602 603 static void pnv_powerdown_notify(Notifier *n, void *opaque) 604 { 605 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 606 607 if (pnv->bmc) { 608 pnv_bmc_powerdown(pnv->bmc); 609 } 610 } 611 612 static void pnv_reset(MachineState *machine, ShutdownCause reason) 613 { 614 PnvMachineState *pnv = PNV_MACHINE(machine); 615 IPMIBmc *bmc; 616 void *fdt; 617 618 qemu_devices_reset(reason); 619 620 /* 621 * The machine should provide by default an internal BMC simulator. 622 * If not, try to use the BMC device that was provided on the command 623 * line. 624 */ 625 bmc = pnv_bmc_find(&error_fatal); 626 if (!pnv->bmc) { 627 if (!bmc) { 628 if (!qtest_enabled()) { 629 warn_report("machine has no BMC device. Use '-device " 630 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 631 "to define one"); 632 } 633 } else { 634 pnv_bmc_set_pnor(bmc, pnv->pnor); 635 pnv->bmc = bmc; 636 } 637 } 638 639 fdt = pnv_dt_create(machine); 640 641 /* Pack resulting tree */ 642 _FDT((fdt_pack(fdt))); 643 644 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 645 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 646 647 /* 648 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 649 * the existing machine->fdt to avoid leaking it during 650 * a reset. 651 */ 652 g_free(machine->fdt); 653 machine->fdt = fdt; 654 } 655 656 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 657 { 658 Pnv8Chip *chip8 = PNV8_CHIP(chip); 659 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 660 661 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 662 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 663 } 664 665 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 666 { 667 Pnv8Chip *chip8 = PNV8_CHIP(chip); 668 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 669 670 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 671 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 672 } 673 674 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 675 { 676 Pnv9Chip *chip9 = PNV9_CHIP(chip); 677 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 678 679 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 680 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 681 } 682 683 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 684 { 685 Pnv10Chip *chip10 = PNV10_CHIP(chip); 686 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 687 688 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 689 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 690 } 691 692 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 693 { 694 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 695 } 696 697 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 698 { 699 Pnv8Chip *chip8 = PNV8_CHIP(chip); 700 int i; 701 702 ics_pic_print_info(&chip8->psi.ics, mon); 703 704 for (i = 0; i < chip8->num_phbs; i++) { 705 PnvPHB *phb = chip8->phbs[i]; 706 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 707 708 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 709 ics_pic_print_info(&phb3->lsis, mon); 710 } 711 } 712 713 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 714 { 715 Monitor *mon = opaque; 716 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 717 718 if (!phb) { 719 return 0; 720 } 721 722 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 723 724 return 0; 725 } 726 727 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 728 { 729 Pnv9Chip *chip9 = PNV9_CHIP(chip); 730 731 pnv_xive_pic_print_info(&chip9->xive, mon); 732 pnv_psi_pic_print_info(&chip9->psi, mon); 733 734 object_child_foreach_recursive(OBJECT(chip), 735 pnv_chip_power9_pic_print_info_child, mon); 736 } 737 738 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 739 uint32_t core_id) 740 { 741 return PNV_XSCOM_EX_BASE(core_id); 742 } 743 744 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 745 uint32_t core_id) 746 { 747 return PNV9_XSCOM_EC_BASE(core_id); 748 } 749 750 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 751 uint32_t core_id) 752 { 753 return PNV10_XSCOM_EC_BASE(core_id); 754 } 755 756 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 757 { 758 PowerPCCPUClass *ppc_default = 759 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 760 PowerPCCPUClass *ppc = 761 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 762 763 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 764 } 765 766 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 767 { 768 ISADevice *dev = isa_new("isa-ipmi-bt"); 769 770 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 771 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 772 isa_realize_and_unref(dev, bus, &error_fatal); 773 } 774 775 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 776 { 777 Pnv10Chip *chip10 = PNV10_CHIP(chip); 778 779 pnv_xive2_pic_print_info(&chip10->xive, mon); 780 pnv_psi_pic_print_info(&chip10->psi, mon); 781 782 object_child_foreach_recursive(OBJECT(chip), 783 pnv_chip_power9_pic_print_info_child, mon); 784 } 785 786 /* Always give the first 1GB to chip 0 else we won't boot */ 787 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 788 { 789 MachineState *machine = MACHINE(pnv); 790 uint64_t ram_per_chip; 791 792 assert(machine->ram_size >= 1 * GiB); 793 794 ram_per_chip = machine->ram_size / pnv->num_chips; 795 if (ram_per_chip >= 1 * GiB) { 796 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 797 } 798 799 assert(pnv->num_chips > 1); 800 801 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 802 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 803 } 804 805 static void pnv_init(MachineState *machine) 806 { 807 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 808 PnvMachineState *pnv = PNV_MACHINE(machine); 809 MachineClass *mc = MACHINE_GET_CLASS(machine); 810 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 811 char *fw_filename; 812 long fw_size; 813 uint64_t chip_ram_start = 0; 814 int i; 815 char *chip_typename; 816 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 817 DeviceState *dev; 818 819 if (kvm_enabled()) { 820 error_report("machine %s does not support the KVM accelerator", 821 mc->name); 822 exit(EXIT_FAILURE); 823 } 824 825 /* allocate RAM */ 826 if (machine->ram_size < mc->default_ram_size) { 827 char *sz = size_to_str(mc->default_ram_size); 828 error_report("Invalid RAM size, should be bigger than %s", sz); 829 g_free(sz); 830 exit(EXIT_FAILURE); 831 } 832 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 833 834 /* 835 * Create our simple PNOR device 836 */ 837 dev = qdev_new(TYPE_PNV_PNOR); 838 if (pnor) { 839 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 840 } 841 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 842 pnv->pnor = PNV_PNOR(dev); 843 844 /* load skiboot firmware */ 845 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 846 if (!fw_filename) { 847 error_report("Could not find OPAL firmware '%s'", bios_name); 848 exit(1); 849 } 850 851 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 852 if (fw_size < 0) { 853 error_report("Could not load OPAL firmware '%s'", fw_filename); 854 exit(1); 855 } 856 g_free(fw_filename); 857 858 /* load kernel */ 859 if (machine->kernel_filename) { 860 long kernel_size; 861 862 kernel_size = load_image_targphys(machine->kernel_filename, 863 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 864 if (kernel_size < 0) { 865 error_report("Could not load kernel '%s'", 866 machine->kernel_filename); 867 exit(1); 868 } 869 } 870 871 /* load initrd */ 872 if (machine->initrd_filename) { 873 pnv->initrd_base = INITRD_LOAD_ADDR; 874 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 875 pnv->initrd_base, INITRD_MAX_SIZE); 876 if (pnv->initrd_size < 0) { 877 error_report("Could not load initial ram disk '%s'", 878 machine->initrd_filename); 879 exit(1); 880 } 881 } 882 883 /* MSIs are supported on this platform */ 884 msi_nonbroken = true; 885 886 /* 887 * Check compatibility of the specified CPU with the machine 888 * default. 889 */ 890 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 891 error_report("invalid CPU model '%s' for %s machine", 892 machine->cpu_type, mc->name); 893 exit(1); 894 } 895 896 /* Create the processor chips */ 897 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 898 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 899 i, machine->cpu_type); 900 if (!object_class_by_name(chip_typename)) { 901 error_report("invalid chip model '%.*s' for %s machine", 902 i, machine->cpu_type, mc->name); 903 exit(1); 904 } 905 906 pnv->num_chips = 907 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 908 909 if (machine->smp.threads > 8) { 910 error_report("Cannot support more than 8 threads/core " 911 "on a powernv machine"); 912 exit(1); 913 } 914 if (!is_power_of_2(machine->smp.threads)) { 915 error_report("Cannot support %d threads/core on a powernv" 916 "machine because it must be a power of 2", 917 machine->smp.threads); 918 exit(1); 919 } 920 /* 921 * TODO: should we decide on how many chips we can create based 922 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 923 */ 924 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 925 error_report("invalid number of chips: '%d'", pnv->num_chips); 926 error_printf( 927 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 928 exit(1); 929 } 930 931 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 932 for (i = 0; i < pnv->num_chips; i++) { 933 char chip_name[32]; 934 Object *chip = OBJECT(qdev_new(chip_typename)); 935 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 936 937 pnv->chips[i] = PNV_CHIP(chip); 938 939 /* Distribute RAM among the chips */ 940 object_property_set_int(chip, "ram-start", chip_ram_start, 941 &error_fatal); 942 object_property_set_int(chip, "ram-size", chip_ram_size, 943 &error_fatal); 944 chip_ram_start += chip_ram_size; 945 946 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 947 object_property_add_child(OBJECT(pnv), chip_name, chip); 948 object_property_set_int(chip, "chip-id", i, &error_fatal); 949 object_property_set_int(chip, "nr-cores", machine->smp.cores, 950 &error_fatal); 951 object_property_set_int(chip, "nr-threads", machine->smp.threads, 952 &error_fatal); 953 /* 954 * The POWER8 machine use the XICS interrupt interface. 955 * Propagate the XICS fabric to the chip and its controllers. 956 */ 957 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 958 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 959 } 960 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 961 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 962 &error_abort); 963 } 964 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 965 } 966 g_free(chip_typename); 967 968 /* Instantiate ISA bus on chip 0 */ 969 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 970 971 /* Create serial port */ 972 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 973 974 /* Create an RTC ISA device too */ 975 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 976 977 /* 978 * Create the machine BMC simulator and the IPMI BT device for 979 * communication with the BMC 980 */ 981 if (defaults_enabled()) { 982 pnv->bmc = pnv_bmc_create(pnv->pnor); 983 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 984 } 985 986 /* 987 * The PNOR is mapped on the LPC FW address space by the BMC. 988 * Since we can not reach the remote BMC machine with LPC memops, 989 * map it always for now. 990 */ 991 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 992 &pnv->pnor->mmio); 993 994 /* 995 * OpenPOWER systems use a IPMI SEL Event message to notify the 996 * host to powerdown 997 */ 998 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 999 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1000 1001 /* 1002 * Create/Connect any machine-specific I2C devices 1003 */ 1004 if (pmc->i2c_init) { 1005 pmc->i2c_init(pnv); 1006 } 1007 } 1008 1009 /* 1010 * 0:21 Reserved - Read as zeros 1011 * 22:24 Chip ID 1012 * 25:28 Core number 1013 * 29:31 Thread ID 1014 */ 1015 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 1016 { 1017 return (chip->chip_id << 7) | (core_id << 3); 1018 } 1019 1020 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1021 Error **errp) 1022 { 1023 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1024 Error *local_err = NULL; 1025 Object *obj; 1026 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1027 1028 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1029 if (local_err) { 1030 error_propagate(errp, local_err); 1031 return; 1032 } 1033 1034 pnv_cpu->intc = obj; 1035 } 1036 1037 1038 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1039 { 1040 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1041 1042 icp_reset(ICP(pnv_cpu->intc)); 1043 } 1044 1045 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1046 { 1047 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1048 1049 icp_destroy(ICP(pnv_cpu->intc)); 1050 pnv_cpu->intc = NULL; 1051 } 1052 1053 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1054 Monitor *mon) 1055 { 1056 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1057 } 1058 1059 /* 1060 * 0:48 Reserved - Read as zeroes 1061 * 49:52 Node ID 1062 * 53:55 Chip ID 1063 * 56 Reserved - Read as zero 1064 * 57:61 Core number 1065 * 62:63 Thread ID 1066 * 1067 * We only care about the lower bits. uint32_t is fine for the moment. 1068 */ 1069 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1070 { 1071 return (chip->chip_id << 8) | (core_id << 2); 1072 } 1073 1074 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1075 { 1076 return (chip->chip_id << 8) | (core_id << 2); 1077 } 1078 1079 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1080 Error **errp) 1081 { 1082 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1083 Error *local_err = NULL; 1084 Object *obj; 1085 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1086 1087 /* 1088 * The core creates its interrupt presenter but the XIVE interrupt 1089 * controller object is initialized afterwards. Hopefully, it's 1090 * only used at runtime. 1091 */ 1092 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1093 &local_err); 1094 if (local_err) { 1095 error_propagate(errp, local_err); 1096 return; 1097 } 1098 1099 pnv_cpu->intc = obj; 1100 } 1101 1102 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1103 { 1104 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1105 1106 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1107 } 1108 1109 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1110 { 1111 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1112 1113 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1114 pnv_cpu->intc = NULL; 1115 } 1116 1117 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1118 Monitor *mon) 1119 { 1120 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1121 } 1122 1123 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1124 Error **errp) 1125 { 1126 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1127 Error *local_err = NULL; 1128 Object *obj; 1129 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1130 1131 /* 1132 * The core creates its interrupt presenter but the XIVE2 interrupt 1133 * controller object is initialized afterwards. Hopefully, it's 1134 * only used at runtime. 1135 */ 1136 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1137 &local_err); 1138 if (local_err) { 1139 error_propagate(errp, local_err); 1140 return; 1141 } 1142 1143 pnv_cpu->intc = obj; 1144 } 1145 1146 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1147 { 1148 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1149 1150 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1151 } 1152 1153 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1154 { 1155 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1156 1157 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1158 pnv_cpu->intc = NULL; 1159 } 1160 1161 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1162 Monitor *mon) 1163 { 1164 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1165 } 1166 1167 /* 1168 * Allowed core identifiers on a POWER8 Processor Chip : 1169 * 1170 * <EX0 reserved> 1171 * EX1 - Venice only 1172 * EX2 - Venice only 1173 * EX3 - Venice only 1174 * EX4 1175 * EX5 1176 * EX6 1177 * <EX7,8 reserved> <reserved> 1178 * EX9 - Venice only 1179 * EX10 - Venice only 1180 * EX11 - Venice only 1181 * EX12 1182 * EX13 1183 * EX14 1184 * <EX15 reserved> 1185 */ 1186 #define POWER8E_CORE_MASK (0x7070ull) 1187 #define POWER8_CORE_MASK (0x7e7eull) 1188 1189 /* 1190 * POWER9 has 24 cores, ids starting at 0x0 1191 */ 1192 #define POWER9_CORE_MASK (0xffffffffffffffull) 1193 1194 1195 #define POWER10_CORE_MASK (0xffffffffffffffull) 1196 1197 static void pnv_chip_power8_instance_init(Object *obj) 1198 { 1199 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1200 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1201 int i; 1202 1203 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1204 (Object **)&chip8->xics, 1205 object_property_allow_set_link, 1206 OBJ_PROP_LINK_STRONG); 1207 1208 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1209 1210 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1211 1212 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1213 1214 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1215 1216 if (defaults_enabled()) { 1217 chip8->num_phbs = pcc->num_phbs; 1218 1219 for (i = 0; i < chip8->num_phbs; i++) { 1220 Object *phb = object_new(TYPE_PNV_PHB); 1221 1222 /* 1223 * We need the chip to parent the PHB to allow the DT 1224 * to build correctly (via pnv_xscom_dt()). 1225 * 1226 * TODO: the PHB should be parented by a PEC device that, at 1227 * this moment, is not modelled powernv8/phb3. 1228 */ 1229 object_property_add_child(obj, "phb[*]", phb); 1230 chip8->phbs[i] = PNV_PHB(phb); 1231 } 1232 } 1233 1234 } 1235 1236 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1237 { 1238 PnvChip *chip = PNV_CHIP(chip8); 1239 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1240 int i, j; 1241 char *name; 1242 1243 name = g_strdup_printf("icp-%x", chip->chip_id); 1244 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1245 g_free(name); 1246 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1247 &chip8->icp_mmio); 1248 1249 /* Map the ICP registers for each thread */ 1250 for (i = 0; i < chip->nr_cores; i++) { 1251 PnvCore *pnv_core = chip->cores[i]; 1252 int core_hwid = CPU_CORE(pnv_core)->core_id; 1253 1254 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1255 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1256 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1257 1258 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1259 &icp->mmio); 1260 } 1261 } 1262 } 1263 1264 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1265 { 1266 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1267 PnvChip *chip = PNV_CHIP(dev); 1268 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1269 Pnv8Psi *psi8 = &chip8->psi; 1270 Error *local_err = NULL; 1271 int i; 1272 1273 assert(chip8->xics); 1274 1275 /* XSCOM bridge is first */ 1276 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1277 1278 pcc->parent_realize(dev, &local_err); 1279 if (local_err) { 1280 error_propagate(errp, local_err); 1281 return; 1282 } 1283 1284 /* Processor Service Interface (PSI) Host Bridge */ 1285 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1286 &error_fatal); 1287 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1288 OBJECT(chip8->xics), &error_abort); 1289 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1290 return; 1291 } 1292 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1293 &PNV_PSI(psi8)->xscom_regs); 1294 1295 /* Create LPC controller */ 1296 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1297 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1298 1299 chip->fw_mr = &chip8->lpc.isa_fw; 1300 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1301 (uint64_t) PNV_XSCOM_BASE(chip), 1302 PNV_XSCOM_LPC_BASE); 1303 1304 /* 1305 * Interrupt Management Area. This is the memory region holding 1306 * all the Interrupt Control Presenter (ICP) registers 1307 */ 1308 pnv_chip_icp_realize(chip8, &local_err); 1309 if (local_err) { 1310 error_propagate(errp, local_err); 1311 return; 1312 } 1313 1314 /* Create the simplified OCC model */ 1315 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1316 return; 1317 } 1318 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1319 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1320 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1321 1322 /* OCC SRAM model */ 1323 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1324 &chip8->occ.sram_regs); 1325 1326 /* HOMER */ 1327 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1328 &error_abort); 1329 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1330 return; 1331 } 1332 /* Homer Xscom region */ 1333 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1334 1335 /* Homer mmio region */ 1336 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1337 &chip8->homer.regs); 1338 1339 /* PHB controllers */ 1340 for (i = 0; i < chip8->num_phbs; i++) { 1341 PnvPHB *phb = chip8->phbs[i]; 1342 1343 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1344 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1345 &error_fatal); 1346 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1347 &error_fatal); 1348 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1349 return; 1350 } 1351 } 1352 } 1353 1354 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1355 { 1356 addr &= (PNV_XSCOM_SIZE - 1); 1357 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1358 } 1359 1360 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1361 { 1362 DeviceClass *dc = DEVICE_CLASS(klass); 1363 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1364 1365 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1366 k->cores_mask = POWER8E_CORE_MASK; 1367 k->num_phbs = 3; 1368 k->core_pir = pnv_chip_core_pir_p8; 1369 k->intc_create = pnv_chip_power8_intc_create; 1370 k->intc_reset = pnv_chip_power8_intc_reset; 1371 k->intc_destroy = pnv_chip_power8_intc_destroy; 1372 k->intc_print_info = pnv_chip_power8_intc_print_info; 1373 k->isa_create = pnv_chip_power8_isa_create; 1374 k->dt_populate = pnv_chip_power8_dt_populate; 1375 k->pic_print_info = pnv_chip_power8_pic_print_info; 1376 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1377 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1378 dc->desc = "PowerNV Chip POWER8E"; 1379 1380 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1381 &k->parent_realize); 1382 } 1383 1384 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1385 { 1386 DeviceClass *dc = DEVICE_CLASS(klass); 1387 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1388 1389 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1390 k->cores_mask = POWER8_CORE_MASK; 1391 k->num_phbs = 3; 1392 k->core_pir = pnv_chip_core_pir_p8; 1393 k->intc_create = pnv_chip_power8_intc_create; 1394 k->intc_reset = pnv_chip_power8_intc_reset; 1395 k->intc_destroy = pnv_chip_power8_intc_destroy; 1396 k->intc_print_info = pnv_chip_power8_intc_print_info; 1397 k->isa_create = pnv_chip_power8_isa_create; 1398 k->dt_populate = pnv_chip_power8_dt_populate; 1399 k->pic_print_info = pnv_chip_power8_pic_print_info; 1400 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1401 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1402 dc->desc = "PowerNV Chip POWER8"; 1403 1404 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1405 &k->parent_realize); 1406 } 1407 1408 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1409 { 1410 DeviceClass *dc = DEVICE_CLASS(klass); 1411 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1412 1413 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1414 k->cores_mask = POWER8_CORE_MASK; 1415 k->num_phbs = 4; 1416 k->core_pir = pnv_chip_core_pir_p8; 1417 k->intc_create = pnv_chip_power8_intc_create; 1418 k->intc_reset = pnv_chip_power8_intc_reset; 1419 k->intc_destroy = pnv_chip_power8_intc_destroy; 1420 k->intc_print_info = pnv_chip_power8_intc_print_info; 1421 k->isa_create = pnv_chip_power8nvl_isa_create; 1422 k->dt_populate = pnv_chip_power8_dt_populate; 1423 k->pic_print_info = pnv_chip_power8_pic_print_info; 1424 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1425 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1426 dc->desc = "PowerNV Chip POWER8NVL"; 1427 1428 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1429 &k->parent_realize); 1430 } 1431 1432 static void pnv_chip_power9_instance_init(Object *obj) 1433 { 1434 PnvChip *chip = PNV_CHIP(obj); 1435 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1436 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1437 int i; 1438 1439 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1440 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1441 "xive-fabric"); 1442 1443 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1444 1445 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1446 1447 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1448 1449 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1450 1451 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1452 1453 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1454 1455 /* Number of PECs is the chip default */ 1456 chip->num_pecs = pcc->num_pecs; 1457 1458 for (i = 0; i < chip->num_pecs; i++) { 1459 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1460 TYPE_PNV_PHB4_PEC); 1461 } 1462 1463 for (i = 0; i < pcc->i2c_num_engines; i++) { 1464 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1465 } 1466 } 1467 1468 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1469 PnvCore *pnv_core, 1470 const char *type) 1471 { 1472 char eq_name[32]; 1473 int core_id = CPU_CORE(pnv_core)->core_id; 1474 1475 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1476 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1477 sizeof(*eq), type, 1478 &error_fatal, NULL); 1479 1480 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1481 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1482 } 1483 1484 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1485 { 1486 PnvChip *chip = PNV_CHIP(chip9); 1487 int i; 1488 1489 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1490 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1491 1492 for (i = 0; i < chip9->nr_quads; i++) { 1493 PnvQuad *eq = &chip9->quads[i]; 1494 1495 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1496 PNV_QUAD_TYPE_NAME("power9")); 1497 1498 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1499 &eq->xscom_regs); 1500 } 1501 } 1502 1503 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1504 { 1505 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1506 int i; 1507 1508 for (i = 0; i < chip->num_pecs; i++) { 1509 PnvPhb4PecState *pec = &chip9->pecs[i]; 1510 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1511 uint32_t pec_nest_base; 1512 uint32_t pec_pci_base; 1513 1514 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1515 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1516 &error_fatal); 1517 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1518 &error_fatal); 1519 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1520 return; 1521 } 1522 1523 pec_nest_base = pecc->xscom_nest_base(pec); 1524 pec_pci_base = pecc->xscom_pci_base(pec); 1525 1526 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1527 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1528 } 1529 } 1530 1531 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1532 { 1533 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1534 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1535 PnvChip *chip = PNV_CHIP(dev); 1536 Pnv9Psi *psi9 = &chip9->psi; 1537 Error *local_err = NULL; 1538 int i; 1539 1540 /* XSCOM bridge is first */ 1541 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1542 1543 pcc->parent_realize(dev, &local_err); 1544 if (local_err) { 1545 error_propagate(errp, local_err); 1546 return; 1547 } 1548 1549 pnv_chip_quad_realize(chip9, &local_err); 1550 if (local_err) { 1551 error_propagate(errp, local_err); 1552 return; 1553 } 1554 1555 /* XIVE interrupt controller (POWER9) */ 1556 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1557 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1558 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1559 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1560 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1561 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1562 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1563 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1564 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1565 &error_abort); 1566 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1567 return; 1568 } 1569 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1570 &chip9->xive.xscom_regs); 1571 1572 /* Processor Service Interface (PSI) Host Bridge */ 1573 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1574 &error_fatal); 1575 /* This is the only device with 4k ESB pages */ 1576 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1577 &error_fatal); 1578 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1579 return; 1580 } 1581 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1582 &PNV_PSI(psi9)->xscom_regs); 1583 1584 /* LPC */ 1585 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1586 return; 1587 } 1588 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1589 &chip9->lpc.xscom_regs); 1590 1591 chip->fw_mr = &chip9->lpc.isa_fw; 1592 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1593 (uint64_t) PNV9_LPCM_BASE(chip)); 1594 1595 /* ChipTOD */ 1596 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1597 chip->chip_id == 0, &error_abort); 1598 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1599 chip->chip_id == 1, &error_abort); 1600 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1601 &error_abort); 1602 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1603 return; 1604 } 1605 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1606 &chip9->chiptod.xscom_regs); 1607 1608 /* Create the simplified OCC model */ 1609 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1610 return; 1611 } 1612 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1613 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1614 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1615 1616 /* OCC SRAM model */ 1617 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1618 &chip9->occ.sram_regs); 1619 1620 /* SBE */ 1621 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1622 return; 1623 } 1624 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1625 &chip9->sbe.xscom_ctrl_regs); 1626 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1627 &chip9->sbe.xscom_mbox_regs); 1628 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1629 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1630 1631 /* HOMER */ 1632 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1633 &error_abort); 1634 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1635 return; 1636 } 1637 /* Homer Xscom region */ 1638 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1639 1640 /* Homer mmio region */ 1641 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1642 &chip9->homer.regs); 1643 1644 /* PEC PHBs */ 1645 pnv_chip_power9_pec_realize(chip, &local_err); 1646 if (local_err) { 1647 error_propagate(errp, local_err); 1648 return; 1649 } 1650 1651 /* 1652 * I2C 1653 */ 1654 for (i = 0; i < pcc->i2c_num_engines; i++) { 1655 Object *obj = OBJECT(&chip9->i2c[i]); 1656 1657 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1658 object_property_set_int(obj, "num-busses", 1659 pcc->i2c_ports_per_engine[i], 1660 &error_fatal); 1661 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1662 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1663 return; 1664 } 1665 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1666 (chip9->i2c[i].engine - 1) * 1667 PNV9_XSCOM_I2CM_SIZE, 1668 &chip9->i2c[i].xscom_regs); 1669 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1670 qdev_get_gpio_in(DEVICE(&chip9->psi), 1671 PSIHB9_IRQ_SBE_I2C)); 1672 } 1673 } 1674 1675 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1676 { 1677 addr &= (PNV9_XSCOM_SIZE - 1); 1678 return addr >> 3; 1679 } 1680 1681 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1682 { 1683 DeviceClass *dc = DEVICE_CLASS(klass); 1684 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1685 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1686 1687 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1688 k->cores_mask = POWER9_CORE_MASK; 1689 k->core_pir = pnv_chip_core_pir_p9; 1690 k->intc_create = pnv_chip_power9_intc_create; 1691 k->intc_reset = pnv_chip_power9_intc_reset; 1692 k->intc_destroy = pnv_chip_power9_intc_destroy; 1693 k->intc_print_info = pnv_chip_power9_intc_print_info; 1694 k->isa_create = pnv_chip_power9_isa_create; 1695 k->dt_populate = pnv_chip_power9_dt_populate; 1696 k->pic_print_info = pnv_chip_power9_pic_print_info; 1697 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1698 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1699 dc->desc = "PowerNV Chip POWER9"; 1700 k->num_pecs = PNV9_CHIP_MAX_PEC; 1701 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1702 k->i2c_ports_per_engine = i2c_ports_per_engine; 1703 1704 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1705 &k->parent_realize); 1706 } 1707 1708 static void pnv_chip_power10_instance_init(Object *obj) 1709 { 1710 PnvChip *chip = PNV_CHIP(obj); 1711 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1712 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1713 int i; 1714 1715 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1716 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1717 "xive-fabric"); 1718 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1719 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1720 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1721 TYPE_PNV10_CHIPTOD); 1722 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1723 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1724 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1725 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1726 TYPE_PNV_N1_CHIPLET); 1727 1728 chip->num_pecs = pcc->num_pecs; 1729 1730 for (i = 0; i < chip->num_pecs; i++) { 1731 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1732 TYPE_PNV_PHB5_PEC); 1733 } 1734 1735 for (i = 0; i < pcc->i2c_num_engines; i++) { 1736 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1737 } 1738 } 1739 1740 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1741 { 1742 PnvChip *chip = PNV_CHIP(chip10); 1743 int i; 1744 1745 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1746 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1747 1748 for (i = 0; i < chip10->nr_quads; i++) { 1749 PnvQuad *eq = &chip10->quads[i]; 1750 1751 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1752 PNV_QUAD_TYPE_NAME("power10")); 1753 1754 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1755 &eq->xscom_regs); 1756 1757 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1758 &eq->xscom_qme_regs); 1759 } 1760 } 1761 1762 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1763 { 1764 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1765 int i; 1766 1767 for (i = 0; i < chip->num_pecs; i++) { 1768 PnvPhb4PecState *pec = &chip10->pecs[i]; 1769 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1770 uint32_t pec_nest_base; 1771 uint32_t pec_pci_base; 1772 1773 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1774 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1775 &error_fatal); 1776 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1777 &error_fatal); 1778 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1779 return; 1780 } 1781 1782 pec_nest_base = pecc->xscom_nest_base(pec); 1783 pec_pci_base = pecc->xscom_pci_base(pec); 1784 1785 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1786 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1787 } 1788 } 1789 1790 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1791 { 1792 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1793 PnvChip *chip = PNV_CHIP(dev); 1794 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1795 Error *local_err = NULL; 1796 int i; 1797 1798 /* XSCOM bridge is first */ 1799 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1800 1801 pcc->parent_realize(dev, &local_err); 1802 if (local_err) { 1803 error_propagate(errp, local_err); 1804 return; 1805 } 1806 1807 pnv_chip_power10_quad_realize(chip10, &local_err); 1808 if (local_err) { 1809 error_propagate(errp, local_err); 1810 return; 1811 } 1812 1813 /* XIVE2 interrupt controller (POWER10) */ 1814 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1815 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1816 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1817 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1818 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1819 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1820 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1821 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1822 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1823 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1824 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1825 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1826 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1827 &error_abort); 1828 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1829 return; 1830 } 1831 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1832 &chip10->xive.xscom_regs); 1833 1834 /* Processor Service Interface (PSI) Host Bridge */ 1835 object_property_set_int(OBJECT(&chip10->psi), "bar", 1836 PNV10_PSIHB_BASE(chip), &error_fatal); 1837 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1838 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1839 &error_fatal); 1840 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1841 return; 1842 } 1843 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1844 &PNV_PSI(&chip10->psi)->xscom_regs); 1845 1846 /* LPC */ 1847 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1848 return; 1849 } 1850 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1851 &chip10->lpc.xscom_regs); 1852 1853 chip->fw_mr = &chip10->lpc.isa_fw; 1854 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1855 (uint64_t) PNV10_LPCM_BASE(chip)); 1856 1857 /* ChipTOD */ 1858 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1859 chip->chip_id == 0, &error_abort); 1860 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1861 chip->chip_id == 1, &error_abort); 1862 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 1863 &error_abort); 1864 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 1865 return; 1866 } 1867 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 1868 &chip10->chiptod.xscom_regs); 1869 1870 /* Create the simplified OCC model */ 1871 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1872 return; 1873 } 1874 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1875 &chip10->occ.xscom_regs); 1876 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1877 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1878 1879 /* OCC SRAM model */ 1880 memory_region_add_subregion(get_system_memory(), 1881 PNV10_OCC_SENSOR_BASE(chip), 1882 &chip10->occ.sram_regs); 1883 1884 /* SBE */ 1885 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1886 return; 1887 } 1888 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1889 &chip10->sbe.xscom_ctrl_regs); 1890 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1891 &chip10->sbe.xscom_mbox_regs); 1892 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1893 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1894 1895 /* HOMER */ 1896 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1897 &error_abort); 1898 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1899 return; 1900 } 1901 /* Homer Xscom region */ 1902 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1903 &chip10->homer.pba_regs); 1904 1905 /* Homer mmio region */ 1906 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1907 &chip10->homer.regs); 1908 1909 /* N1 chiplet */ 1910 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 1911 return; 1912 } 1913 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 1914 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 1915 1916 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 1917 &chip10->n1_chiplet.xscom_pb_eq_mr); 1918 1919 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 1920 &chip10->n1_chiplet.xscom_pb_es_mr); 1921 1922 /* PHBs */ 1923 pnv_chip_power10_phb_realize(chip, &local_err); 1924 if (local_err) { 1925 error_propagate(errp, local_err); 1926 return; 1927 } 1928 1929 1930 /* 1931 * I2C 1932 */ 1933 for (i = 0; i < pcc->i2c_num_engines; i++) { 1934 Object *obj = OBJECT(&chip10->i2c[i]); 1935 1936 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1937 object_property_set_int(obj, "num-busses", 1938 pcc->i2c_ports_per_engine[i], 1939 &error_fatal); 1940 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1941 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1942 return; 1943 } 1944 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 1945 (chip10->i2c[i].engine - 1) * 1946 PNV10_XSCOM_I2CM_SIZE, 1947 &chip10->i2c[i].xscom_regs); 1948 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 1949 qdev_get_gpio_in(DEVICE(&chip10->psi), 1950 PSIHB9_IRQ_SBE_I2C)); 1951 } 1952 1953 } 1954 1955 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 1956 { 1957 int i; 1958 for (i = 0; i < pnv->num_chips; i++) { 1959 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 1960 1961 /* 1962 * Add a PCA9552 I2C device for PCIe hotplug control 1963 * to engine 2, bus 1, address 0x63 1964 */ 1965 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 1966 "pca9552", 0x63); 1967 1968 /* 1969 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 1970 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 1971 * after hypervisor code sets a SLOTx_EN pin high. 1972 */ 1973 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 1974 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 1975 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 1976 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 1977 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 1978 1979 /* 1980 * Add a PCA9554 I2C device for cable card presence detection 1981 * to engine 2, bus 1, address 0x25 1982 */ 1983 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 1984 } 1985 } 1986 1987 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1988 { 1989 addr &= (PNV10_XSCOM_SIZE - 1); 1990 return addr >> 3; 1991 } 1992 1993 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1994 { 1995 DeviceClass *dc = DEVICE_CLASS(klass); 1996 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1997 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 1998 1999 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 2000 k->cores_mask = POWER10_CORE_MASK; 2001 k->core_pir = pnv_chip_core_pir_p10; 2002 k->intc_create = pnv_chip_power10_intc_create; 2003 k->intc_reset = pnv_chip_power10_intc_reset; 2004 k->intc_destroy = pnv_chip_power10_intc_destroy; 2005 k->intc_print_info = pnv_chip_power10_intc_print_info; 2006 k->isa_create = pnv_chip_power10_isa_create; 2007 k->dt_populate = pnv_chip_power10_dt_populate; 2008 k->pic_print_info = pnv_chip_power10_pic_print_info; 2009 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2010 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2011 dc->desc = "PowerNV Chip POWER10"; 2012 k->num_pecs = PNV10_CHIP_MAX_PEC; 2013 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2014 k->i2c_ports_per_engine = i2c_ports_per_engine; 2015 2016 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2017 &k->parent_realize); 2018 } 2019 2020 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2021 { 2022 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2023 int cores_max; 2024 2025 /* 2026 * No custom mask for this chip, let's use the default one from * 2027 * the chip class 2028 */ 2029 if (!chip->cores_mask) { 2030 chip->cores_mask = pcc->cores_mask; 2031 } 2032 2033 /* filter alien core ids ! some are reserved */ 2034 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2035 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2036 chip->cores_mask); 2037 return; 2038 } 2039 chip->cores_mask &= pcc->cores_mask; 2040 2041 /* now that we have a sane layout, let check the number of cores */ 2042 cores_max = ctpop64(chip->cores_mask); 2043 if (chip->nr_cores > cores_max) { 2044 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2045 cores_max); 2046 return; 2047 } 2048 } 2049 2050 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2051 { 2052 Error *error = NULL; 2053 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2054 const char *typename = pnv_chip_core_typename(chip); 2055 int i, core_hwid; 2056 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2057 2058 if (!object_class_by_name(typename)) { 2059 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2060 return; 2061 } 2062 2063 /* Cores */ 2064 pnv_chip_core_sanitize(chip, &error); 2065 if (error) { 2066 error_propagate(errp, error); 2067 return; 2068 } 2069 2070 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2071 2072 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2073 && (i < chip->nr_cores); core_hwid++) { 2074 char core_name[32]; 2075 PnvCore *pnv_core; 2076 uint64_t xscom_core_base; 2077 2078 if (!(chip->cores_mask & (1ull << core_hwid))) { 2079 continue; 2080 } 2081 2082 pnv_core = PNV_CORE(object_new(typename)); 2083 2084 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2085 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2086 chip->cores[i] = pnv_core; 2087 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2088 chip->nr_threads, &error_fatal); 2089 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2090 core_hwid, &error_fatal); 2091 object_property_set_int(OBJECT(pnv_core), "pir", 2092 pcc->core_pir(chip, core_hwid), &error_fatal); 2093 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2094 &error_fatal); 2095 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2096 &error_abort); 2097 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2098 2099 /* Each core has an XSCOM MMIO region */ 2100 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2101 2102 pnv_xscom_add_subregion(chip, xscom_core_base, 2103 &pnv_core->xscom_regs); 2104 i++; 2105 } 2106 } 2107 2108 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2109 { 2110 PnvChip *chip = PNV_CHIP(dev); 2111 Error *error = NULL; 2112 2113 /* Cores */ 2114 pnv_chip_core_realize(chip, &error); 2115 if (error) { 2116 error_propagate(errp, error); 2117 return; 2118 } 2119 } 2120 2121 static Property pnv_chip_properties[] = { 2122 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2123 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2124 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2125 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2126 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2127 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2128 DEFINE_PROP_END_OF_LIST(), 2129 }; 2130 2131 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2132 { 2133 DeviceClass *dc = DEVICE_CLASS(klass); 2134 2135 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2136 dc->realize = pnv_chip_realize; 2137 device_class_set_props(dc, pnv_chip_properties); 2138 dc->desc = "PowerNV Chip"; 2139 } 2140 2141 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2142 { 2143 int i; 2144 2145 for (i = 0; i < chip->nr_cores; i++) { 2146 PnvCore *pc = chip->cores[i]; 2147 CPUCore *cc = CPU_CORE(pc); 2148 2149 if (cc->core_id == core_id) { 2150 return pc; 2151 } 2152 } 2153 return NULL; 2154 } 2155 2156 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2157 { 2158 int i, j; 2159 2160 for (i = 0; i < chip->nr_cores; i++) { 2161 PnvCore *pc = chip->cores[i]; 2162 CPUCore *cc = CPU_CORE(pc); 2163 2164 for (j = 0; j < cc->nr_threads; j++) { 2165 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2166 return pc->threads[j]; 2167 } 2168 } 2169 } 2170 return NULL; 2171 } 2172 2173 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2174 { 2175 PnvMachineState *pnv = PNV_MACHINE(xi); 2176 int i, j; 2177 2178 for (i = 0; i < pnv->num_chips; i++) { 2179 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2180 2181 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2182 return &chip8->psi.ics; 2183 } 2184 2185 for (j = 0; j < chip8->num_phbs; j++) { 2186 PnvPHB *phb = chip8->phbs[j]; 2187 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2188 2189 if (ics_valid_irq(&phb3->lsis, irq)) { 2190 return &phb3->lsis; 2191 } 2192 2193 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2194 return ICS(&phb3->msis); 2195 } 2196 } 2197 } 2198 return NULL; 2199 } 2200 2201 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2202 { 2203 int i; 2204 2205 for (i = 0; i < pnv->num_chips; i++) { 2206 PnvChip *chip = pnv->chips[i]; 2207 if (chip->chip_id == chip_id) { 2208 return chip; 2209 } 2210 } 2211 return NULL; 2212 } 2213 2214 static void pnv_ics_resend(XICSFabric *xi) 2215 { 2216 PnvMachineState *pnv = PNV_MACHINE(xi); 2217 int i, j; 2218 2219 for (i = 0; i < pnv->num_chips; i++) { 2220 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2221 2222 ics_resend(&chip8->psi.ics); 2223 2224 for (j = 0; j < chip8->num_phbs; j++) { 2225 PnvPHB *phb = chip8->phbs[j]; 2226 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2227 2228 ics_resend(&phb3->lsis); 2229 ics_resend(ICS(&phb3->msis)); 2230 } 2231 } 2232 } 2233 2234 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2235 { 2236 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2237 2238 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2239 } 2240 2241 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2242 Monitor *mon) 2243 { 2244 PnvMachineState *pnv = PNV_MACHINE(obj); 2245 int i; 2246 CPUState *cs; 2247 2248 CPU_FOREACH(cs) { 2249 PowerPCCPU *cpu = POWERPC_CPU(cs); 2250 2251 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2252 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2253 mon); 2254 } 2255 2256 for (i = 0; i < pnv->num_chips; i++) { 2257 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2258 } 2259 } 2260 2261 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2262 uint8_t nvt_blk, uint32_t nvt_idx, 2263 bool cam_ignore, uint8_t priority, 2264 uint32_t logic_serv, 2265 XiveTCTXMatch *match) 2266 { 2267 PnvMachineState *pnv = PNV_MACHINE(xfb); 2268 int total_count = 0; 2269 int i; 2270 2271 for (i = 0; i < pnv->num_chips; i++) { 2272 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2273 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2274 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2275 int count; 2276 2277 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2278 priority, logic_serv, match); 2279 2280 if (count < 0) { 2281 return count; 2282 } 2283 2284 total_count += count; 2285 } 2286 2287 return total_count; 2288 } 2289 2290 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2291 uint8_t nvt_blk, uint32_t nvt_idx, 2292 bool cam_ignore, uint8_t priority, 2293 uint32_t logic_serv, 2294 XiveTCTXMatch *match) 2295 { 2296 PnvMachineState *pnv = PNV_MACHINE(xfb); 2297 int total_count = 0; 2298 int i; 2299 2300 for (i = 0; i < pnv->num_chips; i++) { 2301 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2302 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2303 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2304 int count; 2305 2306 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2307 priority, logic_serv, match); 2308 2309 if (count < 0) { 2310 return count; 2311 } 2312 2313 total_count += count; 2314 } 2315 2316 return total_count; 2317 } 2318 2319 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2320 { 2321 MachineClass *mc = MACHINE_CLASS(oc); 2322 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2323 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2324 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2325 2326 static GlobalProperty phb_compat[] = { 2327 { TYPE_PNV_PHB, "version", "3" }, 2328 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2329 }; 2330 2331 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2332 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2333 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2334 2335 xic->icp_get = pnv_icp_get; 2336 xic->ics_get = pnv_ics_get; 2337 xic->ics_resend = pnv_ics_resend; 2338 2339 pmc->compat = compat; 2340 pmc->compat_size = sizeof(compat); 2341 2342 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2343 } 2344 2345 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2346 { 2347 MachineClass *mc = MACHINE_CLASS(oc); 2348 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2349 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2350 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2351 2352 static GlobalProperty phb_compat[] = { 2353 { TYPE_PNV_PHB, "version", "4" }, 2354 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2355 }; 2356 2357 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2358 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2359 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2360 2361 xfc->match_nvt = pnv_match_nvt; 2362 2363 pmc->compat = compat; 2364 pmc->compat_size = sizeof(compat); 2365 pmc->dt_power_mgt = pnv_dt_power_mgt; 2366 2367 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2368 } 2369 2370 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2371 { 2372 MachineClass *mc = MACHINE_CLASS(oc); 2373 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2374 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2375 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2376 2377 static GlobalProperty phb_compat[] = { 2378 { TYPE_PNV_PHB, "version", "5" }, 2379 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2380 }; 2381 2382 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2383 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2384 2385 mc->alias = "powernv"; 2386 2387 pmc->compat = compat; 2388 pmc->compat_size = sizeof(compat); 2389 pmc->dt_power_mgt = pnv_dt_power_mgt; 2390 2391 xfc->match_nvt = pnv10_xive_match_nvt; 2392 2393 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2394 } 2395 2396 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2397 { 2398 MachineClass *mc = MACHINE_CLASS(oc); 2399 2400 pnv_machine_p10_common_class_init(oc, data); 2401 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2402 } 2403 2404 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2405 { 2406 MachineClass *mc = MACHINE_CLASS(oc); 2407 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2408 2409 pnv_machine_p10_common_class_init(oc, data); 2410 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2411 pmc->i2c_init = pnv_rainier_i2c_init; 2412 } 2413 2414 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2415 { 2416 PnvMachineState *pnv = PNV_MACHINE(obj); 2417 2418 return !!pnv->fw_load_addr; 2419 } 2420 2421 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2422 { 2423 PnvMachineState *pnv = PNV_MACHINE(obj); 2424 2425 if (value) { 2426 pnv->fw_load_addr = 0x8000000; 2427 } 2428 } 2429 2430 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2431 { 2432 PowerPCCPU *cpu = POWERPC_CPU(cs); 2433 CPUPPCState *env = &cpu->env; 2434 2435 cpu_synchronize_state(cs); 2436 ppc_cpu_do_system_reset(cs); 2437 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2438 /* 2439 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2440 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2441 * (PPC_BIT(43)). 2442 */ 2443 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2444 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2445 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2446 } 2447 } else { 2448 /* 2449 * For non-powersave system resets, SRR1[42:45] are defined to be 2450 * implementation-dependent. The POWER9 User Manual specifies that 2451 * an external (SCOM driven, which may come from a BMC nmi command or 2452 * another CPU requesting a NMI IPI) system reset exception should be 2453 * 0b0010 (PPC_BIT(44)). 2454 */ 2455 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2456 } 2457 } 2458 2459 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2460 { 2461 CPUState *cs; 2462 2463 CPU_FOREACH(cs) { 2464 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2465 } 2466 } 2467 2468 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2469 { 2470 MachineClass *mc = MACHINE_CLASS(oc); 2471 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2472 NMIClass *nc = NMI_CLASS(oc); 2473 2474 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2475 mc->init = pnv_init; 2476 mc->reset = pnv_reset; 2477 mc->max_cpus = MAX_CPUS; 2478 /* Pnv provides a AHCI device for storage */ 2479 mc->block_default_type = IF_IDE; 2480 mc->no_parallel = 1; 2481 mc->default_boot_order = NULL; 2482 /* 2483 * RAM defaults to less than 2048 for 32-bit hosts, and large 2484 * enough to fit the maximum initrd size at it's load address 2485 */ 2486 mc->default_ram_size = 1 * GiB; 2487 mc->default_ram_id = "pnv.ram"; 2488 ispc->print_info = pnv_pic_print_info; 2489 nc->nmi_monitor_handler = pnv_nmi; 2490 2491 object_class_property_add_bool(oc, "hb-mode", 2492 pnv_machine_get_hb, pnv_machine_set_hb); 2493 object_class_property_set_description(oc, "hb-mode", 2494 "Use a hostboot like boot loader"); 2495 } 2496 2497 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2498 { \ 2499 .name = type, \ 2500 .class_init = class_initfn, \ 2501 .parent = TYPE_PNV8_CHIP, \ 2502 } 2503 2504 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2505 { \ 2506 .name = type, \ 2507 .class_init = class_initfn, \ 2508 .parent = TYPE_PNV9_CHIP, \ 2509 } 2510 2511 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2512 { \ 2513 .name = type, \ 2514 .class_init = class_initfn, \ 2515 .parent = TYPE_PNV10_CHIP, \ 2516 } 2517 2518 static const TypeInfo types[] = { 2519 { 2520 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2521 .parent = MACHINE_TYPE_NAME("powernv10"), 2522 .class_init = pnv_machine_p10_rainier_class_init, 2523 }, 2524 { 2525 .name = MACHINE_TYPE_NAME("powernv10"), 2526 .parent = TYPE_PNV_MACHINE, 2527 .class_init = pnv_machine_power10_class_init, 2528 .interfaces = (InterfaceInfo[]) { 2529 { TYPE_XIVE_FABRIC }, 2530 { }, 2531 }, 2532 }, 2533 { 2534 .name = MACHINE_TYPE_NAME("powernv9"), 2535 .parent = TYPE_PNV_MACHINE, 2536 .class_init = pnv_machine_power9_class_init, 2537 .interfaces = (InterfaceInfo[]) { 2538 { TYPE_XIVE_FABRIC }, 2539 { }, 2540 }, 2541 }, 2542 { 2543 .name = MACHINE_TYPE_NAME("powernv8"), 2544 .parent = TYPE_PNV_MACHINE, 2545 .class_init = pnv_machine_power8_class_init, 2546 .interfaces = (InterfaceInfo[]) { 2547 { TYPE_XICS_FABRIC }, 2548 { }, 2549 }, 2550 }, 2551 { 2552 .name = TYPE_PNV_MACHINE, 2553 .parent = TYPE_MACHINE, 2554 .abstract = true, 2555 .instance_size = sizeof(PnvMachineState), 2556 .class_init = pnv_machine_class_init, 2557 .class_size = sizeof(PnvMachineClass), 2558 .interfaces = (InterfaceInfo[]) { 2559 { TYPE_INTERRUPT_STATS_PROVIDER }, 2560 { TYPE_NMI }, 2561 { }, 2562 }, 2563 }, 2564 { 2565 .name = TYPE_PNV_CHIP, 2566 .parent = TYPE_SYS_BUS_DEVICE, 2567 .class_init = pnv_chip_class_init, 2568 .instance_size = sizeof(PnvChip), 2569 .class_size = sizeof(PnvChipClass), 2570 .abstract = true, 2571 }, 2572 2573 /* 2574 * P10 chip and variants 2575 */ 2576 { 2577 .name = TYPE_PNV10_CHIP, 2578 .parent = TYPE_PNV_CHIP, 2579 .instance_init = pnv_chip_power10_instance_init, 2580 .instance_size = sizeof(Pnv10Chip), 2581 }, 2582 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2583 2584 /* 2585 * P9 chip and variants 2586 */ 2587 { 2588 .name = TYPE_PNV9_CHIP, 2589 .parent = TYPE_PNV_CHIP, 2590 .instance_init = pnv_chip_power9_instance_init, 2591 .instance_size = sizeof(Pnv9Chip), 2592 }, 2593 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2594 2595 /* 2596 * P8 chip and variants 2597 */ 2598 { 2599 .name = TYPE_PNV8_CHIP, 2600 .parent = TYPE_PNV_CHIP, 2601 .instance_init = pnv_chip_power8_instance_init, 2602 .instance_size = sizeof(Pnv8Chip), 2603 }, 2604 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2605 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2606 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2607 pnv_chip_power8nvl_class_init), 2608 }; 2609 2610 DEFINE_TYPES(types) 2611