1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 #include "hw/ppc/pnv_pnor.h" 48 49 #include "hw/isa/isa.h" 50 #include "hw/boards.h" 51 #include "hw/char/serial.h" 52 #include "hw/rtc/mc146818rtc.h" 53 54 #include <libfdt.h> 55 56 #define FDT_MAX_SIZE (1 * MiB) 57 58 #define FW_FILE_NAME "skiboot.lid" 59 #define FW_LOAD_ADDR 0x0 60 #define FW_MAX_SIZE (4 * MiB) 61 62 #define KERNEL_LOAD_ADDR 0x20000000 63 #define KERNEL_MAX_SIZE (256 * MiB) 64 #define INITRD_LOAD_ADDR 0x60000000 65 #define INITRD_MAX_SIZE (256 * MiB) 66 67 static const char *pnv_chip_core_typename(const PnvChip *o) 68 { 69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 72 const char *core_type = object_class_get_name(object_class_by_name(s)); 73 g_free(s); 74 return core_type; 75 } 76 77 /* 78 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 79 * 4 * 4 sockets * 12 cores * 8 threads = 1536 80 * Let's make it 2^11 81 */ 82 #define MAX_CPUS 2048 83 84 /* 85 * Memory nodes are created by hostboot, one for each range of memory 86 * that has a different "affinity". In practice, it means one range 87 * per chip. 88 */ 89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 90 { 91 char *mem_name; 92 uint64_t mem_reg_property[2]; 93 int off; 94 95 mem_reg_property[0] = cpu_to_be64(start); 96 mem_reg_property[1] = cpu_to_be64(size); 97 98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 99 off = fdt_add_subnode(fdt, 0, mem_name); 100 g_free(mem_name); 101 102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 104 sizeof(mem_reg_property)))); 105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 106 } 107 108 static int get_cpus_node(void *fdt) 109 { 110 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 111 112 if (cpus_offset < 0) { 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 114 if (cpus_offset) { 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 117 } 118 } 119 _FDT(cpus_offset); 120 return cpus_offset; 121 } 122 123 /* 124 * The PowerNV cores (and threads) need to use real HW ids and not an 125 * incremental index like it has been done on other platforms. This HW 126 * id is stored in the CPU PIR, it is used to create cpu nodes in the 127 * device tree, used in XSCOM to address cores and in interrupt 128 * servers. 129 */ 130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 131 { 132 PowerPCCPU *cpu = pc->threads[0]; 133 CPUState *cs = CPU(cpu); 134 DeviceClass *dc = DEVICE_GET_CLASS(cs); 135 int smt_threads = CPU_CORE(pc)->nr_threads; 136 CPUPPCState *env = &cpu->env; 137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 138 uint32_t servers_prop[smt_threads]; 139 int i; 140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 141 0xffffffff, 0xffffffff}; 142 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 143 uint32_t cpufreq = 1000000000; 144 uint32_t page_sizes_prop[64]; 145 size_t page_sizes_prop_size; 146 const uint8_t pa_features[] = { 24, 0, 147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 151 int offset; 152 char *nodename; 153 int cpus_offset = get_cpus_node(fdt); 154 155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 156 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 157 _FDT(offset); 158 g_free(nodename); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 172 env->icache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 174 env->icache_line_size))); 175 176 if (pcc->l1_dcache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 178 pcc->l1_dcache_size))); 179 } else { 180 warn_report("Unknown L1 dcache size for cpu"); 181 } 182 if (pcc->l1_icache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 184 pcc->l1_icache_size))); 185 } else { 186 warn_report("Unknown L1 icache size for cpu"); 187 } 188 189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 192 cpu->hash64_opts->slb_size))); 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 195 196 if (env->spr_cb[SPR_PURR].oea_read) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 198 } 199 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 202 segs, sizeof(segs)))); 203 } 204 205 /* 206 * Advertise VMX/VSX (vector extensions) if available 207 * 0 / no property == no vector extensions 208 * 1 == VMX / Altivec available 209 * 2 == VSX available 210 */ 211 if (env->insns_flags & PPC_ALTIVEC) { 212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 213 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 215 } 216 217 /* 218 * Advertise DFP (Decimal Floating Point) if available 219 * 0 / no property == no DFP 220 * 1 == DFP available 221 */ 222 if (env->insns_flags2 & PPC2_DFP) { 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 224 } 225 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 227 sizeof(page_sizes_prop)); 228 if (page_sizes_prop_size) { 229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 230 page_sizes_prop, page_sizes_prop_size))); 231 } 232 233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 234 pa_features, sizeof(pa_features)))); 235 236 /* Build interrupt servers properties */ 237 for (i = 0; i < smt_threads; i++) { 238 servers_prop[i] = cpu_to_be32(pc->pir + i); 239 } 240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 241 servers_prop, sizeof(servers_prop)))); 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 282 { 283 const char *typename = pnv_chip_core_typename(chip); 284 size_t typesize = object_type_get_instance_size(typename); 285 int i; 286 287 pnv_dt_xscom(chip, fdt, 0); 288 289 for (i = 0; i < chip->nr_cores; i++) { 290 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 291 292 pnv_dt_core(chip, pnv_core, fdt); 293 294 /* Interrupt Control Presenters (ICP). One per core. */ 295 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 296 } 297 298 if (chip->ram_size) { 299 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 300 } 301 } 302 303 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 304 { 305 const char *typename = pnv_chip_core_typename(chip); 306 size_t typesize = object_type_get_instance_size(typename); 307 int i; 308 309 pnv_dt_xscom(chip, fdt, 0); 310 311 for (i = 0; i < chip->nr_cores; i++) { 312 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 313 314 pnv_dt_core(chip, pnv_core, fdt); 315 } 316 317 if (chip->ram_size) { 318 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 319 } 320 321 pnv_dt_lpc(chip, fdt, 0); 322 } 323 324 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 325 { 326 uint32_t io_base = d->ioport_id; 327 uint32_t io_regs[] = { 328 cpu_to_be32(1), 329 cpu_to_be32(io_base), 330 cpu_to_be32(2) 331 }; 332 char *name; 333 int node; 334 335 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 336 node = fdt_add_subnode(fdt, lpc_off, name); 337 _FDT(node); 338 g_free(name); 339 340 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 341 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 342 } 343 344 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 345 { 346 const char compatible[] = "ns16550\0pnpPNP,501"; 347 uint32_t io_base = d->ioport_id; 348 uint32_t io_regs[] = { 349 cpu_to_be32(1), 350 cpu_to_be32(io_base), 351 cpu_to_be32(8) 352 }; 353 char *name; 354 int node; 355 356 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 357 node = fdt_add_subnode(fdt, lpc_off, name); 358 _FDT(node); 359 g_free(name); 360 361 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 362 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 363 sizeof(compatible)))); 364 365 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 366 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 367 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 368 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 369 fdt_get_phandle(fdt, lpc_off)))); 370 371 /* This is needed by Linux */ 372 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 373 } 374 375 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 376 { 377 const char compatible[] = "bt\0ipmi-bt"; 378 uint32_t io_base; 379 uint32_t io_regs[] = { 380 cpu_to_be32(1), 381 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 382 cpu_to_be32(3) 383 }; 384 uint32_t irq; 385 char *name; 386 int node; 387 388 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 389 io_regs[1] = cpu_to_be32(io_base); 390 391 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 392 393 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 394 node = fdt_add_subnode(fdt, lpc_off, name); 395 _FDT(node); 396 g_free(name); 397 398 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 399 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 400 sizeof(compatible)))); 401 402 /* Mark it as reserved to avoid Linux trying to claim it */ 403 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 404 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 405 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 406 fdt_get_phandle(fdt, lpc_off)))); 407 } 408 409 typedef struct ForeachPopulateArgs { 410 void *fdt; 411 int offset; 412 } ForeachPopulateArgs; 413 414 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 415 { 416 ForeachPopulateArgs *args = opaque; 417 ISADevice *d = ISA_DEVICE(dev); 418 419 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 420 pnv_dt_rtc(d, args->fdt, args->offset); 421 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 422 pnv_dt_serial(d, args->fdt, args->offset); 423 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 424 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 425 } else { 426 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 427 d->ioport_id); 428 } 429 430 return 0; 431 } 432 433 /* 434 * The default LPC bus of a multichip system is on chip 0. It's 435 * recognized by the firmware (skiboot) using a "primary" property. 436 */ 437 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 438 { 439 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 440 ForeachPopulateArgs args = { 441 .fdt = fdt, 442 .offset = isa_offset, 443 }; 444 uint32_t phandle; 445 446 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 447 448 phandle = qemu_fdt_alloc_phandle(fdt); 449 assert(phandle > 0); 450 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 451 452 /* 453 * ISA devices are not necessarily parented to the ISA bus so we 454 * can not use object_child_foreach() 455 */ 456 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 457 &args); 458 } 459 460 static void pnv_dt_power_mgt(void *fdt) 461 { 462 int off; 463 464 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 465 off = fdt_add_subnode(fdt, off, "power-mgt"); 466 467 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 468 } 469 470 static void *pnv_dt_create(MachineState *machine) 471 { 472 const char plat_compat8[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 473 const char plat_compat9[] = "qemu,powernv9\0ibm,powernv"; 474 PnvMachineState *pnv = PNV_MACHINE(machine); 475 void *fdt; 476 char *buf; 477 int off; 478 int i; 479 480 fdt = g_malloc0(FDT_MAX_SIZE); 481 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 482 483 /* /qemu node */ 484 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 485 486 /* Root node */ 487 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 488 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 489 _FDT((fdt_setprop_string(fdt, 0, "model", 490 "IBM PowerNV (emulated by qemu)"))); 491 if (pnv_is_power9(pnv)) { 492 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, 493 sizeof(plat_compat9)))); 494 } else { 495 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, 496 sizeof(plat_compat8)))); 497 } 498 499 500 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 501 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 502 if (qemu_uuid_set) { 503 _FDT((fdt_property_string(fdt, "system-id", buf))); 504 } 505 g_free(buf); 506 507 off = fdt_add_subnode(fdt, 0, "chosen"); 508 if (machine->kernel_cmdline) { 509 _FDT((fdt_setprop_string(fdt, off, "bootargs", 510 machine->kernel_cmdline))); 511 } 512 513 if (pnv->initrd_size) { 514 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 515 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 516 517 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 518 &start_prop, sizeof(start_prop)))); 519 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 520 &end_prop, sizeof(end_prop)))); 521 } 522 523 /* Populate device tree for each chip */ 524 for (i = 0; i < pnv->num_chips; i++) { 525 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 526 } 527 528 /* Populate ISA devices on chip 0 */ 529 pnv_dt_isa(pnv, fdt); 530 531 if (pnv->bmc) { 532 pnv_dt_bmc_sensors(pnv->bmc, fdt); 533 } 534 535 /* Create an extra node for power management on Power9 */ 536 if (pnv_is_power9(pnv)) { 537 pnv_dt_power_mgt(fdt); 538 } 539 540 return fdt; 541 } 542 543 static void pnv_powerdown_notify(Notifier *n, void *opaque) 544 { 545 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 546 547 if (pnv->bmc) { 548 pnv_bmc_powerdown(pnv->bmc); 549 } 550 } 551 552 static void pnv_reset(MachineState *machine) 553 { 554 PnvMachineState *pnv = PNV_MACHINE(machine); 555 void *fdt; 556 Object *obj; 557 558 qemu_devices_reset(); 559 560 /* 561 * OpenPOWER systems have a BMC, which can be defined on the 562 * command line with: 563 * 564 * -device ipmi-bmc-sim,id=bmc0 565 * 566 * This is the internal simulator but it could also be an external 567 * BMC. 568 */ 569 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 570 if (obj) { 571 pnv->bmc = IPMI_BMC(obj); 572 pnv_bmc_hiomap(pnv->bmc); 573 } 574 575 fdt = pnv_dt_create(machine); 576 577 /* Pack resulting tree */ 578 _FDT((fdt_pack(fdt))); 579 580 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 581 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 582 } 583 584 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 585 { 586 Pnv8Chip *chip8 = PNV8_CHIP(chip); 587 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 588 } 589 590 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 591 { 592 Pnv8Chip *chip8 = PNV8_CHIP(chip); 593 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 594 } 595 596 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 597 { 598 Pnv9Chip *chip9 = PNV9_CHIP(chip); 599 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 600 } 601 602 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 603 { 604 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 605 } 606 607 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 608 { 609 Pnv8Chip *chip8 = PNV8_CHIP(chip); 610 611 ics_pic_print_info(&chip8->psi.ics, mon); 612 } 613 614 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 615 { 616 Pnv9Chip *chip9 = PNV9_CHIP(chip); 617 618 pnv_xive_pic_print_info(&chip9->xive, mon); 619 pnv_psi_pic_print_info(&chip9->psi, mon); 620 } 621 622 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 623 { 624 PowerPCCPUClass *ppc_default = 625 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 626 PowerPCCPUClass *ppc = 627 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 628 629 return ppc_default->pvr_match(ppc_default, ppc->pvr); 630 } 631 632 static void pnv_init(MachineState *machine) 633 { 634 PnvMachineState *pnv = PNV_MACHINE(machine); 635 MachineClass *mc = MACHINE_GET_CLASS(machine); 636 MemoryRegion *ram; 637 char *fw_filename; 638 long fw_size; 639 int i; 640 char *chip_typename; 641 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 642 DeviceState *dev; 643 644 /* allocate RAM */ 645 if (machine->ram_size < (1 * GiB)) { 646 warn_report("skiboot may not work with < 1GB of RAM"); 647 } 648 649 ram = g_new(MemoryRegion, 1); 650 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 651 machine->ram_size); 652 memory_region_add_subregion(get_system_memory(), 0, ram); 653 654 /* 655 * Create our simple PNOR device 656 */ 657 dev = qdev_create(NULL, TYPE_PNV_PNOR); 658 if (pnor) { 659 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 660 &error_abort); 661 } 662 qdev_init_nofail(dev); 663 pnv->pnor = PNV_PNOR(dev); 664 665 /* load skiboot firmware */ 666 if (bios_name == NULL) { 667 bios_name = FW_FILE_NAME; 668 } 669 670 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 671 if (!fw_filename) { 672 error_report("Could not find OPAL firmware '%s'", bios_name); 673 exit(1); 674 } 675 676 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 677 if (fw_size < 0) { 678 error_report("Could not load OPAL firmware '%s'", fw_filename); 679 exit(1); 680 } 681 g_free(fw_filename); 682 683 /* load kernel */ 684 if (machine->kernel_filename) { 685 long kernel_size; 686 687 kernel_size = load_image_targphys(machine->kernel_filename, 688 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 689 if (kernel_size < 0) { 690 error_report("Could not load kernel '%s'", 691 machine->kernel_filename); 692 exit(1); 693 } 694 } 695 696 /* load initrd */ 697 if (machine->initrd_filename) { 698 pnv->initrd_base = INITRD_LOAD_ADDR; 699 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 700 pnv->initrd_base, INITRD_MAX_SIZE); 701 if (pnv->initrd_size < 0) { 702 error_report("Could not load initial ram disk '%s'", 703 machine->initrd_filename); 704 exit(1); 705 } 706 } 707 708 /* 709 * Check compatibility of the specified CPU with the machine 710 * default. 711 */ 712 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 713 error_report("invalid CPU model '%s' for %s machine", 714 machine->cpu_type, mc->name); 715 exit(1); 716 } 717 718 /* Create the processor chips */ 719 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 720 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 721 i, machine->cpu_type); 722 if (!object_class_by_name(chip_typename)) { 723 error_report("invalid chip model '%.*s' for %s machine", 724 i, machine->cpu_type, mc->name); 725 exit(1); 726 } 727 728 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 729 for (i = 0; i < pnv->num_chips; i++) { 730 char chip_name[32]; 731 Object *chip = object_new(chip_typename); 732 733 pnv->chips[i] = PNV_CHIP(chip); 734 735 /* 736 * TODO: put all the memory in one node on chip 0 until we find a 737 * way to specify different ranges for each chip 738 */ 739 if (i == 0) { 740 object_property_set_int(chip, machine->ram_size, "ram-size", 741 &error_fatal); 742 } 743 744 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 745 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 746 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 747 &error_fatal); 748 object_property_set_int(chip, machine->smp.cores, 749 "nr-cores", &error_fatal); 750 object_property_set_bool(chip, true, "realized", &error_fatal); 751 } 752 g_free(chip_typename); 753 754 /* Instantiate ISA bus on chip 0 */ 755 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 756 757 /* Create serial port */ 758 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 759 760 /* Create an RTC ISA device too */ 761 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 762 763 /* 764 * OpenPOWER systems use a IPMI SEL Event message to notify the 765 * host to powerdown 766 */ 767 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 768 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 769 } 770 771 /* 772 * 0:21 Reserved - Read as zeros 773 * 22:24 Chip ID 774 * 25:28 Core number 775 * 29:31 Thread ID 776 */ 777 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 778 { 779 return (chip->chip_id << 7) | (core_id << 3); 780 } 781 782 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 783 Error **errp) 784 { 785 Error *local_err = NULL; 786 Object *obj; 787 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 788 789 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 790 &local_err); 791 if (local_err) { 792 error_propagate(errp, local_err); 793 return; 794 } 795 796 pnv_cpu->intc = obj; 797 } 798 799 800 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 801 { 802 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 803 804 icp_reset(ICP(pnv_cpu->intc)); 805 } 806 807 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 808 { 809 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 810 811 icp_destroy(ICP(pnv_cpu->intc)); 812 pnv_cpu->intc = NULL; 813 } 814 815 /* 816 * 0:48 Reserved - Read as zeroes 817 * 49:52 Node ID 818 * 53:55 Chip ID 819 * 56 Reserved - Read as zero 820 * 57:61 Core number 821 * 62:63 Thread ID 822 * 823 * We only care about the lower bits. uint32_t is fine for the moment. 824 */ 825 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 826 { 827 return (chip->chip_id << 8) | (core_id << 2); 828 } 829 830 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 831 Error **errp) 832 { 833 Pnv9Chip *chip9 = PNV9_CHIP(chip); 834 Error *local_err = NULL; 835 Object *obj; 836 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 837 838 /* 839 * The core creates its interrupt presenter but the XIVE interrupt 840 * controller object is initialized afterwards. Hopefully, it's 841 * only used at runtime. 842 */ 843 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 844 if (local_err) { 845 error_propagate(errp, local_err); 846 return; 847 } 848 849 pnv_cpu->intc = obj; 850 } 851 852 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 853 { 854 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 855 856 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 857 } 858 859 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 860 { 861 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 862 863 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 864 pnv_cpu->intc = NULL; 865 } 866 867 /* 868 * Allowed core identifiers on a POWER8 Processor Chip : 869 * 870 * <EX0 reserved> 871 * EX1 - Venice only 872 * EX2 - Venice only 873 * EX3 - Venice only 874 * EX4 875 * EX5 876 * EX6 877 * <EX7,8 reserved> <reserved> 878 * EX9 - Venice only 879 * EX10 - Venice only 880 * EX11 - Venice only 881 * EX12 882 * EX13 883 * EX14 884 * <EX15 reserved> 885 */ 886 #define POWER8E_CORE_MASK (0x7070ull) 887 #define POWER8_CORE_MASK (0x7e7eull) 888 889 /* 890 * POWER9 has 24 cores, ids starting at 0x0 891 */ 892 #define POWER9_CORE_MASK (0xffffffffffffffull) 893 894 static void pnv_chip_power8_instance_init(Object *obj) 895 { 896 Pnv8Chip *chip8 = PNV8_CHIP(obj); 897 898 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 899 TYPE_PNV8_PSI, &error_abort, NULL); 900 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 901 OBJECT(qdev_get_machine()), &error_abort); 902 903 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 904 TYPE_PNV8_LPC, &error_abort, NULL); 905 906 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 907 TYPE_PNV8_OCC, &error_abort, NULL); 908 909 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 910 TYPE_PNV8_HOMER, &error_abort, NULL); 911 } 912 913 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 914 { 915 PnvChip *chip = PNV_CHIP(chip8); 916 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 917 const char *typename = pnv_chip_core_typename(chip); 918 size_t typesize = object_type_get_instance_size(typename); 919 int i, j; 920 char *name; 921 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 922 923 name = g_strdup_printf("icp-%x", chip->chip_id); 924 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 925 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 926 g_free(name); 927 928 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 929 930 /* Map the ICP registers for each thread */ 931 for (i = 0; i < chip->nr_cores; i++) { 932 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 933 int core_hwid = CPU_CORE(pnv_core)->core_id; 934 935 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 936 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 937 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 938 939 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 940 &icp->mmio); 941 } 942 } 943 } 944 945 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 946 { 947 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 948 PnvChip *chip = PNV_CHIP(dev); 949 Pnv8Chip *chip8 = PNV8_CHIP(dev); 950 Pnv8Psi *psi8 = &chip8->psi; 951 Error *local_err = NULL; 952 953 /* XSCOM bridge is first */ 954 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 955 if (local_err) { 956 error_propagate(errp, local_err); 957 return; 958 } 959 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 960 961 pcc->parent_realize(dev, &local_err); 962 if (local_err) { 963 error_propagate(errp, local_err); 964 return; 965 } 966 967 /* Processor Service Interface (PSI) Host Bridge */ 968 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 969 "bar", &error_fatal); 970 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 971 if (local_err) { 972 error_propagate(errp, local_err); 973 return; 974 } 975 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 976 &PNV_PSI(psi8)->xscom_regs); 977 978 /* Create LPC controller */ 979 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 980 &error_abort); 981 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 982 &error_fatal); 983 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 984 985 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 986 (uint64_t) PNV_XSCOM_BASE(chip), 987 PNV_XSCOM_LPC_BASE); 988 989 /* 990 * Interrupt Management Area. This is the memory region holding 991 * all the Interrupt Control Presenter (ICP) registers 992 */ 993 pnv_chip_icp_realize(chip8, &local_err); 994 if (local_err) { 995 error_propagate(errp, local_err); 996 return; 997 } 998 999 /* Create the simplified OCC model */ 1000 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1001 &error_abort); 1002 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1003 if (local_err) { 1004 error_propagate(errp, local_err); 1005 return; 1006 } 1007 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1008 1009 /* OCC SRAM model */ 1010 memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip), 1011 &chip8->occ.sram_regs); 1012 1013 /* HOMER */ 1014 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1015 &error_abort); 1016 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1017 &local_err); 1018 if (local_err) { 1019 error_propagate(errp, local_err); 1020 return; 1021 } 1022 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1023 &chip8->homer.regs); 1024 } 1025 1026 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1027 { 1028 DeviceClass *dc = DEVICE_CLASS(klass); 1029 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1030 1031 k->chip_type = PNV_CHIP_POWER8E; 1032 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1033 k->cores_mask = POWER8E_CORE_MASK; 1034 k->core_pir = pnv_chip_core_pir_p8; 1035 k->intc_create = pnv_chip_power8_intc_create; 1036 k->intc_reset = pnv_chip_power8_intc_reset; 1037 k->intc_destroy = pnv_chip_power8_intc_destroy; 1038 k->isa_create = pnv_chip_power8_isa_create; 1039 k->dt_populate = pnv_chip_power8_dt_populate; 1040 k->pic_print_info = pnv_chip_power8_pic_print_info; 1041 dc->desc = "PowerNV Chip POWER8E"; 1042 1043 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1044 &k->parent_realize); 1045 } 1046 1047 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1048 { 1049 DeviceClass *dc = DEVICE_CLASS(klass); 1050 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1051 1052 k->chip_type = PNV_CHIP_POWER8; 1053 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1054 k->cores_mask = POWER8_CORE_MASK; 1055 k->core_pir = pnv_chip_core_pir_p8; 1056 k->intc_create = pnv_chip_power8_intc_create; 1057 k->intc_reset = pnv_chip_power8_intc_reset; 1058 k->intc_destroy = pnv_chip_power8_intc_destroy; 1059 k->isa_create = pnv_chip_power8_isa_create; 1060 k->dt_populate = pnv_chip_power8_dt_populate; 1061 k->pic_print_info = pnv_chip_power8_pic_print_info; 1062 dc->desc = "PowerNV Chip POWER8"; 1063 1064 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1065 &k->parent_realize); 1066 } 1067 1068 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1069 { 1070 DeviceClass *dc = DEVICE_CLASS(klass); 1071 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1072 1073 k->chip_type = PNV_CHIP_POWER8NVL; 1074 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1075 k->cores_mask = POWER8_CORE_MASK; 1076 k->core_pir = pnv_chip_core_pir_p8; 1077 k->intc_create = pnv_chip_power8_intc_create; 1078 k->intc_reset = pnv_chip_power8_intc_reset; 1079 k->intc_destroy = pnv_chip_power8_intc_destroy; 1080 k->isa_create = pnv_chip_power8nvl_isa_create; 1081 k->dt_populate = pnv_chip_power8_dt_populate; 1082 k->pic_print_info = pnv_chip_power8_pic_print_info; 1083 dc->desc = "PowerNV Chip POWER8NVL"; 1084 1085 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1086 &k->parent_realize); 1087 } 1088 1089 static void pnv_chip_power9_instance_init(Object *obj) 1090 { 1091 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1092 1093 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1094 TYPE_PNV_XIVE, &error_abort, NULL); 1095 1096 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1097 TYPE_PNV9_PSI, &error_abort, NULL); 1098 1099 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1100 TYPE_PNV9_LPC, &error_abort, NULL); 1101 1102 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1103 TYPE_PNV9_OCC, &error_abort, NULL); 1104 1105 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1106 TYPE_PNV9_HOMER, &error_abort, NULL); 1107 } 1108 1109 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1110 { 1111 PnvChip *chip = PNV_CHIP(chip9); 1112 const char *typename = pnv_chip_core_typename(chip); 1113 size_t typesize = object_type_get_instance_size(typename); 1114 int i; 1115 1116 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1117 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1118 1119 for (i = 0; i < chip9->nr_quads; i++) { 1120 char eq_name[32]; 1121 PnvQuad *eq = &chip9->quads[i]; 1122 PnvCore *pnv_core = PNV_CORE(chip->cores + (i * 4) * typesize); 1123 int core_id = CPU_CORE(pnv_core)->core_id; 1124 1125 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1126 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1127 TYPE_PNV_QUAD, &error_fatal, NULL); 1128 1129 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1130 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1131 1132 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1133 &eq->xscom_regs); 1134 } 1135 } 1136 1137 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1138 { 1139 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1140 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1141 PnvChip *chip = PNV_CHIP(dev); 1142 Pnv9Psi *psi9 = &chip9->psi; 1143 Error *local_err = NULL; 1144 1145 /* XSCOM bridge is first */ 1146 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1147 if (local_err) { 1148 error_propagate(errp, local_err); 1149 return; 1150 } 1151 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1152 1153 pcc->parent_realize(dev, &local_err); 1154 if (local_err) { 1155 error_propagate(errp, local_err); 1156 return; 1157 } 1158 1159 pnv_chip_quad_realize(chip9, &local_err); 1160 if (local_err) { 1161 error_propagate(errp, local_err); 1162 return; 1163 } 1164 1165 /* XIVE interrupt controller (POWER9) */ 1166 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1167 "ic-bar", &error_fatal); 1168 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1169 "vc-bar", &error_fatal); 1170 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1171 "pc-bar", &error_fatal); 1172 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1173 "tm-bar", &error_fatal); 1174 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1175 &error_abort); 1176 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1177 &local_err); 1178 if (local_err) { 1179 error_propagate(errp, local_err); 1180 return; 1181 } 1182 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1183 &chip9->xive.xscom_regs); 1184 1185 /* Processor Service Interface (PSI) Host Bridge */ 1186 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1187 "bar", &error_fatal); 1188 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1189 if (local_err) { 1190 error_propagate(errp, local_err); 1191 return; 1192 } 1193 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1194 &PNV_PSI(psi9)->xscom_regs); 1195 1196 /* LPC */ 1197 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1198 &error_abort); 1199 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1200 if (local_err) { 1201 error_propagate(errp, local_err); 1202 return; 1203 } 1204 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1205 &chip9->lpc.xscom_regs); 1206 1207 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1208 (uint64_t) PNV9_LPCM_BASE(chip)); 1209 1210 /* Create the simplified OCC model */ 1211 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1212 &error_abort); 1213 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1214 if (local_err) { 1215 error_propagate(errp, local_err); 1216 return; 1217 } 1218 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1219 1220 /* OCC SRAM model */ 1221 memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip), 1222 &chip9->occ.sram_regs); 1223 1224 /* HOMER */ 1225 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1226 &error_abort); 1227 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1228 &local_err); 1229 if (local_err) { 1230 error_propagate(errp, local_err); 1231 return; 1232 } 1233 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1234 &chip9->homer.regs); 1235 } 1236 1237 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1238 { 1239 DeviceClass *dc = DEVICE_CLASS(klass); 1240 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1241 1242 k->chip_type = PNV_CHIP_POWER9; 1243 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1244 k->cores_mask = POWER9_CORE_MASK; 1245 k->core_pir = pnv_chip_core_pir_p9; 1246 k->intc_create = pnv_chip_power9_intc_create; 1247 k->intc_reset = pnv_chip_power9_intc_reset; 1248 k->intc_destroy = pnv_chip_power9_intc_destroy; 1249 k->isa_create = pnv_chip_power9_isa_create; 1250 k->dt_populate = pnv_chip_power9_dt_populate; 1251 k->pic_print_info = pnv_chip_power9_pic_print_info; 1252 dc->desc = "PowerNV Chip POWER9"; 1253 1254 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1255 &k->parent_realize); 1256 } 1257 1258 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1259 { 1260 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1261 int cores_max; 1262 1263 /* 1264 * No custom mask for this chip, let's use the default one from * 1265 * the chip class 1266 */ 1267 if (!chip->cores_mask) { 1268 chip->cores_mask = pcc->cores_mask; 1269 } 1270 1271 /* filter alien core ids ! some are reserved */ 1272 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1273 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1274 chip->cores_mask); 1275 return; 1276 } 1277 chip->cores_mask &= pcc->cores_mask; 1278 1279 /* now that we have a sane layout, let check the number of cores */ 1280 cores_max = ctpop64(chip->cores_mask); 1281 if (chip->nr_cores > cores_max) { 1282 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1283 cores_max); 1284 return; 1285 } 1286 } 1287 1288 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1289 { 1290 MachineState *ms = MACHINE(qdev_get_machine()); 1291 Error *error = NULL; 1292 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1293 const char *typename = pnv_chip_core_typename(chip); 1294 size_t typesize = object_type_get_instance_size(typename); 1295 int i, core_hwid; 1296 1297 if (!object_class_by_name(typename)) { 1298 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1299 return; 1300 } 1301 1302 /* Cores */ 1303 pnv_chip_core_sanitize(chip, &error); 1304 if (error) { 1305 error_propagate(errp, error); 1306 return; 1307 } 1308 1309 chip->cores = g_malloc0(typesize * chip->nr_cores); 1310 1311 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1312 && (i < chip->nr_cores); core_hwid++) { 1313 char core_name[32]; 1314 void *pnv_core = chip->cores + i * typesize; 1315 uint64_t xscom_core_base; 1316 1317 if (!(chip->cores_mask & (1ull << core_hwid))) { 1318 continue; 1319 } 1320 1321 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1322 object_initialize_child(OBJECT(chip), core_name, pnv_core, typesize, 1323 typename, &error_fatal, NULL); 1324 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1325 &error_fatal); 1326 object_property_set_int(OBJECT(pnv_core), core_hwid, 1327 CPU_CORE_PROP_CORE_ID, &error_fatal); 1328 object_property_set_int(OBJECT(pnv_core), 1329 pcc->core_pir(chip, core_hwid), 1330 "pir", &error_fatal); 1331 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1332 &error_abort); 1333 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1334 &error_fatal); 1335 1336 /* Each core has an XSCOM MMIO region */ 1337 if (!pnv_chip_is_power9(chip)) { 1338 xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid); 1339 } else { 1340 xscom_core_base = PNV9_XSCOM_EC_BASE(core_hwid); 1341 } 1342 1343 pnv_xscom_add_subregion(chip, xscom_core_base, 1344 &PNV_CORE(pnv_core)->xscom_regs); 1345 i++; 1346 } 1347 } 1348 1349 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1350 { 1351 PnvChip *chip = PNV_CHIP(dev); 1352 Error *error = NULL; 1353 1354 /* Cores */ 1355 pnv_chip_core_realize(chip, &error); 1356 if (error) { 1357 error_propagate(errp, error); 1358 return; 1359 } 1360 } 1361 1362 static Property pnv_chip_properties[] = { 1363 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1364 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1365 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1366 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1367 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1368 DEFINE_PROP_END_OF_LIST(), 1369 }; 1370 1371 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1372 { 1373 DeviceClass *dc = DEVICE_CLASS(klass); 1374 1375 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1376 dc->realize = pnv_chip_realize; 1377 dc->props = pnv_chip_properties; 1378 dc->desc = "PowerNV Chip"; 1379 } 1380 1381 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1382 { 1383 PnvMachineState *pnv = PNV_MACHINE(xi); 1384 int i; 1385 1386 for (i = 0; i < pnv->num_chips; i++) { 1387 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1388 1389 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1390 return &chip8->psi.ics; 1391 } 1392 } 1393 return NULL; 1394 } 1395 1396 static void pnv_ics_resend(XICSFabric *xi) 1397 { 1398 PnvMachineState *pnv = PNV_MACHINE(xi); 1399 int i; 1400 1401 for (i = 0; i < pnv->num_chips; i++) { 1402 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1403 ics_resend(&chip8->psi.ics); 1404 } 1405 } 1406 1407 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1408 { 1409 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1410 1411 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1412 } 1413 1414 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1415 Monitor *mon) 1416 { 1417 PnvMachineState *pnv = PNV_MACHINE(obj); 1418 int i; 1419 CPUState *cs; 1420 1421 CPU_FOREACH(cs) { 1422 PowerPCCPU *cpu = POWERPC_CPU(cs); 1423 1424 if (pnv_chip_is_power9(pnv->chips[0])) { 1425 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1426 } else { 1427 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1428 } 1429 } 1430 1431 for (i = 0; i < pnv->num_chips; i++) { 1432 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1433 } 1434 } 1435 1436 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1437 void *opaque, Error **errp) 1438 { 1439 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1440 } 1441 1442 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1443 void *opaque, Error **errp) 1444 { 1445 PnvMachineState *pnv = PNV_MACHINE(obj); 1446 uint32_t num_chips; 1447 Error *local_err = NULL; 1448 1449 visit_type_uint32(v, name, &num_chips, &local_err); 1450 if (local_err) { 1451 error_propagate(errp, local_err); 1452 return; 1453 } 1454 1455 /* 1456 * TODO: should we decide on how many chips we can create based 1457 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1458 */ 1459 if (!is_power_of_2(num_chips) || num_chips > 4) { 1460 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1461 return; 1462 } 1463 1464 pnv->num_chips = num_chips; 1465 } 1466 1467 static void pnv_machine_instance_init(Object *obj) 1468 { 1469 PnvMachineState *pnv = PNV_MACHINE(obj); 1470 pnv->num_chips = 1; 1471 } 1472 1473 static void pnv_machine_class_props_init(ObjectClass *oc) 1474 { 1475 object_class_property_add(oc, "num-chips", "uint32", 1476 pnv_get_num_chips, pnv_set_num_chips, 1477 NULL, NULL, NULL); 1478 object_class_property_set_description(oc, "num-chips", 1479 "Specifies the number of processor chips", 1480 NULL); 1481 } 1482 1483 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1484 { 1485 MachineClass *mc = MACHINE_CLASS(oc); 1486 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1487 1488 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1489 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1490 1491 xic->icp_get = pnv_icp_get; 1492 xic->ics_get = pnv_ics_get; 1493 xic->ics_resend = pnv_ics_resend; 1494 } 1495 1496 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1497 { 1498 MachineClass *mc = MACHINE_CLASS(oc); 1499 1500 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1501 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1502 1503 mc->alias = "powernv"; 1504 } 1505 1506 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1507 { 1508 MachineClass *mc = MACHINE_CLASS(oc); 1509 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1510 1511 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1512 mc->init = pnv_init; 1513 mc->reset = pnv_reset; 1514 mc->max_cpus = MAX_CPUS; 1515 /* Pnv provides a AHCI device for storage */ 1516 mc->block_default_type = IF_IDE; 1517 mc->no_parallel = 1; 1518 mc->default_boot_order = NULL; 1519 /* 1520 * RAM defaults to less than 2048 for 32-bit hosts, and large 1521 * enough to fit the maximum initrd size at it's load address 1522 */ 1523 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1524 ispc->print_info = pnv_pic_print_info; 1525 1526 pnv_machine_class_props_init(oc); 1527 } 1528 1529 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1530 { \ 1531 .name = type, \ 1532 .class_init = class_initfn, \ 1533 .parent = TYPE_PNV8_CHIP, \ 1534 } 1535 1536 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1537 { \ 1538 .name = type, \ 1539 .class_init = class_initfn, \ 1540 .parent = TYPE_PNV9_CHIP, \ 1541 } 1542 1543 static const TypeInfo types[] = { 1544 { 1545 .name = MACHINE_TYPE_NAME("powernv9"), 1546 .parent = TYPE_PNV_MACHINE, 1547 .class_init = pnv_machine_power9_class_init, 1548 }, 1549 { 1550 .name = MACHINE_TYPE_NAME("powernv8"), 1551 .parent = TYPE_PNV_MACHINE, 1552 .class_init = pnv_machine_power8_class_init, 1553 .interfaces = (InterfaceInfo[]) { 1554 { TYPE_XICS_FABRIC }, 1555 { }, 1556 }, 1557 }, 1558 { 1559 .name = TYPE_PNV_MACHINE, 1560 .parent = TYPE_MACHINE, 1561 .abstract = true, 1562 .instance_size = sizeof(PnvMachineState), 1563 .instance_init = pnv_machine_instance_init, 1564 .class_init = pnv_machine_class_init, 1565 .interfaces = (InterfaceInfo[]) { 1566 { TYPE_INTERRUPT_STATS_PROVIDER }, 1567 { }, 1568 }, 1569 }, 1570 { 1571 .name = TYPE_PNV_CHIP, 1572 .parent = TYPE_SYS_BUS_DEVICE, 1573 .class_init = pnv_chip_class_init, 1574 .instance_size = sizeof(PnvChip), 1575 .class_size = sizeof(PnvChipClass), 1576 .abstract = true, 1577 }, 1578 1579 /* 1580 * P9 chip and variants 1581 */ 1582 { 1583 .name = TYPE_PNV9_CHIP, 1584 .parent = TYPE_PNV_CHIP, 1585 .instance_init = pnv_chip_power9_instance_init, 1586 .instance_size = sizeof(Pnv9Chip), 1587 }, 1588 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1589 1590 /* 1591 * P8 chip and variants 1592 */ 1593 { 1594 .name = TYPE_PNV8_CHIP, 1595 .parent = TYPE_PNV_CHIP, 1596 .instance_init = pnv_chip_power8_instance_init, 1597 .instance_size = sizeof(Pnv8Chip), 1598 }, 1599 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1600 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1601 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1602 pnv_chip_power8nvl_class_init), 1603 }; 1604 1605 DEFINE_TYPES(types) 1606