1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/datadir.h" 23 #include "qemu/units.h" 24 #include "qemu/cutils.h" 25 #include "qapi/error.h" 26 #include "sysemu/qtest.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/numa.h" 29 #include "sysemu/reset.h" 30 #include "sysemu/runstate.h" 31 #include "sysemu/cpus.h" 32 #include "sysemu/device_tree.h" 33 #include "sysemu/hw_accel.h" 34 #include "target/ppc/cpu.h" 35 #include "hw/ppc/fdt.h" 36 #include "hw/ppc/ppc.h" 37 #include "hw/ppc/pnv.h" 38 #include "hw/ppc/pnv_core.h" 39 #include "hw/loader.h" 40 #include "hw/nmi.h" 41 #include "qapi/visitor.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (16 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (128 * MiB) 67 #define INITRD_LOAD_ADDR 0x28000000 68 #define INITRD_MAX_SIZE (128 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (ppc_has_spr(cpu, SPR_PURR)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 285 { 286 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 287 int i; 288 289 pnv_dt_xscom(chip, fdt, 0, 290 cpu_to_be64(PNV_XSCOM_BASE(chip)), 291 cpu_to_be64(PNV_XSCOM_SIZE), 292 compat, sizeof(compat)); 293 294 for (i = 0; i < chip->nr_cores; i++) { 295 PnvCore *pnv_core = chip->cores[i]; 296 297 pnv_dt_core(chip, pnv_core, fdt); 298 299 /* Interrupt Control Presenters (ICP). One per core. */ 300 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 301 } 302 303 if (chip->ram_size) { 304 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 305 } 306 } 307 308 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 309 { 310 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 311 int i; 312 313 pnv_dt_xscom(chip, fdt, 0, 314 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 315 cpu_to_be64(PNV9_XSCOM_SIZE), 316 compat, sizeof(compat)); 317 318 for (i = 0; i < chip->nr_cores; i++) { 319 PnvCore *pnv_core = chip->cores[i]; 320 321 pnv_dt_core(chip, pnv_core, fdt); 322 } 323 324 if (chip->ram_size) { 325 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 326 } 327 328 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 329 } 330 331 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 332 { 333 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 334 int i; 335 336 pnv_dt_xscom(chip, fdt, 0, 337 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 338 cpu_to_be64(PNV10_XSCOM_SIZE), 339 compat, sizeof(compat)); 340 341 for (i = 0; i < chip->nr_cores; i++) { 342 PnvCore *pnv_core = chip->cores[i]; 343 344 pnv_dt_core(chip, pnv_core, fdt); 345 } 346 347 if (chip->ram_size) { 348 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 349 } 350 351 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 352 } 353 354 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 355 { 356 uint32_t io_base = d->ioport_id; 357 uint32_t io_regs[] = { 358 cpu_to_be32(1), 359 cpu_to_be32(io_base), 360 cpu_to_be32(2) 361 }; 362 char *name; 363 int node; 364 365 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 366 node = fdt_add_subnode(fdt, lpc_off, name); 367 _FDT(node); 368 g_free(name); 369 370 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 371 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 372 } 373 374 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 375 { 376 const char compatible[] = "ns16550\0pnpPNP,501"; 377 uint32_t io_base = d->ioport_id; 378 uint32_t io_regs[] = { 379 cpu_to_be32(1), 380 cpu_to_be32(io_base), 381 cpu_to_be32(8) 382 }; 383 char *name; 384 int node; 385 386 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 387 node = fdt_add_subnode(fdt, lpc_off, name); 388 _FDT(node); 389 g_free(name); 390 391 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 392 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 393 sizeof(compatible)))); 394 395 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 396 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 397 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 398 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 399 fdt_get_phandle(fdt, lpc_off)))); 400 401 /* This is needed by Linux */ 402 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 403 } 404 405 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 406 { 407 const char compatible[] = "bt\0ipmi-bt"; 408 uint32_t io_base; 409 uint32_t io_regs[] = { 410 cpu_to_be32(1), 411 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 412 cpu_to_be32(3) 413 }; 414 uint32_t irq; 415 char *name; 416 int node; 417 418 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 419 io_regs[1] = cpu_to_be32(io_base); 420 421 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 422 423 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 424 node = fdt_add_subnode(fdt, lpc_off, name); 425 _FDT(node); 426 g_free(name); 427 428 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 429 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 430 sizeof(compatible)))); 431 432 /* Mark it as reserved to avoid Linux trying to claim it */ 433 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 434 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 435 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 436 fdt_get_phandle(fdt, lpc_off)))); 437 } 438 439 typedef struct ForeachPopulateArgs { 440 void *fdt; 441 int offset; 442 } ForeachPopulateArgs; 443 444 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 445 { 446 ForeachPopulateArgs *args = opaque; 447 ISADevice *d = ISA_DEVICE(dev); 448 449 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 450 pnv_dt_rtc(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 452 pnv_dt_serial(d, args->fdt, args->offset); 453 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 454 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 455 } else { 456 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 457 d->ioport_id); 458 } 459 460 return 0; 461 } 462 463 /* 464 * The default LPC bus of a multichip system is on chip 0. It's 465 * recognized by the firmware (skiboot) using a "primary" property. 466 */ 467 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 468 { 469 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 470 ForeachPopulateArgs args = { 471 .fdt = fdt, 472 .offset = isa_offset, 473 }; 474 uint32_t phandle; 475 476 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 477 478 phandle = qemu_fdt_alloc_phandle(fdt); 479 assert(phandle > 0); 480 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 481 482 /* 483 * ISA devices are not necessarily parented to the ISA bus so we 484 * can not use object_child_foreach() 485 */ 486 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 487 &args); 488 } 489 490 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 491 { 492 int off; 493 494 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 495 off = fdt_add_subnode(fdt, off, "power-mgt"); 496 497 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 498 } 499 500 static void *pnv_dt_create(MachineState *machine) 501 { 502 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 503 PnvMachineState *pnv = PNV_MACHINE(machine); 504 void *fdt; 505 char *buf; 506 int off; 507 int i; 508 509 fdt = g_malloc0(FDT_MAX_SIZE); 510 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 511 512 /* /qemu node */ 513 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 514 515 /* Root node */ 516 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 517 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 518 _FDT((fdt_setprop_string(fdt, 0, "model", 519 "IBM PowerNV (emulated by qemu)"))); 520 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 521 522 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 523 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 524 if (qemu_uuid_set) { 525 _FDT((fdt_property_string(fdt, "system-id", buf))); 526 } 527 g_free(buf); 528 529 off = fdt_add_subnode(fdt, 0, "chosen"); 530 if (machine->kernel_cmdline) { 531 _FDT((fdt_setprop_string(fdt, off, "bootargs", 532 machine->kernel_cmdline))); 533 } 534 535 if (pnv->initrd_size) { 536 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 537 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 538 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 540 &start_prop, sizeof(start_prop)))); 541 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 542 &end_prop, sizeof(end_prop)))); 543 } 544 545 /* Populate device tree for each chip */ 546 for (i = 0; i < pnv->num_chips; i++) { 547 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 548 } 549 550 /* Populate ISA devices on chip 0 */ 551 pnv_dt_isa(pnv, fdt); 552 553 if (pnv->bmc) { 554 pnv_dt_bmc_sensors(pnv->bmc, fdt); 555 } 556 557 /* Create an extra node for power management on machines that support it */ 558 if (pmc->dt_power_mgt) { 559 pmc->dt_power_mgt(pnv, fdt); 560 } 561 562 return fdt; 563 } 564 565 static void pnv_powerdown_notify(Notifier *n, void *opaque) 566 { 567 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 568 569 if (pnv->bmc) { 570 pnv_bmc_powerdown(pnv->bmc); 571 } 572 } 573 574 static void pnv_reset(MachineState *machine) 575 { 576 PnvMachineState *pnv = PNV_MACHINE(machine); 577 IPMIBmc *bmc; 578 void *fdt; 579 580 qemu_devices_reset(); 581 582 /* 583 * The machine should provide by default an internal BMC simulator. 584 * If not, try to use the BMC device that was provided on the command 585 * line. 586 */ 587 bmc = pnv_bmc_find(&error_fatal); 588 if (!pnv->bmc) { 589 if (!bmc) { 590 if (!qtest_enabled()) { 591 warn_report("machine has no BMC device. Use '-device " 592 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 593 "to define one"); 594 } 595 } else { 596 pnv_bmc_set_pnor(bmc, pnv->pnor); 597 pnv->bmc = bmc; 598 } 599 } 600 601 fdt = pnv_dt_create(machine); 602 603 /* Pack resulting tree */ 604 _FDT((fdt_pack(fdt))); 605 606 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 607 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 608 609 g_free(fdt); 610 } 611 612 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 613 { 614 Pnv8Chip *chip8 = PNV8_CHIP(chip); 615 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 616 } 617 618 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 619 { 620 Pnv8Chip *chip8 = PNV8_CHIP(chip); 621 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 622 } 623 624 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 625 { 626 Pnv9Chip *chip9 = PNV9_CHIP(chip); 627 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 628 } 629 630 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 631 { 632 Pnv10Chip *chip10 = PNV10_CHIP(chip); 633 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 634 } 635 636 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 637 { 638 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 639 } 640 641 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 642 { 643 Pnv8Chip *chip8 = PNV8_CHIP(chip); 644 int i; 645 646 ics_pic_print_info(&chip8->psi.ics, mon); 647 for (i = 0; i < chip->num_phbs; i++) { 648 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 649 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 650 } 651 } 652 653 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 654 { 655 Pnv9Chip *chip9 = PNV9_CHIP(chip); 656 int i, j; 657 658 pnv_xive_pic_print_info(&chip9->xive, mon); 659 pnv_psi_pic_print_info(&chip9->psi, mon); 660 661 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 662 PnvPhb4PecState *pec = &chip9->pecs[i]; 663 for (j = 0; j < pec->num_stacks; j++) { 664 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 665 } 666 } 667 } 668 669 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 670 uint32_t core_id) 671 { 672 return PNV_XSCOM_EX_BASE(core_id); 673 } 674 675 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 676 uint32_t core_id) 677 { 678 return PNV9_XSCOM_EC_BASE(core_id); 679 } 680 681 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 682 uint32_t core_id) 683 { 684 return PNV10_XSCOM_EC_BASE(core_id); 685 } 686 687 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 688 { 689 PowerPCCPUClass *ppc_default = 690 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 691 PowerPCCPUClass *ppc = 692 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 693 694 return ppc_default->pvr_match(ppc_default, ppc->pvr); 695 } 696 697 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 698 { 699 ISADevice *dev = isa_new("isa-ipmi-bt"); 700 701 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 702 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 703 isa_realize_and_unref(dev, bus, &error_fatal); 704 } 705 706 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 707 { 708 Pnv10Chip *chip10 = PNV10_CHIP(chip); 709 710 pnv_psi_pic_print_info(&chip10->psi, mon); 711 } 712 713 /* Always give the first 1GB to chip 0 else we won't boot */ 714 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 715 { 716 MachineState *machine = MACHINE(pnv); 717 uint64_t ram_per_chip; 718 719 assert(machine->ram_size >= 1 * GiB); 720 721 ram_per_chip = machine->ram_size / pnv->num_chips; 722 if (ram_per_chip >= 1 * GiB) { 723 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 724 } 725 726 assert(pnv->num_chips > 1); 727 728 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 729 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 730 } 731 732 static void pnv_init(MachineState *machine) 733 { 734 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 735 PnvMachineState *pnv = PNV_MACHINE(machine); 736 MachineClass *mc = MACHINE_GET_CLASS(machine); 737 char *fw_filename; 738 long fw_size; 739 uint64_t chip_ram_start = 0; 740 int i; 741 char *chip_typename; 742 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 743 DeviceState *dev; 744 745 /* allocate RAM */ 746 if (machine->ram_size < mc->default_ram_size) { 747 char *sz = size_to_str(mc->default_ram_size); 748 error_report("Invalid RAM size, should be bigger than %s", sz); 749 g_free(sz); 750 exit(EXIT_FAILURE); 751 } 752 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 753 754 /* 755 * Create our simple PNOR device 756 */ 757 dev = qdev_new(TYPE_PNV_PNOR); 758 if (pnor) { 759 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 760 } 761 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 762 pnv->pnor = PNV_PNOR(dev); 763 764 /* load skiboot firmware */ 765 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 766 if (!fw_filename) { 767 error_report("Could not find OPAL firmware '%s'", bios_name); 768 exit(1); 769 } 770 771 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 772 if (fw_size < 0) { 773 error_report("Could not load OPAL firmware '%s'", fw_filename); 774 exit(1); 775 } 776 g_free(fw_filename); 777 778 /* load kernel */ 779 if (machine->kernel_filename) { 780 long kernel_size; 781 782 kernel_size = load_image_targphys(machine->kernel_filename, 783 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 784 if (kernel_size < 0) { 785 error_report("Could not load kernel '%s'", 786 machine->kernel_filename); 787 exit(1); 788 } 789 } 790 791 /* load initrd */ 792 if (machine->initrd_filename) { 793 pnv->initrd_base = INITRD_LOAD_ADDR; 794 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 795 pnv->initrd_base, INITRD_MAX_SIZE); 796 if (pnv->initrd_size < 0) { 797 error_report("Could not load initial ram disk '%s'", 798 machine->initrd_filename); 799 exit(1); 800 } 801 } 802 803 /* MSIs are supported on this platform */ 804 msi_nonbroken = true; 805 806 /* 807 * Check compatibility of the specified CPU with the machine 808 * default. 809 */ 810 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 811 error_report("invalid CPU model '%s' for %s machine", 812 machine->cpu_type, mc->name); 813 exit(1); 814 } 815 816 /* Create the processor chips */ 817 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 818 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 819 i, machine->cpu_type); 820 if (!object_class_by_name(chip_typename)) { 821 error_report("invalid chip model '%.*s' for %s machine", 822 i, machine->cpu_type, mc->name); 823 exit(1); 824 } 825 826 pnv->num_chips = 827 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 828 /* 829 * TODO: should we decide on how many chips we can create based 830 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 831 */ 832 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 833 error_report("invalid number of chips: '%d'", pnv->num_chips); 834 error_printf( 835 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 836 exit(1); 837 } 838 839 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 840 for (i = 0; i < pnv->num_chips; i++) { 841 char chip_name[32]; 842 Object *chip = OBJECT(qdev_new(chip_typename)); 843 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 844 845 pnv->chips[i] = PNV_CHIP(chip); 846 847 /* Distribute RAM among the chips */ 848 object_property_set_int(chip, "ram-start", chip_ram_start, 849 &error_fatal); 850 object_property_set_int(chip, "ram-size", chip_ram_size, 851 &error_fatal); 852 chip_ram_start += chip_ram_size; 853 854 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 855 object_property_add_child(OBJECT(pnv), chip_name, chip); 856 object_property_set_int(chip, "chip-id", i, &error_fatal); 857 object_property_set_int(chip, "nr-cores", machine->smp.cores, 858 &error_fatal); 859 object_property_set_int(chip, "nr-threads", machine->smp.threads, 860 &error_fatal); 861 /* 862 * The POWER8 machine use the XICS interrupt interface. 863 * Propagate the XICS fabric to the chip and its controllers. 864 */ 865 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 866 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 867 } 868 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 869 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 870 &error_abort); 871 } 872 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 873 } 874 g_free(chip_typename); 875 876 /* Instantiate ISA bus on chip 0 */ 877 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 878 879 /* Create serial port */ 880 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 881 882 /* Create an RTC ISA device too */ 883 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 884 885 /* 886 * Create the machine BMC simulator and the IPMI BT device for 887 * communication with the BMC 888 */ 889 if (defaults_enabled()) { 890 pnv->bmc = pnv_bmc_create(pnv->pnor); 891 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 892 } 893 894 /* 895 * The PNOR is mapped on the LPC FW address space by the BMC. 896 * Since we can not reach the remote BMC machine with LPC memops, 897 * map it always for now. 898 */ 899 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 900 &pnv->pnor->mmio); 901 902 /* 903 * OpenPOWER systems use a IPMI SEL Event message to notify the 904 * host to powerdown 905 */ 906 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 907 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 908 } 909 910 /* 911 * 0:21 Reserved - Read as zeros 912 * 22:24 Chip ID 913 * 25:28 Core number 914 * 29:31 Thread ID 915 */ 916 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 917 { 918 return (chip->chip_id << 7) | (core_id << 3); 919 } 920 921 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 922 Error **errp) 923 { 924 Pnv8Chip *chip8 = PNV8_CHIP(chip); 925 Error *local_err = NULL; 926 Object *obj; 927 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 928 929 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 930 if (local_err) { 931 error_propagate(errp, local_err); 932 return; 933 } 934 935 pnv_cpu->intc = obj; 936 } 937 938 939 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 940 { 941 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 942 943 icp_reset(ICP(pnv_cpu->intc)); 944 } 945 946 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 947 { 948 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 949 950 icp_destroy(ICP(pnv_cpu->intc)); 951 pnv_cpu->intc = NULL; 952 } 953 954 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 955 Monitor *mon) 956 { 957 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 958 } 959 960 /* 961 * 0:48 Reserved - Read as zeroes 962 * 49:52 Node ID 963 * 53:55 Chip ID 964 * 56 Reserved - Read as zero 965 * 57:61 Core number 966 * 62:63 Thread ID 967 * 968 * We only care about the lower bits. uint32_t is fine for the moment. 969 */ 970 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 971 { 972 return (chip->chip_id << 8) | (core_id << 2); 973 } 974 975 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 976 { 977 return (chip->chip_id << 8) | (core_id << 2); 978 } 979 980 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 981 Error **errp) 982 { 983 Pnv9Chip *chip9 = PNV9_CHIP(chip); 984 Error *local_err = NULL; 985 Object *obj; 986 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 987 988 /* 989 * The core creates its interrupt presenter but the XIVE interrupt 990 * controller object is initialized afterwards. Hopefully, it's 991 * only used at runtime. 992 */ 993 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 994 &local_err); 995 if (local_err) { 996 error_propagate(errp, local_err); 997 return; 998 } 999 1000 pnv_cpu->intc = obj; 1001 } 1002 1003 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1004 { 1005 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1006 1007 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1008 } 1009 1010 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1011 { 1012 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1013 1014 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1015 pnv_cpu->intc = NULL; 1016 } 1017 1018 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1019 Monitor *mon) 1020 { 1021 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1022 } 1023 1024 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1025 Error **errp) 1026 { 1027 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1028 1029 /* Will be defined when the interrupt controller is */ 1030 pnv_cpu->intc = NULL; 1031 } 1032 1033 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1034 { 1035 ; 1036 } 1037 1038 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1039 { 1040 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1041 1042 pnv_cpu->intc = NULL; 1043 } 1044 1045 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1046 Monitor *mon) 1047 { 1048 } 1049 1050 /* 1051 * Allowed core identifiers on a POWER8 Processor Chip : 1052 * 1053 * <EX0 reserved> 1054 * EX1 - Venice only 1055 * EX2 - Venice only 1056 * EX3 - Venice only 1057 * EX4 1058 * EX5 1059 * EX6 1060 * <EX7,8 reserved> <reserved> 1061 * EX9 - Venice only 1062 * EX10 - Venice only 1063 * EX11 - Venice only 1064 * EX12 1065 * EX13 1066 * EX14 1067 * <EX15 reserved> 1068 */ 1069 #define POWER8E_CORE_MASK (0x7070ull) 1070 #define POWER8_CORE_MASK (0x7e7eull) 1071 1072 /* 1073 * POWER9 has 24 cores, ids starting at 0x0 1074 */ 1075 #define POWER9_CORE_MASK (0xffffffffffffffull) 1076 1077 1078 #define POWER10_CORE_MASK (0xffffffffffffffull) 1079 1080 static void pnv_chip_power8_instance_init(Object *obj) 1081 { 1082 PnvChip *chip = PNV_CHIP(obj); 1083 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1084 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1085 int i; 1086 1087 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1088 (Object **)&chip8->xics, 1089 object_property_allow_set_link, 1090 OBJ_PROP_LINK_STRONG); 1091 1092 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1093 1094 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1095 1096 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1097 1098 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1099 1100 for (i = 0; i < pcc->num_phbs; i++) { 1101 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB3); 1102 } 1103 1104 /* 1105 * Number of PHBs is the chip default 1106 */ 1107 chip->num_phbs = pcc->num_phbs; 1108 } 1109 1110 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1111 { 1112 PnvChip *chip = PNV_CHIP(chip8); 1113 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1114 int i, j; 1115 char *name; 1116 1117 name = g_strdup_printf("icp-%x", chip->chip_id); 1118 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1119 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1120 g_free(name); 1121 1122 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1123 1124 /* Map the ICP registers for each thread */ 1125 for (i = 0; i < chip->nr_cores; i++) { 1126 PnvCore *pnv_core = chip->cores[i]; 1127 int core_hwid = CPU_CORE(pnv_core)->core_id; 1128 1129 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1130 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1131 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1132 1133 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1134 &icp->mmio); 1135 } 1136 } 1137 } 1138 1139 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1140 { 1141 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1142 PnvChip *chip = PNV_CHIP(dev); 1143 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1144 Pnv8Psi *psi8 = &chip8->psi; 1145 Error *local_err = NULL; 1146 int i; 1147 1148 assert(chip8->xics); 1149 1150 /* XSCOM bridge is first */ 1151 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1152 if (local_err) { 1153 error_propagate(errp, local_err); 1154 return; 1155 } 1156 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1157 1158 pcc->parent_realize(dev, &local_err); 1159 if (local_err) { 1160 error_propagate(errp, local_err); 1161 return; 1162 } 1163 1164 /* Processor Service Interface (PSI) Host Bridge */ 1165 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1166 &error_fatal); 1167 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1168 OBJECT(chip8->xics), &error_abort); 1169 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1170 return; 1171 } 1172 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1173 &PNV_PSI(psi8)->xscom_regs); 1174 1175 /* Create LPC controller */ 1176 object_property_set_link(OBJECT(&chip8->lpc), "psi", OBJECT(&chip8->psi), 1177 &error_abort); 1178 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1179 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1180 1181 chip->fw_mr = &chip8->lpc.isa_fw; 1182 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1183 (uint64_t) PNV_XSCOM_BASE(chip), 1184 PNV_XSCOM_LPC_BASE); 1185 1186 /* 1187 * Interrupt Management Area. This is the memory region holding 1188 * all the Interrupt Control Presenter (ICP) registers 1189 */ 1190 pnv_chip_icp_realize(chip8, &local_err); 1191 if (local_err) { 1192 error_propagate(errp, local_err); 1193 return; 1194 } 1195 1196 /* Create the simplified OCC model */ 1197 object_property_set_link(OBJECT(&chip8->occ), "psi", OBJECT(&chip8->psi), 1198 &error_abort); 1199 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1200 return; 1201 } 1202 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1203 1204 /* OCC SRAM model */ 1205 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1206 &chip8->occ.sram_regs); 1207 1208 /* HOMER */ 1209 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1210 &error_abort); 1211 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1212 return; 1213 } 1214 /* Homer Xscom region */ 1215 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1216 1217 /* Homer mmio region */ 1218 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1219 &chip8->homer.regs); 1220 1221 /* PHB3 controllers */ 1222 for (i = 0; i < chip->num_phbs; i++) { 1223 PnvPHB3 *phb = &chip8->phbs[i]; 1224 PnvPBCQState *pbcq = &phb->pbcq; 1225 1226 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1227 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1228 &error_fatal); 1229 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1230 return; 1231 } 1232 1233 /* Populate the XSCOM address space. */ 1234 pnv_xscom_add_subregion(chip, 1235 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1236 &pbcq->xscom_nest_regs); 1237 pnv_xscom_add_subregion(chip, 1238 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1239 &pbcq->xscom_pci_regs); 1240 pnv_xscom_add_subregion(chip, 1241 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1242 &pbcq->xscom_spci_regs); 1243 } 1244 } 1245 1246 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1247 { 1248 addr &= (PNV_XSCOM_SIZE - 1); 1249 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1250 } 1251 1252 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1253 { 1254 DeviceClass *dc = DEVICE_CLASS(klass); 1255 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1256 1257 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1258 k->cores_mask = POWER8E_CORE_MASK; 1259 k->num_phbs = 3; 1260 k->core_pir = pnv_chip_core_pir_p8; 1261 k->intc_create = pnv_chip_power8_intc_create; 1262 k->intc_reset = pnv_chip_power8_intc_reset; 1263 k->intc_destroy = pnv_chip_power8_intc_destroy; 1264 k->intc_print_info = pnv_chip_power8_intc_print_info; 1265 k->isa_create = pnv_chip_power8_isa_create; 1266 k->dt_populate = pnv_chip_power8_dt_populate; 1267 k->pic_print_info = pnv_chip_power8_pic_print_info; 1268 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1269 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1270 dc->desc = "PowerNV Chip POWER8E"; 1271 1272 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1273 &k->parent_realize); 1274 } 1275 1276 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1277 { 1278 DeviceClass *dc = DEVICE_CLASS(klass); 1279 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1280 1281 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1282 k->cores_mask = POWER8_CORE_MASK; 1283 k->num_phbs = 3; 1284 k->core_pir = pnv_chip_core_pir_p8; 1285 k->intc_create = pnv_chip_power8_intc_create; 1286 k->intc_reset = pnv_chip_power8_intc_reset; 1287 k->intc_destroy = pnv_chip_power8_intc_destroy; 1288 k->intc_print_info = pnv_chip_power8_intc_print_info; 1289 k->isa_create = pnv_chip_power8_isa_create; 1290 k->dt_populate = pnv_chip_power8_dt_populate; 1291 k->pic_print_info = pnv_chip_power8_pic_print_info; 1292 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1293 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1294 dc->desc = "PowerNV Chip POWER8"; 1295 1296 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1297 &k->parent_realize); 1298 } 1299 1300 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1301 { 1302 DeviceClass *dc = DEVICE_CLASS(klass); 1303 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1304 1305 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1306 k->cores_mask = POWER8_CORE_MASK; 1307 k->num_phbs = 3; 1308 k->core_pir = pnv_chip_core_pir_p8; 1309 k->intc_create = pnv_chip_power8_intc_create; 1310 k->intc_reset = pnv_chip_power8_intc_reset; 1311 k->intc_destroy = pnv_chip_power8_intc_destroy; 1312 k->intc_print_info = pnv_chip_power8_intc_print_info; 1313 k->isa_create = pnv_chip_power8nvl_isa_create; 1314 k->dt_populate = pnv_chip_power8_dt_populate; 1315 k->pic_print_info = pnv_chip_power8_pic_print_info; 1316 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1317 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1318 dc->desc = "PowerNV Chip POWER8NVL"; 1319 1320 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1321 &k->parent_realize); 1322 } 1323 1324 static void pnv_chip_power9_instance_init(Object *obj) 1325 { 1326 PnvChip *chip = PNV_CHIP(obj); 1327 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1328 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1329 int i; 1330 1331 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1332 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1333 "xive-fabric"); 1334 1335 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1336 1337 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1338 1339 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1340 1341 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1342 1343 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1344 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1345 TYPE_PNV_PHB4_PEC); 1346 } 1347 1348 /* 1349 * Number of PHBs is the chip default 1350 */ 1351 chip->num_phbs = pcc->num_phbs; 1352 } 1353 1354 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1355 { 1356 PnvChip *chip = PNV_CHIP(chip9); 1357 int i; 1358 1359 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1360 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1361 1362 for (i = 0; i < chip9->nr_quads; i++) { 1363 char eq_name[32]; 1364 PnvQuad *eq = &chip9->quads[i]; 1365 PnvCore *pnv_core = chip->cores[i * 4]; 1366 int core_id = CPU_CORE(pnv_core)->core_id; 1367 1368 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1369 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1370 sizeof(*eq), TYPE_PNV_QUAD, 1371 &error_fatal, NULL); 1372 1373 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1374 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1375 1376 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1377 &eq->xscom_regs); 1378 } 1379 } 1380 1381 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1382 { 1383 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1384 int i, j; 1385 int phb_id = 0; 1386 1387 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1388 PnvPhb4PecState *pec = &chip9->pecs[i]; 1389 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1390 uint32_t pec_nest_base; 1391 uint32_t pec_pci_base; 1392 1393 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1394 /* 1395 * PEC0 -> 1 stack 1396 * PEC1 -> 2 stacks 1397 * PEC2 -> 3 stacks 1398 */ 1399 object_property_set_int(OBJECT(pec), "num-stacks", i + 1, 1400 &error_fatal); 1401 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1402 &error_fatal); 1403 object_property_set_link(OBJECT(pec), "system-memory", 1404 OBJECT(get_system_memory()), &error_abort); 1405 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1406 return; 1407 } 1408 1409 pec_nest_base = pecc->xscom_nest_base(pec); 1410 pec_pci_base = pecc->xscom_pci_base(pec); 1411 1412 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1413 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1414 1415 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1416 j++, phb_id++) { 1417 PnvPhb4PecStack *stack = &pec->stacks[j]; 1418 Object *obj = OBJECT(&stack->phb); 1419 1420 object_property_set_int(obj, "index", phb_id, &error_fatal); 1421 object_property_set_int(obj, "chip-id", chip->chip_id, 1422 &error_fatal); 1423 object_property_set_int(obj, "version", PNV_PHB4_VERSION, 1424 &error_fatal); 1425 object_property_set_int(obj, "device-id", PNV_PHB4_DEVICE_ID, 1426 &error_fatal); 1427 object_property_set_link(obj, "stack", OBJECT(stack), 1428 &error_abort); 1429 if (!sysbus_realize(SYS_BUS_DEVICE(obj), errp)) { 1430 return; 1431 } 1432 1433 /* Populate the XSCOM address space. */ 1434 pnv_xscom_add_subregion(chip, 1435 pec_nest_base + 0x40 * (stack->stack_no + 1), 1436 &stack->nest_regs_mr); 1437 pnv_xscom_add_subregion(chip, 1438 pec_pci_base + 0x40 * (stack->stack_no + 1), 1439 &stack->pci_regs_mr); 1440 pnv_xscom_add_subregion(chip, 1441 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1442 0x40 * stack->stack_no, 1443 &stack->phb_regs_mr); 1444 } 1445 } 1446 } 1447 1448 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1449 { 1450 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1451 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1452 PnvChip *chip = PNV_CHIP(dev); 1453 Pnv9Psi *psi9 = &chip9->psi; 1454 Error *local_err = NULL; 1455 1456 /* XSCOM bridge is first */ 1457 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1458 if (local_err) { 1459 error_propagate(errp, local_err); 1460 return; 1461 } 1462 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1463 1464 pcc->parent_realize(dev, &local_err); 1465 if (local_err) { 1466 error_propagate(errp, local_err); 1467 return; 1468 } 1469 1470 pnv_chip_quad_realize(chip9, &local_err); 1471 if (local_err) { 1472 error_propagate(errp, local_err); 1473 return; 1474 } 1475 1476 /* XIVE interrupt controller (POWER9) */ 1477 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1478 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1479 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1480 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1481 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1482 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1483 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1484 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1485 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1486 &error_abort); 1487 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1488 return; 1489 } 1490 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1491 &chip9->xive.xscom_regs); 1492 1493 /* Processor Service Interface (PSI) Host Bridge */ 1494 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1495 &error_fatal); 1496 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1497 return; 1498 } 1499 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1500 &PNV_PSI(psi9)->xscom_regs); 1501 1502 /* LPC */ 1503 object_property_set_link(OBJECT(&chip9->lpc), "psi", OBJECT(&chip9->psi), 1504 &error_abort); 1505 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1506 return; 1507 } 1508 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1509 &chip9->lpc.xscom_regs); 1510 1511 chip->fw_mr = &chip9->lpc.isa_fw; 1512 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1513 (uint64_t) PNV9_LPCM_BASE(chip)); 1514 1515 /* Create the simplified OCC model */ 1516 object_property_set_link(OBJECT(&chip9->occ), "psi", OBJECT(&chip9->psi), 1517 &error_abort); 1518 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1519 return; 1520 } 1521 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1522 1523 /* OCC SRAM model */ 1524 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1525 &chip9->occ.sram_regs); 1526 1527 /* HOMER */ 1528 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1529 &error_abort); 1530 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1531 return; 1532 } 1533 /* Homer Xscom region */ 1534 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1535 1536 /* Homer mmio region */ 1537 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1538 &chip9->homer.regs); 1539 1540 /* PHBs */ 1541 pnv_chip_power9_phb_realize(chip, &local_err); 1542 if (local_err) { 1543 error_propagate(errp, local_err); 1544 return; 1545 } 1546 } 1547 1548 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1549 { 1550 addr &= (PNV9_XSCOM_SIZE - 1); 1551 return addr >> 3; 1552 } 1553 1554 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1555 { 1556 DeviceClass *dc = DEVICE_CLASS(klass); 1557 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1558 1559 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1560 k->cores_mask = POWER9_CORE_MASK; 1561 k->core_pir = pnv_chip_core_pir_p9; 1562 k->intc_create = pnv_chip_power9_intc_create; 1563 k->intc_reset = pnv_chip_power9_intc_reset; 1564 k->intc_destroy = pnv_chip_power9_intc_destroy; 1565 k->intc_print_info = pnv_chip_power9_intc_print_info; 1566 k->isa_create = pnv_chip_power9_isa_create; 1567 k->dt_populate = pnv_chip_power9_dt_populate; 1568 k->pic_print_info = pnv_chip_power9_pic_print_info; 1569 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1570 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1571 dc->desc = "PowerNV Chip POWER9"; 1572 k->num_phbs = 6; 1573 1574 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1575 &k->parent_realize); 1576 } 1577 1578 static void pnv_chip_power10_instance_init(Object *obj) 1579 { 1580 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1581 1582 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1583 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1584 } 1585 1586 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1587 { 1588 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1589 PnvChip *chip = PNV_CHIP(dev); 1590 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1591 Error *local_err = NULL; 1592 1593 /* XSCOM bridge is first */ 1594 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1595 if (local_err) { 1596 error_propagate(errp, local_err); 1597 return; 1598 } 1599 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1600 1601 pcc->parent_realize(dev, &local_err); 1602 if (local_err) { 1603 error_propagate(errp, local_err); 1604 return; 1605 } 1606 1607 /* Processor Service Interface (PSI) Host Bridge */ 1608 object_property_set_int(OBJECT(&chip10->psi), "bar", 1609 PNV10_PSIHB_BASE(chip), &error_fatal); 1610 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1611 return; 1612 } 1613 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1614 &PNV_PSI(&chip10->psi)->xscom_regs); 1615 1616 /* LPC */ 1617 object_property_set_link(OBJECT(&chip10->lpc), "psi", 1618 OBJECT(&chip10->psi), &error_abort); 1619 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1620 return; 1621 } 1622 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1623 &chip10->lpc.xscom_regs); 1624 1625 chip->fw_mr = &chip10->lpc.isa_fw; 1626 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1627 (uint64_t) PNV10_LPCM_BASE(chip)); 1628 } 1629 1630 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1631 { 1632 addr &= (PNV10_XSCOM_SIZE - 1); 1633 return addr >> 3; 1634 } 1635 1636 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1637 { 1638 DeviceClass *dc = DEVICE_CLASS(klass); 1639 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1640 1641 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1642 k->cores_mask = POWER10_CORE_MASK; 1643 k->core_pir = pnv_chip_core_pir_p10; 1644 k->intc_create = pnv_chip_power10_intc_create; 1645 k->intc_reset = pnv_chip_power10_intc_reset; 1646 k->intc_destroy = pnv_chip_power10_intc_destroy; 1647 k->intc_print_info = pnv_chip_power10_intc_print_info; 1648 k->isa_create = pnv_chip_power10_isa_create; 1649 k->dt_populate = pnv_chip_power10_dt_populate; 1650 k->pic_print_info = pnv_chip_power10_pic_print_info; 1651 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1652 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1653 dc->desc = "PowerNV Chip POWER10"; 1654 1655 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1656 &k->parent_realize); 1657 } 1658 1659 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1660 { 1661 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1662 int cores_max; 1663 1664 /* 1665 * No custom mask for this chip, let's use the default one from * 1666 * the chip class 1667 */ 1668 if (!chip->cores_mask) { 1669 chip->cores_mask = pcc->cores_mask; 1670 } 1671 1672 /* filter alien core ids ! some are reserved */ 1673 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1674 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1675 chip->cores_mask); 1676 return; 1677 } 1678 chip->cores_mask &= pcc->cores_mask; 1679 1680 /* now that we have a sane layout, let check the number of cores */ 1681 cores_max = ctpop64(chip->cores_mask); 1682 if (chip->nr_cores > cores_max) { 1683 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1684 cores_max); 1685 return; 1686 } 1687 } 1688 1689 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1690 { 1691 Error *error = NULL; 1692 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1693 const char *typename = pnv_chip_core_typename(chip); 1694 int i, core_hwid; 1695 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1696 1697 if (!object_class_by_name(typename)) { 1698 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1699 return; 1700 } 1701 1702 /* Cores */ 1703 pnv_chip_core_sanitize(chip, &error); 1704 if (error) { 1705 error_propagate(errp, error); 1706 return; 1707 } 1708 1709 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1710 1711 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1712 && (i < chip->nr_cores); core_hwid++) { 1713 char core_name[32]; 1714 PnvCore *pnv_core; 1715 uint64_t xscom_core_base; 1716 1717 if (!(chip->cores_mask & (1ull << core_hwid))) { 1718 continue; 1719 } 1720 1721 pnv_core = PNV_CORE(object_new(typename)); 1722 1723 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1724 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1725 chip->cores[i] = pnv_core; 1726 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1727 chip->nr_threads, &error_fatal); 1728 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1729 core_hwid, &error_fatal); 1730 object_property_set_int(OBJECT(pnv_core), "pir", 1731 pcc->core_pir(chip, core_hwid), &error_fatal); 1732 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1733 &error_fatal); 1734 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1735 &error_abort); 1736 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1737 1738 /* Each core has an XSCOM MMIO region */ 1739 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1740 1741 pnv_xscom_add_subregion(chip, xscom_core_base, 1742 &pnv_core->xscom_regs); 1743 i++; 1744 } 1745 } 1746 1747 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1748 { 1749 PnvChip *chip = PNV_CHIP(dev); 1750 Error *error = NULL; 1751 1752 /* Cores */ 1753 pnv_chip_core_realize(chip, &error); 1754 if (error) { 1755 error_propagate(errp, error); 1756 return; 1757 } 1758 } 1759 1760 static Property pnv_chip_properties[] = { 1761 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1762 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1763 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1764 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1765 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1766 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1767 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1768 DEFINE_PROP_END_OF_LIST(), 1769 }; 1770 1771 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1772 { 1773 DeviceClass *dc = DEVICE_CLASS(klass); 1774 1775 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1776 dc->realize = pnv_chip_realize; 1777 device_class_set_props(dc, pnv_chip_properties); 1778 dc->desc = "PowerNV Chip"; 1779 } 1780 1781 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1782 { 1783 int i, j; 1784 1785 for (i = 0; i < chip->nr_cores; i++) { 1786 PnvCore *pc = chip->cores[i]; 1787 CPUCore *cc = CPU_CORE(pc); 1788 1789 for (j = 0; j < cc->nr_threads; j++) { 1790 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1791 return pc->threads[j]; 1792 } 1793 } 1794 } 1795 return NULL; 1796 } 1797 1798 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1799 { 1800 PnvMachineState *pnv = PNV_MACHINE(xi); 1801 int i, j; 1802 1803 for (i = 0; i < pnv->num_chips; i++) { 1804 PnvChip *chip = pnv->chips[i]; 1805 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1806 1807 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1808 return &chip8->psi.ics; 1809 } 1810 for (j = 0; j < chip->num_phbs; j++) { 1811 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1812 return &chip8->phbs[j].lsis; 1813 } 1814 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1815 return ICS(&chip8->phbs[j].msis); 1816 } 1817 } 1818 } 1819 return NULL; 1820 } 1821 1822 static void pnv_ics_resend(XICSFabric *xi) 1823 { 1824 PnvMachineState *pnv = PNV_MACHINE(xi); 1825 int i, j; 1826 1827 for (i = 0; i < pnv->num_chips; i++) { 1828 PnvChip *chip = pnv->chips[i]; 1829 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1830 1831 ics_resend(&chip8->psi.ics); 1832 for (j = 0; j < chip->num_phbs; j++) { 1833 ics_resend(&chip8->phbs[j].lsis); 1834 ics_resend(ICS(&chip8->phbs[j].msis)); 1835 } 1836 } 1837 } 1838 1839 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1840 { 1841 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1842 1843 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1844 } 1845 1846 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1847 Monitor *mon) 1848 { 1849 PnvMachineState *pnv = PNV_MACHINE(obj); 1850 int i; 1851 CPUState *cs; 1852 1853 CPU_FOREACH(cs) { 1854 PowerPCCPU *cpu = POWERPC_CPU(cs); 1855 1856 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1857 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1858 mon); 1859 } 1860 1861 for (i = 0; i < pnv->num_chips; i++) { 1862 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1863 } 1864 } 1865 1866 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1867 uint8_t nvt_blk, uint32_t nvt_idx, 1868 bool cam_ignore, uint8_t priority, 1869 uint32_t logic_serv, 1870 XiveTCTXMatch *match) 1871 { 1872 PnvMachineState *pnv = PNV_MACHINE(xfb); 1873 int total_count = 0; 1874 int i; 1875 1876 for (i = 0; i < pnv->num_chips; i++) { 1877 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1878 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1879 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1880 int count; 1881 1882 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1883 priority, logic_serv, match); 1884 1885 if (count < 0) { 1886 return count; 1887 } 1888 1889 total_count += count; 1890 } 1891 1892 return total_count; 1893 } 1894 1895 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1896 { 1897 MachineClass *mc = MACHINE_CLASS(oc); 1898 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1899 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1900 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1901 1902 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1903 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1904 1905 xic->icp_get = pnv_icp_get; 1906 xic->ics_get = pnv_ics_get; 1907 xic->ics_resend = pnv_ics_resend; 1908 1909 pmc->compat = compat; 1910 pmc->compat_size = sizeof(compat); 1911 } 1912 1913 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1914 { 1915 MachineClass *mc = MACHINE_CLASS(oc); 1916 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1917 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1918 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1919 1920 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1921 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1922 xfc->match_nvt = pnv_match_nvt; 1923 1924 mc->alias = "powernv"; 1925 1926 pmc->compat = compat; 1927 pmc->compat_size = sizeof(compat); 1928 pmc->dt_power_mgt = pnv_dt_power_mgt; 1929 } 1930 1931 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1932 { 1933 MachineClass *mc = MACHINE_CLASS(oc); 1934 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1935 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1936 1937 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1938 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 1939 1940 pmc->compat = compat; 1941 pmc->compat_size = sizeof(compat); 1942 pmc->dt_power_mgt = pnv_dt_power_mgt; 1943 } 1944 1945 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1946 { 1947 PnvMachineState *pnv = PNV_MACHINE(obj); 1948 1949 return !!pnv->fw_load_addr; 1950 } 1951 1952 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1953 { 1954 PnvMachineState *pnv = PNV_MACHINE(obj); 1955 1956 if (value) { 1957 pnv->fw_load_addr = 0x8000000; 1958 } 1959 } 1960 1961 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 1962 { 1963 PowerPCCPU *cpu = POWERPC_CPU(cs); 1964 CPUPPCState *env = &cpu->env; 1965 1966 cpu_synchronize_state(cs); 1967 ppc_cpu_do_system_reset(cs); 1968 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 1969 /* 1970 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 1971 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 1972 * (PPC_BIT(43)). 1973 */ 1974 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 1975 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 1976 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 1977 } 1978 } else { 1979 /* 1980 * For non-powersave system resets, SRR1[42:45] are defined to be 1981 * implementation-dependent. The POWER9 User Manual specifies that 1982 * an external (SCOM driven, which may come from a BMC nmi command or 1983 * another CPU requesting a NMI IPI) system reset exception should be 1984 * 0b0010 (PPC_BIT(44)). 1985 */ 1986 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 1987 } 1988 } 1989 1990 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 1991 { 1992 CPUState *cs; 1993 1994 CPU_FOREACH(cs) { 1995 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 1996 } 1997 } 1998 1999 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2000 { 2001 MachineClass *mc = MACHINE_CLASS(oc); 2002 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2003 NMIClass *nc = NMI_CLASS(oc); 2004 2005 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2006 mc->init = pnv_init; 2007 mc->reset = pnv_reset; 2008 mc->max_cpus = MAX_CPUS; 2009 /* Pnv provides a AHCI device for storage */ 2010 mc->block_default_type = IF_IDE; 2011 mc->no_parallel = 1; 2012 mc->default_boot_order = NULL; 2013 /* 2014 * RAM defaults to less than 2048 for 32-bit hosts, and large 2015 * enough to fit the maximum initrd size at it's load address 2016 */ 2017 mc->default_ram_size = 1 * GiB; 2018 mc->default_ram_id = "pnv.ram"; 2019 ispc->print_info = pnv_pic_print_info; 2020 nc->nmi_monitor_handler = pnv_nmi; 2021 2022 object_class_property_add_bool(oc, "hb-mode", 2023 pnv_machine_get_hb, pnv_machine_set_hb); 2024 object_class_property_set_description(oc, "hb-mode", 2025 "Use a hostboot like boot loader"); 2026 } 2027 2028 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2029 { \ 2030 .name = type, \ 2031 .class_init = class_initfn, \ 2032 .parent = TYPE_PNV8_CHIP, \ 2033 } 2034 2035 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2036 { \ 2037 .name = type, \ 2038 .class_init = class_initfn, \ 2039 .parent = TYPE_PNV9_CHIP, \ 2040 } 2041 2042 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2043 { \ 2044 .name = type, \ 2045 .class_init = class_initfn, \ 2046 .parent = TYPE_PNV10_CHIP, \ 2047 } 2048 2049 static const TypeInfo types[] = { 2050 { 2051 .name = MACHINE_TYPE_NAME("powernv10"), 2052 .parent = TYPE_PNV_MACHINE, 2053 .class_init = pnv_machine_power10_class_init, 2054 }, 2055 { 2056 .name = MACHINE_TYPE_NAME("powernv9"), 2057 .parent = TYPE_PNV_MACHINE, 2058 .class_init = pnv_machine_power9_class_init, 2059 .interfaces = (InterfaceInfo[]) { 2060 { TYPE_XIVE_FABRIC }, 2061 { }, 2062 }, 2063 }, 2064 { 2065 .name = MACHINE_TYPE_NAME("powernv8"), 2066 .parent = TYPE_PNV_MACHINE, 2067 .class_init = pnv_machine_power8_class_init, 2068 .interfaces = (InterfaceInfo[]) { 2069 { TYPE_XICS_FABRIC }, 2070 { }, 2071 }, 2072 }, 2073 { 2074 .name = TYPE_PNV_MACHINE, 2075 .parent = TYPE_MACHINE, 2076 .abstract = true, 2077 .instance_size = sizeof(PnvMachineState), 2078 .class_init = pnv_machine_class_init, 2079 .class_size = sizeof(PnvMachineClass), 2080 .interfaces = (InterfaceInfo[]) { 2081 { TYPE_INTERRUPT_STATS_PROVIDER }, 2082 { TYPE_NMI }, 2083 { }, 2084 }, 2085 }, 2086 { 2087 .name = TYPE_PNV_CHIP, 2088 .parent = TYPE_SYS_BUS_DEVICE, 2089 .class_init = pnv_chip_class_init, 2090 .instance_size = sizeof(PnvChip), 2091 .class_size = sizeof(PnvChipClass), 2092 .abstract = true, 2093 }, 2094 2095 /* 2096 * P10 chip and variants 2097 */ 2098 { 2099 .name = TYPE_PNV10_CHIP, 2100 .parent = TYPE_PNV_CHIP, 2101 .instance_init = pnv_chip_power10_instance_init, 2102 .instance_size = sizeof(Pnv10Chip), 2103 }, 2104 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2105 2106 /* 2107 * P9 chip and variants 2108 */ 2109 { 2110 .name = TYPE_PNV9_CHIP, 2111 .parent = TYPE_PNV_CHIP, 2112 .instance_init = pnv_chip_power9_instance_init, 2113 .instance_size = sizeof(Pnv9Chip), 2114 }, 2115 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2116 2117 /* 2118 * P8 chip and variants 2119 */ 2120 { 2121 .name = TYPE_PNV8_CHIP, 2122 .parent = TYPE_PNV_CHIP, 2123 .instance_init = pnv_chip_power8_instance_init, 2124 .instance_size = sizeof(Pnv8Chip), 2125 }, 2126 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2127 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2128 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2129 pnv_chip_power8nvl_class_init), 2130 }; 2131 2132 DEFINE_TYPES(types) 2133