1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016-2024, IBM Corporation. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2.1 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/datadir.h" 24 #include "qemu/log.h" 25 #include "qemu/units.h" 26 #include "qemu/cutils.h" 27 #include "qapi/error.h" 28 #include "system/qtest.h" 29 #include "system/system.h" 30 #include "system/numa.h" 31 #include "system/reset.h" 32 #include "system/runstate.h" 33 #include "system/cpus.h" 34 #include "system/device_tree.h" 35 #include "system/hw_accel.h" 36 #include "target/ppc/cpu.h" 37 #include "hw/ppc/fdt.h" 38 #include "hw/ppc/ppc.h" 39 #include "hw/ppc/pnv.h" 40 #include "hw/ppc/pnv_core.h" 41 #include "hw/loader.h" 42 #include "hw/nmi.h" 43 #include "qapi/visitor.h" 44 #include "hw/intc/intc.h" 45 #include "hw/ipmi/ipmi.h" 46 #include "target/ppc/mmu-hash64.h" 47 #include "hw/pci/msi.h" 48 #include "hw/pci-host/pnv_phb.h" 49 #include "hw/pci-host/pnv_phb3.h" 50 #include "hw/pci-host/pnv_phb4.h" 51 52 #include "hw/ppc/xics.h" 53 #include "hw/qdev-properties.h" 54 #include "hw/ppc/pnv_chip.h" 55 #include "hw/ppc/pnv_xscom.h" 56 #include "hw/ppc/pnv_pnor.h" 57 58 #include "hw/isa/isa.h" 59 #include "hw/char/serial-isa.h" 60 #include "hw/rtc/mc146818rtc.h" 61 62 #include <libfdt.h> 63 64 #define FDT_MAX_SIZE (1 * MiB) 65 66 #define FW_FILE_NAME "skiboot.lid" 67 #define FW_LOAD_ADDR 0x0 68 #define FW_MAX_SIZE (16 * MiB) 69 70 #define PNOR_FILE_NAME "pnv-pnor.bin" 71 72 #define KERNEL_LOAD_ADDR 0x20000000 73 #define KERNEL_MAX_SIZE (128 * MiB) 74 #define INITRD_LOAD_ADDR 0x28000000 75 #define INITRD_MAX_SIZE (128 * MiB) 76 77 static const char *pnv_chip_core_typename(const PnvChip *o) 78 { 79 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 80 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 81 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 82 const char *core_type = object_class_get_name(object_class_by_name(s)); 83 g_free(s); 84 return core_type; 85 } 86 87 /* 88 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 89 * 4 * 4 sockets * 12 cores * 8 threads = 1536 90 * Let's make it 2^11 91 */ 92 #define MAX_CPUS 2048 93 94 /* 95 * Memory nodes are created by hostboot, one for each range of memory 96 * that has a different "affinity". In practice, it means one range 97 * per chip. 98 */ 99 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 100 { 101 char *mem_name; 102 uint64_t mem_reg_property[2]; 103 int off; 104 105 mem_reg_property[0] = cpu_to_be64(start); 106 mem_reg_property[1] = cpu_to_be64(size); 107 108 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 109 off = fdt_add_subnode(fdt, 0, mem_name); 110 g_free(mem_name); 111 112 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 113 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 114 sizeof(mem_reg_property)))); 115 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 116 } 117 118 static int get_cpus_node(void *fdt) 119 { 120 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 121 122 if (cpus_offset < 0) { 123 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 124 if (cpus_offset) { 125 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 126 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 127 } 128 } 129 _FDT(cpus_offset); 130 return cpus_offset; 131 } 132 133 /* 134 * The PowerNV cores (and threads) need to use real HW ids and not an 135 * incremental index like it has been done on other platforms. This HW 136 * id is stored in the CPU PIR, it is used to create cpu nodes in the 137 * device tree, used in XSCOM to address cores and in interrupt 138 * servers. 139 */ 140 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 141 { 142 PowerPCCPU *cpu = pc->threads[0]; 143 CPUState *cs = CPU(cpu); 144 DeviceClass *dc = DEVICE_GET_CLASS(cs); 145 int smt_threads = CPU_CORE(pc)->nr_threads; 146 CPUPPCState *env = &cpu->env; 147 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 148 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 149 uint32_t *servers_prop; 150 int i; 151 uint32_t pir, tir; 152 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 153 0xffffffff, 0xffffffff}; 154 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 155 uint32_t cpufreq = 1000000000; 156 uint32_t page_sizes_prop[64]; 157 size_t page_sizes_prop_size; 158 int offset; 159 char *nodename; 160 int cpus_offset = get_cpus_node(fdt); 161 162 pnv_cc->get_pir_tir(chip, pc->hwid, 0, &pir, &tir); 163 164 /* Only one DT node per (big) core */ 165 g_assert(tir == 0); 166 167 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 168 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 169 _FDT(offset); 170 g_free(nodename); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 173 174 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 175 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 176 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 177 178 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 179 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 180 env->dcache_line_size))); 181 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 182 env->dcache_line_size))); 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 184 env->icache_line_size))); 185 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 186 env->icache_line_size))); 187 188 if (pcc->l1_dcache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 190 pcc->l1_dcache_size))); 191 } else { 192 warn_report("Unknown L1 dcache size for cpu"); 193 } 194 if (pcc->l1_icache_size) { 195 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 196 pcc->l1_icache_size))); 197 } else { 198 warn_report("Unknown L1 icache size for cpu"); 199 } 200 201 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 202 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 203 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 204 cpu->hash64_opts->slb_size))); 205 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 206 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 207 208 if (ppc_has_spr(cpu, SPR_PURR)) { 209 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 210 } 211 212 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 213 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 214 segs, sizeof(segs)))); 215 } 216 217 /* 218 * Advertise VMX/VSX (vector extensions) if available 219 * 0 / no property == no vector extensions 220 * 1 == VMX / Altivec available 221 * 2 == VSX available 222 */ 223 if (env->insns_flags & PPC_ALTIVEC) { 224 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 225 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 227 } 228 229 /* 230 * Advertise DFP (Decimal Floating Point) if available 231 * 0 / no property == no DFP 232 * 1 == DFP available 233 */ 234 if (env->insns_flags2 & PPC2_DFP) { 235 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 236 } 237 238 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 239 sizeof(page_sizes_prop)); 240 if (page_sizes_prop_size) { 241 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 242 page_sizes_prop, page_sizes_prop_size))); 243 } 244 245 /* Build interrupt servers properties */ 246 if (pc->big_core) { 247 servers_prop = g_new(uint32_t, smt_threads * 2); 248 for (i = 0; i < smt_threads; i++) { 249 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 250 servers_prop[i * 2] = cpu_to_be32(pir); 251 252 pnv_cc->get_pir_tir(chip, pc->hwid + 1, i, &pir, NULL); 253 servers_prop[i * 2 + 1] = cpu_to_be32(pir); 254 } 255 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 256 servers_prop, sizeof(*servers_prop) * smt_threads 257 * 2))); 258 } else { 259 servers_prop = g_new(uint32_t, smt_threads); 260 for (i = 0; i < smt_threads; i++) { 261 pnv_cc->get_pir_tir(chip, pc->hwid, i, &pir, NULL); 262 servers_prop[i] = cpu_to_be32(pir); 263 } 264 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 265 servers_prop, sizeof(*servers_prop) * smt_threads))); 266 } 267 g_free(servers_prop); 268 269 return offset; 270 } 271 272 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 273 uint32_t nr_threads) 274 { 275 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 276 uint32_t pir; 277 uint64_t addr; 278 char *name; 279 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 280 uint32_t irange[2], i, rsize; 281 uint64_t *reg; 282 int offset; 283 284 pcc->get_pir_tir(chip, hwid, 0, &pir, NULL); 285 addr = PNV_ICP_BASE(chip) | (pir << 12); 286 287 irange[0] = cpu_to_be32(pir); 288 irange[1] = cpu_to_be32(nr_threads); 289 290 rsize = sizeof(uint64_t) * 2 * nr_threads; 291 reg = g_malloc(rsize); 292 for (i = 0; i < nr_threads; i++) { 293 /* We know P8 PIR is linear with thread id */ 294 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 295 reg[i * 2 + 1] = cpu_to_be64(0x1000); 296 } 297 298 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 299 offset = fdt_add_subnode(fdt, 0, name); 300 _FDT(offset); 301 g_free(name); 302 303 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 304 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 305 _FDT((fdt_setprop_string(fdt, offset, "device_type", 306 "PowerPC-External-Interrupt-Presentation"))); 307 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 308 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 309 irange, sizeof(irange)))); 310 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 311 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 312 g_free(reg); 313 } 314 315 /* 316 * Adds a PnvPHB to the chip on P8. 317 * Implemented here, like for defaults PHBs 318 */ 319 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 320 { 321 Pnv8Chip *chip8 = PNV8_CHIP(chip); 322 323 phb->chip = chip; 324 325 chip8->phbs[chip8->num_phbs] = phb; 326 chip8->num_phbs++; 327 return chip; 328 } 329 330 /* 331 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 332 * HTM is always enabled because TCG does implement HTM, it's just a 333 * degenerate implementation. 334 */ 335 static const uint8_t pa_features_207[] = { 24, 0, 336 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 337 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 338 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 339 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 340 341 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 342 { 343 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 344 int i; 345 346 pnv_dt_xscom(chip, fdt, 0, 347 cpu_to_be64(PNV_XSCOM_BASE(chip)), 348 cpu_to_be64(PNV_XSCOM_SIZE), 349 compat, sizeof(compat)); 350 351 for (i = 0; i < chip->nr_cores; i++) { 352 PnvCore *pnv_core = chip->cores[i]; 353 int offset; 354 355 offset = pnv_dt_core(chip, pnv_core, fdt); 356 357 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 358 pa_features_207, sizeof(pa_features_207)))); 359 360 /* Interrupt Control Presenters (ICP). One per core. */ 361 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 362 } 363 364 if (chip->ram_size) { 365 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 366 } 367 } 368 369 /* 370 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 371 */ 372 static const uint8_t pa_features_300[] = { 66, 0, 373 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 374 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 375 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 376 /* 6: DS207 */ 377 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 378 /* 16: Vector */ 379 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 380 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 381 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 382 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 383 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 384 /* 32: LE atomic, 34: EBB + ext EBB */ 385 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 386 /* 40: Radix MMU */ 387 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 388 /* 42: PM, 44: PC RA, 46: SC vec'd */ 389 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 390 /* 48: SIMD, 50: QP BFP, 52: String */ 391 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 392 /* 54: DecFP, 56: DecI, 58: SHA */ 393 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 394 /* 60: NM atomic, 62: RNG */ 395 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 396 }; 397 398 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 399 { 400 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 401 int i; 402 403 pnv_dt_xscom(chip, fdt, 0, 404 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 405 cpu_to_be64(PNV9_XSCOM_SIZE), 406 compat, sizeof(compat)); 407 408 for (i = 0; i < chip->nr_cores; i++) { 409 PnvCore *pnv_core = chip->cores[i]; 410 int offset; 411 412 offset = pnv_dt_core(chip, pnv_core, fdt); 413 414 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 415 pa_features_300, sizeof(pa_features_300)))); 416 417 if (pnv_core->big_core) { 418 i++; /* Big-core groups two QEMU cores */ 419 } 420 } 421 422 if (chip->ram_size) { 423 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 424 } 425 426 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 427 } 428 429 /* 430 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 431 * always disables copy/paste. 432 */ 433 static const uint8_t pa_features_31[] = { 74, 0, 434 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 435 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 436 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 437 /* 6: DS207 */ 438 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 439 /* 16: Vector */ 440 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 441 /* 18: Vec. Scalar, 20: Vec. XOR */ 442 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 443 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 444 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 445 /* 32: LE atomic, 34: EBB + ext EBB */ 446 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 447 /* 40: Radix MMU */ 448 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 449 /* 42: PM, 44: PC RA, 46: SC vec'd */ 450 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 451 /* 48: SIMD, 50: QP BFP, 52: String */ 452 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 453 /* 54: DecFP, 56: DecI, 58: SHA */ 454 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 455 /* 60: NM atomic, 62: RNG */ 456 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 457 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 458 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 459 /* 72: [P]HASHST/[P]HASHCHK */ 460 0x80, 0x00, /* 72 - 73 */ 461 }; 462 463 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 464 { 465 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 466 int i; 467 468 pnv_dt_xscom(chip, fdt, 0, 469 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 470 cpu_to_be64(PNV10_XSCOM_SIZE), 471 compat, sizeof(compat)); 472 473 for (i = 0; i < chip->nr_cores; i++) { 474 PnvCore *pnv_core = chip->cores[i]; 475 int offset; 476 477 offset = pnv_dt_core(chip, pnv_core, fdt); 478 479 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 480 pa_features_31, sizeof(pa_features_31)))); 481 482 if (pnv_core->big_core) { 483 i++; /* Big-core groups two QEMU cores */ 484 } 485 } 486 487 if (chip->ram_size) { 488 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 489 } 490 491 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 492 } 493 494 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 495 { 496 uint32_t io_base = d->ioport_id; 497 uint32_t io_regs[] = { 498 cpu_to_be32(1), 499 cpu_to_be32(io_base), 500 cpu_to_be32(2) 501 }; 502 char *name; 503 int node; 504 505 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 506 node = fdt_add_subnode(fdt, lpc_off, name); 507 _FDT(node); 508 g_free(name); 509 510 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 511 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 512 } 513 514 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 515 { 516 const char compatible[] = "ns16550\0pnpPNP,501"; 517 uint32_t io_base = d->ioport_id; 518 uint32_t io_regs[] = { 519 cpu_to_be32(1), 520 cpu_to_be32(io_base), 521 cpu_to_be32(8) 522 }; 523 uint32_t irq; 524 char *name; 525 int node; 526 527 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 528 529 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 530 node = fdt_add_subnode(fdt, lpc_off, name); 531 _FDT(node); 532 g_free(name); 533 534 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 535 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 536 sizeof(compatible)))); 537 538 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 539 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 540 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 541 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 542 fdt_get_phandle(fdt, lpc_off)))); 543 544 /* This is needed by Linux */ 545 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 546 } 547 548 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 549 { 550 const char compatible[] = "bt\0ipmi-bt"; 551 uint32_t io_base; 552 uint32_t io_regs[] = { 553 cpu_to_be32(1), 554 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 555 cpu_to_be32(3) 556 }; 557 uint32_t irq; 558 char *name; 559 int node; 560 561 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 562 io_regs[1] = cpu_to_be32(io_base); 563 564 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 565 566 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 567 node = fdt_add_subnode(fdt, lpc_off, name); 568 _FDT(node); 569 g_free(name); 570 571 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 572 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 573 sizeof(compatible)))); 574 575 /* Mark it as reserved to avoid Linux trying to claim it */ 576 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 577 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 578 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 579 fdt_get_phandle(fdt, lpc_off)))); 580 } 581 582 typedef struct ForeachPopulateArgs { 583 void *fdt; 584 int offset; 585 } ForeachPopulateArgs; 586 587 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 588 { 589 ForeachPopulateArgs *args = opaque; 590 ISADevice *d = ISA_DEVICE(dev); 591 592 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 593 pnv_dt_rtc(d, args->fdt, args->offset); 594 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 595 pnv_dt_serial(d, args->fdt, args->offset); 596 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 597 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 598 } else { 599 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 600 d->ioport_id); 601 } 602 603 return 0; 604 } 605 606 /* 607 * The default LPC bus of a multichip system is on chip 0. It's 608 * recognized by the firmware (skiboot) using a "primary" property. 609 */ 610 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 611 { 612 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 613 ForeachPopulateArgs args = { 614 .fdt = fdt, 615 .offset = isa_offset, 616 }; 617 uint32_t phandle; 618 619 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 620 621 phandle = qemu_fdt_alloc_phandle(fdt); 622 assert(phandle > 0); 623 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 624 625 /* 626 * ISA devices are not necessarily parented to the ISA bus so we 627 * can not use object_child_foreach() 628 */ 629 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 630 &args); 631 } 632 633 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 634 { 635 int off; 636 637 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 638 off = fdt_add_subnode(fdt, off, "power-mgt"); 639 640 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 641 } 642 643 static void *pnv_dt_create(MachineState *machine) 644 { 645 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 646 PnvMachineState *pnv = PNV_MACHINE(machine); 647 void *fdt; 648 char *buf; 649 int off; 650 int i; 651 652 fdt = g_malloc0(FDT_MAX_SIZE); 653 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 654 655 /* /qemu node */ 656 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 657 658 /* Root node */ 659 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 660 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 661 _FDT((fdt_setprop_string(fdt, 0, "model", 662 "IBM PowerNV (emulated by qemu)"))); 663 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 664 665 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 666 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 667 if (qemu_uuid_set) { 668 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 669 } 670 g_free(buf); 671 672 off = fdt_add_subnode(fdt, 0, "chosen"); 673 if (machine->kernel_cmdline) { 674 _FDT((fdt_setprop_string(fdt, off, "bootargs", 675 machine->kernel_cmdline))); 676 } 677 678 if (pnv->initrd_size) { 679 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 680 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 681 682 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 683 &start_prop, sizeof(start_prop)))); 684 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 685 &end_prop, sizeof(end_prop)))); 686 } 687 688 /* Populate device tree for each chip */ 689 for (i = 0; i < pnv->num_chips; i++) { 690 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 691 } 692 693 /* Populate ISA devices on chip 0 */ 694 pnv_dt_isa(pnv, fdt); 695 696 if (pnv->bmc) { 697 pnv_dt_bmc_sensors(pnv->bmc, fdt); 698 } 699 700 /* Create an extra node for power management on machines that support it */ 701 if (pmc->dt_power_mgt) { 702 pmc->dt_power_mgt(pnv, fdt); 703 } 704 705 return fdt; 706 } 707 708 static void pnv_powerdown_notify(Notifier *n, void *opaque) 709 { 710 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 711 712 if (pnv->bmc) { 713 pnv_bmc_powerdown(pnv->bmc); 714 } 715 } 716 717 static void pnv_reset(MachineState *machine, ResetType type) 718 { 719 PnvMachineState *pnv = PNV_MACHINE(machine); 720 IPMIBmc *bmc; 721 void *fdt; 722 723 qemu_devices_reset(type); 724 725 /* 726 * The machine should provide by default an internal BMC simulator. 727 * If not, try to use the BMC device that was provided on the command 728 * line. 729 */ 730 bmc = pnv_bmc_find(&error_fatal); 731 if (!pnv->bmc) { 732 if (!bmc) { 733 if (!qtest_enabled()) { 734 warn_report("machine has no BMC device. Use '-device " 735 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 736 "to define one"); 737 } 738 } else { 739 pnv_bmc_set_pnor(bmc, pnv->pnor); 740 pnv->bmc = bmc; 741 } 742 } 743 744 if (machine->fdt) { 745 fdt = machine->fdt; 746 } else { 747 fdt = pnv_dt_create(machine); 748 /* Pack resulting tree */ 749 _FDT((fdt_pack(fdt))); 750 } 751 752 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 753 754 /* Update machine->fdt with latest fdt */ 755 if (machine->fdt != fdt) { 756 /* 757 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 758 * the existing machine->fdt to avoid leaking it during 759 * a reset. 760 */ 761 g_free(machine->fdt); 762 machine->fdt = fdt; 763 } 764 } 765 766 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 767 { 768 Pnv8Chip *chip8 = PNV8_CHIP(chip); 769 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 770 771 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 772 773 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 774 } 775 776 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 777 { 778 Pnv8Chip *chip8 = PNV8_CHIP(chip); 779 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 780 781 qdev_connect_gpio_out_named(DEVICE(&chip8->lpc), "LPCHC", 0, irq); 782 783 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 784 } 785 786 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 787 { 788 Pnv9Chip *chip9 = PNV9_CHIP(chip); 789 qemu_irq irq; 790 791 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 792 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "LPCHC", 0, irq); 793 794 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ0); 795 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 0, irq); 796 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ1); 797 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 1, irq); 798 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ2); 799 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 2, irq); 800 irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPC_SIRQ3); 801 qdev_connect_gpio_out_named(DEVICE(&chip9->lpc), "SERIRQ", 3, irq); 802 803 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 804 } 805 806 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 807 { 808 Pnv10Chip *chip10 = PNV10_CHIP(chip); 809 qemu_irq irq; 810 811 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 812 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "LPCHC", 0, irq); 813 814 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ0); 815 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 0, irq); 816 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ1); 817 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 1, irq); 818 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ2); 819 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 2, irq); 820 irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPC_SIRQ3); 821 qdev_connect_gpio_out_named(DEVICE(&chip10->lpc), "SERIRQ", 3, irq); 822 823 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 824 } 825 826 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 827 { 828 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 829 } 830 831 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 832 { 833 Pnv8Chip *chip8 = PNV8_CHIP(chip); 834 int i; 835 836 ics_pic_print_info(&chip8->psi.ics, buf); 837 838 for (i = 0; i < chip8->num_phbs; i++) { 839 PnvPHB *phb = chip8->phbs[i]; 840 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 841 842 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 843 ics_pic_print_info(&phb3->lsis, buf); 844 } 845 } 846 847 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 848 { 849 GString *buf = opaque; 850 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 851 852 if (!phb) { 853 return 0; 854 } 855 856 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 857 858 return 0; 859 } 860 861 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 862 { 863 Pnv9Chip *chip9 = PNV9_CHIP(chip); 864 865 pnv_xive_pic_print_info(&chip9->xive, buf); 866 pnv_psi_pic_print_info(&chip9->psi, buf); 867 object_child_foreach_recursive(OBJECT(chip), 868 pnv_chip_power9_pic_print_info_child, buf); 869 } 870 871 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 872 uint32_t core_id) 873 { 874 return PNV_XSCOM_EX_BASE(core_id); 875 } 876 877 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 878 uint32_t core_id) 879 { 880 return PNV9_XSCOM_EC_BASE(core_id); 881 } 882 883 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 884 uint32_t core_id) 885 { 886 return PNV10_XSCOM_EC_BASE(core_id); 887 } 888 889 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 890 { 891 PowerPCCPUClass *ppc_default = 892 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 893 PowerPCCPUClass *ppc = 894 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 895 896 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 897 } 898 899 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 900 { 901 ISADevice *dev = isa_new("isa-ipmi-bt"); 902 903 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 904 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 905 isa_realize_and_unref(dev, bus, &error_fatal); 906 } 907 908 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 909 { 910 Pnv10Chip *chip10 = PNV10_CHIP(chip); 911 912 pnv_xive2_pic_print_info(&chip10->xive, buf); 913 pnv_psi_pic_print_info(&chip10->psi, buf); 914 object_child_foreach_recursive(OBJECT(chip), 915 pnv_chip_power9_pic_print_info_child, buf); 916 } 917 918 /* Always give the first 1GB to chip 0 else we won't boot */ 919 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 920 { 921 MachineState *machine = MACHINE(pnv); 922 uint64_t ram_per_chip; 923 924 assert(machine->ram_size >= 1 * GiB); 925 926 ram_per_chip = machine->ram_size / pnv->num_chips; 927 if (ram_per_chip >= 1 * GiB) { 928 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 929 } 930 931 assert(pnv->num_chips > 1); 932 933 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 934 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 935 } 936 937 static void pnv_init(MachineState *machine) 938 { 939 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 940 PnvMachineState *pnv = PNV_MACHINE(machine); 941 MachineClass *mc = MACHINE_GET_CLASS(machine); 942 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 943 int max_smt_threads = pmc->max_smt_threads; 944 char *fw_filename; 945 long fw_size; 946 uint64_t chip_ram_start = 0; 947 int i; 948 char *chip_typename; 949 DriveInfo *pnor; 950 DeviceState *dev; 951 952 if (kvm_enabled()) { 953 error_report("machine %s does not support the KVM accelerator", 954 mc->name); 955 exit(EXIT_FAILURE); 956 } 957 958 /* allocate RAM */ 959 if (machine->ram_size < mc->default_ram_size) { 960 char *sz = size_to_str(mc->default_ram_size); 961 error_report("Invalid RAM size, should be bigger than %s", sz); 962 g_free(sz); 963 exit(EXIT_FAILURE); 964 } 965 966 /* checks for invalid option combinations */ 967 if (machine->dtb && (strlen(machine->kernel_cmdline) != 0)) { 968 error_report("-append and -dtb cannot be used together, as passed" 969 " command line is ignored in case of custom dtb"); 970 exit(EXIT_FAILURE); 971 } 972 973 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 974 975 /* 976 * Create our simple PNOR device 977 */ 978 dev = qdev_new(TYPE_PNV_PNOR); 979 pnor = drive_get(IF_MTD, 0, 0); 980 if (!pnor && defaults_enabled()) { 981 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, PNOR_FILE_NAME); 982 if (!fw_filename) { 983 warn_report("Could not find PNOR '%s'", PNOR_FILE_NAME); 984 } else { 985 QemuOpts *opts; 986 opts = drive_add(IF_MTD, -1, fw_filename, "format=raw,readonly=on"); 987 pnor = drive_new(opts, IF_MTD, &error_fatal); 988 g_free(fw_filename); 989 } 990 } 991 if (pnor) { 992 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 993 } 994 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 995 pnv->pnor = PNV_PNOR(dev); 996 997 /* load skiboot firmware */ 998 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 999 if (!fw_filename) { 1000 error_report("Could not find OPAL firmware '%s'", bios_name); 1001 exit(1); 1002 } 1003 1004 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 1005 if (fw_size < 0) { 1006 error_report("Could not load OPAL firmware '%s'", fw_filename); 1007 exit(1); 1008 } 1009 g_free(fw_filename); 1010 1011 /* load kernel */ 1012 if (machine->kernel_filename) { 1013 long kernel_size; 1014 1015 kernel_size = load_image_targphys(machine->kernel_filename, 1016 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 1017 if (kernel_size < 0) { 1018 error_report("Could not load kernel '%s'", 1019 machine->kernel_filename); 1020 exit(1); 1021 } 1022 } 1023 1024 /* load initrd */ 1025 if (machine->initrd_filename) { 1026 pnv->initrd_base = INITRD_LOAD_ADDR; 1027 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 1028 pnv->initrd_base, INITRD_MAX_SIZE); 1029 if (pnv->initrd_size < 0) { 1030 error_report("Could not load initial ram disk '%s'", 1031 machine->initrd_filename); 1032 exit(1); 1033 } 1034 } 1035 1036 /* load dtb if passed */ 1037 if (machine->dtb) { 1038 int fdt_size; 1039 1040 warn_report("with manually passed dtb, some options like '-append'" 1041 " will get ignored and the dtb passed will be used as-is"); 1042 1043 /* read the file 'machine->dtb', and load it into 'fdt' buffer */ 1044 machine->fdt = load_device_tree(machine->dtb, &fdt_size); 1045 if (!machine->fdt) { 1046 error_report("Could not load dtb '%s'", machine->dtb); 1047 exit(1); 1048 } 1049 } 1050 1051 /* MSIs are supported on this platform */ 1052 msi_nonbroken = true; 1053 1054 /* 1055 * Check compatibility of the specified CPU with the machine 1056 * default. 1057 */ 1058 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 1059 error_report("invalid CPU model '%s' for %s machine", 1060 machine->cpu_type, mc->name); 1061 exit(1); 1062 } 1063 1064 /* Create the processor chips */ 1065 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 1066 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 1067 i, machine->cpu_type); 1068 if (!object_class_by_name(chip_typename)) { 1069 error_report("invalid chip model '%.*s' for %s machine", 1070 i, machine->cpu_type, mc->name); 1071 exit(1); 1072 } 1073 1074 /* Set lpar-per-core mode if lpar-per-thread is not supported */ 1075 if (!pmc->has_lpar_per_thread) { 1076 pnv->lpar_per_core = true; 1077 } 1078 1079 pnv->num_chips = 1080 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 1081 1082 if (pnv->big_core) { 1083 if (machine->smp.threads % 2 == 1) { 1084 error_report("Cannot support %d threads with big-core option " 1085 "because it must be an even number", 1086 machine->smp.threads); 1087 exit(1); 1088 } 1089 max_smt_threads *= 2; 1090 } 1091 1092 if (machine->smp.threads > max_smt_threads) { 1093 error_report("Cannot support more than %d threads/core " 1094 "on %s machine", max_smt_threads, mc->desc); 1095 if (pmc->max_smt_threads == 4) { 1096 error_report("(use big-core=on for 8 threads per core)"); 1097 } 1098 exit(1); 1099 } 1100 1101 if (pnv->big_core) { 1102 /* 1103 * powernv models PnvCore as a SMT4 core. Big-core requires 2xPnvCore 1104 * per core, so adjust topology here. pnv_dt_core() processor 1105 * device-tree and TCG SMT code make the 2 cores appear as one big core 1106 * from software point of view. pnv pervasive models and xscoms tend to 1107 * see the big core as 2 small core halves. 1108 */ 1109 machine->smp.cores *= 2; 1110 machine->smp.threads /= 2; 1111 } 1112 1113 if (!is_power_of_2(machine->smp.threads)) { 1114 error_report("Cannot support %d threads/core on a powernv " 1115 "machine because it must be a power of 2", 1116 machine->smp.threads); 1117 exit(1); 1118 } 1119 1120 /* 1121 * TODO: should we decide on how many chips we can create based 1122 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1123 */ 1124 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1125 error_report("invalid number of chips: '%d'", pnv->num_chips); 1126 error_printf( 1127 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1128 exit(1); 1129 } 1130 1131 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1132 for (i = 0; i < pnv->num_chips; i++) { 1133 char chip_name[32]; 1134 Object *chip = OBJECT(qdev_new(chip_typename)); 1135 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1136 1137 pnv->chips[i] = PNV_CHIP(chip); 1138 1139 /* Distribute RAM among the chips */ 1140 object_property_set_int(chip, "ram-start", chip_ram_start, 1141 &error_fatal); 1142 object_property_set_int(chip, "ram-size", chip_ram_size, 1143 &error_fatal); 1144 chip_ram_start += chip_ram_size; 1145 1146 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1147 object_property_add_child(OBJECT(pnv), chip_name, chip); 1148 object_property_set_int(chip, "chip-id", i, &error_fatal); 1149 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1150 &error_fatal); 1151 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1152 &error_fatal); 1153 object_property_set_bool(chip, "big-core", pnv->big_core, 1154 &error_fatal); 1155 object_property_set_bool(chip, "lpar-per-core", pnv->lpar_per_core, 1156 &error_fatal); 1157 /* 1158 * The POWER8 machine use the XICS interrupt interface. 1159 * Propagate the XICS fabric to the chip and its controllers. 1160 */ 1161 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1162 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1163 } 1164 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1165 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1166 &error_abort); 1167 } 1168 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1169 } 1170 g_free(chip_typename); 1171 1172 /* Instantiate ISA bus on chip 0 */ 1173 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1174 1175 /* Create serial port */ 1176 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1177 1178 /* Create an RTC ISA device too */ 1179 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1180 1181 /* 1182 * Create the machine BMC simulator and the IPMI BT device for 1183 * communication with the BMC 1184 */ 1185 if (defaults_enabled()) { 1186 pnv->bmc = pnv_bmc_create(pnv->pnor); 1187 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1188 } 1189 1190 /* 1191 * The PNOR is mapped on the LPC FW address space by the BMC. 1192 * Since we can not reach the remote BMC machine with LPC memops, 1193 * map it always for now. 1194 */ 1195 memory_region_add_subregion(pnv->chips[0]->fw_mr, pnv->pnor->lpc_address, 1196 &pnv->pnor->mmio); 1197 1198 /* 1199 * OpenPOWER systems use a IPMI SEL Event message to notify the 1200 * host to powerdown 1201 */ 1202 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1203 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1204 1205 /* 1206 * Create/Connect any machine-specific I2C devices 1207 */ 1208 if (pmc->i2c_init) { 1209 pmc->i2c_init(pnv); 1210 } 1211 } 1212 1213 /* 1214 * 0:21 Reserved - Read as zeros 1215 * 22:24 Chip ID 1216 * 25:28 Core number 1217 * 29:31 Thread ID 1218 */ 1219 static void pnv_get_pir_tir_p8(PnvChip *chip, 1220 uint32_t core_id, uint32_t thread_id, 1221 uint32_t *pir, uint32_t *tir) 1222 { 1223 if (pir) { 1224 *pir = (chip->chip_id << 7) | (core_id << 3) | thread_id; 1225 } 1226 if (tir) { 1227 *tir = thread_id; 1228 } 1229 } 1230 1231 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1232 Error **errp) 1233 { 1234 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1235 Error *local_err = NULL; 1236 Object *obj; 1237 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1238 1239 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1240 if (local_err) { 1241 error_propagate(errp, local_err); 1242 return; 1243 } 1244 1245 pnv_cpu->intc = obj; 1246 } 1247 1248 1249 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1250 { 1251 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1252 1253 icp_reset(ICP(pnv_cpu->intc)); 1254 } 1255 1256 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1257 { 1258 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1259 1260 icp_destroy(ICP(pnv_cpu->intc)); 1261 pnv_cpu->intc = NULL; 1262 } 1263 1264 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1265 GString *buf) 1266 { 1267 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1268 } 1269 1270 /* 1271 * 0:48 Reserved - Read as zeroes 1272 * 49:52 Node ID 1273 * 53:55 Chip ID 1274 * 56 Reserved - Read as zero 1275 * 57:61 Core number 1276 * 62:63 Thread ID 1277 * 1278 * We only care about the lower bits. uint32_t is fine for the moment. 1279 */ 1280 static void pnv_get_pir_tir_p9(PnvChip *chip, 1281 uint32_t core_id, uint32_t thread_id, 1282 uint32_t *pir, uint32_t *tir) 1283 { 1284 if (chip->big_core) { 1285 /* Big-core interleaves thread ID between small-cores */ 1286 thread_id <<= 1; 1287 thread_id |= core_id & 1; 1288 core_id >>= 1; 1289 1290 if (pir) { 1291 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1292 } 1293 } else { 1294 if (pir) { 1295 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1296 } 1297 } 1298 if (tir) { 1299 *tir = thread_id; 1300 } 1301 } 1302 1303 /* 1304 * 0:48 Reserved - Read as zeroes 1305 * 49:52 Node ID 1306 * 53:55 Chip ID 1307 * 56 Reserved - Read as zero 1308 * 57:59 Quad ID 1309 * 60 Core Chiplet Pair ID 1310 * 61:63 Thread/Core Chiplet ID t0-t2 1311 * 1312 * We only care about the lower bits. uint32_t is fine for the moment. 1313 */ 1314 static void pnv_get_pir_tir_p10(PnvChip *chip, 1315 uint32_t core_id, uint32_t thread_id, 1316 uint32_t *pir, uint32_t *tir) 1317 { 1318 if (chip->big_core) { 1319 /* Big-core interleaves thread ID between small-cores */ 1320 thread_id <<= 1; 1321 thread_id |= core_id & 1; 1322 core_id >>= 1; 1323 1324 if (pir) { 1325 *pir = (chip->chip_id << 8) | (core_id << 3) | thread_id; 1326 } 1327 } else { 1328 if (pir) { 1329 *pir = (chip->chip_id << 8) | (core_id << 2) | thread_id; 1330 } 1331 } 1332 if (tir) { 1333 *tir = thread_id; 1334 } 1335 } 1336 1337 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1338 Error **errp) 1339 { 1340 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1341 Error *local_err = NULL; 1342 Object *obj; 1343 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1344 1345 /* 1346 * The core creates its interrupt presenter but the XIVE interrupt 1347 * controller object is initialized afterwards. Hopefully, it's 1348 * only used at runtime. 1349 */ 1350 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1351 &local_err); 1352 if (local_err) { 1353 error_propagate(errp, local_err); 1354 return; 1355 } 1356 1357 pnv_cpu->intc = obj; 1358 } 1359 1360 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1361 { 1362 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1363 1364 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1365 } 1366 1367 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1368 { 1369 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1370 1371 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1372 pnv_cpu->intc = NULL; 1373 } 1374 1375 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1376 GString *buf) 1377 { 1378 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1379 } 1380 1381 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1382 Error **errp) 1383 { 1384 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1385 Error *local_err = NULL; 1386 Object *obj; 1387 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1388 1389 /* 1390 * The core creates its interrupt presenter but the XIVE2 interrupt 1391 * controller object is initialized afterwards. Hopefully, it's 1392 * only used at runtime. 1393 */ 1394 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1395 &local_err); 1396 if (local_err) { 1397 error_propagate(errp, local_err); 1398 return; 1399 } 1400 1401 pnv_cpu->intc = obj; 1402 } 1403 1404 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1405 { 1406 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1407 1408 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1409 } 1410 1411 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1412 { 1413 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1414 1415 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1416 pnv_cpu->intc = NULL; 1417 } 1418 1419 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1420 GString *buf) 1421 { 1422 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1423 } 1424 1425 /* 1426 * Allowed core identifiers on a POWER8 Processor Chip : 1427 * 1428 * <EX0 reserved> 1429 * EX1 - Venice only 1430 * EX2 - Venice only 1431 * EX3 - Venice only 1432 * EX4 1433 * EX5 1434 * EX6 1435 * <EX7,8 reserved> <reserved> 1436 * EX9 - Venice only 1437 * EX10 - Venice only 1438 * EX11 - Venice only 1439 * EX12 1440 * EX13 1441 * EX14 1442 * <EX15 reserved> 1443 */ 1444 #define POWER8E_CORE_MASK (0x7070ull) 1445 #define POWER8_CORE_MASK (0x7e7eull) 1446 1447 /* 1448 * POWER9 has 24 cores, ids starting at 0x0 1449 */ 1450 #define POWER9_CORE_MASK (0xffffffffffffffull) 1451 1452 1453 #define POWER10_CORE_MASK (0xffffffffffffffull) 1454 1455 static void pnv_chip_power8_instance_init(Object *obj) 1456 { 1457 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1458 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1459 int i; 1460 1461 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1462 (Object **)&chip8->xics, 1463 object_property_allow_set_link, 1464 OBJ_PROP_LINK_STRONG); 1465 1466 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1467 1468 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1469 1470 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1471 1472 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1473 1474 if (defaults_enabled()) { 1475 chip8->num_phbs = pcc->num_phbs; 1476 1477 for (i = 0; i < chip8->num_phbs; i++) { 1478 Object *phb = object_new(TYPE_PNV_PHB); 1479 1480 /* 1481 * We need the chip to parent the PHB to allow the DT 1482 * to build correctly (via pnv_xscom_dt()). 1483 * 1484 * TODO: the PHB should be parented by a PEC device that, at 1485 * this moment, is not modelled powernv8/phb3. 1486 */ 1487 object_property_add_child(obj, "phb[*]", phb); 1488 chip8->phbs[i] = PNV_PHB(phb); 1489 } 1490 } 1491 1492 } 1493 1494 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1495 { 1496 PnvChip *chip = PNV_CHIP(chip8); 1497 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1498 int i, j; 1499 char *name; 1500 1501 name = g_strdup_printf("icp-%x", chip->chip_id); 1502 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1503 g_free(name); 1504 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1505 &chip8->icp_mmio); 1506 1507 /* Map the ICP registers for each thread */ 1508 for (i = 0; i < chip->nr_cores; i++) { 1509 PnvCore *pnv_core = chip->cores[i]; 1510 int core_hwid = CPU_CORE(pnv_core)->core_id; 1511 1512 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1513 uint32_t pir; 1514 PnvICPState *icp; 1515 1516 pcc->get_pir_tir(chip, core_hwid, j, &pir, NULL); 1517 icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1518 1519 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1520 &icp->mmio); 1521 } 1522 } 1523 } 1524 1525 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1526 { 1527 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1528 PnvChip *chip = PNV_CHIP(dev); 1529 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1530 Pnv8Psi *psi8 = &chip8->psi; 1531 Error *local_err = NULL; 1532 int i; 1533 1534 assert(chip8->xics); 1535 1536 /* XSCOM bridge is first */ 1537 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1538 1539 pcc->parent_realize(dev, &local_err); 1540 if (local_err) { 1541 error_propagate(errp, local_err); 1542 return; 1543 } 1544 1545 /* Processor Service Interface (PSI) Host Bridge */ 1546 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1547 &error_fatal); 1548 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1549 OBJECT(chip8->xics), &error_abort); 1550 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1551 return; 1552 } 1553 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1554 &PNV_PSI(psi8)->xscom_regs); 1555 1556 /* Create LPC controller */ 1557 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1558 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1559 1560 chip->fw_mr = &chip8->lpc.isa_fw; 1561 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1562 (uint64_t) PNV_XSCOM_BASE(chip), 1563 PNV_XSCOM_LPC_BASE); 1564 1565 /* 1566 * Interrupt Management Area. This is the memory region holding 1567 * all the Interrupt Control Presenter (ICP) registers 1568 */ 1569 pnv_chip_icp_realize(chip8, &local_err); 1570 if (local_err) { 1571 error_propagate(errp, local_err); 1572 return; 1573 } 1574 1575 /* HOMER (must be created before OCC) */ 1576 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1577 &error_abort); 1578 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1579 return; 1580 } 1581 /* Homer Xscom region */ 1582 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1583 /* Homer RAM region */ 1584 memory_region_add_subregion(get_system_memory(), chip8->homer.base, 1585 &chip8->homer.mem); 1586 1587 /* Create the simplified OCC model */ 1588 object_property_set_link(OBJECT(&chip8->occ), "homer", 1589 OBJECT(&chip8->homer), &error_abort); 1590 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1591 return; 1592 } 1593 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1594 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1595 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1596 1597 /* OCC SRAM model */ 1598 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1599 &chip8->occ.sram_regs); 1600 1601 /* PHB controllers */ 1602 for (i = 0; i < chip8->num_phbs; i++) { 1603 PnvPHB *phb = chip8->phbs[i]; 1604 1605 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1606 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1607 &error_fatal); 1608 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1609 &error_fatal); 1610 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1611 return; 1612 } 1613 } 1614 } 1615 1616 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1617 { 1618 addr &= (PNV_XSCOM_SIZE - 1); 1619 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1620 } 1621 1622 static void pnv_chip_power8e_class_init(ObjectClass *klass, const void *data) 1623 { 1624 DeviceClass *dc = DEVICE_CLASS(klass); 1625 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1626 1627 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1628 k->cores_mask = POWER8E_CORE_MASK; 1629 k->num_phbs = 3; 1630 k->get_pir_tir = pnv_get_pir_tir_p8; 1631 k->intc_create = pnv_chip_power8_intc_create; 1632 k->intc_reset = pnv_chip_power8_intc_reset; 1633 k->intc_destroy = pnv_chip_power8_intc_destroy; 1634 k->intc_print_info = pnv_chip_power8_intc_print_info; 1635 k->isa_create = pnv_chip_power8_isa_create; 1636 k->dt_populate = pnv_chip_power8_dt_populate; 1637 k->pic_print_info = pnv_chip_power8_pic_print_info; 1638 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1639 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1640 dc->desc = "PowerNV Chip POWER8E"; 1641 1642 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1643 &k->parent_realize); 1644 } 1645 1646 static void pnv_chip_power8_class_init(ObjectClass *klass, const void *data) 1647 { 1648 DeviceClass *dc = DEVICE_CLASS(klass); 1649 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1650 1651 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1652 k->cores_mask = POWER8_CORE_MASK; 1653 k->num_phbs = 3; 1654 k->get_pir_tir = pnv_get_pir_tir_p8; 1655 k->intc_create = pnv_chip_power8_intc_create; 1656 k->intc_reset = pnv_chip_power8_intc_reset; 1657 k->intc_destroy = pnv_chip_power8_intc_destroy; 1658 k->intc_print_info = pnv_chip_power8_intc_print_info; 1659 k->isa_create = pnv_chip_power8_isa_create; 1660 k->dt_populate = pnv_chip_power8_dt_populate; 1661 k->pic_print_info = pnv_chip_power8_pic_print_info; 1662 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1663 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1664 dc->desc = "PowerNV Chip POWER8"; 1665 1666 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1667 &k->parent_realize); 1668 } 1669 1670 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, const void *data) 1671 { 1672 DeviceClass *dc = DEVICE_CLASS(klass); 1673 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1674 1675 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1676 k->cores_mask = POWER8_CORE_MASK; 1677 k->num_phbs = 4; 1678 k->get_pir_tir = pnv_get_pir_tir_p8; 1679 k->intc_create = pnv_chip_power8_intc_create; 1680 k->intc_reset = pnv_chip_power8_intc_reset; 1681 k->intc_destroy = pnv_chip_power8_intc_destroy; 1682 k->intc_print_info = pnv_chip_power8_intc_print_info; 1683 k->isa_create = pnv_chip_power8nvl_isa_create; 1684 k->dt_populate = pnv_chip_power8_dt_populate; 1685 k->pic_print_info = pnv_chip_power8_pic_print_info; 1686 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1687 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1688 dc->desc = "PowerNV Chip POWER8NVL"; 1689 1690 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1691 &k->parent_realize); 1692 } 1693 1694 static void pnv_chip_power9_instance_init(Object *obj) 1695 { 1696 PnvChip *chip = PNV_CHIP(obj); 1697 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1698 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1699 int i; 1700 1701 object_initialize_child(obj, "adu", &chip9->adu, TYPE_PNV_ADU); 1702 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1703 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1704 "xive-fabric"); 1705 1706 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1707 1708 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1709 1710 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1711 1712 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1713 1714 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1715 1716 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1717 1718 /* Number of PECs is the chip default */ 1719 chip->num_pecs = pcc->num_pecs; 1720 1721 for (i = 0; i < chip->num_pecs; i++) { 1722 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1723 TYPE_PNV_PHB4_PEC); 1724 } 1725 1726 for (i = 0; i < pcc->i2c_num_engines; i++) { 1727 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1728 } 1729 } 1730 1731 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1732 PnvCore *pnv_core, 1733 const char *type) 1734 { 1735 char eq_name[32]; 1736 int core_id = CPU_CORE(pnv_core)->core_id; 1737 1738 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1739 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1740 sizeof(*eq), type, 1741 &error_fatal, NULL); 1742 1743 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1744 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1745 } 1746 1747 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1748 { 1749 PnvChip *chip = PNV_CHIP(chip9); 1750 int i; 1751 1752 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1753 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1754 1755 for (i = 0; i < chip9->nr_quads; i++) { 1756 PnvQuad *eq = &chip9->quads[i]; 1757 1758 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1759 PNV_QUAD_TYPE_NAME("power9")); 1760 1761 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1762 &eq->xscom_regs); 1763 } 1764 } 1765 1766 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1767 { 1768 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1769 int i; 1770 1771 for (i = 0; i < chip->num_pecs; i++) { 1772 PnvPhb4PecState *pec = &chip9->pecs[i]; 1773 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1774 uint32_t pec_cplt_base; 1775 uint32_t pec_nest_base; 1776 uint32_t pec_pci_base; 1777 1778 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1779 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1780 &error_fatal); 1781 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1782 &error_fatal); 1783 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1784 return; 1785 } 1786 1787 pec_cplt_base = pecc->xscom_cplt_base(pec); 1788 pec_nest_base = pecc->xscom_nest_base(pec); 1789 pec_pci_base = pecc->xscom_pci_base(pec); 1790 1791 pnv_xscom_add_subregion(chip, pec_cplt_base, 1792 &pec->nest_pervasive.xscom_ctrl_regs_mr); 1793 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1794 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1795 } 1796 } 1797 1798 static uint64_t pnv_handle_sprd_load(CPUPPCState *env) 1799 { 1800 PowerPCCPU *cpu = env_archcpu(env); 1801 PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; 1802 uint64_t sprc = env->spr[SPR_POWER_SPRC]; 1803 1804 if (pc->big_core) { 1805 pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); 1806 } 1807 1808 switch (sprc & 0x3e0) { 1809 case 0: /* SCRATCH0-3 */ 1810 case 1: /* SCRATCH4-7 */ 1811 return pc->scratch[(sprc >> 3) & 0x7]; 1812 1813 case 0x1e0: /* core thread state */ 1814 if (env->excp_model == POWERPC_EXCP_POWER9) { 1815 /* 1816 * Only implement for POWER9 because skiboot uses it to check 1817 * big-core mode. Other bits are unimplemented so we would 1818 * prefer to get unimplemented message on POWER10 if it were 1819 * used anywhere. 1820 */ 1821 if (pc->big_core) { 1822 return PPC_BIT(63); 1823 } else { 1824 return 0; 1825 } 1826 } 1827 /* fallthru */ 1828 1829 default: 1830 qemu_log_mask(LOG_UNIMP, "mfSPRD: Unimplemented SPRC:0x" 1831 TARGET_FMT_lx"\n", sprc); 1832 break; 1833 } 1834 return 0; 1835 } 1836 1837 static void pnv_handle_sprd_store(CPUPPCState *env, uint64_t val) 1838 { 1839 PowerPCCPU *cpu = env_archcpu(env); 1840 uint64_t sprc = env->spr[SPR_POWER_SPRC]; 1841 PnvCore *pc = pnv_cpu_state(cpu)->pnv_core; 1842 int nr; 1843 1844 if (pc->big_core) { 1845 pc = pnv_chip_find_core(pc->chip, CPU_CORE(pc)->core_id & ~0x1); 1846 } 1847 1848 switch (sprc & 0x3e0) { 1849 case 0: /* SCRATCH0-3 */ 1850 case 1: /* SCRATCH4-7 */ 1851 /* 1852 * Log stores to SCRATCH, because some firmware uses these for 1853 * debugging and logging, but they would normally be read by the BMC, 1854 * which is not implemented in QEMU yet. This gives a way to get at the 1855 * information. Could also dump these upon checkstop. 1856 */ 1857 nr = (sprc >> 3) & 0x7; 1858 pc->scratch[nr] = val; 1859 break; 1860 default: 1861 qemu_log_mask(LOG_UNIMP, "mtSPRD: Unimplemented SPRC:0x" 1862 TARGET_FMT_lx"\n", sprc); 1863 break; 1864 } 1865 } 1866 1867 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1868 { 1869 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1870 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1871 PnvChip *chip = PNV_CHIP(dev); 1872 Pnv9Psi *psi9 = &chip9->psi; 1873 PowerPCCPU *cpu; 1874 PowerPCCPUClass *cpu_class; 1875 Error *local_err = NULL; 1876 int i; 1877 1878 /* XSCOM bridge is first */ 1879 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1880 1881 pcc->parent_realize(dev, &local_err); 1882 if (local_err) { 1883 error_propagate(errp, local_err); 1884 return; 1885 } 1886 1887 /* ADU */ 1888 object_property_set_link(OBJECT(&chip9->adu), "lpc", OBJECT(&chip9->lpc), 1889 &error_abort); 1890 if (!qdev_realize(DEVICE(&chip9->adu), NULL, errp)) { 1891 return; 1892 } 1893 pnv_xscom_add_subregion(chip, PNV9_XSCOM_ADU_BASE, 1894 &chip9->adu.xscom_regs); 1895 1896 pnv_chip_quad_realize(chip9, &local_err); 1897 if (local_err) { 1898 error_propagate(errp, local_err); 1899 return; 1900 } 1901 1902 /* Set handlers for Special registers, such as SPRD */ 1903 cpu = chip->cores[0]->threads[0]; 1904 cpu_class = POWERPC_CPU_GET_CLASS(cpu); 1905 cpu_class->load_sprd = pnv_handle_sprd_load; 1906 cpu_class->store_sprd = pnv_handle_sprd_store; 1907 1908 /* XIVE interrupt controller (POWER9) */ 1909 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1910 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1911 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1912 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1913 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1914 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1915 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1916 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1917 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1918 &error_abort); 1919 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1920 return; 1921 } 1922 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1923 &chip9->xive.xscom_regs); 1924 1925 /* Processor Service Interface (PSI) Host Bridge */ 1926 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1927 &error_fatal); 1928 /* This is the only device with 4k ESB pages */ 1929 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1930 &error_fatal); 1931 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1932 return; 1933 } 1934 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1935 &PNV_PSI(psi9)->xscom_regs); 1936 1937 /* LPC */ 1938 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1939 return; 1940 } 1941 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1942 &chip9->lpc.xscom_regs); 1943 1944 chip->fw_mr = &chip9->lpc.isa_fw; 1945 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1946 (uint64_t) PNV9_LPCM_BASE(chip)); 1947 1948 /* ChipTOD */ 1949 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1950 chip->chip_id == 0, &error_abort); 1951 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1952 chip->chip_id == 1, &error_abort); 1953 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1954 &error_abort); 1955 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1956 return; 1957 } 1958 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1959 &chip9->chiptod.xscom_regs); 1960 1961 /* SBE */ 1962 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1963 return; 1964 } 1965 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1966 &chip9->sbe.xscom_ctrl_regs); 1967 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1968 &chip9->sbe.xscom_mbox_regs); 1969 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1970 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1971 1972 /* HOMER (must be created before OCC) */ 1973 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1974 &error_abort); 1975 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1976 return; 1977 } 1978 /* Homer Xscom region */ 1979 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1980 /* Homer RAM region */ 1981 memory_region_add_subregion(get_system_memory(), chip9->homer.base, 1982 &chip9->homer.mem); 1983 1984 /* Create the simplified OCC model */ 1985 object_property_set_link(OBJECT(&chip9->occ), "homer", 1986 OBJECT(&chip9->homer), &error_abort); 1987 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1988 return; 1989 } 1990 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1991 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1992 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1993 1994 /* OCC SRAM model */ 1995 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1996 &chip9->occ.sram_regs); 1997 1998 /* PEC PHBs */ 1999 pnv_chip_power9_pec_realize(chip, &local_err); 2000 if (local_err) { 2001 error_propagate(errp, local_err); 2002 return; 2003 } 2004 2005 /* 2006 * I2C 2007 */ 2008 for (i = 0; i < pcc->i2c_num_engines; i++) { 2009 Object *obj = OBJECT(&chip9->i2c[i]); 2010 2011 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2012 object_property_set_int(obj, "num-busses", 2013 pcc->i2c_ports_per_engine[i], 2014 &error_fatal); 2015 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2016 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2017 return; 2018 } 2019 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 2020 (chip9->i2c[i].engine - 1) * 2021 PNV9_XSCOM_I2CM_SIZE, 2022 &chip9->i2c[i].xscom_regs); 2023 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 2024 qdev_get_gpio_in(DEVICE(psi9), 2025 PSIHB9_IRQ_SBE_I2C)); 2026 } 2027 } 2028 2029 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 2030 { 2031 addr &= (PNV9_XSCOM_SIZE - 1); 2032 return addr >> 3; 2033 } 2034 2035 static void pnv_chip_power9_class_init(ObjectClass *klass, const void *data) 2036 { 2037 DeviceClass *dc = DEVICE_CLASS(klass); 2038 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2039 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 2040 2041 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 2042 k->cores_mask = POWER9_CORE_MASK; 2043 k->get_pir_tir = pnv_get_pir_tir_p9; 2044 k->intc_create = pnv_chip_power9_intc_create; 2045 k->intc_reset = pnv_chip_power9_intc_reset; 2046 k->intc_destroy = pnv_chip_power9_intc_destroy; 2047 k->intc_print_info = pnv_chip_power9_intc_print_info; 2048 k->isa_create = pnv_chip_power9_isa_create; 2049 k->dt_populate = pnv_chip_power9_dt_populate; 2050 k->pic_print_info = pnv_chip_power9_pic_print_info; 2051 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 2052 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 2053 dc->desc = "PowerNV Chip POWER9"; 2054 k->num_pecs = PNV9_CHIP_MAX_PEC; 2055 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 2056 k->i2c_ports_per_engine = i2c_ports_per_engine; 2057 2058 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 2059 &k->parent_realize); 2060 } 2061 2062 static void pnv_chip_power10_instance_init(Object *obj) 2063 { 2064 PnvChip *chip = PNV_CHIP(obj); 2065 Pnv10Chip *chip10 = PNV10_CHIP(obj); 2066 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 2067 int i; 2068 2069 object_initialize_child(obj, "adu", &chip10->adu, TYPE_PNV_ADU); 2070 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 2071 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 2072 "xive-fabric"); 2073 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 2074 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 2075 object_initialize_child(obj, "chiptod", &chip10->chiptod, 2076 TYPE_PNV10_CHIPTOD); 2077 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 2078 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 2079 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 2080 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 2081 TYPE_PNV_N1_CHIPLET); 2082 2083 chip->num_pecs = pcc->num_pecs; 2084 2085 for (i = 0; i < chip->num_pecs; i++) { 2086 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 2087 TYPE_PNV_PHB5_PEC); 2088 } 2089 2090 for (i = 0; i < pcc->i2c_num_engines; i++) { 2091 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 2092 } 2093 2094 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2095 object_initialize_child(obj, "pib_spic[*]", &chip10->pib_spic[i], 2096 TYPE_PNV_SPI); 2097 } 2098 } 2099 2100 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 2101 { 2102 PnvChip *chip = PNV_CHIP(chip10); 2103 int i; 2104 2105 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 2106 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 2107 2108 for (i = 0; i < chip10->nr_quads; i++) { 2109 PnvQuad *eq = &chip10->quads[i]; 2110 2111 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 2112 PNV_QUAD_TYPE_NAME("power10")); 2113 2114 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 2115 &eq->xscom_regs); 2116 2117 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 2118 &eq->xscom_qme_regs); 2119 } 2120 } 2121 2122 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 2123 { 2124 Pnv10Chip *chip10 = PNV10_CHIP(chip); 2125 int i; 2126 2127 for (i = 0; i < chip->num_pecs; i++) { 2128 PnvPhb4PecState *pec = &chip10->pecs[i]; 2129 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 2130 uint32_t pec_cplt_base; 2131 uint32_t pec_nest_base; 2132 uint32_t pec_pci_base; 2133 2134 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 2135 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 2136 &error_fatal); 2137 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 2138 &error_fatal); 2139 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 2140 return; 2141 } 2142 2143 pec_cplt_base = pecc->xscom_cplt_base(pec); 2144 pec_nest_base = pecc->xscom_nest_base(pec); 2145 pec_pci_base = pecc->xscom_pci_base(pec); 2146 2147 pnv_xscom_add_subregion(chip, pec_cplt_base, 2148 &pec->nest_pervasive.xscom_ctrl_regs_mr); 2149 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 2150 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 2151 } 2152 } 2153 2154 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 2155 { 2156 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 2157 PnvChip *chip = PNV_CHIP(dev); 2158 Pnv10Chip *chip10 = PNV10_CHIP(dev); 2159 PowerPCCPU *cpu; 2160 PowerPCCPUClass *cpu_class; 2161 Error *local_err = NULL; 2162 int i; 2163 2164 /* XSCOM bridge is first */ 2165 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 2166 2167 pcc->parent_realize(dev, &local_err); 2168 if (local_err) { 2169 error_propagate(errp, local_err); 2170 return; 2171 } 2172 2173 /* ADU */ 2174 object_property_set_link(OBJECT(&chip10->adu), "lpc", OBJECT(&chip10->lpc), 2175 &error_abort); 2176 if (!qdev_realize(DEVICE(&chip10->adu), NULL, errp)) { 2177 return; 2178 } 2179 pnv_xscom_add_subregion(chip, PNV10_XSCOM_ADU_BASE, 2180 &chip10->adu.xscom_regs); 2181 2182 pnv_chip_power10_quad_realize(chip10, &local_err); 2183 if (local_err) { 2184 error_propagate(errp, local_err); 2185 return; 2186 } 2187 2188 /* Set handlers for Special registers, such as SPRD */ 2189 cpu = chip->cores[0]->threads[0]; 2190 cpu_class = POWERPC_CPU_GET_CLASS(cpu); 2191 cpu_class->load_sprd = pnv_handle_sprd_load; 2192 cpu_class->store_sprd = pnv_handle_sprd_store; 2193 2194 /* XIVE2 interrupt controller (POWER10) */ 2195 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 2196 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 2197 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 2198 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 2199 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 2200 PNV10_XIVE2_END_BASE(chip), &error_fatal); 2201 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 2202 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 2203 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 2204 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 2205 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 2206 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 2207 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 2208 &error_abort); 2209 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 2210 return; 2211 } 2212 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 2213 &chip10->xive.xscom_regs); 2214 2215 /* Processor Service Interface (PSI) Host Bridge */ 2216 object_property_set_int(OBJECT(&chip10->psi), "bar", 2217 PNV10_PSIHB_BASE(chip), &error_fatal); 2218 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 2219 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 2220 &error_fatal); 2221 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 2222 return; 2223 } 2224 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 2225 &PNV_PSI(&chip10->psi)->xscom_regs); 2226 2227 /* LPC */ 2228 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 2229 return; 2230 } 2231 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 2232 &chip10->lpc.xscom_regs); 2233 2234 chip->fw_mr = &chip10->lpc.isa_fw; 2235 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 2236 (uint64_t) PNV10_LPCM_BASE(chip)); 2237 2238 /* ChipTOD */ 2239 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 2240 chip->chip_id == 0, &error_abort); 2241 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 2242 chip->chip_id == 1, &error_abort); 2243 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 2244 &error_abort); 2245 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 2246 return; 2247 } 2248 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 2249 &chip10->chiptod.xscom_regs); 2250 2251 /* HOMER (must be created before OCC) */ 2252 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2253 &error_abort); 2254 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2255 return; 2256 } 2257 /* Homer Xscom region */ 2258 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2259 &chip10->homer.pba_regs); 2260 /* Homer RAM region */ 2261 memory_region_add_subregion(get_system_memory(), chip10->homer.base, 2262 &chip10->homer.mem); 2263 2264 /* Create the simplified OCC model */ 2265 object_property_set_link(OBJECT(&chip10->occ), "homer", 2266 OBJECT(&chip10->homer), &error_abort); 2267 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 2268 return; 2269 } 2270 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 2271 &chip10->occ.xscom_regs); 2272 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 2273 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 2274 2275 /* OCC SRAM model */ 2276 memory_region_add_subregion(get_system_memory(), 2277 PNV10_OCC_SENSOR_BASE(chip), 2278 &chip10->occ.sram_regs); 2279 2280 /* SBE */ 2281 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 2282 return; 2283 } 2284 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 2285 &chip10->sbe.xscom_ctrl_regs); 2286 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 2287 &chip10->sbe.xscom_mbox_regs); 2288 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 2289 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 2290 2291 /* N1 chiplet */ 2292 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2293 return; 2294 } 2295 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2296 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2297 2298 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2299 &chip10->n1_chiplet.xscom_pb_eq_mr); 2300 2301 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2302 &chip10->n1_chiplet.xscom_pb_es_mr); 2303 2304 /* PHBs */ 2305 pnv_chip_power10_phb_realize(chip, &local_err); 2306 if (local_err) { 2307 error_propagate(errp, local_err); 2308 return; 2309 } 2310 2311 2312 /* 2313 * I2C 2314 */ 2315 for (i = 0; i < pcc->i2c_num_engines; i++) { 2316 Object *obj = OBJECT(&chip10->i2c[i]); 2317 2318 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2319 object_property_set_int(obj, "num-busses", 2320 pcc->i2c_ports_per_engine[i], 2321 &error_fatal); 2322 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2323 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2324 return; 2325 } 2326 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2327 (chip10->i2c[i].engine - 1) * 2328 PNV10_XSCOM_I2CM_SIZE, 2329 &chip10->i2c[i].xscom_regs); 2330 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2331 qdev_get_gpio_in(DEVICE(&chip10->psi), 2332 PSIHB9_IRQ_SBE_I2C)); 2333 } 2334 /* PIB SPI Controller */ 2335 for (i = 0; i < PNV10_CHIP_MAX_PIB_SPIC; i++) { 2336 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "spic_num", 2337 i, &error_fatal); 2338 /* pib_spic[2] connected to 25csm04 which implements 1 byte transfer */ 2339 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "transfer_len", 2340 (i == 2) ? 1 : 4, &error_fatal); 2341 object_property_set_int(OBJECT(&chip10->pib_spic[i]), "chip-id", 2342 chip->chip_id, &error_fatal); 2343 if (!sysbus_realize(SYS_BUS_DEVICE(OBJECT 2344 (&chip10->pib_spic[i])), errp)) { 2345 return; 2346 } 2347 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PIB_SPIC_BASE + 2348 i * PNV10_XSCOM_PIB_SPIC_SIZE, 2349 &chip10->pib_spic[i].xscom_spic_regs); 2350 } 2351 } 2352 2353 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2354 { 2355 int i; 2356 for (i = 0; i < pnv->num_chips; i++) { 2357 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2358 2359 /* 2360 * Add a PCA9552 I2C device for PCIe hotplug control 2361 * to engine 2, bus 1, address 0x63 2362 */ 2363 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2364 "pca9552", 0x63); 2365 2366 /* 2367 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2368 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2369 * after hypervisor code sets a SLOTx_EN pin high. 2370 */ 2371 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2372 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2373 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2374 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2375 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2376 2377 /* 2378 * Add a PCA9554 I2C device for cable card presence detection 2379 * to engine 2, bus 1, address 0x25 2380 */ 2381 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2382 } 2383 } 2384 2385 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2386 { 2387 addr &= (PNV10_XSCOM_SIZE - 1); 2388 return addr >> 3; 2389 } 2390 2391 static void pnv_chip_power10_class_init(ObjectClass *klass, const void *data) 2392 { 2393 DeviceClass *dc = DEVICE_CLASS(klass); 2394 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2395 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2396 2397 k->chip_cfam_id = 0x220da04980000000ull; /* P10 DD2.0 (with NX) */ 2398 k->cores_mask = POWER10_CORE_MASK; 2399 k->get_pir_tir = pnv_get_pir_tir_p10; 2400 k->intc_create = pnv_chip_power10_intc_create; 2401 k->intc_reset = pnv_chip_power10_intc_reset; 2402 k->intc_destroy = pnv_chip_power10_intc_destroy; 2403 k->intc_print_info = pnv_chip_power10_intc_print_info; 2404 k->isa_create = pnv_chip_power10_isa_create; 2405 k->dt_populate = pnv_chip_power10_dt_populate; 2406 k->pic_print_info = pnv_chip_power10_pic_print_info; 2407 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2408 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2409 dc->desc = "PowerNV Chip POWER10"; 2410 k->num_pecs = PNV10_CHIP_MAX_PEC; 2411 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2412 k->i2c_ports_per_engine = i2c_ports_per_engine; 2413 2414 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2415 &k->parent_realize); 2416 } 2417 2418 static void pnv_chip_core_sanitize(PnvMachineState *pnv, PnvChip *chip, 2419 Error **errp) 2420 { 2421 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2422 int cores_max; 2423 2424 /* 2425 * No custom mask for this chip, let's use the default one from * 2426 * the chip class 2427 */ 2428 if (!chip->cores_mask) { 2429 chip->cores_mask = pcc->cores_mask; 2430 } 2431 2432 /* filter alien core ids ! some are reserved */ 2433 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2434 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2435 chip->cores_mask); 2436 return; 2437 } 2438 chip->cores_mask &= pcc->cores_mask; 2439 2440 /* Ensure small-cores a paired up in big-core mode */ 2441 if (pnv->big_core) { 2442 uint64_t even_cores = chip->cores_mask & 0x5555555555555555ULL; 2443 uint64_t odd_cores = chip->cores_mask & 0xaaaaaaaaaaaaaaaaULL; 2444 2445 if (even_cores ^ (odd_cores >> 1)) { 2446 error_setg(errp, "warning: unpaired cores in big-core mode !"); 2447 return; 2448 } 2449 } 2450 2451 /* now that we have a sane layout, let check the number of cores */ 2452 cores_max = ctpop64(chip->cores_mask); 2453 if (chip->nr_cores > cores_max) { 2454 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2455 cores_max); 2456 return; 2457 } 2458 } 2459 2460 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2461 { 2462 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2463 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(pnv); 2464 Error *error = NULL; 2465 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2466 const char *typename = pnv_chip_core_typename(chip); 2467 int i, core_hwid; 2468 2469 if (!object_class_by_name(typename)) { 2470 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2471 return; 2472 } 2473 2474 /* Cores */ 2475 pnv_chip_core_sanitize(pnv, chip, &error); 2476 if (error) { 2477 error_propagate(errp, error); 2478 return; 2479 } 2480 2481 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2482 2483 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2484 && (i < chip->nr_cores); core_hwid++) { 2485 char core_name[32]; 2486 PnvCore *pnv_core; 2487 uint64_t xscom_core_base; 2488 2489 if (!(chip->cores_mask & (1ull << core_hwid))) { 2490 continue; 2491 } 2492 2493 pnv_core = PNV_CORE(object_new(typename)); 2494 2495 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2496 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2497 chip->cores[i] = pnv_core; 2498 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2499 chip->nr_threads, &error_fatal); 2500 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2501 core_hwid, &error_fatal); 2502 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2503 &error_fatal); 2504 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2505 &error_fatal); 2506 object_property_set_bool(OBJECT(pnv_core), "big-core", chip->big_core, 2507 &error_fatal); 2508 object_property_set_bool(OBJECT(pnv_core), "quirk-tb-big-core", 2509 pmc->quirk_tb_big_core, &error_fatal); 2510 object_property_set_bool(OBJECT(pnv_core), "lpar-per-core", 2511 chip->lpar_per_core, &error_fatal); 2512 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2513 &error_abort); 2514 2515 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2516 2517 /* Each core has an XSCOM MMIO region */ 2518 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2519 2520 pnv_xscom_add_subregion(chip, xscom_core_base, 2521 &pnv_core->xscom_regs); 2522 i++; 2523 } 2524 } 2525 2526 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2527 { 2528 PnvChip *chip = PNV_CHIP(dev); 2529 Error *error = NULL; 2530 2531 /* Cores */ 2532 pnv_chip_core_realize(chip, &error); 2533 if (error) { 2534 error_propagate(errp, error); 2535 return; 2536 } 2537 } 2538 2539 static const Property pnv_chip_properties[] = { 2540 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2541 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2542 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2543 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2544 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2545 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2546 DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false), 2547 DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false), 2548 }; 2549 2550 static void pnv_chip_class_init(ObjectClass *klass, const void *data) 2551 { 2552 DeviceClass *dc = DEVICE_CLASS(klass); 2553 2554 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2555 dc->realize = pnv_chip_realize; 2556 device_class_set_props(dc, pnv_chip_properties); 2557 dc->desc = "PowerNV Chip"; 2558 } 2559 2560 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2561 { 2562 int i; 2563 2564 for (i = 0; i < chip->nr_cores; i++) { 2565 PnvCore *pc = chip->cores[i]; 2566 CPUCore *cc = CPU_CORE(pc); 2567 2568 if (cc->core_id == core_id) { 2569 return pc; 2570 } 2571 } 2572 return NULL; 2573 } 2574 2575 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2576 { 2577 int i, j; 2578 2579 for (i = 0; i < chip->nr_cores; i++) { 2580 PnvCore *pc = chip->cores[i]; 2581 CPUCore *cc = CPU_CORE(pc); 2582 2583 for (j = 0; j < cc->nr_threads; j++) { 2584 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2585 return pc->threads[j]; 2586 } 2587 } 2588 } 2589 return NULL; 2590 } 2591 2592 static void pnv_chip_foreach_cpu(PnvChip *chip, 2593 void (*fn)(PnvChip *chip, PowerPCCPU *cpu, void *opaque), 2594 void *opaque) 2595 { 2596 int i, j; 2597 2598 for (i = 0; i < chip->nr_cores; i++) { 2599 PnvCore *pc = chip->cores[i]; 2600 2601 for (j = 0; j < CPU_CORE(pc)->nr_threads; j++) { 2602 fn(chip, pc->threads[j], opaque); 2603 } 2604 } 2605 } 2606 2607 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2608 { 2609 PnvMachineState *pnv = PNV_MACHINE(xi); 2610 int i, j; 2611 2612 for (i = 0; i < pnv->num_chips; i++) { 2613 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2614 2615 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2616 return &chip8->psi.ics; 2617 } 2618 2619 for (j = 0; j < chip8->num_phbs; j++) { 2620 PnvPHB *phb = chip8->phbs[j]; 2621 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2622 2623 if (ics_valid_irq(&phb3->lsis, irq)) { 2624 return &phb3->lsis; 2625 } 2626 2627 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2628 return ICS(&phb3->msis); 2629 } 2630 } 2631 } 2632 return NULL; 2633 } 2634 2635 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2636 { 2637 int i; 2638 2639 for (i = 0; i < pnv->num_chips; i++) { 2640 PnvChip *chip = pnv->chips[i]; 2641 if (chip->chip_id == chip_id) { 2642 return chip; 2643 } 2644 } 2645 return NULL; 2646 } 2647 2648 static void pnv_ics_resend(XICSFabric *xi) 2649 { 2650 PnvMachineState *pnv = PNV_MACHINE(xi); 2651 int i, j; 2652 2653 for (i = 0; i < pnv->num_chips; i++) { 2654 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2655 2656 ics_resend(&chip8->psi.ics); 2657 2658 for (j = 0; j < chip8->num_phbs; j++) { 2659 PnvPHB *phb = chip8->phbs[j]; 2660 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2661 2662 ics_resend(&phb3->lsis); 2663 ics_resend(ICS(&phb3->msis)); 2664 } 2665 } 2666 } 2667 2668 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2669 { 2670 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2671 2672 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2673 } 2674 2675 static void pnv_pic_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 2676 void *opaque) 2677 { 2678 PNV_CHIP_GET_CLASS(chip)->intc_print_info(chip, cpu, opaque); 2679 } 2680 2681 static void pnv_pic_print_info(InterruptStatsProvider *obj, GString *buf) 2682 { 2683 PnvMachineState *pnv = PNV_MACHINE(obj); 2684 int i; 2685 2686 for (i = 0; i < pnv->num_chips; i++) { 2687 PnvChip *chip = pnv->chips[i]; 2688 2689 /* First CPU presenters */ 2690 pnv_chip_foreach_cpu(chip, pnv_pic_intc_print_info, buf); 2691 2692 /* Then other devices, PHB, PSI, XIVE */ 2693 PNV_CHIP_GET_CLASS(chip)->pic_print_info(chip, buf); 2694 } 2695 } 2696 2697 static bool pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2698 uint8_t nvt_blk, uint32_t nvt_idx, 2699 bool crowd, bool cam_ignore, uint8_t priority, 2700 uint32_t logic_serv, 2701 XiveTCTXMatch *match) 2702 { 2703 PnvMachineState *pnv = PNV_MACHINE(xfb); 2704 int i; 2705 2706 for (i = 0; i < pnv->num_chips; i++) { 2707 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2708 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2709 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2710 2711 xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, 2712 cam_ignore, priority, logic_serv, match); 2713 } 2714 2715 return !!match->count; 2716 } 2717 2718 static bool pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2719 uint8_t nvt_blk, uint32_t nvt_idx, 2720 bool crowd, bool cam_ignore, uint8_t priority, 2721 uint32_t logic_serv, 2722 XiveTCTXMatch *match) 2723 { 2724 PnvMachineState *pnv = PNV_MACHINE(xfb); 2725 int i; 2726 2727 for (i = 0; i < pnv->num_chips; i++) { 2728 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2729 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2730 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2731 2732 xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, crowd, 2733 cam_ignore, priority, logic_serv, match); 2734 } 2735 2736 return !!match->count; 2737 } 2738 2739 static int pnv10_xive_broadcast(XiveFabric *xfb, 2740 uint8_t nvt_blk, uint32_t nvt_idx, 2741 bool crowd, bool cam_ignore, 2742 uint8_t priority) 2743 { 2744 PnvMachineState *pnv = PNV_MACHINE(xfb); 2745 int i; 2746 2747 for (i = 0; i < pnv->num_chips; i++) { 2748 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2749 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2750 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2751 2752 xpc->broadcast(xptr, nvt_blk, nvt_idx, crowd, cam_ignore, priority); 2753 } 2754 return 0; 2755 } 2756 2757 static bool pnv_machine_get_big_core(Object *obj, Error **errp) 2758 { 2759 PnvMachineState *pnv = PNV_MACHINE(obj); 2760 return pnv->big_core; 2761 } 2762 2763 static void pnv_machine_set_big_core(Object *obj, bool value, Error **errp) 2764 { 2765 PnvMachineState *pnv = PNV_MACHINE(obj); 2766 pnv->big_core = value; 2767 } 2768 2769 static bool pnv_machine_get_lpar_per_core(Object *obj, Error **errp) 2770 { 2771 PnvMachineState *pnv = PNV_MACHINE(obj); 2772 return pnv->lpar_per_core; 2773 } 2774 2775 static void pnv_machine_set_lpar_per_core(Object *obj, bool value, Error **errp) 2776 { 2777 PnvMachineState *pnv = PNV_MACHINE(obj); 2778 pnv->lpar_per_core = value; 2779 } 2780 2781 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2782 { 2783 PnvMachineState *pnv = PNV_MACHINE(obj); 2784 2785 return !!pnv->fw_load_addr; 2786 } 2787 2788 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2789 { 2790 PnvMachineState *pnv = PNV_MACHINE(obj); 2791 2792 if (value) { 2793 pnv->fw_load_addr = 0x8000000; 2794 } 2795 } 2796 2797 static void pnv_machine_power8_class_init(ObjectClass *oc, const void *data) 2798 { 2799 MachineClass *mc = MACHINE_CLASS(oc); 2800 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2801 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2802 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2803 2804 static GlobalProperty phb_compat[] = { 2805 { TYPE_PNV_PHB, "version", "3" }, 2806 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2807 }; 2808 2809 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2810 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2811 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2812 2813 xic->icp_get = pnv_icp_get; 2814 xic->ics_get = pnv_ics_get; 2815 xic->ics_resend = pnv_ics_resend; 2816 2817 pmc->compat = compat; 2818 pmc->compat_size = sizeof(compat); 2819 pmc->max_smt_threads = 8; 2820 /* POWER8 is always lpar-per-core mode */ 2821 pmc->has_lpar_per_thread = false; 2822 2823 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2824 } 2825 2826 static void pnv_machine_power9_class_init(ObjectClass *oc, const void *data) 2827 { 2828 MachineClass *mc = MACHINE_CLASS(oc); 2829 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2830 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2831 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2832 2833 static GlobalProperty phb_compat[] = { 2834 { TYPE_PNV_PHB, "version", "4" }, 2835 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2836 }; 2837 2838 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2839 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2840 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2841 2842 xfc->match_nvt = pnv_match_nvt; 2843 2844 pmc->compat = compat; 2845 pmc->compat_size = sizeof(compat); 2846 pmc->max_smt_threads = 4; 2847 pmc->has_lpar_per_thread = true; 2848 pmc->dt_power_mgt = pnv_dt_power_mgt; 2849 2850 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2851 2852 object_class_property_add_bool(oc, "big-core", 2853 pnv_machine_get_big_core, 2854 pnv_machine_set_big_core); 2855 object_class_property_set_description(oc, "big-core", 2856 "Use big-core (aka fused-core) mode"); 2857 2858 object_class_property_add_bool(oc, "lpar-per-core", 2859 pnv_machine_get_lpar_per_core, 2860 pnv_machine_set_lpar_per_core); 2861 object_class_property_set_description(oc, "lpar-per-core", 2862 "Use 1 LPAR per core mode"); 2863 } 2864 2865 static void pnv_machine_p10_common_class_init(ObjectClass *oc, const void *data) 2866 { 2867 MachineClass *mc = MACHINE_CLASS(oc); 2868 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2869 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2870 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2871 2872 static GlobalProperty phb_compat[] = { 2873 { TYPE_PNV_PHB, "version", "5" }, 2874 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2875 }; 2876 2877 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2878 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2879 2880 mc->alias = "powernv"; 2881 2882 pmc->compat = compat; 2883 pmc->compat_size = sizeof(compat); 2884 pmc->max_smt_threads = 4; 2885 pmc->has_lpar_per_thread = true; 2886 pmc->quirk_tb_big_core = true; 2887 pmc->dt_power_mgt = pnv_dt_power_mgt; 2888 2889 xfc->match_nvt = pnv10_xive_match_nvt; 2890 xfc->broadcast = pnv10_xive_broadcast; 2891 2892 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2893 } 2894 2895 static void pnv_machine_power10_class_init(ObjectClass *oc, const void *data) 2896 { 2897 MachineClass *mc = MACHINE_CLASS(oc); 2898 2899 pnv_machine_p10_common_class_init(oc, data); 2900 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2901 2902 /* 2903 * This is the parent of POWER10 Rainier class, so properies go here 2904 * rather than common init (which would add them to both parent and 2905 * child which is invalid). 2906 */ 2907 object_class_property_add_bool(oc, "big-core", 2908 pnv_machine_get_big_core, 2909 pnv_machine_set_big_core); 2910 object_class_property_set_description(oc, "big-core", 2911 "Use big-core (aka fused-core) mode"); 2912 2913 object_class_property_add_bool(oc, "lpar-per-core", 2914 pnv_machine_get_lpar_per_core, 2915 pnv_machine_set_lpar_per_core); 2916 object_class_property_set_description(oc, "lpar-per-core", 2917 "Use 1 LPAR per core mode"); 2918 } 2919 2920 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, 2921 const void *data) 2922 { 2923 MachineClass *mc = MACHINE_CLASS(oc); 2924 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2925 2926 pnv_machine_p10_common_class_init(oc, data); 2927 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2928 pmc->i2c_init = pnv_rainier_i2c_init; 2929 } 2930 2931 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2932 { 2933 CPUPPCState *env = cpu_env(cs); 2934 2935 cpu_synchronize_state(cs); 2936 ppc_cpu_do_system_reset(cs); 2937 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2938 /* 2939 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2940 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2941 * (PPC_BIT(43)). 2942 */ 2943 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2944 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2945 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2946 } 2947 } else { 2948 /* 2949 * For non-powersave system resets, SRR1[42:45] are defined to be 2950 * implementation-dependent. The POWER9 User Manual specifies that 2951 * an external (SCOM driven, which may come from a BMC nmi command or 2952 * another CPU requesting a NMI IPI) system reset exception should be 2953 * 0b0010 (PPC_BIT(44)). 2954 */ 2955 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2956 } 2957 if (arg.host_int == 1) { 2958 cpu_resume(cs); 2959 } 2960 } 2961 2962 /* 2963 * Send a SRESET (NMI) interrupt to the CPU, and resume execution if it was 2964 * paused. 2965 */ 2966 void pnv_cpu_do_nmi_resume(CPUState *cs) 2967 { 2968 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(1)); 2969 } 2970 2971 static void pnv_cpu_do_nmi(PnvChip *chip, PowerPCCPU *cpu, void *opaque) 2972 { 2973 async_run_on_cpu(CPU(cpu), pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_HOST_INT(0)); 2974 } 2975 2976 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2977 { 2978 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2979 int i; 2980 2981 for (i = 0; i < pnv->num_chips; i++) { 2982 pnv_chip_foreach_cpu(pnv->chips[i], pnv_cpu_do_nmi, NULL); 2983 } 2984 } 2985 2986 static void pnv_machine_class_init(ObjectClass *oc, const void *data) 2987 { 2988 MachineClass *mc = MACHINE_CLASS(oc); 2989 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2990 NMIClass *nc = NMI_CLASS(oc); 2991 2992 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2993 mc->init = pnv_init; 2994 mc->reset = pnv_reset; 2995 mc->max_cpus = MAX_CPUS; 2996 /* Pnv provides a AHCI device for storage */ 2997 mc->block_default_type = IF_IDE; 2998 mc->no_parallel = 1; 2999 mc->default_boot_order = NULL; 3000 /* 3001 * RAM defaults to less than 2048 for 32-bit hosts, and large 3002 * enough to fit the maximum initrd size at it's load address 3003 */ 3004 mc->default_ram_size = 1 * GiB; 3005 mc->default_ram_id = "pnv.ram"; 3006 ispc->print_info = pnv_pic_print_info; 3007 nc->nmi_monitor_handler = pnv_nmi; 3008 3009 object_class_property_add_bool(oc, "hb-mode", 3010 pnv_machine_get_hb, pnv_machine_set_hb); 3011 object_class_property_set_description(oc, "hb-mode", 3012 "Use a hostboot like boot loader"); 3013 } 3014 3015 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 3016 { \ 3017 .name = type, \ 3018 .class_init = class_initfn, \ 3019 .parent = TYPE_PNV8_CHIP, \ 3020 } 3021 3022 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 3023 { \ 3024 .name = type, \ 3025 .class_init = class_initfn, \ 3026 .parent = TYPE_PNV9_CHIP, \ 3027 } 3028 3029 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 3030 { \ 3031 .name = type, \ 3032 .class_init = class_initfn, \ 3033 .parent = TYPE_PNV10_CHIP, \ 3034 } 3035 3036 static const TypeInfo types[] = { 3037 { 3038 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 3039 .parent = MACHINE_TYPE_NAME("powernv10"), 3040 .class_init = pnv_machine_p10_rainier_class_init, 3041 }, 3042 { 3043 .name = MACHINE_TYPE_NAME("powernv10"), 3044 .parent = TYPE_PNV_MACHINE, 3045 .class_init = pnv_machine_power10_class_init, 3046 .interfaces = (const InterfaceInfo[]) { 3047 { TYPE_XIVE_FABRIC }, 3048 { }, 3049 }, 3050 }, 3051 { 3052 .name = MACHINE_TYPE_NAME("powernv9"), 3053 .parent = TYPE_PNV_MACHINE, 3054 .class_init = pnv_machine_power9_class_init, 3055 .interfaces = (const InterfaceInfo[]) { 3056 { TYPE_XIVE_FABRIC }, 3057 { }, 3058 }, 3059 }, 3060 { 3061 .name = MACHINE_TYPE_NAME("powernv8"), 3062 .parent = TYPE_PNV_MACHINE, 3063 .class_init = pnv_machine_power8_class_init, 3064 .interfaces = (const InterfaceInfo[]) { 3065 { TYPE_XICS_FABRIC }, 3066 { }, 3067 }, 3068 }, 3069 { 3070 .name = TYPE_PNV_MACHINE, 3071 .parent = TYPE_MACHINE, 3072 .abstract = true, 3073 .instance_size = sizeof(PnvMachineState), 3074 .class_init = pnv_machine_class_init, 3075 .class_size = sizeof(PnvMachineClass), 3076 .interfaces = (const InterfaceInfo[]) { 3077 { TYPE_INTERRUPT_STATS_PROVIDER }, 3078 { TYPE_NMI }, 3079 { }, 3080 }, 3081 }, 3082 { 3083 .name = TYPE_PNV_CHIP, 3084 .parent = TYPE_SYS_BUS_DEVICE, 3085 .class_init = pnv_chip_class_init, 3086 .instance_size = sizeof(PnvChip), 3087 .class_size = sizeof(PnvChipClass), 3088 .abstract = true, 3089 }, 3090 3091 /* 3092 * P10 chip and variants 3093 */ 3094 { 3095 .name = TYPE_PNV10_CHIP, 3096 .parent = TYPE_PNV_CHIP, 3097 .instance_init = pnv_chip_power10_instance_init, 3098 .instance_size = sizeof(Pnv10Chip), 3099 }, 3100 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 3101 3102 /* 3103 * P9 chip and variants 3104 */ 3105 { 3106 .name = TYPE_PNV9_CHIP, 3107 .parent = TYPE_PNV_CHIP, 3108 .instance_init = pnv_chip_power9_instance_init, 3109 .instance_size = sizeof(Pnv9Chip), 3110 }, 3111 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 3112 3113 /* 3114 * P8 chip and variants 3115 */ 3116 { 3117 .name = TYPE_PNV8_CHIP, 3118 .parent = TYPE_PNV_CHIP, 3119 .instance_init = pnv_chip_power8_instance_init, 3120 .instance_size = sizeof(Pnv8Chip), 3121 }, 3122 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 3123 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 3124 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 3125 pnv_chip_power8nvl_class_init), 3126 }; 3127 3128 DEFINE_TYPES(types) 3129