1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 #include "hw/ppc/pnv_pnor.h" 48 49 #include "hw/isa/isa.h" 50 #include "hw/boards.h" 51 #include "hw/char/serial.h" 52 #include "hw/rtc/mc146818rtc.h" 53 54 #include <libfdt.h> 55 56 #define FDT_MAX_SIZE (1 * MiB) 57 58 #define FW_FILE_NAME "skiboot.lid" 59 #define FW_LOAD_ADDR 0x0 60 #define FW_MAX_SIZE (4 * MiB) 61 62 #define KERNEL_LOAD_ADDR 0x20000000 63 #define KERNEL_MAX_SIZE (256 * MiB) 64 #define INITRD_LOAD_ADDR 0x60000000 65 #define INITRD_MAX_SIZE (256 * MiB) 66 67 static const char *pnv_chip_core_typename(const PnvChip *o) 68 { 69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 72 const char *core_type = object_class_get_name(object_class_by_name(s)); 73 g_free(s); 74 return core_type; 75 } 76 77 /* 78 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 79 * 4 * 4 sockets * 12 cores * 8 threads = 1536 80 * Let's make it 2^11 81 */ 82 #define MAX_CPUS 2048 83 84 /* 85 * Memory nodes are created by hostboot, one for each range of memory 86 * that has a different "affinity". In practice, it means one range 87 * per chip. 88 */ 89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 90 { 91 char *mem_name; 92 uint64_t mem_reg_property[2]; 93 int off; 94 95 mem_reg_property[0] = cpu_to_be64(start); 96 mem_reg_property[1] = cpu_to_be64(size); 97 98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 99 off = fdt_add_subnode(fdt, 0, mem_name); 100 g_free(mem_name); 101 102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 104 sizeof(mem_reg_property)))); 105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 106 } 107 108 static int get_cpus_node(void *fdt) 109 { 110 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 111 112 if (cpus_offset < 0) { 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 114 if (cpus_offset) { 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 117 } 118 } 119 _FDT(cpus_offset); 120 return cpus_offset; 121 } 122 123 /* 124 * The PowerNV cores (and threads) need to use real HW ids and not an 125 * incremental index like it has been done on other platforms. This HW 126 * id is stored in the CPU PIR, it is used to create cpu nodes in the 127 * device tree, used in XSCOM to address cores and in interrupt 128 * servers. 129 */ 130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 131 { 132 PowerPCCPU *cpu = pc->threads[0]; 133 CPUState *cs = CPU(cpu); 134 DeviceClass *dc = DEVICE_GET_CLASS(cs); 135 int smt_threads = CPU_CORE(pc)->nr_threads; 136 CPUPPCState *env = &cpu->env; 137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 138 uint32_t servers_prop[smt_threads]; 139 int i; 140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 141 0xffffffff, 0xffffffff}; 142 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 143 uint32_t cpufreq = 1000000000; 144 uint32_t page_sizes_prop[64]; 145 size_t page_sizes_prop_size; 146 const uint8_t pa_features[] = { 24, 0, 147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 151 int offset; 152 char *nodename; 153 int cpus_offset = get_cpus_node(fdt); 154 155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 156 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 157 _FDT(offset); 158 g_free(nodename); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 172 env->icache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 174 env->icache_line_size))); 175 176 if (pcc->l1_dcache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 178 pcc->l1_dcache_size))); 179 } else { 180 warn_report("Unknown L1 dcache size for cpu"); 181 } 182 if (pcc->l1_icache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 184 pcc->l1_icache_size))); 185 } else { 186 warn_report("Unknown L1 icache size for cpu"); 187 } 188 189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 192 cpu->hash64_opts->slb_size))); 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 195 196 if (env->spr_cb[SPR_PURR].oea_read) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 198 } 199 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 202 segs, sizeof(segs)))); 203 } 204 205 /* 206 * Advertise VMX/VSX (vector extensions) if available 207 * 0 / no property == no vector extensions 208 * 1 == VMX / Altivec available 209 * 2 == VSX available 210 */ 211 if (env->insns_flags & PPC_ALTIVEC) { 212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 213 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 215 } 216 217 /* 218 * Advertise DFP (Decimal Floating Point) if available 219 * 0 / no property == no DFP 220 * 1 == DFP available 221 */ 222 if (env->insns_flags2 & PPC2_DFP) { 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 224 } 225 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 227 sizeof(page_sizes_prop)); 228 if (page_sizes_prop_size) { 229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 230 page_sizes_prop, page_sizes_prop_size))); 231 } 232 233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 234 pa_features, sizeof(pa_features)))); 235 236 /* Build interrupt servers properties */ 237 for (i = 0; i < smt_threads; i++) { 238 servers_prop[i] = cpu_to_be32(pc->pir + i); 239 } 240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 241 servers_prop, sizeof(servers_prop)))); 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 282 { 283 int i; 284 285 pnv_dt_xscom(chip, fdt, 0); 286 287 for (i = 0; i < chip->nr_cores; i++) { 288 PnvCore *pnv_core = chip->cores[i]; 289 290 pnv_dt_core(chip, pnv_core, fdt); 291 292 /* Interrupt Control Presenters (ICP). One per core. */ 293 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 294 } 295 296 if (chip->ram_size) { 297 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 298 } 299 } 300 301 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 302 { 303 int i; 304 305 pnv_dt_xscom(chip, fdt, 0); 306 307 for (i = 0; i < chip->nr_cores; i++) { 308 PnvCore *pnv_core = chip->cores[i]; 309 310 pnv_dt_core(chip, pnv_core, fdt); 311 } 312 313 if (chip->ram_size) { 314 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 315 } 316 317 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 318 } 319 320 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 321 { 322 int i; 323 324 pnv_dt_xscom(chip, fdt, 0); 325 326 for (i = 0; i < chip->nr_cores; i++) { 327 PnvCore *pnv_core = chip->cores[i]; 328 329 pnv_dt_core(chip, pnv_core, fdt); 330 } 331 332 if (chip->ram_size) { 333 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 334 } 335 336 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 337 } 338 339 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 340 { 341 uint32_t io_base = d->ioport_id; 342 uint32_t io_regs[] = { 343 cpu_to_be32(1), 344 cpu_to_be32(io_base), 345 cpu_to_be32(2) 346 }; 347 char *name; 348 int node; 349 350 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 351 node = fdt_add_subnode(fdt, lpc_off, name); 352 _FDT(node); 353 g_free(name); 354 355 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 356 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 357 } 358 359 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 360 { 361 const char compatible[] = "ns16550\0pnpPNP,501"; 362 uint32_t io_base = d->ioport_id; 363 uint32_t io_regs[] = { 364 cpu_to_be32(1), 365 cpu_to_be32(io_base), 366 cpu_to_be32(8) 367 }; 368 char *name; 369 int node; 370 371 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 372 node = fdt_add_subnode(fdt, lpc_off, name); 373 _FDT(node); 374 g_free(name); 375 376 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 377 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 378 sizeof(compatible)))); 379 380 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 381 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 382 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 383 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 384 fdt_get_phandle(fdt, lpc_off)))); 385 386 /* This is needed by Linux */ 387 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 388 } 389 390 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 391 { 392 const char compatible[] = "bt\0ipmi-bt"; 393 uint32_t io_base; 394 uint32_t io_regs[] = { 395 cpu_to_be32(1), 396 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 397 cpu_to_be32(3) 398 }; 399 uint32_t irq; 400 char *name; 401 int node; 402 403 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 404 io_regs[1] = cpu_to_be32(io_base); 405 406 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 407 408 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 409 node = fdt_add_subnode(fdt, lpc_off, name); 410 _FDT(node); 411 g_free(name); 412 413 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 414 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 415 sizeof(compatible)))); 416 417 /* Mark it as reserved to avoid Linux trying to claim it */ 418 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 419 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 420 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 421 fdt_get_phandle(fdt, lpc_off)))); 422 } 423 424 typedef struct ForeachPopulateArgs { 425 void *fdt; 426 int offset; 427 } ForeachPopulateArgs; 428 429 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 430 { 431 ForeachPopulateArgs *args = opaque; 432 ISADevice *d = ISA_DEVICE(dev); 433 434 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 435 pnv_dt_rtc(d, args->fdt, args->offset); 436 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 437 pnv_dt_serial(d, args->fdt, args->offset); 438 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 439 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 440 } else { 441 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 442 d->ioport_id); 443 } 444 445 return 0; 446 } 447 448 /* 449 * The default LPC bus of a multichip system is on chip 0. It's 450 * recognized by the firmware (skiboot) using a "primary" property. 451 */ 452 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 453 { 454 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 455 ForeachPopulateArgs args = { 456 .fdt = fdt, 457 .offset = isa_offset, 458 }; 459 uint32_t phandle; 460 461 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 462 463 phandle = qemu_fdt_alloc_phandle(fdt); 464 assert(phandle > 0); 465 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 466 467 /* 468 * ISA devices are not necessarily parented to the ISA bus so we 469 * can not use object_child_foreach() 470 */ 471 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 472 &args); 473 } 474 475 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 476 { 477 int off; 478 479 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 480 off = fdt_add_subnode(fdt, off, "power-mgt"); 481 482 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 483 } 484 485 static void *pnv_dt_create(MachineState *machine) 486 { 487 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 488 PnvMachineState *pnv = PNV_MACHINE(machine); 489 void *fdt; 490 char *buf; 491 int off; 492 int i; 493 494 fdt = g_malloc0(FDT_MAX_SIZE); 495 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 496 497 /* /qemu node */ 498 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 499 500 /* Root node */ 501 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 502 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 503 _FDT((fdt_setprop_string(fdt, 0, "model", 504 "IBM PowerNV (emulated by qemu)"))); 505 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 506 507 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 508 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 509 if (qemu_uuid_set) { 510 _FDT((fdt_property_string(fdt, "system-id", buf))); 511 } 512 g_free(buf); 513 514 off = fdt_add_subnode(fdt, 0, "chosen"); 515 if (machine->kernel_cmdline) { 516 _FDT((fdt_setprop_string(fdt, off, "bootargs", 517 machine->kernel_cmdline))); 518 } 519 520 if (pnv->initrd_size) { 521 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 522 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 523 524 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 525 &start_prop, sizeof(start_prop)))); 526 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 527 &end_prop, sizeof(end_prop)))); 528 } 529 530 /* Populate device tree for each chip */ 531 for (i = 0; i < pnv->num_chips; i++) { 532 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 533 } 534 535 /* Populate ISA devices on chip 0 */ 536 pnv_dt_isa(pnv, fdt); 537 538 if (pnv->bmc) { 539 pnv_dt_bmc_sensors(pnv->bmc, fdt); 540 } 541 542 /* Create an extra node for power management on machines that support it */ 543 if (pmc->dt_power_mgt) { 544 pmc->dt_power_mgt(pnv, fdt); 545 } 546 547 return fdt; 548 } 549 550 static void pnv_powerdown_notify(Notifier *n, void *opaque) 551 { 552 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 553 554 if (pnv->bmc) { 555 pnv_bmc_powerdown(pnv->bmc); 556 } 557 } 558 559 static void pnv_reset(MachineState *machine) 560 { 561 void *fdt; 562 563 qemu_devices_reset(); 564 565 fdt = pnv_dt_create(machine); 566 567 /* Pack resulting tree */ 568 _FDT((fdt_pack(fdt))); 569 570 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 571 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 572 } 573 574 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 575 { 576 Pnv8Chip *chip8 = PNV8_CHIP(chip); 577 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 578 } 579 580 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 581 { 582 Pnv8Chip *chip8 = PNV8_CHIP(chip); 583 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 584 } 585 586 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 587 { 588 Pnv9Chip *chip9 = PNV9_CHIP(chip); 589 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 590 } 591 592 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 593 { 594 Pnv10Chip *chip10 = PNV10_CHIP(chip); 595 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 596 } 597 598 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 599 { 600 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 601 } 602 603 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 604 { 605 Pnv8Chip *chip8 = PNV8_CHIP(chip); 606 607 ics_pic_print_info(&chip8->psi.ics, mon); 608 } 609 610 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 611 { 612 Pnv9Chip *chip9 = PNV9_CHIP(chip); 613 614 pnv_xive_pic_print_info(&chip9->xive, mon); 615 pnv_psi_pic_print_info(&chip9->psi, mon); 616 } 617 618 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 619 uint32_t core_id) 620 { 621 return PNV_XSCOM_EX_BASE(core_id); 622 } 623 624 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 625 uint32_t core_id) 626 { 627 return PNV9_XSCOM_EC_BASE(core_id); 628 } 629 630 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 631 uint32_t core_id) 632 { 633 return PNV10_XSCOM_EC_BASE(core_id); 634 } 635 636 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 637 { 638 PowerPCCPUClass *ppc_default = 639 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 640 PowerPCCPUClass *ppc = 641 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 642 643 return ppc_default->pvr_match(ppc_default, ppc->pvr); 644 } 645 646 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 647 { 648 Object *obj; 649 650 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 651 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 652 object_property_set_int(obj, irq, "irq", &error_fatal); 653 object_property_set_bool(obj, true, "realized", &error_fatal); 654 } 655 656 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 657 { 658 Pnv10Chip *chip10 = PNV10_CHIP(chip); 659 660 pnv_psi_pic_print_info(&chip10->psi, mon); 661 } 662 663 static void pnv_init(MachineState *machine) 664 { 665 PnvMachineState *pnv = PNV_MACHINE(machine); 666 MachineClass *mc = MACHINE_GET_CLASS(machine); 667 MemoryRegion *ram; 668 char *fw_filename; 669 long fw_size; 670 int i; 671 char *chip_typename; 672 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 673 DeviceState *dev; 674 675 /* allocate RAM */ 676 if (machine->ram_size < (1 * GiB)) { 677 warn_report("skiboot may not work with < 1GB of RAM"); 678 } 679 680 ram = g_new(MemoryRegion, 1); 681 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 682 machine->ram_size); 683 memory_region_add_subregion(get_system_memory(), 0, ram); 684 685 /* 686 * Create our simple PNOR device 687 */ 688 dev = qdev_create(NULL, TYPE_PNV_PNOR); 689 if (pnor) { 690 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 691 &error_abort); 692 } 693 qdev_init_nofail(dev); 694 pnv->pnor = PNV_PNOR(dev); 695 696 /* load skiboot firmware */ 697 if (bios_name == NULL) { 698 bios_name = FW_FILE_NAME; 699 } 700 701 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 702 if (!fw_filename) { 703 error_report("Could not find OPAL firmware '%s'", bios_name); 704 exit(1); 705 } 706 707 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 708 if (fw_size < 0) { 709 error_report("Could not load OPAL firmware '%s'", fw_filename); 710 exit(1); 711 } 712 g_free(fw_filename); 713 714 /* load kernel */ 715 if (machine->kernel_filename) { 716 long kernel_size; 717 718 kernel_size = load_image_targphys(machine->kernel_filename, 719 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 720 if (kernel_size < 0) { 721 error_report("Could not load kernel '%s'", 722 machine->kernel_filename); 723 exit(1); 724 } 725 } 726 727 /* load initrd */ 728 if (machine->initrd_filename) { 729 pnv->initrd_base = INITRD_LOAD_ADDR; 730 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 731 pnv->initrd_base, INITRD_MAX_SIZE); 732 if (pnv->initrd_size < 0) { 733 error_report("Could not load initial ram disk '%s'", 734 machine->initrd_filename); 735 exit(1); 736 } 737 } 738 739 /* 740 * Check compatibility of the specified CPU with the machine 741 * default. 742 */ 743 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 744 error_report("invalid CPU model '%s' for %s machine", 745 machine->cpu_type, mc->name); 746 exit(1); 747 } 748 749 /* Create the processor chips */ 750 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 751 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 752 i, machine->cpu_type); 753 if (!object_class_by_name(chip_typename)) { 754 error_report("invalid chip model '%.*s' for %s machine", 755 i, machine->cpu_type, mc->name); 756 exit(1); 757 } 758 759 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 760 for (i = 0; i < pnv->num_chips; i++) { 761 char chip_name[32]; 762 Object *chip = object_new(chip_typename); 763 764 pnv->chips[i] = PNV_CHIP(chip); 765 766 /* 767 * TODO: put all the memory in one node on chip 0 until we find a 768 * way to specify different ranges for each chip 769 */ 770 if (i == 0) { 771 object_property_set_int(chip, machine->ram_size, "ram-size", 772 &error_fatal); 773 } 774 775 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 776 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 777 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 778 &error_fatal); 779 object_property_set_int(chip, machine->smp.cores, 780 "nr-cores", &error_fatal); 781 object_property_set_bool(chip, true, "realized", &error_fatal); 782 } 783 g_free(chip_typename); 784 785 /* Create the machine BMC simulator */ 786 pnv->bmc = pnv_bmc_create(); 787 788 /* Instantiate ISA bus on chip 0 */ 789 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 790 791 /* Create serial port */ 792 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 793 794 /* Create an RTC ISA device too */ 795 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 796 797 /* Create the IPMI BT device for communication with the BMC */ 798 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 799 800 /* 801 * OpenPOWER systems use a IPMI SEL Event message to notify the 802 * host to powerdown 803 */ 804 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 805 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 806 } 807 808 /* 809 * 0:21 Reserved - Read as zeros 810 * 22:24 Chip ID 811 * 25:28 Core number 812 * 29:31 Thread ID 813 */ 814 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 815 { 816 return (chip->chip_id << 7) | (core_id << 3); 817 } 818 819 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 820 Error **errp) 821 { 822 Error *local_err = NULL; 823 Object *obj; 824 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 825 826 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 827 &local_err); 828 if (local_err) { 829 error_propagate(errp, local_err); 830 return; 831 } 832 833 pnv_cpu->intc = obj; 834 } 835 836 837 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 838 { 839 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 840 841 icp_reset(ICP(pnv_cpu->intc)); 842 } 843 844 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 845 { 846 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 847 848 icp_destroy(ICP(pnv_cpu->intc)); 849 pnv_cpu->intc = NULL; 850 } 851 852 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 853 Monitor *mon) 854 { 855 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 856 } 857 858 /* 859 * 0:48 Reserved - Read as zeroes 860 * 49:52 Node ID 861 * 53:55 Chip ID 862 * 56 Reserved - Read as zero 863 * 57:61 Core number 864 * 62:63 Thread ID 865 * 866 * We only care about the lower bits. uint32_t is fine for the moment. 867 */ 868 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 869 { 870 return (chip->chip_id << 8) | (core_id << 2); 871 } 872 873 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 874 { 875 return (chip->chip_id << 8) | (core_id << 2); 876 } 877 878 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 879 Error **errp) 880 { 881 Pnv9Chip *chip9 = PNV9_CHIP(chip); 882 Error *local_err = NULL; 883 Object *obj; 884 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 885 886 /* 887 * The core creates its interrupt presenter but the XIVE interrupt 888 * controller object is initialized afterwards. Hopefully, it's 889 * only used at runtime. 890 */ 891 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 892 if (local_err) { 893 error_propagate(errp, local_err); 894 return; 895 } 896 897 pnv_cpu->intc = obj; 898 } 899 900 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 901 { 902 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 903 904 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 905 } 906 907 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 908 { 909 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 910 911 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 912 pnv_cpu->intc = NULL; 913 } 914 915 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 916 Monitor *mon) 917 { 918 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 919 } 920 921 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 922 Error **errp) 923 { 924 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 925 926 /* Will be defined when the interrupt controller is */ 927 pnv_cpu->intc = NULL; 928 } 929 930 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 931 { 932 ; 933 } 934 935 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 936 { 937 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 938 939 pnv_cpu->intc = NULL; 940 } 941 942 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 943 Monitor *mon) 944 { 945 } 946 947 /* 948 * Allowed core identifiers on a POWER8 Processor Chip : 949 * 950 * <EX0 reserved> 951 * EX1 - Venice only 952 * EX2 - Venice only 953 * EX3 - Venice only 954 * EX4 955 * EX5 956 * EX6 957 * <EX7,8 reserved> <reserved> 958 * EX9 - Venice only 959 * EX10 - Venice only 960 * EX11 - Venice only 961 * EX12 962 * EX13 963 * EX14 964 * <EX15 reserved> 965 */ 966 #define POWER8E_CORE_MASK (0x7070ull) 967 #define POWER8_CORE_MASK (0x7e7eull) 968 969 /* 970 * POWER9 has 24 cores, ids starting at 0x0 971 */ 972 #define POWER9_CORE_MASK (0xffffffffffffffull) 973 974 975 #define POWER10_CORE_MASK (0xffffffffffffffull) 976 977 static void pnv_chip_power8_instance_init(Object *obj) 978 { 979 Pnv8Chip *chip8 = PNV8_CHIP(obj); 980 981 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 982 TYPE_PNV8_PSI, &error_abort, NULL); 983 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 984 OBJECT(qdev_get_machine()), &error_abort); 985 986 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 987 TYPE_PNV8_LPC, &error_abort, NULL); 988 989 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 990 TYPE_PNV8_OCC, &error_abort, NULL); 991 992 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 993 TYPE_PNV8_HOMER, &error_abort, NULL); 994 } 995 996 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 997 { 998 PnvChip *chip = PNV_CHIP(chip8); 999 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1000 int i, j; 1001 char *name; 1002 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 1003 1004 name = g_strdup_printf("icp-%x", chip->chip_id); 1005 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1006 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1007 g_free(name); 1008 1009 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1010 1011 /* Map the ICP registers for each thread */ 1012 for (i = 0; i < chip->nr_cores; i++) { 1013 PnvCore *pnv_core = chip->cores[i]; 1014 int core_hwid = CPU_CORE(pnv_core)->core_id; 1015 1016 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1017 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1018 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 1019 1020 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1021 &icp->mmio); 1022 } 1023 } 1024 } 1025 1026 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1027 { 1028 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1029 PnvChip *chip = PNV_CHIP(dev); 1030 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1031 Pnv8Psi *psi8 = &chip8->psi; 1032 Error *local_err = NULL; 1033 1034 /* XSCOM bridge is first */ 1035 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1036 if (local_err) { 1037 error_propagate(errp, local_err); 1038 return; 1039 } 1040 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1041 1042 pcc->parent_realize(dev, &local_err); 1043 if (local_err) { 1044 error_propagate(errp, local_err); 1045 return; 1046 } 1047 1048 /* Processor Service Interface (PSI) Host Bridge */ 1049 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1050 "bar", &error_fatal); 1051 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1052 if (local_err) { 1053 error_propagate(errp, local_err); 1054 return; 1055 } 1056 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1057 &PNV_PSI(psi8)->xscom_regs); 1058 1059 /* Create LPC controller */ 1060 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1061 &error_abort); 1062 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1063 &error_fatal); 1064 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1065 1066 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1067 (uint64_t) PNV_XSCOM_BASE(chip), 1068 PNV_XSCOM_LPC_BASE); 1069 1070 /* 1071 * Interrupt Management Area. This is the memory region holding 1072 * all the Interrupt Control Presenter (ICP) registers 1073 */ 1074 pnv_chip_icp_realize(chip8, &local_err); 1075 if (local_err) { 1076 error_propagate(errp, local_err); 1077 return; 1078 } 1079 1080 /* Create the simplified OCC model */ 1081 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1082 &error_abort); 1083 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1084 if (local_err) { 1085 error_propagate(errp, local_err); 1086 return; 1087 } 1088 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1089 1090 /* OCC SRAM model */ 1091 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1092 &chip8->occ.sram_regs); 1093 1094 /* HOMER */ 1095 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1096 &error_abort); 1097 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1098 &local_err); 1099 if (local_err) { 1100 error_propagate(errp, local_err); 1101 return; 1102 } 1103 /* Homer Xscom region */ 1104 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1105 1106 /* Homer mmio region */ 1107 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1108 &chip8->homer.regs); 1109 } 1110 1111 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1112 { 1113 DeviceClass *dc = DEVICE_CLASS(klass); 1114 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1115 1116 k->chip_type = PNV_CHIP_POWER8E; 1117 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1118 k->cores_mask = POWER8E_CORE_MASK; 1119 k->core_pir = pnv_chip_core_pir_p8; 1120 k->intc_create = pnv_chip_power8_intc_create; 1121 k->intc_reset = pnv_chip_power8_intc_reset; 1122 k->intc_destroy = pnv_chip_power8_intc_destroy; 1123 k->intc_print_info = pnv_chip_power8_intc_print_info; 1124 k->isa_create = pnv_chip_power8_isa_create; 1125 k->dt_populate = pnv_chip_power8_dt_populate; 1126 k->pic_print_info = pnv_chip_power8_pic_print_info; 1127 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1128 dc->desc = "PowerNV Chip POWER8E"; 1129 1130 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1131 &k->parent_realize); 1132 } 1133 1134 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1135 { 1136 DeviceClass *dc = DEVICE_CLASS(klass); 1137 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1138 1139 k->chip_type = PNV_CHIP_POWER8; 1140 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1141 k->cores_mask = POWER8_CORE_MASK; 1142 k->core_pir = pnv_chip_core_pir_p8; 1143 k->intc_create = pnv_chip_power8_intc_create; 1144 k->intc_reset = pnv_chip_power8_intc_reset; 1145 k->intc_destroy = pnv_chip_power8_intc_destroy; 1146 k->intc_print_info = pnv_chip_power8_intc_print_info; 1147 k->isa_create = pnv_chip_power8_isa_create; 1148 k->dt_populate = pnv_chip_power8_dt_populate; 1149 k->pic_print_info = pnv_chip_power8_pic_print_info; 1150 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1151 dc->desc = "PowerNV Chip POWER8"; 1152 1153 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1154 &k->parent_realize); 1155 } 1156 1157 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1158 { 1159 DeviceClass *dc = DEVICE_CLASS(klass); 1160 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1161 1162 k->chip_type = PNV_CHIP_POWER8NVL; 1163 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1164 k->cores_mask = POWER8_CORE_MASK; 1165 k->core_pir = pnv_chip_core_pir_p8; 1166 k->intc_create = pnv_chip_power8_intc_create; 1167 k->intc_reset = pnv_chip_power8_intc_reset; 1168 k->intc_destroy = pnv_chip_power8_intc_destroy; 1169 k->intc_print_info = pnv_chip_power8_intc_print_info; 1170 k->isa_create = pnv_chip_power8nvl_isa_create; 1171 k->dt_populate = pnv_chip_power8_dt_populate; 1172 k->pic_print_info = pnv_chip_power8_pic_print_info; 1173 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1174 dc->desc = "PowerNV Chip POWER8NVL"; 1175 1176 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1177 &k->parent_realize); 1178 } 1179 1180 static void pnv_chip_power9_instance_init(Object *obj) 1181 { 1182 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1183 1184 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1185 TYPE_PNV_XIVE, &error_abort, NULL); 1186 1187 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1188 TYPE_PNV9_PSI, &error_abort, NULL); 1189 1190 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1191 TYPE_PNV9_LPC, &error_abort, NULL); 1192 1193 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1194 TYPE_PNV9_OCC, &error_abort, NULL); 1195 1196 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1197 TYPE_PNV9_HOMER, &error_abort, NULL); 1198 } 1199 1200 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1201 { 1202 PnvChip *chip = PNV_CHIP(chip9); 1203 int i; 1204 1205 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1206 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1207 1208 for (i = 0; i < chip9->nr_quads; i++) { 1209 char eq_name[32]; 1210 PnvQuad *eq = &chip9->quads[i]; 1211 PnvCore *pnv_core = chip->cores[i * 4]; 1212 int core_id = CPU_CORE(pnv_core)->core_id; 1213 1214 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1215 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1216 TYPE_PNV_QUAD, &error_fatal, NULL); 1217 1218 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1219 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1220 1221 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1222 &eq->xscom_regs); 1223 } 1224 } 1225 1226 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1227 { 1228 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1229 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1230 PnvChip *chip = PNV_CHIP(dev); 1231 Pnv9Psi *psi9 = &chip9->psi; 1232 Error *local_err = NULL; 1233 1234 /* XSCOM bridge is first */ 1235 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1236 if (local_err) { 1237 error_propagate(errp, local_err); 1238 return; 1239 } 1240 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1241 1242 pcc->parent_realize(dev, &local_err); 1243 if (local_err) { 1244 error_propagate(errp, local_err); 1245 return; 1246 } 1247 1248 pnv_chip_quad_realize(chip9, &local_err); 1249 if (local_err) { 1250 error_propagate(errp, local_err); 1251 return; 1252 } 1253 1254 /* XIVE interrupt controller (POWER9) */ 1255 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1256 "ic-bar", &error_fatal); 1257 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1258 "vc-bar", &error_fatal); 1259 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1260 "pc-bar", &error_fatal); 1261 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1262 "tm-bar", &error_fatal); 1263 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1264 &error_abort); 1265 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1266 &local_err); 1267 if (local_err) { 1268 error_propagate(errp, local_err); 1269 return; 1270 } 1271 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1272 &chip9->xive.xscom_regs); 1273 1274 /* Processor Service Interface (PSI) Host Bridge */ 1275 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1276 "bar", &error_fatal); 1277 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1278 if (local_err) { 1279 error_propagate(errp, local_err); 1280 return; 1281 } 1282 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1283 &PNV_PSI(psi9)->xscom_regs); 1284 1285 /* LPC */ 1286 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1287 &error_abort); 1288 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1289 if (local_err) { 1290 error_propagate(errp, local_err); 1291 return; 1292 } 1293 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1294 &chip9->lpc.xscom_regs); 1295 1296 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1297 (uint64_t) PNV9_LPCM_BASE(chip)); 1298 1299 /* Create the simplified OCC model */ 1300 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1301 &error_abort); 1302 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1303 if (local_err) { 1304 error_propagate(errp, local_err); 1305 return; 1306 } 1307 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1308 1309 /* OCC SRAM model */ 1310 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1311 &chip9->occ.sram_regs); 1312 1313 /* HOMER */ 1314 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1315 &error_abort); 1316 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1317 &local_err); 1318 if (local_err) { 1319 error_propagate(errp, local_err); 1320 return; 1321 } 1322 /* Homer Xscom region */ 1323 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1324 1325 /* Homer mmio region */ 1326 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1327 &chip9->homer.regs); 1328 } 1329 1330 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1331 { 1332 DeviceClass *dc = DEVICE_CLASS(klass); 1333 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1334 1335 k->chip_type = PNV_CHIP_POWER9; 1336 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1337 k->cores_mask = POWER9_CORE_MASK; 1338 k->core_pir = pnv_chip_core_pir_p9; 1339 k->intc_create = pnv_chip_power9_intc_create; 1340 k->intc_reset = pnv_chip_power9_intc_reset; 1341 k->intc_destroy = pnv_chip_power9_intc_destroy; 1342 k->intc_print_info = pnv_chip_power9_intc_print_info; 1343 k->isa_create = pnv_chip_power9_isa_create; 1344 k->dt_populate = pnv_chip_power9_dt_populate; 1345 k->pic_print_info = pnv_chip_power9_pic_print_info; 1346 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1347 dc->desc = "PowerNV Chip POWER9"; 1348 1349 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1350 &k->parent_realize); 1351 } 1352 1353 static void pnv_chip_power10_instance_init(Object *obj) 1354 { 1355 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1356 1357 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1358 TYPE_PNV10_PSI, &error_abort, NULL); 1359 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1360 TYPE_PNV10_LPC, &error_abort, NULL); 1361 } 1362 1363 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1364 { 1365 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1366 PnvChip *chip = PNV_CHIP(dev); 1367 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1368 Error *local_err = NULL; 1369 1370 /* XSCOM bridge is first */ 1371 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1372 if (local_err) { 1373 error_propagate(errp, local_err); 1374 return; 1375 } 1376 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1377 1378 pcc->parent_realize(dev, &local_err); 1379 if (local_err) { 1380 error_propagate(errp, local_err); 1381 return; 1382 } 1383 1384 /* Processor Service Interface (PSI) Host Bridge */ 1385 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1386 "bar", &error_fatal); 1387 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1388 &local_err); 1389 if (local_err) { 1390 error_propagate(errp, local_err); 1391 return; 1392 } 1393 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1394 &PNV_PSI(&chip10->psi)->xscom_regs); 1395 1396 /* LPC */ 1397 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1398 &error_abort); 1399 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1400 &local_err); 1401 if (local_err) { 1402 error_propagate(errp, local_err); 1403 return; 1404 } 1405 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1406 &chip10->lpc.xscom_regs); 1407 1408 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1409 (uint64_t) PNV10_LPCM_BASE(chip)); 1410 } 1411 1412 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1413 { 1414 DeviceClass *dc = DEVICE_CLASS(klass); 1415 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1416 1417 k->chip_type = PNV_CHIP_POWER10; 1418 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1419 k->cores_mask = POWER10_CORE_MASK; 1420 k->core_pir = pnv_chip_core_pir_p10; 1421 k->intc_create = pnv_chip_power10_intc_create; 1422 k->intc_reset = pnv_chip_power10_intc_reset; 1423 k->intc_destroy = pnv_chip_power10_intc_destroy; 1424 k->intc_print_info = pnv_chip_power10_intc_print_info; 1425 k->isa_create = pnv_chip_power10_isa_create; 1426 k->dt_populate = pnv_chip_power10_dt_populate; 1427 k->pic_print_info = pnv_chip_power10_pic_print_info; 1428 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1429 dc->desc = "PowerNV Chip POWER10"; 1430 1431 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1432 &k->parent_realize); 1433 } 1434 1435 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1436 { 1437 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1438 int cores_max; 1439 1440 /* 1441 * No custom mask for this chip, let's use the default one from * 1442 * the chip class 1443 */ 1444 if (!chip->cores_mask) { 1445 chip->cores_mask = pcc->cores_mask; 1446 } 1447 1448 /* filter alien core ids ! some are reserved */ 1449 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1450 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1451 chip->cores_mask); 1452 return; 1453 } 1454 chip->cores_mask &= pcc->cores_mask; 1455 1456 /* now that we have a sane layout, let check the number of cores */ 1457 cores_max = ctpop64(chip->cores_mask); 1458 if (chip->nr_cores > cores_max) { 1459 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1460 cores_max); 1461 return; 1462 } 1463 } 1464 1465 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1466 { 1467 MachineState *ms = MACHINE(qdev_get_machine()); 1468 Error *error = NULL; 1469 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1470 const char *typename = pnv_chip_core_typename(chip); 1471 int i, core_hwid; 1472 1473 if (!object_class_by_name(typename)) { 1474 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1475 return; 1476 } 1477 1478 /* Cores */ 1479 pnv_chip_core_sanitize(chip, &error); 1480 if (error) { 1481 error_propagate(errp, error); 1482 return; 1483 } 1484 1485 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1486 1487 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1488 && (i < chip->nr_cores); core_hwid++) { 1489 char core_name[32]; 1490 PnvCore *pnv_core; 1491 uint64_t xscom_core_base; 1492 1493 if (!(chip->cores_mask & (1ull << core_hwid))) { 1494 continue; 1495 } 1496 1497 pnv_core = PNV_CORE(object_new(typename)); 1498 1499 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1500 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1501 &error_abort); 1502 chip->cores[i] = pnv_core; 1503 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1504 &error_fatal); 1505 object_property_set_int(OBJECT(pnv_core), core_hwid, 1506 CPU_CORE_PROP_CORE_ID, &error_fatal); 1507 object_property_set_int(OBJECT(pnv_core), 1508 pcc->core_pir(chip, core_hwid), 1509 "pir", &error_fatal); 1510 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1511 &error_abort); 1512 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1513 &error_fatal); 1514 1515 /* Each core has an XSCOM MMIO region */ 1516 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1517 1518 pnv_xscom_add_subregion(chip, xscom_core_base, 1519 &pnv_core->xscom_regs); 1520 i++; 1521 } 1522 } 1523 1524 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1525 { 1526 PnvChip *chip = PNV_CHIP(dev); 1527 Error *error = NULL; 1528 1529 /* Cores */ 1530 pnv_chip_core_realize(chip, &error); 1531 if (error) { 1532 error_propagate(errp, error); 1533 return; 1534 } 1535 } 1536 1537 static Property pnv_chip_properties[] = { 1538 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1539 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1540 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1541 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1542 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1543 DEFINE_PROP_END_OF_LIST(), 1544 }; 1545 1546 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1547 { 1548 DeviceClass *dc = DEVICE_CLASS(klass); 1549 1550 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1551 dc->realize = pnv_chip_realize; 1552 dc->props = pnv_chip_properties; 1553 dc->desc = "PowerNV Chip"; 1554 } 1555 1556 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1557 { 1558 int i, j; 1559 1560 for (i = 0; i < chip->nr_cores; i++) { 1561 PnvCore *pc = chip->cores[i]; 1562 CPUCore *cc = CPU_CORE(pc); 1563 1564 for (j = 0; j < cc->nr_threads; j++) { 1565 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1566 return pc->threads[j]; 1567 } 1568 } 1569 } 1570 return NULL; 1571 } 1572 1573 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1574 { 1575 PnvMachineState *pnv = PNV_MACHINE(xi); 1576 int i; 1577 1578 for (i = 0; i < pnv->num_chips; i++) { 1579 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1580 1581 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1582 return &chip8->psi.ics; 1583 } 1584 } 1585 return NULL; 1586 } 1587 1588 static void pnv_ics_resend(XICSFabric *xi) 1589 { 1590 PnvMachineState *pnv = PNV_MACHINE(xi); 1591 int i; 1592 1593 for (i = 0; i < pnv->num_chips; i++) { 1594 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1595 ics_resend(&chip8->psi.ics); 1596 } 1597 } 1598 1599 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1600 { 1601 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1602 1603 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1604 } 1605 1606 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1607 Monitor *mon) 1608 { 1609 PnvMachineState *pnv = PNV_MACHINE(obj); 1610 int i; 1611 CPUState *cs; 1612 1613 CPU_FOREACH(cs) { 1614 PowerPCCPU *cpu = POWERPC_CPU(cs); 1615 1616 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1617 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1618 mon); 1619 } 1620 1621 for (i = 0; i < pnv->num_chips; i++) { 1622 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1623 } 1624 } 1625 1626 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1627 uint8_t nvt_blk, uint32_t nvt_idx, 1628 bool cam_ignore, uint8_t priority, 1629 uint32_t logic_serv, 1630 XiveTCTXMatch *match) 1631 { 1632 PnvMachineState *pnv = PNV_MACHINE(xfb); 1633 int total_count = 0; 1634 int i; 1635 1636 for (i = 0; i < pnv->num_chips; i++) { 1637 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1638 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1639 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1640 int count; 1641 1642 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1643 priority, logic_serv, match); 1644 1645 if (count < 0) { 1646 return count; 1647 } 1648 1649 total_count += count; 1650 } 1651 1652 return total_count; 1653 } 1654 1655 PnvChip *pnv_get_chip(uint32_t chip_id) 1656 { 1657 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1658 int i; 1659 1660 for (i = 0; i < pnv->num_chips; i++) { 1661 PnvChip *chip = pnv->chips[i]; 1662 if (chip->chip_id == chip_id) { 1663 return chip; 1664 } 1665 } 1666 return NULL; 1667 } 1668 1669 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1670 void *opaque, Error **errp) 1671 { 1672 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1673 } 1674 1675 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1676 void *opaque, Error **errp) 1677 { 1678 PnvMachineState *pnv = PNV_MACHINE(obj); 1679 uint32_t num_chips; 1680 Error *local_err = NULL; 1681 1682 visit_type_uint32(v, name, &num_chips, &local_err); 1683 if (local_err) { 1684 error_propagate(errp, local_err); 1685 return; 1686 } 1687 1688 /* 1689 * TODO: should we decide on how many chips we can create based 1690 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1691 */ 1692 if (!is_power_of_2(num_chips) || num_chips > 4) { 1693 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1694 return; 1695 } 1696 1697 pnv->num_chips = num_chips; 1698 } 1699 1700 static void pnv_machine_instance_init(Object *obj) 1701 { 1702 PnvMachineState *pnv = PNV_MACHINE(obj); 1703 pnv->num_chips = 1; 1704 } 1705 1706 static void pnv_machine_class_props_init(ObjectClass *oc) 1707 { 1708 object_class_property_add(oc, "num-chips", "uint32", 1709 pnv_get_num_chips, pnv_set_num_chips, 1710 NULL, NULL, NULL); 1711 object_class_property_set_description(oc, "num-chips", 1712 "Specifies the number of processor chips", 1713 NULL); 1714 } 1715 1716 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1717 { 1718 MachineClass *mc = MACHINE_CLASS(oc); 1719 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1720 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1721 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1722 1723 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1724 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1725 1726 xic->icp_get = pnv_icp_get; 1727 xic->ics_get = pnv_ics_get; 1728 xic->ics_resend = pnv_ics_resend; 1729 1730 pmc->compat = compat; 1731 pmc->compat_size = sizeof(compat); 1732 } 1733 1734 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1735 { 1736 MachineClass *mc = MACHINE_CLASS(oc); 1737 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1738 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1739 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1740 1741 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1742 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1743 xfc->match_nvt = pnv_match_nvt; 1744 1745 mc->alias = "powernv"; 1746 1747 pmc->compat = compat; 1748 pmc->compat_size = sizeof(compat); 1749 pmc->dt_power_mgt = pnv_dt_power_mgt; 1750 } 1751 1752 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1753 { 1754 MachineClass *mc = MACHINE_CLASS(oc); 1755 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1756 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1757 1758 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1759 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1760 1761 pmc->compat = compat; 1762 pmc->compat_size = sizeof(compat); 1763 pmc->dt_power_mgt = pnv_dt_power_mgt; 1764 } 1765 1766 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1767 { 1768 MachineClass *mc = MACHINE_CLASS(oc); 1769 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1770 1771 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1772 mc->init = pnv_init; 1773 mc->reset = pnv_reset; 1774 mc->max_cpus = MAX_CPUS; 1775 /* Pnv provides a AHCI device for storage */ 1776 mc->block_default_type = IF_IDE; 1777 mc->no_parallel = 1; 1778 mc->default_boot_order = NULL; 1779 /* 1780 * RAM defaults to less than 2048 for 32-bit hosts, and large 1781 * enough to fit the maximum initrd size at it's load address 1782 */ 1783 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1784 ispc->print_info = pnv_pic_print_info; 1785 1786 pnv_machine_class_props_init(oc); 1787 } 1788 1789 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1790 { \ 1791 .name = type, \ 1792 .class_init = class_initfn, \ 1793 .parent = TYPE_PNV8_CHIP, \ 1794 } 1795 1796 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1797 { \ 1798 .name = type, \ 1799 .class_init = class_initfn, \ 1800 .parent = TYPE_PNV9_CHIP, \ 1801 } 1802 1803 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 1804 { \ 1805 .name = type, \ 1806 .class_init = class_initfn, \ 1807 .parent = TYPE_PNV10_CHIP, \ 1808 } 1809 1810 static const TypeInfo types[] = { 1811 { 1812 .name = MACHINE_TYPE_NAME("powernv10"), 1813 .parent = TYPE_PNV_MACHINE, 1814 .class_init = pnv_machine_power10_class_init, 1815 }, 1816 { 1817 .name = MACHINE_TYPE_NAME("powernv9"), 1818 .parent = TYPE_PNV_MACHINE, 1819 .class_init = pnv_machine_power9_class_init, 1820 .interfaces = (InterfaceInfo[]) { 1821 { TYPE_XIVE_FABRIC }, 1822 { }, 1823 }, 1824 }, 1825 { 1826 .name = MACHINE_TYPE_NAME("powernv8"), 1827 .parent = TYPE_PNV_MACHINE, 1828 .class_init = pnv_machine_power8_class_init, 1829 .interfaces = (InterfaceInfo[]) { 1830 { TYPE_XICS_FABRIC }, 1831 { }, 1832 }, 1833 }, 1834 { 1835 .name = TYPE_PNV_MACHINE, 1836 .parent = TYPE_MACHINE, 1837 .abstract = true, 1838 .instance_size = sizeof(PnvMachineState), 1839 .instance_init = pnv_machine_instance_init, 1840 .class_init = pnv_machine_class_init, 1841 .class_size = sizeof(PnvMachineClass), 1842 .interfaces = (InterfaceInfo[]) { 1843 { TYPE_INTERRUPT_STATS_PROVIDER }, 1844 { }, 1845 }, 1846 }, 1847 { 1848 .name = TYPE_PNV_CHIP, 1849 .parent = TYPE_SYS_BUS_DEVICE, 1850 .class_init = pnv_chip_class_init, 1851 .instance_size = sizeof(PnvChip), 1852 .class_size = sizeof(PnvChipClass), 1853 .abstract = true, 1854 }, 1855 1856 /* 1857 * P10 chip and variants 1858 */ 1859 { 1860 .name = TYPE_PNV10_CHIP, 1861 .parent = TYPE_PNV_CHIP, 1862 .instance_init = pnv_chip_power10_instance_init, 1863 .instance_size = sizeof(Pnv10Chip), 1864 }, 1865 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 1866 1867 /* 1868 * P9 chip and variants 1869 */ 1870 { 1871 .name = TYPE_PNV9_CHIP, 1872 .parent = TYPE_PNV_CHIP, 1873 .instance_init = pnv_chip_power9_instance_init, 1874 .instance_size = sizeof(Pnv9Chip), 1875 }, 1876 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1877 1878 /* 1879 * P8 chip and variants 1880 */ 1881 { 1882 .name = TYPE_PNV8_CHIP, 1883 .parent = TYPE_PNV_CHIP, 1884 .instance_init = pnv_chip_power8_instance_init, 1885 .instance_size = sizeof(Pnv8Chip), 1886 }, 1887 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1888 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1889 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1890 pnv_chip_power8nvl_class_init), 1891 }; 1892 1893 DEFINE_TYPES(types) 1894