1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qapi/error.h" 22 #include "sysemu/sysemu.h" 23 #include "sysemu/numa.h" 24 #include "sysemu/cpus.h" 25 #include "hw/hw.h" 26 #include "target/ppc/cpu.h" 27 #include "qemu/log.h" 28 #include "hw/ppc/fdt.h" 29 #include "hw/ppc/ppc.h" 30 #include "hw/ppc/pnv.h" 31 #include "hw/ppc/pnv_core.h" 32 #include "hw/loader.h" 33 #include "exec/address-spaces.h" 34 #include "qemu/cutils.h" 35 #include "qapi/visitor.h" 36 #include "monitor/monitor.h" 37 #include "hw/intc/intc.h" 38 #include "hw/ipmi/ipmi.h" 39 40 #include "hw/ppc/xics.h" 41 #include "hw/ppc/pnv_xscom.h" 42 43 #include "hw/isa/isa.h" 44 #include "hw/char/serial.h" 45 #include "hw/timer/mc146818rtc.h" 46 47 #include <libfdt.h> 48 49 #define FDT_MAX_SIZE 0x00100000 50 51 #define FW_FILE_NAME "skiboot.lid" 52 #define FW_LOAD_ADDR 0x0 53 #define FW_MAX_SIZE 0x00400000 54 55 #define KERNEL_LOAD_ADDR 0x20000000 56 #define INITRD_LOAD_ADDR 0x40000000 57 58 static const char *pnv_chip_core_typename(const PnvChip *o) 59 { 60 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 61 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 62 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 63 const char *core_type = object_class_get_name(object_class_by_name(s)); 64 g_free(s); 65 return core_type; 66 } 67 68 /* 69 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 70 * 4 * 4 sockets * 12 cores * 8 threads = 1536 71 * Let's make it 2^11 72 */ 73 #define MAX_CPUS 2048 74 75 /* 76 * Memory nodes are created by hostboot, one for each range of memory 77 * that has a different "affinity". In practice, it means one range 78 * per chip. 79 */ 80 static void powernv_populate_memory_node(void *fdt, int chip_id, hwaddr start, 81 hwaddr size) 82 { 83 char *mem_name; 84 uint64_t mem_reg_property[2]; 85 int off; 86 87 mem_reg_property[0] = cpu_to_be64(start); 88 mem_reg_property[1] = cpu_to_be64(size); 89 90 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 91 off = fdt_add_subnode(fdt, 0, mem_name); 92 g_free(mem_name); 93 94 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 95 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 96 sizeof(mem_reg_property)))); 97 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 98 } 99 100 static int get_cpus_node(void *fdt) 101 { 102 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 103 104 if (cpus_offset < 0) { 105 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 106 if (cpus_offset) { 107 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 108 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 109 } 110 } 111 _FDT(cpus_offset); 112 return cpus_offset; 113 } 114 115 /* 116 * The PowerNV cores (and threads) need to use real HW ids and not an 117 * incremental index like it has been done on other platforms. This HW 118 * id is stored in the CPU PIR, it is used to create cpu nodes in the 119 * device tree, used in XSCOM to address cores and in interrupt 120 * servers. 121 */ 122 static void powernv_create_core_node(PnvChip *chip, PnvCore *pc, void *fdt) 123 { 124 CPUState *cs = CPU(DEVICE(pc->threads)); 125 DeviceClass *dc = DEVICE_GET_CLASS(cs); 126 PowerPCCPU *cpu = POWERPC_CPU(cs); 127 int smt_threads = CPU_CORE(pc)->nr_threads; 128 CPUPPCState *env = &cpu->env; 129 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 130 uint32_t servers_prop[smt_threads]; 131 int i; 132 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 133 0xffffffff, 0xffffffff}; 134 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 135 uint32_t cpufreq = 1000000000; 136 uint32_t page_sizes_prop[64]; 137 size_t page_sizes_prop_size; 138 const uint8_t pa_features[] = { 24, 0, 139 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 140 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 141 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 142 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 143 int offset; 144 char *nodename; 145 int cpus_offset = get_cpus_node(fdt); 146 147 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 148 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 149 _FDT(offset); 150 g_free(nodename); 151 152 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 153 154 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 155 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 156 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 157 158 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 159 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 160 env->dcache_line_size))); 161 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 162 env->dcache_line_size))); 163 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 164 env->icache_line_size))); 165 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 166 env->icache_line_size))); 167 168 if (pcc->l1_dcache_size) { 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 170 pcc->l1_dcache_size))); 171 } else { 172 warn_report("Unknown L1 dcache size for cpu"); 173 } 174 if (pcc->l1_icache_size) { 175 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 176 pcc->l1_icache_size))); 177 } else { 178 warn_report("Unknown L1 icache size for cpu"); 179 } 180 181 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 182 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 183 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", env->slb_nr))); 184 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 185 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 186 187 if (env->spr_cb[SPR_PURR].oea_read) { 188 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 189 } 190 191 if (env->mmu_model & POWERPC_MMU_1TSEG) { 192 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 193 segs, sizeof(segs)))); 194 } 195 196 /* Advertise VMX/VSX (vector extensions) if available 197 * 0 / no property == no vector extensions 198 * 1 == VMX / Altivec available 199 * 2 == VSX available */ 200 if (env->insns_flags & PPC_ALTIVEC) { 201 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 202 203 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 204 } 205 206 /* Advertise DFP (Decimal Floating Point) if available 207 * 0 / no property == no DFP 208 * 1 == DFP available */ 209 if (env->insns_flags2 & PPC2_DFP) { 210 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 211 } 212 213 page_sizes_prop_size = ppc_create_page_sizes_prop(env, page_sizes_prop, 214 sizeof(page_sizes_prop)); 215 if (page_sizes_prop_size) { 216 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 217 page_sizes_prop, page_sizes_prop_size))); 218 } 219 220 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 221 pa_features, sizeof(pa_features)))); 222 223 /* Build interrupt servers properties */ 224 for (i = 0; i < smt_threads; i++) { 225 servers_prop[i] = cpu_to_be32(pc->pir + i); 226 } 227 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 228 servers_prop, sizeof(servers_prop)))); 229 } 230 231 static void powernv_populate_icp(PnvChip *chip, void *fdt, uint32_t pir, 232 uint32_t nr_threads) 233 { 234 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 235 char *name; 236 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 237 uint32_t irange[2], i, rsize; 238 uint64_t *reg; 239 int offset; 240 241 irange[0] = cpu_to_be32(pir); 242 irange[1] = cpu_to_be32(nr_threads); 243 244 rsize = sizeof(uint64_t) * 2 * nr_threads; 245 reg = g_malloc(rsize); 246 for (i = 0; i < nr_threads; i++) { 247 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 248 reg[i * 2 + 1] = cpu_to_be64(0x1000); 249 } 250 251 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 252 offset = fdt_add_subnode(fdt, 0, name); 253 _FDT(offset); 254 g_free(name); 255 256 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 257 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 258 _FDT((fdt_setprop_string(fdt, offset, "device_type", 259 "PowerPC-External-Interrupt-Presentation"))); 260 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 261 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 262 irange, sizeof(irange)))); 263 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 264 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 265 g_free(reg); 266 } 267 268 static int pnv_chip_lpc_offset(PnvChip *chip, void *fdt) 269 { 270 char *name; 271 int offset; 272 273 name = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 274 (uint64_t) PNV_XSCOM_BASE(chip), PNV_XSCOM_LPC_BASE); 275 offset = fdt_path_offset(fdt, name); 276 g_free(name); 277 return offset; 278 } 279 280 static void powernv_populate_chip(PnvChip *chip, void *fdt) 281 { 282 const char *typename = pnv_chip_core_typename(chip); 283 size_t typesize = object_type_get_instance_size(typename); 284 int i; 285 286 pnv_xscom_populate(chip, fdt, 0); 287 288 /* The default LPC bus of a multichip system is on chip 0. It's 289 * recognized by the firmware (skiboot) using a "primary" 290 * property. 291 */ 292 if (chip->chip_id == 0x0) { 293 int lpc_offset = pnv_chip_lpc_offset(chip, fdt); 294 295 _FDT((fdt_setprop(fdt, lpc_offset, "primary", NULL, 0))); 296 } 297 298 for (i = 0; i < chip->nr_cores; i++) { 299 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 300 301 powernv_create_core_node(chip, pnv_core, fdt); 302 303 /* Interrupt Control Presenters (ICP). One per core. */ 304 powernv_populate_icp(chip, fdt, pnv_core->pir, 305 CPU_CORE(pnv_core)->nr_threads); 306 } 307 308 if (chip->ram_size) { 309 powernv_populate_memory_node(fdt, chip->chip_id, chip->ram_start, 310 chip->ram_size); 311 } 312 } 313 314 static void powernv_populate_rtc(ISADevice *d, void *fdt, int lpc_off) 315 { 316 uint32_t io_base = d->ioport_id; 317 uint32_t io_regs[] = { 318 cpu_to_be32(1), 319 cpu_to_be32(io_base), 320 cpu_to_be32(2) 321 }; 322 char *name; 323 int node; 324 325 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 326 node = fdt_add_subnode(fdt, lpc_off, name); 327 _FDT(node); 328 g_free(name); 329 330 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 331 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 332 } 333 334 static void powernv_populate_serial(ISADevice *d, void *fdt, int lpc_off) 335 { 336 const char compatible[] = "ns16550\0pnpPNP,501"; 337 uint32_t io_base = d->ioport_id; 338 uint32_t io_regs[] = { 339 cpu_to_be32(1), 340 cpu_to_be32(io_base), 341 cpu_to_be32(8) 342 }; 343 char *name; 344 int node; 345 346 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 347 node = fdt_add_subnode(fdt, lpc_off, name); 348 _FDT(node); 349 g_free(name); 350 351 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 352 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 353 sizeof(compatible)))); 354 355 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 356 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 357 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 358 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 359 fdt_get_phandle(fdt, lpc_off)))); 360 361 /* This is needed by Linux */ 362 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 363 } 364 365 static void powernv_populate_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 366 { 367 const char compatible[] = "bt\0ipmi-bt"; 368 uint32_t io_base; 369 uint32_t io_regs[] = { 370 cpu_to_be32(1), 371 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 372 cpu_to_be32(3) 373 }; 374 uint32_t irq; 375 char *name; 376 int node; 377 378 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 379 io_regs[1] = cpu_to_be32(io_base); 380 381 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 382 383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 384 node = fdt_add_subnode(fdt, lpc_off, name); 385 _FDT(node); 386 g_free(name); 387 388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 389 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 390 sizeof(compatible)))); 391 392 /* Mark it as reserved to avoid Linux trying to claim it */ 393 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 394 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 395 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 396 fdt_get_phandle(fdt, lpc_off)))); 397 } 398 399 typedef struct ForeachPopulateArgs { 400 void *fdt; 401 int offset; 402 } ForeachPopulateArgs; 403 404 static int powernv_populate_isa_device(DeviceState *dev, void *opaque) 405 { 406 ForeachPopulateArgs *args = opaque; 407 ISADevice *d = ISA_DEVICE(dev); 408 409 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 410 powernv_populate_rtc(d, args->fdt, args->offset); 411 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 412 powernv_populate_serial(d, args->fdt, args->offset); 413 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 414 powernv_populate_ipmi_bt(d, args->fdt, args->offset); 415 } else { 416 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 417 d->ioport_id); 418 } 419 420 return 0; 421 } 422 423 static void powernv_populate_isa(ISABus *bus, void *fdt, int lpc_offset) 424 { 425 ForeachPopulateArgs args = { 426 .fdt = fdt, 427 .offset = lpc_offset, 428 }; 429 430 /* ISA devices are not necessarily parented to the ISA bus so we 431 * can not use object_child_foreach() */ 432 qbus_walk_children(BUS(bus), powernv_populate_isa_device, 433 NULL, NULL, NULL, &args); 434 } 435 436 static void *powernv_create_fdt(MachineState *machine) 437 { 438 const char plat_compat[] = "qemu,powernv\0ibm,powernv"; 439 PnvMachineState *pnv = POWERNV_MACHINE(machine); 440 void *fdt; 441 char *buf; 442 int off; 443 int i; 444 int lpc_offset; 445 446 fdt = g_malloc0(FDT_MAX_SIZE); 447 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 448 449 /* Root node */ 450 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 451 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 452 _FDT((fdt_setprop_string(fdt, 0, "model", 453 "IBM PowerNV (emulated by qemu)"))); 454 _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat, 455 sizeof(plat_compat)))); 456 457 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 458 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 459 if (qemu_uuid_set) { 460 _FDT((fdt_property_string(fdt, "system-id", buf))); 461 } 462 g_free(buf); 463 464 off = fdt_add_subnode(fdt, 0, "chosen"); 465 if (machine->kernel_cmdline) { 466 _FDT((fdt_setprop_string(fdt, off, "bootargs", 467 machine->kernel_cmdline))); 468 } 469 470 if (pnv->initrd_size) { 471 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 472 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 473 474 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 475 &start_prop, sizeof(start_prop)))); 476 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 477 &end_prop, sizeof(end_prop)))); 478 } 479 480 /* Populate device tree for each chip */ 481 for (i = 0; i < pnv->num_chips; i++) { 482 powernv_populate_chip(pnv->chips[i], fdt); 483 } 484 485 /* Populate ISA devices on chip 0 */ 486 lpc_offset = pnv_chip_lpc_offset(pnv->chips[0], fdt); 487 powernv_populate_isa(pnv->isa_bus, fdt, lpc_offset); 488 489 if (pnv->bmc) { 490 pnv_bmc_populate_sensors(pnv->bmc, fdt); 491 } 492 493 return fdt; 494 } 495 496 static void pnv_powerdown_notify(Notifier *n, void *opaque) 497 { 498 PnvMachineState *pnv = POWERNV_MACHINE(qdev_get_machine()); 499 500 if (pnv->bmc) { 501 pnv_bmc_powerdown(pnv->bmc); 502 } 503 } 504 505 static void ppc_powernv_reset(void) 506 { 507 MachineState *machine = MACHINE(qdev_get_machine()); 508 PnvMachineState *pnv = POWERNV_MACHINE(machine); 509 void *fdt; 510 Object *obj; 511 512 qemu_devices_reset(); 513 514 /* OpenPOWER systems have a BMC, which can be defined on the 515 * command line with: 516 * 517 * -device ipmi-bmc-sim,id=bmc0 518 * 519 * This is the internal simulator but it could also be an external 520 * BMC. 521 */ 522 obj = object_resolve_path_type("", "ipmi-bmc-sim", NULL); 523 if (obj) { 524 pnv->bmc = IPMI_BMC(obj); 525 } 526 527 fdt = powernv_create_fdt(machine); 528 529 /* Pack resulting tree */ 530 _FDT((fdt_pack(fdt))); 531 532 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 533 } 534 535 static ISABus *pnv_isa_create(PnvChip *chip) 536 { 537 PnvLpcController *lpc = &chip->lpc; 538 ISABus *isa_bus; 539 qemu_irq *irqs; 540 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 541 542 /* let isa_bus_new() create its own bridge on SysBus otherwise 543 * devices speficied on the command line won't find the bus and 544 * will fail to create. 545 */ 546 isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, 547 &error_fatal); 548 549 irqs = pnv_lpc_isa_irq_create(lpc, pcc->chip_type, ISA_NUM_IRQS); 550 551 isa_bus_irqs(isa_bus, irqs); 552 return isa_bus; 553 } 554 555 static void ppc_powernv_init(MachineState *machine) 556 { 557 PnvMachineState *pnv = POWERNV_MACHINE(machine); 558 MemoryRegion *ram; 559 char *fw_filename; 560 long fw_size; 561 int i; 562 char *chip_typename; 563 564 /* allocate RAM */ 565 if (machine->ram_size < (1 * G_BYTE)) { 566 warn_report("skiboot may not work with < 1GB of RAM"); 567 } 568 569 ram = g_new(MemoryRegion, 1); 570 memory_region_allocate_system_memory(ram, NULL, "ppc_powernv.ram", 571 machine->ram_size); 572 memory_region_add_subregion(get_system_memory(), 0, ram); 573 574 /* load skiboot firmware */ 575 if (bios_name == NULL) { 576 bios_name = FW_FILE_NAME; 577 } 578 579 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 580 if (!fw_filename) { 581 error_report("Could not find OPAL firmware '%s'", bios_name); 582 exit(1); 583 } 584 585 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 586 if (fw_size < 0) { 587 error_report("Could not load OPAL firmware '%s'", fw_filename); 588 exit(1); 589 } 590 g_free(fw_filename); 591 592 /* load kernel */ 593 if (machine->kernel_filename) { 594 long kernel_size; 595 596 kernel_size = load_image_targphys(machine->kernel_filename, 597 KERNEL_LOAD_ADDR, 0x2000000); 598 if (kernel_size < 0) { 599 error_report("Could not load kernel '%s'", 600 machine->kernel_filename); 601 exit(1); 602 } 603 } 604 605 /* load initrd */ 606 if (machine->initrd_filename) { 607 pnv->initrd_base = INITRD_LOAD_ADDR; 608 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 609 pnv->initrd_base, 0x10000000); /* 128MB max */ 610 if (pnv->initrd_size < 0) { 611 error_report("Could not load initial ram disk '%s'", 612 machine->initrd_filename); 613 exit(1); 614 } 615 } 616 617 /* Create the processor chips */ 618 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 619 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 620 i, machine->cpu_type); 621 if (!object_class_by_name(chip_typename)) { 622 error_report("invalid CPU model '%.*s' for %s machine", 623 i, machine->cpu_type, MACHINE_GET_CLASS(machine)->name); 624 exit(1); 625 } 626 627 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 628 for (i = 0; i < pnv->num_chips; i++) { 629 char chip_name[32]; 630 Object *chip = object_new(chip_typename); 631 632 pnv->chips[i] = PNV_CHIP(chip); 633 634 /* TODO: put all the memory in one node on chip 0 until we find a 635 * way to specify different ranges for each chip 636 */ 637 if (i == 0) { 638 object_property_set_int(chip, machine->ram_size, "ram-size", 639 &error_fatal); 640 } 641 642 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 643 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 644 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 645 &error_fatal); 646 object_property_set_int(chip, smp_cores, "nr-cores", &error_fatal); 647 object_property_set_bool(chip, true, "realized", &error_fatal); 648 } 649 g_free(chip_typename); 650 651 /* Instantiate ISA bus on chip 0 */ 652 pnv->isa_bus = pnv_isa_create(pnv->chips[0]); 653 654 /* Create serial port */ 655 serial_hds_isa_init(pnv->isa_bus, 0, MAX_SERIAL_PORTS); 656 657 /* Create an RTC ISA device too */ 658 rtc_init(pnv->isa_bus, 2000, NULL); 659 660 /* OpenPOWER systems use a IPMI SEL Event message to notify the 661 * host to powerdown */ 662 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 663 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 664 } 665 666 /* 667 * 0:21 Reserved - Read as zeros 668 * 22:24 Chip ID 669 * 25:28 Core number 670 * 29:31 Thread ID 671 */ 672 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 673 { 674 return (chip->chip_id << 7) | (core_id << 3); 675 } 676 677 /* 678 * 0:48 Reserved - Read as zeroes 679 * 49:52 Node ID 680 * 53:55 Chip ID 681 * 56 Reserved - Read as zero 682 * 57:61 Core number 683 * 62:63 Thread ID 684 * 685 * We only care about the lower bits. uint32_t is fine for the moment. 686 */ 687 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 688 { 689 return (chip->chip_id << 8) | (core_id << 2); 690 } 691 692 /* Allowed core identifiers on a POWER8 Processor Chip : 693 * 694 * <EX0 reserved> 695 * EX1 - Venice only 696 * EX2 - Venice only 697 * EX3 - Venice only 698 * EX4 699 * EX5 700 * EX6 701 * <EX7,8 reserved> <reserved> 702 * EX9 - Venice only 703 * EX10 - Venice only 704 * EX11 - Venice only 705 * EX12 706 * EX13 707 * EX14 708 * <EX15 reserved> 709 */ 710 #define POWER8E_CORE_MASK (0x7070ull) 711 #define POWER8_CORE_MASK (0x7e7eull) 712 713 /* 714 * POWER9 has 24 cores, ids starting at 0x20 715 */ 716 #define POWER9_CORE_MASK (0xffffff00000000ull) 717 718 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 719 { 720 DeviceClass *dc = DEVICE_CLASS(klass); 721 PnvChipClass *k = PNV_CHIP_CLASS(klass); 722 723 k->chip_type = PNV_CHIP_POWER8E; 724 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 725 k->cores_mask = POWER8E_CORE_MASK; 726 k->core_pir = pnv_chip_core_pir_p8; 727 k->xscom_base = 0x003fc0000000000ull; 728 k->xscom_core_base = 0x10000000ull; 729 dc->desc = "PowerNV Chip POWER8E"; 730 } 731 732 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 733 { 734 DeviceClass *dc = DEVICE_CLASS(klass); 735 PnvChipClass *k = PNV_CHIP_CLASS(klass); 736 737 k->chip_type = PNV_CHIP_POWER8; 738 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 739 k->cores_mask = POWER8_CORE_MASK; 740 k->core_pir = pnv_chip_core_pir_p8; 741 k->xscom_base = 0x003fc0000000000ull; 742 k->xscom_core_base = 0x10000000ull; 743 dc->desc = "PowerNV Chip POWER8"; 744 } 745 746 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 747 { 748 DeviceClass *dc = DEVICE_CLASS(klass); 749 PnvChipClass *k = PNV_CHIP_CLASS(klass); 750 751 k->chip_type = PNV_CHIP_POWER8NVL; 752 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 753 k->cores_mask = POWER8_CORE_MASK; 754 k->core_pir = pnv_chip_core_pir_p8; 755 k->xscom_base = 0x003fc0000000000ull; 756 k->xscom_core_base = 0x10000000ull; 757 dc->desc = "PowerNV Chip POWER8NVL"; 758 } 759 760 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 761 { 762 DeviceClass *dc = DEVICE_CLASS(klass); 763 PnvChipClass *k = PNV_CHIP_CLASS(klass); 764 765 k->chip_type = PNV_CHIP_POWER9; 766 k->chip_cfam_id = 0x100d104980000000ull; /* P9 Nimbus DD1.0 */ 767 k->cores_mask = POWER9_CORE_MASK; 768 k->core_pir = pnv_chip_core_pir_p9; 769 k->xscom_base = 0x00603fc00000000ull; 770 k->xscom_core_base = 0x0ull; 771 dc->desc = "PowerNV Chip POWER9"; 772 } 773 774 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 775 { 776 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 777 int cores_max; 778 779 /* 780 * No custom mask for this chip, let's use the default one from * 781 * the chip class 782 */ 783 if (!chip->cores_mask) { 784 chip->cores_mask = pcc->cores_mask; 785 } 786 787 /* filter alien core ids ! some are reserved */ 788 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 789 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 790 chip->cores_mask); 791 return; 792 } 793 chip->cores_mask &= pcc->cores_mask; 794 795 /* now that we have a sane layout, let check the number of cores */ 796 cores_max = ctpop64(chip->cores_mask); 797 if (chip->nr_cores > cores_max) { 798 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 799 cores_max); 800 return; 801 } 802 } 803 804 static void pnv_chip_init(Object *obj) 805 { 806 PnvChip *chip = PNV_CHIP(obj); 807 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 808 809 chip->xscom_base = pcc->xscom_base; 810 811 object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC); 812 object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL); 813 814 object_initialize(&chip->psi, sizeof(chip->psi), TYPE_PNV_PSI); 815 object_property_add_child(obj, "psi", OBJECT(&chip->psi), NULL); 816 object_property_add_const_link(OBJECT(&chip->psi), "xics", 817 OBJECT(qdev_get_machine()), &error_abort); 818 819 object_initialize(&chip->occ, sizeof(chip->occ), TYPE_PNV_OCC); 820 object_property_add_child(obj, "occ", OBJECT(&chip->occ), NULL); 821 object_property_add_const_link(OBJECT(&chip->occ), "psi", 822 OBJECT(&chip->psi), &error_abort); 823 824 /* The LPC controller needs PSI to generate interrupts */ 825 object_property_add_const_link(OBJECT(&chip->lpc), "psi", 826 OBJECT(&chip->psi), &error_abort); 827 } 828 829 static void pnv_chip_icp_realize(PnvChip *chip, Error **errp) 830 { 831 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 832 const char *typename = pnv_chip_core_typename(chip); 833 size_t typesize = object_type_get_instance_size(typename); 834 int i, j; 835 char *name; 836 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 837 838 name = g_strdup_printf("icp-%x", chip->chip_id); 839 memory_region_init(&chip->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 840 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip->icp_mmio); 841 g_free(name); 842 843 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 844 845 /* Map the ICP registers for each thread */ 846 for (i = 0; i < chip->nr_cores; i++) { 847 PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize); 848 int core_hwid = CPU_CORE(pnv_core)->core_id; 849 850 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 851 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 852 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 853 854 memory_region_add_subregion(&chip->icp_mmio, pir << 12, &icp->mmio); 855 } 856 } 857 } 858 859 static void pnv_chip_realize(DeviceState *dev, Error **errp) 860 { 861 PnvChip *chip = PNV_CHIP(dev); 862 Error *error = NULL; 863 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 864 const char *typename = pnv_chip_core_typename(chip); 865 size_t typesize = object_type_get_instance_size(typename); 866 int i, core_hwid; 867 868 if (!object_class_by_name(typename)) { 869 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 870 return; 871 } 872 873 /* XSCOM bridge */ 874 pnv_xscom_realize(chip, &error); 875 if (error) { 876 error_propagate(errp, error); 877 return; 878 } 879 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 880 881 /* Cores */ 882 pnv_chip_core_sanitize(chip, &error); 883 if (error) { 884 error_propagate(errp, error); 885 return; 886 } 887 888 chip->cores = g_malloc0(typesize * chip->nr_cores); 889 890 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 891 && (i < chip->nr_cores); core_hwid++) { 892 char core_name[32]; 893 void *pnv_core = chip->cores + i * typesize; 894 895 if (!(chip->cores_mask & (1ull << core_hwid))) { 896 continue; 897 } 898 899 object_initialize(pnv_core, typesize, typename); 900 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 901 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 902 &error_fatal); 903 object_property_set_int(OBJECT(pnv_core), smp_threads, "nr-threads", 904 &error_fatal); 905 object_property_set_int(OBJECT(pnv_core), core_hwid, 906 CPU_CORE_PROP_CORE_ID, &error_fatal); 907 object_property_set_int(OBJECT(pnv_core), 908 pcc->core_pir(chip, core_hwid), 909 "pir", &error_fatal); 910 object_property_add_const_link(OBJECT(pnv_core), "xics", 911 qdev_get_machine(), &error_fatal); 912 object_property_set_bool(OBJECT(pnv_core), true, "realized", 913 &error_fatal); 914 object_unref(OBJECT(pnv_core)); 915 916 /* Each core has an XSCOM MMIO region */ 917 pnv_xscom_add_subregion(chip, 918 PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base, 919 core_hwid), 920 &PNV_CORE(pnv_core)->xscom_regs); 921 i++; 922 } 923 924 /* Create LPC controller */ 925 object_property_set_bool(OBJECT(&chip->lpc), true, "realized", 926 &error_fatal); 927 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip->lpc.xscom_regs); 928 929 /* Interrupt Management Area. This is the memory region holding 930 * all the Interrupt Control Presenter (ICP) registers */ 931 pnv_chip_icp_realize(chip, &error); 932 if (error) { 933 error_propagate(errp, error); 934 return; 935 } 936 937 /* Processor Service Interface (PSI) Host Bridge */ 938 object_property_set_int(OBJECT(&chip->psi), PNV_PSIHB_BASE(chip), 939 "bar", &error_fatal); 940 object_property_set_bool(OBJECT(&chip->psi), true, "realized", &error); 941 if (error) { 942 error_propagate(errp, error); 943 return; 944 } 945 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, &chip->psi.xscom_regs); 946 947 /* Create the simplified OCC model */ 948 object_property_set_bool(OBJECT(&chip->occ), true, "realized", &error); 949 if (error) { 950 error_propagate(errp, error); 951 return; 952 } 953 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip->occ.xscom_regs); 954 } 955 956 static Property pnv_chip_properties[] = { 957 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 958 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 959 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 960 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 961 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 962 DEFINE_PROP_END_OF_LIST(), 963 }; 964 965 static void pnv_chip_class_init(ObjectClass *klass, void *data) 966 { 967 DeviceClass *dc = DEVICE_CLASS(klass); 968 969 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 970 dc->realize = pnv_chip_realize; 971 dc->props = pnv_chip_properties; 972 dc->desc = "PowerNV Chip"; 973 } 974 975 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 976 { 977 PnvMachineState *pnv = POWERNV_MACHINE(xi); 978 int i; 979 980 for (i = 0; i < pnv->num_chips; i++) { 981 if (ics_valid_irq(&pnv->chips[i]->psi.ics, irq)) { 982 return &pnv->chips[i]->psi.ics; 983 } 984 } 985 return NULL; 986 } 987 988 static void pnv_ics_resend(XICSFabric *xi) 989 { 990 PnvMachineState *pnv = POWERNV_MACHINE(xi); 991 int i; 992 993 for (i = 0; i < pnv->num_chips; i++) { 994 ics_resend(&pnv->chips[i]->psi.ics); 995 } 996 } 997 998 static PowerPCCPU *ppc_get_vcpu_by_pir(int pir) 999 { 1000 CPUState *cs; 1001 1002 CPU_FOREACH(cs) { 1003 PowerPCCPU *cpu = POWERPC_CPU(cs); 1004 CPUPPCState *env = &cpu->env; 1005 1006 if (env->spr_cb[SPR_PIR].default_value == pir) { 1007 return cpu; 1008 } 1009 } 1010 1011 return NULL; 1012 } 1013 1014 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1015 { 1016 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1017 1018 return cpu ? ICP(cpu->intc) : NULL; 1019 } 1020 1021 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1022 Monitor *mon) 1023 { 1024 PnvMachineState *pnv = POWERNV_MACHINE(obj); 1025 int i; 1026 CPUState *cs; 1027 1028 CPU_FOREACH(cs) { 1029 PowerPCCPU *cpu = POWERPC_CPU(cs); 1030 1031 icp_pic_print_info(ICP(cpu->intc), mon); 1032 } 1033 1034 for (i = 0; i < pnv->num_chips; i++) { 1035 ics_pic_print_info(&pnv->chips[i]->psi.ics, mon); 1036 } 1037 } 1038 1039 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1040 void *opaque, Error **errp) 1041 { 1042 visit_type_uint32(v, name, &POWERNV_MACHINE(obj)->num_chips, errp); 1043 } 1044 1045 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1046 void *opaque, Error **errp) 1047 { 1048 PnvMachineState *pnv = POWERNV_MACHINE(obj); 1049 uint32_t num_chips; 1050 Error *local_err = NULL; 1051 1052 visit_type_uint32(v, name, &num_chips, &local_err); 1053 if (local_err) { 1054 error_propagate(errp, local_err); 1055 return; 1056 } 1057 1058 /* 1059 * TODO: should we decide on how many chips we can create based 1060 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1061 */ 1062 if (!is_power_of_2(num_chips) || num_chips > 4) { 1063 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1064 return; 1065 } 1066 1067 pnv->num_chips = num_chips; 1068 } 1069 1070 static void powernv_machine_initfn(Object *obj) 1071 { 1072 PnvMachineState *pnv = POWERNV_MACHINE(obj); 1073 pnv->num_chips = 1; 1074 } 1075 1076 static void powernv_machine_class_props_init(ObjectClass *oc) 1077 { 1078 object_class_property_add(oc, "num-chips", "uint32", 1079 pnv_get_num_chips, pnv_set_num_chips, 1080 NULL, NULL, NULL); 1081 object_class_property_set_description(oc, "num-chips", 1082 "Specifies the number of processor chips", 1083 NULL); 1084 } 1085 1086 static void powernv_machine_class_init(ObjectClass *oc, void *data) 1087 { 1088 MachineClass *mc = MACHINE_CLASS(oc); 1089 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1090 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1091 1092 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1093 mc->init = ppc_powernv_init; 1094 mc->reset = ppc_powernv_reset; 1095 mc->max_cpus = MAX_CPUS; 1096 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1097 mc->block_default_type = IF_IDE; /* Pnv provides a AHCI device for 1098 * storage */ 1099 mc->no_parallel = 1; 1100 mc->default_boot_order = NULL; 1101 mc->default_ram_size = 1 * G_BYTE; 1102 xic->icp_get = pnv_icp_get; 1103 xic->ics_get = pnv_ics_get; 1104 xic->ics_resend = pnv_ics_resend; 1105 ispc->print_info = pnv_pic_print_info; 1106 1107 powernv_machine_class_props_init(oc); 1108 } 1109 1110 #define DEFINE_PNV_CHIP_TYPE(type, class_initfn) \ 1111 { \ 1112 .name = type, \ 1113 .class_init = class_initfn, \ 1114 .parent = TYPE_PNV_CHIP, \ 1115 } 1116 1117 static const TypeInfo types[] = { 1118 { 1119 .name = TYPE_POWERNV_MACHINE, 1120 .parent = TYPE_MACHINE, 1121 .instance_size = sizeof(PnvMachineState), 1122 .instance_init = powernv_machine_initfn, 1123 .class_init = powernv_machine_class_init, 1124 .interfaces = (InterfaceInfo[]) { 1125 { TYPE_XICS_FABRIC }, 1126 { TYPE_INTERRUPT_STATS_PROVIDER }, 1127 { }, 1128 }, 1129 }, 1130 { 1131 .name = TYPE_PNV_CHIP, 1132 .parent = TYPE_SYS_BUS_DEVICE, 1133 .class_init = pnv_chip_class_init, 1134 .instance_init = pnv_chip_init, 1135 .instance_size = sizeof(PnvChip), 1136 .class_size = sizeof(PnvChipClass), 1137 .abstract = true, 1138 }, 1139 DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1140 DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1141 DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1142 DEFINE_PNV_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1143 pnv_chip_power8nvl_class_init), 1144 }; 1145 1146 DEFINE_TYPES(types) 1147