1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 44 #include "hw/ppc/xics.h" 45 #include "hw/qdev-properties.h" 46 #include "hw/ppc/pnv_xscom.h" 47 #include "hw/ppc/pnv_pnor.h" 48 49 #include "hw/isa/isa.h" 50 #include "hw/boards.h" 51 #include "hw/char/serial.h" 52 #include "hw/rtc/mc146818rtc.h" 53 54 #include <libfdt.h> 55 56 #define FDT_MAX_SIZE (1 * MiB) 57 58 #define FW_FILE_NAME "skiboot.lid" 59 #define FW_LOAD_ADDR 0x0 60 #define FW_MAX_SIZE (4 * MiB) 61 62 #define KERNEL_LOAD_ADDR 0x20000000 63 #define KERNEL_MAX_SIZE (256 * MiB) 64 #define INITRD_LOAD_ADDR 0x60000000 65 #define INITRD_MAX_SIZE (256 * MiB) 66 67 static const char *pnv_chip_core_typename(const PnvChip *o) 68 { 69 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 70 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 71 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 72 const char *core_type = object_class_get_name(object_class_by_name(s)); 73 g_free(s); 74 return core_type; 75 } 76 77 /* 78 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 79 * 4 * 4 sockets * 12 cores * 8 threads = 1536 80 * Let's make it 2^11 81 */ 82 #define MAX_CPUS 2048 83 84 /* 85 * Memory nodes are created by hostboot, one for each range of memory 86 * that has a different "affinity". In practice, it means one range 87 * per chip. 88 */ 89 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 90 { 91 char *mem_name; 92 uint64_t mem_reg_property[2]; 93 int off; 94 95 mem_reg_property[0] = cpu_to_be64(start); 96 mem_reg_property[1] = cpu_to_be64(size); 97 98 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 99 off = fdt_add_subnode(fdt, 0, mem_name); 100 g_free(mem_name); 101 102 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 103 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 104 sizeof(mem_reg_property)))); 105 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 106 } 107 108 static int get_cpus_node(void *fdt) 109 { 110 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 111 112 if (cpus_offset < 0) { 113 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 114 if (cpus_offset) { 115 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 117 } 118 } 119 _FDT(cpus_offset); 120 return cpus_offset; 121 } 122 123 /* 124 * The PowerNV cores (and threads) need to use real HW ids and not an 125 * incremental index like it has been done on other platforms. This HW 126 * id is stored in the CPU PIR, it is used to create cpu nodes in the 127 * device tree, used in XSCOM to address cores and in interrupt 128 * servers. 129 */ 130 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 131 { 132 PowerPCCPU *cpu = pc->threads[0]; 133 CPUState *cs = CPU(cpu); 134 DeviceClass *dc = DEVICE_GET_CLASS(cs); 135 int smt_threads = CPU_CORE(pc)->nr_threads; 136 CPUPPCState *env = &cpu->env; 137 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 138 uint32_t servers_prop[smt_threads]; 139 int i; 140 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 141 0xffffffff, 0xffffffff}; 142 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 143 uint32_t cpufreq = 1000000000; 144 uint32_t page_sizes_prop[64]; 145 size_t page_sizes_prop_size; 146 const uint8_t pa_features[] = { 24, 0, 147 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 148 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 150 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 151 int offset; 152 char *nodename; 153 int cpus_offset = get_cpus_node(fdt); 154 155 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 156 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 157 _FDT(offset); 158 g_free(nodename); 159 160 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 161 162 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 164 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 167 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 168 env->dcache_line_size))); 169 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 170 env->dcache_line_size))); 171 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 172 env->icache_line_size))); 173 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 174 env->icache_line_size))); 175 176 if (pcc->l1_dcache_size) { 177 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 178 pcc->l1_dcache_size))); 179 } else { 180 warn_report("Unknown L1 dcache size for cpu"); 181 } 182 if (pcc->l1_icache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 184 pcc->l1_icache_size))); 185 } else { 186 warn_report("Unknown L1 icache size for cpu"); 187 } 188 189 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 190 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 192 cpu->hash64_opts->slb_size))); 193 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 194 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 195 196 if (env->spr_cb[SPR_PURR].oea_read) { 197 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 198 } 199 200 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 201 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 202 segs, sizeof(segs)))); 203 } 204 205 /* 206 * Advertise VMX/VSX (vector extensions) if available 207 * 0 / no property == no vector extensions 208 * 1 == VMX / Altivec available 209 * 2 == VSX available 210 */ 211 if (env->insns_flags & PPC_ALTIVEC) { 212 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 213 214 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 215 } 216 217 /* 218 * Advertise DFP (Decimal Floating Point) if available 219 * 0 / no property == no DFP 220 * 1 == DFP available 221 */ 222 if (env->insns_flags2 & PPC2_DFP) { 223 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 224 } 225 226 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 227 sizeof(page_sizes_prop)); 228 if (page_sizes_prop_size) { 229 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 230 page_sizes_prop, page_sizes_prop_size))); 231 } 232 233 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 234 pa_features, sizeof(pa_features)))); 235 236 /* Build interrupt servers properties */ 237 for (i = 0; i < smt_threads; i++) { 238 servers_prop[i] = cpu_to_be32(pc->pir + i); 239 } 240 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 241 servers_prop, sizeof(servers_prop)))); 242 } 243 244 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 245 uint32_t nr_threads) 246 { 247 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 248 char *name; 249 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 250 uint32_t irange[2], i, rsize; 251 uint64_t *reg; 252 int offset; 253 254 irange[0] = cpu_to_be32(pir); 255 irange[1] = cpu_to_be32(nr_threads); 256 257 rsize = sizeof(uint64_t) * 2 * nr_threads; 258 reg = g_malloc(rsize); 259 for (i = 0; i < nr_threads; i++) { 260 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 261 reg[i * 2 + 1] = cpu_to_be64(0x1000); 262 } 263 264 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 265 offset = fdt_add_subnode(fdt, 0, name); 266 _FDT(offset); 267 g_free(name); 268 269 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 270 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 271 _FDT((fdt_setprop_string(fdt, offset, "device_type", 272 "PowerPC-External-Interrupt-Presentation"))); 273 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 274 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 275 irange, sizeof(irange)))); 276 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 278 g_free(reg); 279 } 280 281 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 282 { 283 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 284 int i; 285 286 pnv_dt_xscom(chip, fdt, 0, 287 cpu_to_be64(PNV_XSCOM_BASE(chip)), 288 cpu_to_be64(PNV_XSCOM_SIZE), 289 compat, sizeof(compat)); 290 291 for (i = 0; i < chip->nr_cores; i++) { 292 PnvCore *pnv_core = chip->cores[i]; 293 294 pnv_dt_core(chip, pnv_core, fdt); 295 296 /* Interrupt Control Presenters (ICP). One per core. */ 297 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 298 } 299 300 if (chip->ram_size) { 301 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 302 } 303 } 304 305 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 306 { 307 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 308 int i; 309 310 pnv_dt_xscom(chip, fdt, 0, 311 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 312 cpu_to_be64(PNV9_XSCOM_SIZE), 313 compat, sizeof(compat)); 314 315 for (i = 0; i < chip->nr_cores; i++) { 316 PnvCore *pnv_core = chip->cores[i]; 317 318 pnv_dt_core(chip, pnv_core, fdt); 319 } 320 321 if (chip->ram_size) { 322 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 323 } 324 325 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 326 } 327 328 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 329 { 330 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 331 int i; 332 333 pnv_dt_xscom(chip, fdt, 0, 334 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 335 cpu_to_be64(PNV10_XSCOM_SIZE), 336 compat, sizeof(compat)); 337 338 for (i = 0; i < chip->nr_cores; i++) { 339 PnvCore *pnv_core = chip->cores[i]; 340 341 pnv_dt_core(chip, pnv_core, fdt); 342 } 343 344 if (chip->ram_size) { 345 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 346 } 347 348 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 349 } 350 351 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 352 { 353 uint32_t io_base = d->ioport_id; 354 uint32_t io_regs[] = { 355 cpu_to_be32(1), 356 cpu_to_be32(io_base), 357 cpu_to_be32(2) 358 }; 359 char *name; 360 int node; 361 362 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 363 node = fdt_add_subnode(fdt, lpc_off, name); 364 _FDT(node); 365 g_free(name); 366 367 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 368 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 369 } 370 371 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 372 { 373 const char compatible[] = "ns16550\0pnpPNP,501"; 374 uint32_t io_base = d->ioport_id; 375 uint32_t io_regs[] = { 376 cpu_to_be32(1), 377 cpu_to_be32(io_base), 378 cpu_to_be32(8) 379 }; 380 char *name; 381 int node; 382 383 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 384 node = fdt_add_subnode(fdt, lpc_off, name); 385 _FDT(node); 386 g_free(name); 387 388 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 389 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 390 sizeof(compatible)))); 391 392 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 393 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 394 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 395 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 396 fdt_get_phandle(fdt, lpc_off)))); 397 398 /* This is needed by Linux */ 399 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 400 } 401 402 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 403 { 404 const char compatible[] = "bt\0ipmi-bt"; 405 uint32_t io_base; 406 uint32_t io_regs[] = { 407 cpu_to_be32(1), 408 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 409 cpu_to_be32(3) 410 }; 411 uint32_t irq; 412 char *name; 413 int node; 414 415 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 416 io_regs[1] = cpu_to_be32(io_base); 417 418 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 419 420 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 421 node = fdt_add_subnode(fdt, lpc_off, name); 422 _FDT(node); 423 g_free(name); 424 425 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 426 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 427 sizeof(compatible)))); 428 429 /* Mark it as reserved to avoid Linux trying to claim it */ 430 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 431 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 432 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 433 fdt_get_phandle(fdt, lpc_off)))); 434 } 435 436 typedef struct ForeachPopulateArgs { 437 void *fdt; 438 int offset; 439 } ForeachPopulateArgs; 440 441 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 442 { 443 ForeachPopulateArgs *args = opaque; 444 ISADevice *d = ISA_DEVICE(dev); 445 446 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 447 pnv_dt_rtc(d, args->fdt, args->offset); 448 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 449 pnv_dt_serial(d, args->fdt, args->offset); 450 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 451 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 452 } else { 453 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 454 d->ioport_id); 455 } 456 457 return 0; 458 } 459 460 /* 461 * The default LPC bus of a multichip system is on chip 0. It's 462 * recognized by the firmware (skiboot) using a "primary" property. 463 */ 464 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 465 { 466 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 467 ForeachPopulateArgs args = { 468 .fdt = fdt, 469 .offset = isa_offset, 470 }; 471 uint32_t phandle; 472 473 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 474 475 phandle = qemu_fdt_alloc_phandle(fdt); 476 assert(phandle > 0); 477 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 478 479 /* 480 * ISA devices are not necessarily parented to the ISA bus so we 481 * can not use object_child_foreach() 482 */ 483 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 484 &args); 485 } 486 487 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 488 { 489 int off; 490 491 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 492 off = fdt_add_subnode(fdt, off, "power-mgt"); 493 494 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 495 } 496 497 static void *pnv_dt_create(MachineState *machine) 498 { 499 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 500 PnvMachineState *pnv = PNV_MACHINE(machine); 501 void *fdt; 502 char *buf; 503 int off; 504 int i; 505 506 fdt = g_malloc0(FDT_MAX_SIZE); 507 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 508 509 /* /qemu node */ 510 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 511 512 /* Root node */ 513 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 514 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 515 _FDT((fdt_setprop_string(fdt, 0, "model", 516 "IBM PowerNV (emulated by qemu)"))); 517 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 518 519 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 520 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 521 if (qemu_uuid_set) { 522 _FDT((fdt_property_string(fdt, "system-id", buf))); 523 } 524 g_free(buf); 525 526 off = fdt_add_subnode(fdt, 0, "chosen"); 527 if (machine->kernel_cmdline) { 528 _FDT((fdt_setprop_string(fdt, off, "bootargs", 529 machine->kernel_cmdline))); 530 } 531 532 if (pnv->initrd_size) { 533 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 534 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 535 536 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 537 &start_prop, sizeof(start_prop)))); 538 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 539 &end_prop, sizeof(end_prop)))); 540 } 541 542 /* Populate device tree for each chip */ 543 for (i = 0; i < pnv->num_chips; i++) { 544 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 545 } 546 547 /* Populate ISA devices on chip 0 */ 548 pnv_dt_isa(pnv, fdt); 549 550 if (pnv->bmc) { 551 pnv_dt_bmc_sensors(pnv->bmc, fdt); 552 } 553 554 /* Create an extra node for power management on machines that support it */ 555 if (pmc->dt_power_mgt) { 556 pmc->dt_power_mgt(pnv, fdt); 557 } 558 559 return fdt; 560 } 561 562 static void pnv_powerdown_notify(Notifier *n, void *opaque) 563 { 564 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 565 566 if (pnv->bmc) { 567 pnv_bmc_powerdown(pnv->bmc); 568 } 569 } 570 571 static void pnv_reset(MachineState *machine) 572 { 573 void *fdt; 574 575 qemu_devices_reset(); 576 577 fdt = pnv_dt_create(machine); 578 579 /* Pack resulting tree */ 580 _FDT((fdt_pack(fdt))); 581 582 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 583 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 584 } 585 586 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 587 { 588 Pnv8Chip *chip8 = PNV8_CHIP(chip); 589 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 590 } 591 592 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 593 { 594 Pnv8Chip *chip8 = PNV8_CHIP(chip); 595 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 596 } 597 598 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 599 { 600 Pnv9Chip *chip9 = PNV9_CHIP(chip); 601 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 602 } 603 604 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 605 { 606 Pnv10Chip *chip10 = PNV10_CHIP(chip); 607 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 608 } 609 610 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 611 { 612 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 613 } 614 615 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 616 { 617 Pnv8Chip *chip8 = PNV8_CHIP(chip); 618 619 ics_pic_print_info(&chip8->psi.ics, mon); 620 } 621 622 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 623 { 624 Pnv9Chip *chip9 = PNV9_CHIP(chip); 625 626 pnv_xive_pic_print_info(&chip9->xive, mon); 627 pnv_psi_pic_print_info(&chip9->psi, mon); 628 } 629 630 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 631 uint32_t core_id) 632 { 633 return PNV_XSCOM_EX_BASE(core_id); 634 } 635 636 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 637 uint32_t core_id) 638 { 639 return PNV9_XSCOM_EC_BASE(core_id); 640 } 641 642 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 643 uint32_t core_id) 644 { 645 return PNV10_XSCOM_EC_BASE(core_id); 646 } 647 648 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 649 { 650 PowerPCCPUClass *ppc_default = 651 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 652 PowerPCCPUClass *ppc = 653 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 654 655 return ppc_default->pvr_match(ppc_default, ppc->pvr); 656 } 657 658 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 659 { 660 Object *obj; 661 662 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 663 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 664 object_property_set_int(obj, irq, "irq", &error_fatal); 665 object_property_set_bool(obj, true, "realized", &error_fatal); 666 } 667 668 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 669 { 670 Pnv10Chip *chip10 = PNV10_CHIP(chip); 671 672 pnv_psi_pic_print_info(&chip10->psi, mon); 673 } 674 675 static void pnv_init(MachineState *machine) 676 { 677 PnvMachineState *pnv = PNV_MACHINE(machine); 678 MachineClass *mc = MACHINE_GET_CLASS(machine); 679 MemoryRegion *ram; 680 char *fw_filename; 681 long fw_size; 682 int i; 683 char *chip_typename; 684 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 685 DeviceState *dev; 686 687 /* allocate RAM */ 688 if (machine->ram_size < (1 * GiB)) { 689 warn_report("skiboot may not work with < 1GB of RAM"); 690 } 691 692 ram = g_new(MemoryRegion, 1); 693 memory_region_allocate_system_memory(ram, NULL, "pnv.ram", 694 machine->ram_size); 695 memory_region_add_subregion(get_system_memory(), 0, ram); 696 697 /* 698 * Create our simple PNOR device 699 */ 700 dev = qdev_create(NULL, TYPE_PNV_PNOR); 701 if (pnor) { 702 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 703 &error_abort); 704 } 705 qdev_init_nofail(dev); 706 pnv->pnor = PNV_PNOR(dev); 707 708 /* load skiboot firmware */ 709 if (bios_name == NULL) { 710 bios_name = FW_FILE_NAME; 711 } 712 713 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 714 if (!fw_filename) { 715 error_report("Could not find OPAL firmware '%s'", bios_name); 716 exit(1); 717 } 718 719 fw_size = load_image_targphys(fw_filename, FW_LOAD_ADDR, FW_MAX_SIZE); 720 if (fw_size < 0) { 721 error_report("Could not load OPAL firmware '%s'", fw_filename); 722 exit(1); 723 } 724 g_free(fw_filename); 725 726 /* load kernel */ 727 if (machine->kernel_filename) { 728 long kernel_size; 729 730 kernel_size = load_image_targphys(machine->kernel_filename, 731 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 732 if (kernel_size < 0) { 733 error_report("Could not load kernel '%s'", 734 machine->kernel_filename); 735 exit(1); 736 } 737 } 738 739 /* load initrd */ 740 if (machine->initrd_filename) { 741 pnv->initrd_base = INITRD_LOAD_ADDR; 742 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 743 pnv->initrd_base, INITRD_MAX_SIZE); 744 if (pnv->initrd_size < 0) { 745 error_report("Could not load initial ram disk '%s'", 746 machine->initrd_filename); 747 exit(1); 748 } 749 } 750 751 /* 752 * Check compatibility of the specified CPU with the machine 753 * default. 754 */ 755 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 756 error_report("invalid CPU model '%s' for %s machine", 757 machine->cpu_type, mc->name); 758 exit(1); 759 } 760 761 /* Create the processor chips */ 762 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 763 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 764 i, machine->cpu_type); 765 if (!object_class_by_name(chip_typename)) { 766 error_report("invalid chip model '%.*s' for %s machine", 767 i, machine->cpu_type, mc->name); 768 exit(1); 769 } 770 771 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 772 for (i = 0; i < pnv->num_chips; i++) { 773 char chip_name[32]; 774 Object *chip = object_new(chip_typename); 775 776 pnv->chips[i] = PNV_CHIP(chip); 777 778 /* 779 * TODO: put all the memory in one node on chip 0 until we find a 780 * way to specify different ranges for each chip 781 */ 782 if (i == 0) { 783 object_property_set_int(chip, machine->ram_size, "ram-size", 784 &error_fatal); 785 } 786 787 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 788 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 789 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 790 &error_fatal); 791 object_property_set_int(chip, machine->smp.cores, 792 "nr-cores", &error_fatal); 793 object_property_set_bool(chip, true, "realized", &error_fatal); 794 } 795 g_free(chip_typename); 796 797 /* Create the machine BMC simulator */ 798 pnv->bmc = pnv_bmc_create(); 799 800 /* Instantiate ISA bus on chip 0 */ 801 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 802 803 /* Create serial port */ 804 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 805 806 /* Create an RTC ISA device too */ 807 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 808 809 /* Create the IPMI BT device for communication with the BMC */ 810 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 811 812 /* 813 * OpenPOWER systems use a IPMI SEL Event message to notify the 814 * host to powerdown 815 */ 816 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 817 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 818 } 819 820 /* 821 * 0:21 Reserved - Read as zeros 822 * 22:24 Chip ID 823 * 25:28 Core number 824 * 29:31 Thread ID 825 */ 826 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 827 { 828 return (chip->chip_id << 7) | (core_id << 3); 829 } 830 831 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 832 Error **errp) 833 { 834 Error *local_err = NULL; 835 Object *obj; 836 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 837 838 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), 839 &local_err); 840 if (local_err) { 841 error_propagate(errp, local_err); 842 return; 843 } 844 845 pnv_cpu->intc = obj; 846 } 847 848 849 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 850 { 851 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 852 853 icp_reset(ICP(pnv_cpu->intc)); 854 } 855 856 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 857 { 858 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 859 860 icp_destroy(ICP(pnv_cpu->intc)); 861 pnv_cpu->intc = NULL; 862 } 863 864 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 865 Monitor *mon) 866 { 867 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 868 } 869 870 /* 871 * 0:48 Reserved - Read as zeroes 872 * 49:52 Node ID 873 * 53:55 Chip ID 874 * 56 Reserved - Read as zero 875 * 57:61 Core number 876 * 62:63 Thread ID 877 * 878 * We only care about the lower bits. uint32_t is fine for the moment. 879 */ 880 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 881 { 882 return (chip->chip_id << 8) | (core_id << 2); 883 } 884 885 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 886 { 887 return (chip->chip_id << 8) | (core_id << 2); 888 } 889 890 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 891 Error **errp) 892 { 893 Pnv9Chip *chip9 = PNV9_CHIP(chip); 894 Error *local_err = NULL; 895 Object *obj; 896 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 897 898 /* 899 * The core creates its interrupt presenter but the XIVE interrupt 900 * controller object is initialized afterwards. Hopefully, it's 901 * only used at runtime. 902 */ 903 obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); 904 if (local_err) { 905 error_propagate(errp, local_err); 906 return; 907 } 908 909 pnv_cpu->intc = obj; 910 } 911 912 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 913 { 914 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 915 916 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 917 } 918 919 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 920 { 921 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 922 923 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 924 pnv_cpu->intc = NULL; 925 } 926 927 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 928 Monitor *mon) 929 { 930 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 931 } 932 933 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 934 Error **errp) 935 { 936 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 937 938 /* Will be defined when the interrupt controller is */ 939 pnv_cpu->intc = NULL; 940 } 941 942 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 943 { 944 ; 945 } 946 947 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 948 { 949 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 950 951 pnv_cpu->intc = NULL; 952 } 953 954 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 955 Monitor *mon) 956 { 957 } 958 959 /* 960 * Allowed core identifiers on a POWER8 Processor Chip : 961 * 962 * <EX0 reserved> 963 * EX1 - Venice only 964 * EX2 - Venice only 965 * EX3 - Venice only 966 * EX4 967 * EX5 968 * EX6 969 * <EX7,8 reserved> <reserved> 970 * EX9 - Venice only 971 * EX10 - Venice only 972 * EX11 - Venice only 973 * EX12 974 * EX13 975 * EX14 976 * <EX15 reserved> 977 */ 978 #define POWER8E_CORE_MASK (0x7070ull) 979 #define POWER8_CORE_MASK (0x7e7eull) 980 981 /* 982 * POWER9 has 24 cores, ids starting at 0x0 983 */ 984 #define POWER9_CORE_MASK (0xffffffffffffffull) 985 986 987 #define POWER10_CORE_MASK (0xffffffffffffffull) 988 989 static void pnv_chip_power8_instance_init(Object *obj) 990 { 991 Pnv8Chip *chip8 = PNV8_CHIP(obj); 992 993 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 994 TYPE_PNV8_PSI, &error_abort, NULL); 995 object_property_add_const_link(OBJECT(&chip8->psi), "xics", 996 OBJECT(qdev_get_machine()), &error_abort); 997 998 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 999 TYPE_PNV8_LPC, &error_abort, NULL); 1000 1001 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 1002 TYPE_PNV8_OCC, &error_abort, NULL); 1003 1004 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 1005 TYPE_PNV8_HOMER, &error_abort, NULL); 1006 } 1007 1008 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1009 { 1010 PnvChip *chip = PNV_CHIP(chip8); 1011 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1012 int i, j; 1013 char *name; 1014 XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); 1015 1016 name = g_strdup_printf("icp-%x", chip->chip_id); 1017 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1018 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1019 g_free(name); 1020 1021 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1022 1023 /* Map the ICP registers for each thread */ 1024 for (i = 0; i < chip->nr_cores; i++) { 1025 PnvCore *pnv_core = chip->cores[i]; 1026 int core_hwid = CPU_CORE(pnv_core)->core_id; 1027 1028 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1029 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1030 PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); 1031 1032 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1033 &icp->mmio); 1034 } 1035 } 1036 } 1037 1038 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1039 { 1040 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1041 PnvChip *chip = PNV_CHIP(dev); 1042 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1043 Pnv8Psi *psi8 = &chip8->psi; 1044 Error *local_err = NULL; 1045 1046 /* XSCOM bridge is first */ 1047 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1048 if (local_err) { 1049 error_propagate(errp, local_err); 1050 return; 1051 } 1052 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1053 1054 pcc->parent_realize(dev, &local_err); 1055 if (local_err) { 1056 error_propagate(errp, local_err); 1057 return; 1058 } 1059 1060 /* Processor Service Interface (PSI) Host Bridge */ 1061 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1062 "bar", &error_fatal); 1063 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1064 if (local_err) { 1065 error_propagate(errp, local_err); 1066 return; 1067 } 1068 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1069 &PNV_PSI(psi8)->xscom_regs); 1070 1071 /* Create LPC controller */ 1072 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1073 &error_abort); 1074 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1075 &error_fatal); 1076 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1077 1078 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1079 (uint64_t) PNV_XSCOM_BASE(chip), 1080 PNV_XSCOM_LPC_BASE); 1081 1082 /* 1083 * Interrupt Management Area. This is the memory region holding 1084 * all the Interrupt Control Presenter (ICP) registers 1085 */ 1086 pnv_chip_icp_realize(chip8, &local_err); 1087 if (local_err) { 1088 error_propagate(errp, local_err); 1089 return; 1090 } 1091 1092 /* Create the simplified OCC model */ 1093 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1094 &error_abort); 1095 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1096 if (local_err) { 1097 error_propagate(errp, local_err); 1098 return; 1099 } 1100 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1101 1102 /* OCC SRAM model */ 1103 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1104 &chip8->occ.sram_regs); 1105 1106 /* HOMER */ 1107 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1108 &error_abort); 1109 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1110 &local_err); 1111 if (local_err) { 1112 error_propagate(errp, local_err); 1113 return; 1114 } 1115 /* Homer Xscom region */ 1116 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1117 1118 /* Homer mmio region */ 1119 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1120 &chip8->homer.regs); 1121 } 1122 1123 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1124 { 1125 DeviceClass *dc = DEVICE_CLASS(klass); 1126 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1127 1128 k->chip_type = PNV_CHIP_POWER8E; 1129 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1130 k->cores_mask = POWER8E_CORE_MASK; 1131 k->core_pir = pnv_chip_core_pir_p8; 1132 k->intc_create = pnv_chip_power8_intc_create; 1133 k->intc_reset = pnv_chip_power8_intc_reset; 1134 k->intc_destroy = pnv_chip_power8_intc_destroy; 1135 k->intc_print_info = pnv_chip_power8_intc_print_info; 1136 k->isa_create = pnv_chip_power8_isa_create; 1137 k->dt_populate = pnv_chip_power8_dt_populate; 1138 k->pic_print_info = pnv_chip_power8_pic_print_info; 1139 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1140 dc->desc = "PowerNV Chip POWER8E"; 1141 1142 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1143 &k->parent_realize); 1144 } 1145 1146 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1147 { 1148 DeviceClass *dc = DEVICE_CLASS(klass); 1149 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1150 1151 k->chip_type = PNV_CHIP_POWER8; 1152 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1153 k->cores_mask = POWER8_CORE_MASK; 1154 k->core_pir = pnv_chip_core_pir_p8; 1155 k->intc_create = pnv_chip_power8_intc_create; 1156 k->intc_reset = pnv_chip_power8_intc_reset; 1157 k->intc_destroy = pnv_chip_power8_intc_destroy; 1158 k->intc_print_info = pnv_chip_power8_intc_print_info; 1159 k->isa_create = pnv_chip_power8_isa_create; 1160 k->dt_populate = pnv_chip_power8_dt_populate; 1161 k->pic_print_info = pnv_chip_power8_pic_print_info; 1162 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1163 dc->desc = "PowerNV Chip POWER8"; 1164 1165 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1166 &k->parent_realize); 1167 } 1168 1169 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1170 { 1171 DeviceClass *dc = DEVICE_CLASS(klass); 1172 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1173 1174 k->chip_type = PNV_CHIP_POWER8NVL; 1175 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1176 k->cores_mask = POWER8_CORE_MASK; 1177 k->core_pir = pnv_chip_core_pir_p8; 1178 k->intc_create = pnv_chip_power8_intc_create; 1179 k->intc_reset = pnv_chip_power8_intc_reset; 1180 k->intc_destroy = pnv_chip_power8_intc_destroy; 1181 k->intc_print_info = pnv_chip_power8_intc_print_info; 1182 k->isa_create = pnv_chip_power8nvl_isa_create; 1183 k->dt_populate = pnv_chip_power8_dt_populate; 1184 k->pic_print_info = pnv_chip_power8_pic_print_info; 1185 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1186 dc->desc = "PowerNV Chip POWER8NVL"; 1187 1188 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1189 &k->parent_realize); 1190 } 1191 1192 static void pnv_chip_power9_instance_init(Object *obj) 1193 { 1194 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1195 1196 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1197 TYPE_PNV_XIVE, &error_abort, NULL); 1198 1199 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1200 TYPE_PNV9_PSI, &error_abort, NULL); 1201 1202 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1203 TYPE_PNV9_LPC, &error_abort, NULL); 1204 1205 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1206 TYPE_PNV9_OCC, &error_abort, NULL); 1207 1208 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1209 TYPE_PNV9_HOMER, &error_abort, NULL); 1210 } 1211 1212 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1213 { 1214 PnvChip *chip = PNV_CHIP(chip9); 1215 int i; 1216 1217 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1218 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1219 1220 for (i = 0; i < chip9->nr_quads; i++) { 1221 char eq_name[32]; 1222 PnvQuad *eq = &chip9->quads[i]; 1223 PnvCore *pnv_core = chip->cores[i * 4]; 1224 int core_id = CPU_CORE(pnv_core)->core_id; 1225 1226 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1227 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1228 TYPE_PNV_QUAD, &error_fatal, NULL); 1229 1230 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1231 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1232 1233 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1234 &eq->xscom_regs); 1235 } 1236 } 1237 1238 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1239 { 1240 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1241 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1242 PnvChip *chip = PNV_CHIP(dev); 1243 Pnv9Psi *psi9 = &chip9->psi; 1244 Error *local_err = NULL; 1245 1246 /* XSCOM bridge is first */ 1247 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1248 if (local_err) { 1249 error_propagate(errp, local_err); 1250 return; 1251 } 1252 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1253 1254 pcc->parent_realize(dev, &local_err); 1255 if (local_err) { 1256 error_propagate(errp, local_err); 1257 return; 1258 } 1259 1260 pnv_chip_quad_realize(chip9, &local_err); 1261 if (local_err) { 1262 error_propagate(errp, local_err); 1263 return; 1264 } 1265 1266 /* XIVE interrupt controller (POWER9) */ 1267 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1268 "ic-bar", &error_fatal); 1269 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1270 "vc-bar", &error_fatal); 1271 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1272 "pc-bar", &error_fatal); 1273 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1274 "tm-bar", &error_fatal); 1275 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1276 &error_abort); 1277 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1278 &local_err); 1279 if (local_err) { 1280 error_propagate(errp, local_err); 1281 return; 1282 } 1283 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1284 &chip9->xive.xscom_regs); 1285 1286 /* Processor Service Interface (PSI) Host Bridge */ 1287 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1288 "bar", &error_fatal); 1289 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1290 if (local_err) { 1291 error_propagate(errp, local_err); 1292 return; 1293 } 1294 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1295 &PNV_PSI(psi9)->xscom_regs); 1296 1297 /* LPC */ 1298 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1299 &error_abort); 1300 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1301 if (local_err) { 1302 error_propagate(errp, local_err); 1303 return; 1304 } 1305 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1306 &chip9->lpc.xscom_regs); 1307 1308 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1309 (uint64_t) PNV9_LPCM_BASE(chip)); 1310 1311 /* Create the simplified OCC model */ 1312 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1313 &error_abort); 1314 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1315 if (local_err) { 1316 error_propagate(errp, local_err); 1317 return; 1318 } 1319 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1320 1321 /* OCC SRAM model */ 1322 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1323 &chip9->occ.sram_regs); 1324 1325 /* HOMER */ 1326 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1327 &error_abort); 1328 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1329 &local_err); 1330 if (local_err) { 1331 error_propagate(errp, local_err); 1332 return; 1333 } 1334 /* Homer Xscom region */ 1335 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1336 1337 /* Homer mmio region */ 1338 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1339 &chip9->homer.regs); 1340 } 1341 1342 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1343 { 1344 DeviceClass *dc = DEVICE_CLASS(klass); 1345 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1346 1347 k->chip_type = PNV_CHIP_POWER9; 1348 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1349 k->cores_mask = POWER9_CORE_MASK; 1350 k->core_pir = pnv_chip_core_pir_p9; 1351 k->intc_create = pnv_chip_power9_intc_create; 1352 k->intc_reset = pnv_chip_power9_intc_reset; 1353 k->intc_destroy = pnv_chip_power9_intc_destroy; 1354 k->intc_print_info = pnv_chip_power9_intc_print_info; 1355 k->isa_create = pnv_chip_power9_isa_create; 1356 k->dt_populate = pnv_chip_power9_dt_populate; 1357 k->pic_print_info = pnv_chip_power9_pic_print_info; 1358 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1359 dc->desc = "PowerNV Chip POWER9"; 1360 1361 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1362 &k->parent_realize); 1363 } 1364 1365 static void pnv_chip_power10_instance_init(Object *obj) 1366 { 1367 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1368 1369 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1370 TYPE_PNV10_PSI, &error_abort, NULL); 1371 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1372 TYPE_PNV10_LPC, &error_abort, NULL); 1373 } 1374 1375 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1376 { 1377 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1378 PnvChip *chip = PNV_CHIP(dev); 1379 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1380 Error *local_err = NULL; 1381 1382 /* XSCOM bridge is first */ 1383 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1384 if (local_err) { 1385 error_propagate(errp, local_err); 1386 return; 1387 } 1388 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1389 1390 pcc->parent_realize(dev, &local_err); 1391 if (local_err) { 1392 error_propagate(errp, local_err); 1393 return; 1394 } 1395 1396 /* Processor Service Interface (PSI) Host Bridge */ 1397 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1398 "bar", &error_fatal); 1399 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1400 &local_err); 1401 if (local_err) { 1402 error_propagate(errp, local_err); 1403 return; 1404 } 1405 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1406 &PNV_PSI(&chip10->psi)->xscom_regs); 1407 1408 /* LPC */ 1409 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1410 &error_abort); 1411 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1412 &local_err); 1413 if (local_err) { 1414 error_propagate(errp, local_err); 1415 return; 1416 } 1417 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1418 &chip10->lpc.xscom_regs); 1419 1420 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1421 (uint64_t) PNV10_LPCM_BASE(chip)); 1422 } 1423 1424 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1425 { 1426 DeviceClass *dc = DEVICE_CLASS(klass); 1427 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1428 1429 k->chip_type = PNV_CHIP_POWER10; 1430 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1431 k->cores_mask = POWER10_CORE_MASK; 1432 k->core_pir = pnv_chip_core_pir_p10; 1433 k->intc_create = pnv_chip_power10_intc_create; 1434 k->intc_reset = pnv_chip_power10_intc_reset; 1435 k->intc_destroy = pnv_chip_power10_intc_destroy; 1436 k->intc_print_info = pnv_chip_power10_intc_print_info; 1437 k->isa_create = pnv_chip_power10_isa_create; 1438 k->dt_populate = pnv_chip_power10_dt_populate; 1439 k->pic_print_info = pnv_chip_power10_pic_print_info; 1440 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1441 dc->desc = "PowerNV Chip POWER10"; 1442 1443 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1444 &k->parent_realize); 1445 } 1446 1447 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1448 { 1449 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1450 int cores_max; 1451 1452 /* 1453 * No custom mask for this chip, let's use the default one from * 1454 * the chip class 1455 */ 1456 if (!chip->cores_mask) { 1457 chip->cores_mask = pcc->cores_mask; 1458 } 1459 1460 /* filter alien core ids ! some are reserved */ 1461 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1462 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1463 chip->cores_mask); 1464 return; 1465 } 1466 chip->cores_mask &= pcc->cores_mask; 1467 1468 /* now that we have a sane layout, let check the number of cores */ 1469 cores_max = ctpop64(chip->cores_mask); 1470 if (chip->nr_cores > cores_max) { 1471 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1472 cores_max); 1473 return; 1474 } 1475 } 1476 1477 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1478 { 1479 MachineState *ms = MACHINE(qdev_get_machine()); 1480 Error *error = NULL; 1481 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1482 const char *typename = pnv_chip_core_typename(chip); 1483 int i, core_hwid; 1484 1485 if (!object_class_by_name(typename)) { 1486 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1487 return; 1488 } 1489 1490 /* Cores */ 1491 pnv_chip_core_sanitize(chip, &error); 1492 if (error) { 1493 error_propagate(errp, error); 1494 return; 1495 } 1496 1497 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1498 1499 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1500 && (i < chip->nr_cores); core_hwid++) { 1501 char core_name[32]; 1502 PnvCore *pnv_core; 1503 uint64_t xscom_core_base; 1504 1505 if (!(chip->cores_mask & (1ull << core_hwid))) { 1506 continue; 1507 } 1508 1509 pnv_core = PNV_CORE(object_new(typename)); 1510 1511 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1512 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1513 &error_abort); 1514 chip->cores[i] = pnv_core; 1515 object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", 1516 &error_fatal); 1517 object_property_set_int(OBJECT(pnv_core), core_hwid, 1518 CPU_CORE_PROP_CORE_ID, &error_fatal); 1519 object_property_set_int(OBJECT(pnv_core), 1520 pcc->core_pir(chip, core_hwid), 1521 "pir", &error_fatal); 1522 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1523 &error_abort); 1524 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1525 &error_fatal); 1526 1527 /* Each core has an XSCOM MMIO region */ 1528 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1529 1530 pnv_xscom_add_subregion(chip, xscom_core_base, 1531 &pnv_core->xscom_regs); 1532 i++; 1533 } 1534 } 1535 1536 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1537 { 1538 PnvChip *chip = PNV_CHIP(dev); 1539 Error *error = NULL; 1540 1541 /* Cores */ 1542 pnv_chip_core_realize(chip, &error); 1543 if (error) { 1544 error_propagate(errp, error); 1545 return; 1546 } 1547 } 1548 1549 static Property pnv_chip_properties[] = { 1550 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1551 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1552 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1553 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1554 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1555 DEFINE_PROP_END_OF_LIST(), 1556 }; 1557 1558 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1559 { 1560 DeviceClass *dc = DEVICE_CLASS(klass); 1561 1562 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1563 dc->realize = pnv_chip_realize; 1564 dc->props = pnv_chip_properties; 1565 dc->desc = "PowerNV Chip"; 1566 } 1567 1568 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1569 { 1570 int i, j; 1571 1572 for (i = 0; i < chip->nr_cores; i++) { 1573 PnvCore *pc = chip->cores[i]; 1574 CPUCore *cc = CPU_CORE(pc); 1575 1576 for (j = 0; j < cc->nr_threads; j++) { 1577 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1578 return pc->threads[j]; 1579 } 1580 } 1581 } 1582 return NULL; 1583 } 1584 1585 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1586 { 1587 PnvMachineState *pnv = PNV_MACHINE(xi); 1588 int i; 1589 1590 for (i = 0; i < pnv->num_chips; i++) { 1591 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1592 1593 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1594 return &chip8->psi.ics; 1595 } 1596 } 1597 return NULL; 1598 } 1599 1600 static void pnv_ics_resend(XICSFabric *xi) 1601 { 1602 PnvMachineState *pnv = PNV_MACHINE(xi); 1603 int i; 1604 1605 for (i = 0; i < pnv->num_chips; i++) { 1606 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1607 ics_resend(&chip8->psi.ics); 1608 } 1609 } 1610 1611 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1612 { 1613 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1614 1615 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1616 } 1617 1618 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1619 Monitor *mon) 1620 { 1621 PnvMachineState *pnv = PNV_MACHINE(obj); 1622 int i; 1623 CPUState *cs; 1624 1625 CPU_FOREACH(cs) { 1626 PowerPCCPU *cpu = POWERPC_CPU(cs); 1627 1628 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1629 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1630 mon); 1631 } 1632 1633 for (i = 0; i < pnv->num_chips; i++) { 1634 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1635 } 1636 } 1637 1638 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1639 uint8_t nvt_blk, uint32_t nvt_idx, 1640 bool cam_ignore, uint8_t priority, 1641 uint32_t logic_serv, 1642 XiveTCTXMatch *match) 1643 { 1644 PnvMachineState *pnv = PNV_MACHINE(xfb); 1645 int total_count = 0; 1646 int i; 1647 1648 for (i = 0; i < pnv->num_chips; i++) { 1649 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1650 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1651 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1652 int count; 1653 1654 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1655 priority, logic_serv, match); 1656 1657 if (count < 0) { 1658 return count; 1659 } 1660 1661 total_count += count; 1662 } 1663 1664 return total_count; 1665 } 1666 1667 PnvChip *pnv_get_chip(uint32_t chip_id) 1668 { 1669 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1670 int i; 1671 1672 for (i = 0; i < pnv->num_chips; i++) { 1673 PnvChip *chip = pnv->chips[i]; 1674 if (chip->chip_id == chip_id) { 1675 return chip; 1676 } 1677 } 1678 return NULL; 1679 } 1680 1681 static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, 1682 void *opaque, Error **errp) 1683 { 1684 visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); 1685 } 1686 1687 static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, 1688 void *opaque, Error **errp) 1689 { 1690 PnvMachineState *pnv = PNV_MACHINE(obj); 1691 uint32_t num_chips; 1692 Error *local_err = NULL; 1693 1694 visit_type_uint32(v, name, &num_chips, &local_err); 1695 if (local_err) { 1696 error_propagate(errp, local_err); 1697 return; 1698 } 1699 1700 /* 1701 * TODO: should we decide on how many chips we can create based 1702 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1703 */ 1704 if (!is_power_of_2(num_chips) || num_chips > 4) { 1705 error_setg(errp, "invalid number of chips: '%d'", num_chips); 1706 return; 1707 } 1708 1709 pnv->num_chips = num_chips; 1710 } 1711 1712 static void pnv_machine_instance_init(Object *obj) 1713 { 1714 PnvMachineState *pnv = PNV_MACHINE(obj); 1715 pnv->num_chips = 1; 1716 } 1717 1718 static void pnv_machine_class_props_init(ObjectClass *oc) 1719 { 1720 object_class_property_add(oc, "num-chips", "uint32", 1721 pnv_get_num_chips, pnv_set_num_chips, 1722 NULL, NULL, NULL); 1723 object_class_property_set_description(oc, "num-chips", 1724 "Specifies the number of processor chips", 1725 NULL); 1726 } 1727 1728 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1729 { 1730 MachineClass *mc = MACHINE_CLASS(oc); 1731 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1732 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1733 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1734 1735 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1736 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1737 1738 xic->icp_get = pnv_icp_get; 1739 xic->ics_get = pnv_ics_get; 1740 xic->ics_resend = pnv_ics_resend; 1741 1742 pmc->compat = compat; 1743 pmc->compat_size = sizeof(compat); 1744 } 1745 1746 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1747 { 1748 MachineClass *mc = MACHINE_CLASS(oc); 1749 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1750 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1751 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1752 1753 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1754 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1755 xfc->match_nvt = pnv_match_nvt; 1756 1757 mc->alias = "powernv"; 1758 1759 pmc->compat = compat; 1760 pmc->compat_size = sizeof(compat); 1761 pmc->dt_power_mgt = pnv_dt_power_mgt; 1762 } 1763 1764 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1765 { 1766 MachineClass *mc = MACHINE_CLASS(oc); 1767 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1768 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1769 1770 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1771 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1772 1773 pmc->compat = compat; 1774 pmc->compat_size = sizeof(compat); 1775 pmc->dt_power_mgt = pnv_dt_power_mgt; 1776 } 1777 1778 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1779 { 1780 MachineClass *mc = MACHINE_CLASS(oc); 1781 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1782 1783 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1784 mc->init = pnv_init; 1785 mc->reset = pnv_reset; 1786 mc->max_cpus = MAX_CPUS; 1787 /* Pnv provides a AHCI device for storage */ 1788 mc->block_default_type = IF_IDE; 1789 mc->no_parallel = 1; 1790 mc->default_boot_order = NULL; 1791 /* 1792 * RAM defaults to less than 2048 for 32-bit hosts, and large 1793 * enough to fit the maximum initrd size at it's load address 1794 */ 1795 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1796 ispc->print_info = pnv_pic_print_info; 1797 1798 pnv_machine_class_props_init(oc); 1799 } 1800 1801 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1802 { \ 1803 .name = type, \ 1804 .class_init = class_initfn, \ 1805 .parent = TYPE_PNV8_CHIP, \ 1806 } 1807 1808 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1809 { \ 1810 .name = type, \ 1811 .class_init = class_initfn, \ 1812 .parent = TYPE_PNV9_CHIP, \ 1813 } 1814 1815 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 1816 { \ 1817 .name = type, \ 1818 .class_init = class_initfn, \ 1819 .parent = TYPE_PNV10_CHIP, \ 1820 } 1821 1822 static const TypeInfo types[] = { 1823 { 1824 .name = MACHINE_TYPE_NAME("powernv10"), 1825 .parent = TYPE_PNV_MACHINE, 1826 .class_init = pnv_machine_power10_class_init, 1827 }, 1828 { 1829 .name = MACHINE_TYPE_NAME("powernv9"), 1830 .parent = TYPE_PNV_MACHINE, 1831 .class_init = pnv_machine_power9_class_init, 1832 .interfaces = (InterfaceInfo[]) { 1833 { TYPE_XIVE_FABRIC }, 1834 { }, 1835 }, 1836 }, 1837 { 1838 .name = MACHINE_TYPE_NAME("powernv8"), 1839 .parent = TYPE_PNV_MACHINE, 1840 .class_init = pnv_machine_power8_class_init, 1841 .interfaces = (InterfaceInfo[]) { 1842 { TYPE_XICS_FABRIC }, 1843 { }, 1844 }, 1845 }, 1846 { 1847 .name = TYPE_PNV_MACHINE, 1848 .parent = TYPE_MACHINE, 1849 .abstract = true, 1850 .instance_size = sizeof(PnvMachineState), 1851 .instance_init = pnv_machine_instance_init, 1852 .class_init = pnv_machine_class_init, 1853 .class_size = sizeof(PnvMachineClass), 1854 .interfaces = (InterfaceInfo[]) { 1855 { TYPE_INTERRUPT_STATS_PROVIDER }, 1856 { }, 1857 }, 1858 }, 1859 { 1860 .name = TYPE_PNV_CHIP, 1861 .parent = TYPE_SYS_BUS_DEVICE, 1862 .class_init = pnv_chip_class_init, 1863 .instance_size = sizeof(PnvChip), 1864 .class_size = sizeof(PnvChipClass), 1865 .abstract = true, 1866 }, 1867 1868 /* 1869 * P10 chip and variants 1870 */ 1871 { 1872 .name = TYPE_PNV10_CHIP, 1873 .parent = TYPE_PNV_CHIP, 1874 .instance_init = pnv_chip_power10_instance_init, 1875 .instance_size = sizeof(Pnv10Chip), 1876 }, 1877 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 1878 1879 /* 1880 * P9 chip and variants 1881 */ 1882 { 1883 .name = TYPE_PNV9_CHIP, 1884 .parent = TYPE_PNV_CHIP, 1885 .instance_init = pnv_chip_power9_instance_init, 1886 .instance_size = sizeof(Pnv9Chip), 1887 }, 1888 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 1889 1890 /* 1891 * P8 chip and variants 1892 */ 1893 { 1894 .name = TYPE_PNV8_CHIP, 1895 .parent = TYPE_PNV_CHIP, 1896 .instance_init = pnv_chip_power8_instance_init, 1897 .instance_size = sizeof(Pnv8Chip), 1898 }, 1899 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 1900 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 1901 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 1902 pnv_chip_power8nvl_class_init), 1903 }; 1904 1905 DEFINE_TYPES(types) 1906