1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "qapi/type-helpers.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci-host/pnv_phb.h" 48 #include "hw/pci-host/pnv_phb3.h" 49 #include "hw/pci-host/pnv_phb4.h" 50 51 #include "hw/ppc/xics.h" 52 #include "hw/qdev-properties.h" 53 #include "hw/ppc/pnv_chip.h" 54 #include "hw/ppc/pnv_xscom.h" 55 #include "hw/ppc/pnv_pnor.h" 56 57 #include "hw/isa/isa.h" 58 #include "hw/char/serial.h" 59 #include "hw/rtc/mc146818rtc.h" 60 61 #include <libfdt.h> 62 63 #define FDT_MAX_SIZE (1 * MiB) 64 65 #define FW_FILE_NAME "skiboot.lid" 66 #define FW_LOAD_ADDR 0x0 67 #define FW_MAX_SIZE (16 * MiB) 68 69 #define KERNEL_LOAD_ADDR 0x20000000 70 #define KERNEL_MAX_SIZE (128 * MiB) 71 #define INITRD_LOAD_ADDR 0x28000000 72 #define INITRD_MAX_SIZE (128 * MiB) 73 74 static const char *pnv_chip_core_typename(const PnvChip *o) 75 { 76 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 77 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 78 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 79 const char *core_type = object_class_get_name(object_class_by_name(s)); 80 g_free(s); 81 return core_type; 82 } 83 84 /* 85 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 86 * 4 * 4 sockets * 12 cores * 8 threads = 1536 87 * Let's make it 2^11 88 */ 89 #define MAX_CPUS 2048 90 91 /* 92 * Memory nodes are created by hostboot, one for each range of memory 93 * that has a different "affinity". In practice, it means one range 94 * per chip. 95 */ 96 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 97 { 98 char *mem_name; 99 uint64_t mem_reg_property[2]; 100 int off; 101 102 mem_reg_property[0] = cpu_to_be64(start); 103 mem_reg_property[1] = cpu_to_be64(size); 104 105 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 106 off = fdt_add_subnode(fdt, 0, mem_name); 107 g_free(mem_name); 108 109 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 110 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 111 sizeof(mem_reg_property)))); 112 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 113 } 114 115 static int get_cpus_node(void *fdt) 116 { 117 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 118 119 if (cpus_offset < 0) { 120 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 121 if (cpus_offset) { 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 123 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 124 } 125 } 126 _FDT(cpus_offset); 127 return cpus_offset; 128 } 129 130 /* 131 * The PowerNV cores (and threads) need to use real HW ids and not an 132 * incremental index like it has been done on other platforms. This HW 133 * id is stored in the CPU PIR, it is used to create cpu nodes in the 134 * device tree, used in XSCOM to address cores and in interrupt 135 * servers. 136 */ 137 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 138 { 139 PowerPCCPU *cpu = pc->threads[0]; 140 CPUState *cs = CPU(cpu); 141 DeviceClass *dc = DEVICE_GET_CLASS(cs); 142 int smt_threads = CPU_CORE(pc)->nr_threads; 143 CPUPPCState *env = &cpu->env; 144 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 145 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 146 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 147 int i; 148 uint32_t pir; 149 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 150 0xffffffff, 0xffffffff}; 151 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 152 uint32_t cpufreq = 1000000000; 153 uint32_t page_sizes_prop[64]; 154 size_t page_sizes_prop_size; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 pir = pnv_cc->chip_pir(chip, pc->hwid, 0); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i)); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(*servers_prop) * smt_threads))); 245 246 return offset; 247 } 248 249 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 250 uint32_t nr_threads) 251 { 252 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 253 uint32_t pir = pcc->chip_pir(chip, hwid, 0); 254 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 255 char *name; 256 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 257 uint32_t irange[2], i, rsize; 258 uint64_t *reg; 259 int offset; 260 261 irange[0] = cpu_to_be32(pir); 262 irange[1] = cpu_to_be32(nr_threads); 263 264 rsize = sizeof(uint64_t) * 2 * nr_threads; 265 reg = g_malloc(rsize); 266 for (i = 0; i < nr_threads; i++) { 267 /* We know P8 PIR is linear with thread id */ 268 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 269 reg[i * 2 + 1] = cpu_to_be64(0x1000); 270 } 271 272 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 273 offset = fdt_add_subnode(fdt, 0, name); 274 _FDT(offset); 275 g_free(name); 276 277 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 278 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 279 _FDT((fdt_setprop_string(fdt, offset, "device_type", 280 "PowerPC-External-Interrupt-Presentation"))); 281 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 282 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 283 irange, sizeof(irange)))); 284 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 285 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 286 g_free(reg); 287 } 288 289 /* 290 * Adds a PnvPHB to the chip on P8. 291 * Implemented here, like for defaults PHBs 292 */ 293 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 294 { 295 Pnv8Chip *chip8 = PNV8_CHIP(chip); 296 297 phb->chip = chip; 298 299 chip8->phbs[chip8->num_phbs] = phb; 300 chip8->num_phbs++; 301 return chip; 302 } 303 304 /* 305 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 306 * HTM is always enabled because TCG does implement HTM, it's just a 307 * degenerate implementation. 308 */ 309 static const uint8_t pa_features_207[] = { 24, 0, 310 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 311 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 312 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 313 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 314 315 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 316 { 317 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 318 int i; 319 320 pnv_dt_xscom(chip, fdt, 0, 321 cpu_to_be64(PNV_XSCOM_BASE(chip)), 322 cpu_to_be64(PNV_XSCOM_SIZE), 323 compat, sizeof(compat)); 324 325 for (i = 0; i < chip->nr_cores; i++) { 326 PnvCore *pnv_core = chip->cores[i]; 327 int offset; 328 329 offset = pnv_dt_core(chip, pnv_core, fdt); 330 331 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 332 pa_features_207, sizeof(pa_features_207)))); 333 334 /* Interrupt Control Presenters (ICP). One per core. */ 335 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 336 } 337 338 if (chip->ram_size) { 339 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 340 } 341 } 342 343 /* 344 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 345 */ 346 static const uint8_t pa_features_300[] = { 66, 0, 347 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 348 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 349 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 350 /* 6: DS207 */ 351 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 352 /* 16: Vector */ 353 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 354 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 356 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 357 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 358 /* 32: LE atomic, 34: EBB + ext EBB */ 359 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 360 /* 40: Radix MMU */ 361 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 362 /* 42: PM, 44: PC RA, 46: SC vec'd */ 363 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 364 /* 48: SIMD, 50: QP BFP, 52: String */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 366 /* 54: DecFP, 56: DecI, 58: SHA */ 367 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 368 /* 60: NM atomic, 62: RNG */ 369 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 370 }; 371 372 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 373 { 374 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 375 int i; 376 377 pnv_dt_xscom(chip, fdt, 0, 378 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 379 cpu_to_be64(PNV9_XSCOM_SIZE), 380 compat, sizeof(compat)); 381 382 for (i = 0; i < chip->nr_cores; i++) { 383 PnvCore *pnv_core = chip->cores[i]; 384 int offset; 385 386 offset = pnv_dt_core(chip, pnv_core, fdt); 387 388 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 389 pa_features_300, sizeof(pa_features_300)))); 390 } 391 392 if (chip->ram_size) { 393 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 394 } 395 396 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 397 } 398 399 /* 400 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 401 * always disables copy/paste. 402 */ 403 static const uint8_t pa_features_31[] = { 74, 0, 404 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 405 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 406 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 407 /* 6: DS207 */ 408 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 409 /* 16: Vector */ 410 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 411 /* 18: Vec. Scalar, 20: Vec. XOR */ 412 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 413 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 414 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 415 /* 32: LE atomic, 34: EBB + ext EBB */ 416 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 417 /* 40: Radix MMU */ 418 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 419 /* 42: PM, 44: PC RA, 46: SC vec'd */ 420 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 421 /* 48: SIMD, 50: QP BFP, 52: String */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 423 /* 54: DecFP, 56: DecI, 58: SHA */ 424 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 425 /* 60: NM atomic, 62: RNG */ 426 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 427 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 428 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 429 /* 72: [P]HASHST/[P]HASHCHK */ 430 0x80, 0x00, /* 72 - 73 */ 431 }; 432 433 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 434 { 435 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 436 int i; 437 438 pnv_dt_xscom(chip, fdt, 0, 439 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 440 cpu_to_be64(PNV10_XSCOM_SIZE), 441 compat, sizeof(compat)); 442 443 for (i = 0; i < chip->nr_cores; i++) { 444 PnvCore *pnv_core = chip->cores[i]; 445 int offset; 446 447 offset = pnv_dt_core(chip, pnv_core, fdt); 448 449 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 450 pa_features_31, sizeof(pa_features_31)))); 451 } 452 453 if (chip->ram_size) { 454 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 455 } 456 457 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 458 } 459 460 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 461 { 462 uint32_t io_base = d->ioport_id; 463 uint32_t io_regs[] = { 464 cpu_to_be32(1), 465 cpu_to_be32(io_base), 466 cpu_to_be32(2) 467 }; 468 char *name; 469 int node; 470 471 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 472 node = fdt_add_subnode(fdt, lpc_off, name); 473 _FDT(node); 474 g_free(name); 475 476 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 477 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 478 } 479 480 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 481 { 482 const char compatible[] = "ns16550\0pnpPNP,501"; 483 uint32_t io_base = d->ioport_id; 484 uint32_t io_regs[] = { 485 cpu_to_be32(1), 486 cpu_to_be32(io_base), 487 cpu_to_be32(8) 488 }; 489 uint32_t irq; 490 char *name; 491 int node; 492 493 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 494 495 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 496 node = fdt_add_subnode(fdt, lpc_off, name); 497 _FDT(node); 498 g_free(name); 499 500 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 501 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 502 sizeof(compatible)))); 503 504 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 505 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 506 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 507 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 508 fdt_get_phandle(fdt, lpc_off)))); 509 510 /* This is needed by Linux */ 511 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 512 } 513 514 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 515 { 516 const char compatible[] = "bt\0ipmi-bt"; 517 uint32_t io_base; 518 uint32_t io_regs[] = { 519 cpu_to_be32(1), 520 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 521 cpu_to_be32(3) 522 }; 523 uint32_t irq; 524 char *name; 525 int node; 526 527 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 528 io_regs[1] = cpu_to_be32(io_base); 529 530 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 531 532 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 533 node = fdt_add_subnode(fdt, lpc_off, name); 534 _FDT(node); 535 g_free(name); 536 537 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 538 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 539 sizeof(compatible)))); 540 541 /* Mark it as reserved to avoid Linux trying to claim it */ 542 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 543 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 544 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 545 fdt_get_phandle(fdt, lpc_off)))); 546 } 547 548 typedef struct ForeachPopulateArgs { 549 void *fdt; 550 int offset; 551 } ForeachPopulateArgs; 552 553 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 554 { 555 ForeachPopulateArgs *args = opaque; 556 ISADevice *d = ISA_DEVICE(dev); 557 558 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 559 pnv_dt_rtc(d, args->fdt, args->offset); 560 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 561 pnv_dt_serial(d, args->fdt, args->offset); 562 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 563 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 564 } else { 565 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 566 d->ioport_id); 567 } 568 569 return 0; 570 } 571 572 /* 573 * The default LPC bus of a multichip system is on chip 0. It's 574 * recognized by the firmware (skiboot) using a "primary" property. 575 */ 576 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 577 { 578 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 579 ForeachPopulateArgs args = { 580 .fdt = fdt, 581 .offset = isa_offset, 582 }; 583 uint32_t phandle; 584 585 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 586 587 phandle = qemu_fdt_alloc_phandle(fdt); 588 assert(phandle > 0); 589 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 590 591 /* 592 * ISA devices are not necessarily parented to the ISA bus so we 593 * can not use object_child_foreach() 594 */ 595 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 596 &args); 597 } 598 599 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 600 { 601 int off; 602 603 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 604 off = fdt_add_subnode(fdt, off, "power-mgt"); 605 606 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 607 } 608 609 static void *pnv_dt_create(MachineState *machine) 610 { 611 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 612 PnvMachineState *pnv = PNV_MACHINE(machine); 613 void *fdt; 614 char *buf; 615 int off; 616 int i; 617 618 fdt = g_malloc0(FDT_MAX_SIZE); 619 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 620 621 /* /qemu node */ 622 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 623 624 /* Root node */ 625 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 626 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 627 _FDT((fdt_setprop_string(fdt, 0, "model", 628 "IBM PowerNV (emulated by qemu)"))); 629 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 630 631 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 632 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 633 if (qemu_uuid_set) { 634 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 635 } 636 g_free(buf); 637 638 off = fdt_add_subnode(fdt, 0, "chosen"); 639 if (machine->kernel_cmdline) { 640 _FDT((fdt_setprop_string(fdt, off, "bootargs", 641 machine->kernel_cmdline))); 642 } 643 644 if (pnv->initrd_size) { 645 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 646 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 647 648 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 649 &start_prop, sizeof(start_prop)))); 650 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 651 &end_prop, sizeof(end_prop)))); 652 } 653 654 /* Populate device tree for each chip */ 655 for (i = 0; i < pnv->num_chips; i++) { 656 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 657 } 658 659 /* Populate ISA devices on chip 0 */ 660 pnv_dt_isa(pnv, fdt); 661 662 if (pnv->bmc) { 663 pnv_dt_bmc_sensors(pnv->bmc, fdt); 664 } 665 666 /* Create an extra node for power management on machines that support it */ 667 if (pmc->dt_power_mgt) { 668 pmc->dt_power_mgt(pnv, fdt); 669 } 670 671 return fdt; 672 } 673 674 static void pnv_powerdown_notify(Notifier *n, void *opaque) 675 { 676 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 677 678 if (pnv->bmc) { 679 pnv_bmc_powerdown(pnv->bmc); 680 } 681 } 682 683 static void pnv_reset(MachineState *machine, ShutdownCause reason) 684 { 685 PnvMachineState *pnv = PNV_MACHINE(machine); 686 IPMIBmc *bmc; 687 void *fdt; 688 689 qemu_devices_reset(reason); 690 691 /* 692 * The machine should provide by default an internal BMC simulator. 693 * If not, try to use the BMC device that was provided on the command 694 * line. 695 */ 696 bmc = pnv_bmc_find(&error_fatal); 697 if (!pnv->bmc) { 698 if (!bmc) { 699 if (!qtest_enabled()) { 700 warn_report("machine has no BMC device. Use '-device " 701 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 702 "to define one"); 703 } 704 } else { 705 pnv_bmc_set_pnor(bmc, pnv->pnor); 706 pnv->bmc = bmc; 707 } 708 } 709 710 fdt = pnv_dt_create(machine); 711 712 /* Pack resulting tree */ 713 _FDT((fdt_pack(fdt))); 714 715 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 716 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 717 718 /* 719 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 720 * the existing machine->fdt to avoid leaking it during 721 * a reset. 722 */ 723 g_free(machine->fdt); 724 machine->fdt = fdt; 725 } 726 727 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 728 { 729 Pnv8Chip *chip8 = PNV8_CHIP(chip); 730 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 731 732 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 733 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 734 } 735 736 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 737 { 738 Pnv8Chip *chip8 = PNV8_CHIP(chip); 739 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 740 741 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 742 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 743 } 744 745 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 746 { 747 Pnv9Chip *chip9 = PNV9_CHIP(chip); 748 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 749 750 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 751 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 752 } 753 754 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 755 { 756 Pnv10Chip *chip10 = PNV10_CHIP(chip); 757 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 758 759 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 760 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 761 } 762 763 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 764 { 765 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 766 } 767 768 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 769 { 770 Pnv8Chip *chip8 = PNV8_CHIP(chip); 771 int i; 772 773 g_autoptr(GString) buf = g_string_new(""); 774 g_autoptr(HumanReadableText) info = NULL; 775 776 ics_pic_print_info(&chip8->psi.ics, buf); 777 778 for (i = 0; i < chip8->num_phbs; i++) { 779 PnvPHB *phb = chip8->phbs[i]; 780 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 781 782 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 783 ics_pic_print_info(&phb3->lsis, buf); 784 } 785 786 info = human_readable_text_from_str(buf); 787 monitor_puts(mon, info->human_readable_text); 788 } 789 790 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 791 { 792 Monitor *mon = opaque; 793 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 794 g_autoptr(GString) buf = g_string_new(""); 795 g_autoptr(HumanReadableText) info = NULL; 796 797 if (!phb) { 798 return 0; 799 } 800 801 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 802 info = human_readable_text_from_str(buf); 803 monitor_puts(mon, info->human_readable_text); 804 805 return 0; 806 } 807 808 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 809 { 810 Pnv9Chip *chip9 = PNV9_CHIP(chip); 811 812 pnv_xive_pic_print_info(&chip9->xive, mon); 813 pnv_psi_pic_print_info(&chip9->psi, mon); 814 815 object_child_foreach_recursive(OBJECT(chip), 816 pnv_chip_power9_pic_print_info_child, mon); 817 } 818 819 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 820 uint32_t core_id) 821 { 822 return PNV_XSCOM_EX_BASE(core_id); 823 } 824 825 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 826 uint32_t core_id) 827 { 828 return PNV9_XSCOM_EC_BASE(core_id); 829 } 830 831 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 832 uint32_t core_id) 833 { 834 return PNV10_XSCOM_EC_BASE(core_id); 835 } 836 837 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 838 { 839 PowerPCCPUClass *ppc_default = 840 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 841 PowerPCCPUClass *ppc = 842 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 843 844 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 845 } 846 847 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 848 { 849 ISADevice *dev = isa_new("isa-ipmi-bt"); 850 851 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 852 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 853 isa_realize_and_unref(dev, bus, &error_fatal); 854 } 855 856 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 857 { 858 Pnv10Chip *chip10 = PNV10_CHIP(chip); 859 860 pnv_xive2_pic_print_info(&chip10->xive, mon); 861 pnv_psi_pic_print_info(&chip10->psi, mon); 862 863 object_child_foreach_recursive(OBJECT(chip), 864 pnv_chip_power9_pic_print_info_child, mon); 865 } 866 867 /* Always give the first 1GB to chip 0 else we won't boot */ 868 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 869 { 870 MachineState *machine = MACHINE(pnv); 871 uint64_t ram_per_chip; 872 873 assert(machine->ram_size >= 1 * GiB); 874 875 ram_per_chip = machine->ram_size / pnv->num_chips; 876 if (ram_per_chip >= 1 * GiB) { 877 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 878 } 879 880 assert(pnv->num_chips > 1); 881 882 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 883 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 884 } 885 886 static void pnv_init(MachineState *machine) 887 { 888 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 889 PnvMachineState *pnv = PNV_MACHINE(machine); 890 MachineClass *mc = MACHINE_GET_CLASS(machine); 891 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 892 char *fw_filename; 893 long fw_size; 894 uint64_t chip_ram_start = 0; 895 int i; 896 char *chip_typename; 897 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 898 DeviceState *dev; 899 900 if (kvm_enabled()) { 901 error_report("machine %s does not support the KVM accelerator", 902 mc->name); 903 exit(EXIT_FAILURE); 904 } 905 906 /* allocate RAM */ 907 if (machine->ram_size < mc->default_ram_size) { 908 char *sz = size_to_str(mc->default_ram_size); 909 error_report("Invalid RAM size, should be bigger than %s", sz); 910 g_free(sz); 911 exit(EXIT_FAILURE); 912 } 913 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 914 915 /* 916 * Create our simple PNOR device 917 */ 918 dev = qdev_new(TYPE_PNV_PNOR); 919 if (pnor) { 920 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 921 } 922 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 923 pnv->pnor = PNV_PNOR(dev); 924 925 /* load skiboot firmware */ 926 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 927 if (!fw_filename) { 928 error_report("Could not find OPAL firmware '%s'", bios_name); 929 exit(1); 930 } 931 932 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 933 if (fw_size < 0) { 934 error_report("Could not load OPAL firmware '%s'", fw_filename); 935 exit(1); 936 } 937 g_free(fw_filename); 938 939 /* load kernel */ 940 if (machine->kernel_filename) { 941 long kernel_size; 942 943 kernel_size = load_image_targphys(machine->kernel_filename, 944 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 945 if (kernel_size < 0) { 946 error_report("Could not load kernel '%s'", 947 machine->kernel_filename); 948 exit(1); 949 } 950 } 951 952 /* load initrd */ 953 if (machine->initrd_filename) { 954 pnv->initrd_base = INITRD_LOAD_ADDR; 955 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 956 pnv->initrd_base, INITRD_MAX_SIZE); 957 if (pnv->initrd_size < 0) { 958 error_report("Could not load initial ram disk '%s'", 959 machine->initrd_filename); 960 exit(1); 961 } 962 } 963 964 /* MSIs are supported on this platform */ 965 msi_nonbroken = true; 966 967 /* 968 * Check compatibility of the specified CPU with the machine 969 * default. 970 */ 971 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 972 error_report("invalid CPU model '%s' for %s machine", 973 machine->cpu_type, mc->name); 974 exit(1); 975 } 976 977 /* Create the processor chips */ 978 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 979 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 980 i, machine->cpu_type); 981 if (!object_class_by_name(chip_typename)) { 982 error_report("invalid chip model '%.*s' for %s machine", 983 i, machine->cpu_type, mc->name); 984 exit(1); 985 } 986 987 pnv->num_chips = 988 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 989 990 if (machine->smp.threads > 8) { 991 error_report("Cannot support more than 8 threads/core " 992 "on a powernv machine"); 993 exit(1); 994 } 995 if (!is_power_of_2(machine->smp.threads)) { 996 error_report("Cannot support %d threads/core on a powernv" 997 "machine because it must be a power of 2", 998 machine->smp.threads); 999 exit(1); 1000 } 1001 /* 1002 * TODO: should we decide on how many chips we can create based 1003 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 1004 */ 1005 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 1006 error_report("invalid number of chips: '%d'", pnv->num_chips); 1007 error_printf( 1008 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 1009 exit(1); 1010 } 1011 1012 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1013 for (i = 0; i < pnv->num_chips; i++) { 1014 char chip_name[32]; 1015 Object *chip = OBJECT(qdev_new(chip_typename)); 1016 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1017 1018 pnv->chips[i] = PNV_CHIP(chip); 1019 1020 /* Distribute RAM among the chips */ 1021 object_property_set_int(chip, "ram-start", chip_ram_start, 1022 &error_fatal); 1023 object_property_set_int(chip, "ram-size", chip_ram_size, 1024 &error_fatal); 1025 chip_ram_start += chip_ram_size; 1026 1027 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1028 object_property_add_child(OBJECT(pnv), chip_name, chip); 1029 object_property_set_int(chip, "chip-id", i, &error_fatal); 1030 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1031 &error_fatal); 1032 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1033 &error_fatal); 1034 /* 1035 * The POWER8 machine use the XICS interrupt interface. 1036 * Propagate the XICS fabric to the chip and its controllers. 1037 */ 1038 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1039 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1040 } 1041 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1042 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1043 &error_abort); 1044 } 1045 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1046 } 1047 g_free(chip_typename); 1048 1049 /* Instantiate ISA bus on chip 0 */ 1050 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1051 1052 /* Create serial port */ 1053 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1054 1055 /* Create an RTC ISA device too */ 1056 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1057 1058 /* 1059 * Create the machine BMC simulator and the IPMI BT device for 1060 * communication with the BMC 1061 */ 1062 if (defaults_enabled()) { 1063 pnv->bmc = pnv_bmc_create(pnv->pnor); 1064 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1065 } 1066 1067 /* 1068 * The PNOR is mapped on the LPC FW address space by the BMC. 1069 * Since we can not reach the remote BMC machine with LPC memops, 1070 * map it always for now. 1071 */ 1072 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1073 &pnv->pnor->mmio); 1074 1075 /* 1076 * OpenPOWER systems use a IPMI SEL Event message to notify the 1077 * host to powerdown 1078 */ 1079 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1080 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1081 1082 /* 1083 * Create/Connect any machine-specific I2C devices 1084 */ 1085 if (pmc->i2c_init) { 1086 pmc->i2c_init(pnv); 1087 } 1088 } 1089 1090 /* 1091 * 0:21 Reserved - Read as zeros 1092 * 22:24 Chip ID 1093 * 25:28 Core number 1094 * 29:31 Thread ID 1095 */ 1096 static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, 1097 uint32_t thread_id) 1098 { 1099 return (chip->chip_id << 7) | (core_id << 3) | thread_id; 1100 } 1101 1102 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1103 Error **errp) 1104 { 1105 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1106 Error *local_err = NULL; 1107 Object *obj; 1108 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1109 1110 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1111 if (local_err) { 1112 error_propagate(errp, local_err); 1113 return; 1114 } 1115 1116 pnv_cpu->intc = obj; 1117 } 1118 1119 1120 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1121 { 1122 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1123 1124 icp_reset(ICP(pnv_cpu->intc)); 1125 } 1126 1127 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1128 { 1129 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1130 1131 icp_destroy(ICP(pnv_cpu->intc)); 1132 pnv_cpu->intc = NULL; 1133 } 1134 1135 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1136 GString *buf) 1137 { 1138 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1139 } 1140 1141 /* 1142 * 0:48 Reserved - Read as zeroes 1143 * 49:52 Node ID 1144 * 53:55 Chip ID 1145 * 56 Reserved - Read as zero 1146 * 57:61 Core number 1147 * 62:63 Thread ID 1148 * 1149 * We only care about the lower bits. uint32_t is fine for the moment. 1150 */ 1151 static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, 1152 uint32_t thread_id) 1153 { 1154 if (chip->nr_threads == 8) { 1155 return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) | 1156 (thread_id >> 1); 1157 } else { 1158 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1159 } 1160 } 1161 1162 /* 1163 * 0:48 Reserved - Read as zeroes 1164 * 49:52 Node ID 1165 * 53:55 Chip ID 1166 * 56 Reserved - Read as zero 1167 * 57:59 Quad ID 1168 * 60 Core Chiplet Pair ID 1169 * 61:63 Thread/Core Chiplet ID t0-t2 1170 * 1171 * We only care about the lower bits. uint32_t is fine for the moment. 1172 */ 1173 static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, 1174 uint32_t thread_id) 1175 { 1176 if (chip->nr_threads == 8) { 1177 return (chip->chip_id << 8) | ((core_id / 4) << 4) | 1178 ((core_id % 2) << 3) | thread_id; 1179 } else { 1180 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1181 } 1182 } 1183 1184 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1185 Error **errp) 1186 { 1187 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1188 Error *local_err = NULL; 1189 Object *obj; 1190 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1191 1192 /* 1193 * The core creates its interrupt presenter but the XIVE interrupt 1194 * controller object is initialized afterwards. Hopefully, it's 1195 * only used at runtime. 1196 */ 1197 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1198 &local_err); 1199 if (local_err) { 1200 error_propagate(errp, local_err); 1201 return; 1202 } 1203 1204 pnv_cpu->intc = obj; 1205 } 1206 1207 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1208 { 1209 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1210 1211 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1212 } 1213 1214 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1215 { 1216 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1217 1218 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1219 pnv_cpu->intc = NULL; 1220 } 1221 1222 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1223 GString *buf) 1224 { 1225 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1226 } 1227 1228 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1229 Error **errp) 1230 { 1231 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1232 Error *local_err = NULL; 1233 Object *obj; 1234 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1235 1236 /* 1237 * The core creates its interrupt presenter but the XIVE2 interrupt 1238 * controller object is initialized afterwards. Hopefully, it's 1239 * only used at runtime. 1240 */ 1241 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1242 &local_err); 1243 if (local_err) { 1244 error_propagate(errp, local_err); 1245 return; 1246 } 1247 1248 pnv_cpu->intc = obj; 1249 } 1250 1251 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1252 { 1253 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1254 1255 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1256 } 1257 1258 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1259 { 1260 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1261 1262 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1263 pnv_cpu->intc = NULL; 1264 } 1265 1266 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1267 GString *buf) 1268 { 1269 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1270 } 1271 1272 /* 1273 * Allowed core identifiers on a POWER8 Processor Chip : 1274 * 1275 * <EX0 reserved> 1276 * EX1 - Venice only 1277 * EX2 - Venice only 1278 * EX3 - Venice only 1279 * EX4 1280 * EX5 1281 * EX6 1282 * <EX7,8 reserved> <reserved> 1283 * EX9 - Venice only 1284 * EX10 - Venice only 1285 * EX11 - Venice only 1286 * EX12 1287 * EX13 1288 * EX14 1289 * <EX15 reserved> 1290 */ 1291 #define POWER8E_CORE_MASK (0x7070ull) 1292 #define POWER8_CORE_MASK (0x7e7eull) 1293 1294 /* 1295 * POWER9 has 24 cores, ids starting at 0x0 1296 */ 1297 #define POWER9_CORE_MASK (0xffffffffffffffull) 1298 1299 1300 #define POWER10_CORE_MASK (0xffffffffffffffull) 1301 1302 static void pnv_chip_power8_instance_init(Object *obj) 1303 { 1304 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1305 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1306 int i; 1307 1308 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1309 (Object **)&chip8->xics, 1310 object_property_allow_set_link, 1311 OBJ_PROP_LINK_STRONG); 1312 1313 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1314 1315 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1316 1317 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1318 1319 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1320 1321 if (defaults_enabled()) { 1322 chip8->num_phbs = pcc->num_phbs; 1323 1324 for (i = 0; i < chip8->num_phbs; i++) { 1325 Object *phb = object_new(TYPE_PNV_PHB); 1326 1327 /* 1328 * We need the chip to parent the PHB to allow the DT 1329 * to build correctly (via pnv_xscom_dt()). 1330 * 1331 * TODO: the PHB should be parented by a PEC device that, at 1332 * this moment, is not modelled powernv8/phb3. 1333 */ 1334 object_property_add_child(obj, "phb[*]", phb); 1335 chip8->phbs[i] = PNV_PHB(phb); 1336 } 1337 } 1338 1339 } 1340 1341 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1342 { 1343 PnvChip *chip = PNV_CHIP(chip8); 1344 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1345 int i, j; 1346 char *name; 1347 1348 name = g_strdup_printf("icp-%x", chip->chip_id); 1349 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1350 g_free(name); 1351 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1352 &chip8->icp_mmio); 1353 1354 /* Map the ICP registers for each thread */ 1355 for (i = 0; i < chip->nr_cores; i++) { 1356 PnvCore *pnv_core = chip->cores[i]; 1357 int core_hwid = CPU_CORE(pnv_core)->core_id; 1358 1359 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1360 uint32_t pir = pcc->chip_pir(chip, core_hwid, j); 1361 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1362 1363 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1364 &icp->mmio); 1365 } 1366 } 1367 } 1368 1369 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1370 { 1371 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1372 PnvChip *chip = PNV_CHIP(dev); 1373 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1374 Pnv8Psi *psi8 = &chip8->psi; 1375 Error *local_err = NULL; 1376 int i; 1377 1378 assert(chip8->xics); 1379 1380 /* XSCOM bridge is first */ 1381 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1382 1383 pcc->parent_realize(dev, &local_err); 1384 if (local_err) { 1385 error_propagate(errp, local_err); 1386 return; 1387 } 1388 1389 /* Processor Service Interface (PSI) Host Bridge */ 1390 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1391 &error_fatal); 1392 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1393 OBJECT(chip8->xics), &error_abort); 1394 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1395 return; 1396 } 1397 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1398 &PNV_PSI(psi8)->xscom_regs); 1399 1400 /* Create LPC controller */ 1401 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1402 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1403 1404 chip->fw_mr = &chip8->lpc.isa_fw; 1405 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1406 (uint64_t) PNV_XSCOM_BASE(chip), 1407 PNV_XSCOM_LPC_BASE); 1408 1409 /* 1410 * Interrupt Management Area. This is the memory region holding 1411 * all the Interrupt Control Presenter (ICP) registers 1412 */ 1413 pnv_chip_icp_realize(chip8, &local_err); 1414 if (local_err) { 1415 error_propagate(errp, local_err); 1416 return; 1417 } 1418 1419 /* Create the simplified OCC model */ 1420 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1421 return; 1422 } 1423 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1424 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1425 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1426 1427 /* OCC SRAM model */ 1428 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1429 &chip8->occ.sram_regs); 1430 1431 /* HOMER */ 1432 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1433 &error_abort); 1434 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1435 return; 1436 } 1437 /* Homer Xscom region */ 1438 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1439 1440 /* Homer mmio region */ 1441 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1442 &chip8->homer.regs); 1443 1444 /* PHB controllers */ 1445 for (i = 0; i < chip8->num_phbs; i++) { 1446 PnvPHB *phb = chip8->phbs[i]; 1447 1448 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1449 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1450 &error_fatal); 1451 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1452 &error_fatal); 1453 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1454 return; 1455 } 1456 } 1457 } 1458 1459 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1460 { 1461 addr &= (PNV_XSCOM_SIZE - 1); 1462 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1463 } 1464 1465 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1466 { 1467 DeviceClass *dc = DEVICE_CLASS(klass); 1468 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1469 1470 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1471 k->cores_mask = POWER8E_CORE_MASK; 1472 k->num_phbs = 3; 1473 k->chip_pir = pnv_chip_pir_p8; 1474 k->intc_create = pnv_chip_power8_intc_create; 1475 k->intc_reset = pnv_chip_power8_intc_reset; 1476 k->intc_destroy = pnv_chip_power8_intc_destroy; 1477 k->intc_print_info = pnv_chip_power8_intc_print_info; 1478 k->isa_create = pnv_chip_power8_isa_create; 1479 k->dt_populate = pnv_chip_power8_dt_populate; 1480 k->pic_print_info = pnv_chip_power8_pic_print_info; 1481 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1482 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1483 dc->desc = "PowerNV Chip POWER8E"; 1484 1485 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1486 &k->parent_realize); 1487 } 1488 1489 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1490 { 1491 DeviceClass *dc = DEVICE_CLASS(klass); 1492 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1493 1494 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1495 k->cores_mask = POWER8_CORE_MASK; 1496 k->num_phbs = 3; 1497 k->chip_pir = pnv_chip_pir_p8; 1498 k->intc_create = pnv_chip_power8_intc_create; 1499 k->intc_reset = pnv_chip_power8_intc_reset; 1500 k->intc_destroy = pnv_chip_power8_intc_destroy; 1501 k->intc_print_info = pnv_chip_power8_intc_print_info; 1502 k->isa_create = pnv_chip_power8_isa_create; 1503 k->dt_populate = pnv_chip_power8_dt_populate; 1504 k->pic_print_info = pnv_chip_power8_pic_print_info; 1505 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1506 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1507 dc->desc = "PowerNV Chip POWER8"; 1508 1509 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1510 &k->parent_realize); 1511 } 1512 1513 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1514 { 1515 DeviceClass *dc = DEVICE_CLASS(klass); 1516 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1517 1518 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1519 k->cores_mask = POWER8_CORE_MASK; 1520 k->num_phbs = 4; 1521 k->chip_pir = pnv_chip_pir_p8; 1522 k->intc_create = pnv_chip_power8_intc_create; 1523 k->intc_reset = pnv_chip_power8_intc_reset; 1524 k->intc_destroy = pnv_chip_power8_intc_destroy; 1525 k->intc_print_info = pnv_chip_power8_intc_print_info; 1526 k->isa_create = pnv_chip_power8nvl_isa_create; 1527 k->dt_populate = pnv_chip_power8_dt_populate; 1528 k->pic_print_info = pnv_chip_power8_pic_print_info; 1529 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1530 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1531 dc->desc = "PowerNV Chip POWER8NVL"; 1532 1533 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1534 &k->parent_realize); 1535 } 1536 1537 static void pnv_chip_power9_instance_init(Object *obj) 1538 { 1539 PnvChip *chip = PNV_CHIP(obj); 1540 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1541 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1542 int i; 1543 1544 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1545 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1546 "xive-fabric"); 1547 1548 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1549 1550 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1551 1552 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1553 1554 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1555 1556 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1557 1558 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1559 1560 /* Number of PECs is the chip default */ 1561 chip->num_pecs = pcc->num_pecs; 1562 1563 for (i = 0; i < chip->num_pecs; i++) { 1564 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1565 TYPE_PNV_PHB4_PEC); 1566 } 1567 1568 for (i = 0; i < pcc->i2c_num_engines; i++) { 1569 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1570 } 1571 } 1572 1573 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1574 PnvCore *pnv_core, 1575 const char *type) 1576 { 1577 char eq_name[32]; 1578 int core_id = CPU_CORE(pnv_core)->core_id; 1579 1580 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1581 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1582 sizeof(*eq), type, 1583 &error_fatal, NULL); 1584 1585 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1586 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1587 } 1588 1589 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1590 { 1591 PnvChip *chip = PNV_CHIP(chip9); 1592 int i; 1593 1594 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1595 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1596 1597 for (i = 0; i < chip9->nr_quads; i++) { 1598 PnvQuad *eq = &chip9->quads[i]; 1599 1600 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1601 PNV_QUAD_TYPE_NAME("power9")); 1602 1603 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1604 &eq->xscom_regs); 1605 } 1606 } 1607 1608 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1609 { 1610 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1611 int i; 1612 1613 for (i = 0; i < chip->num_pecs; i++) { 1614 PnvPhb4PecState *pec = &chip9->pecs[i]; 1615 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1616 uint32_t pec_nest_base; 1617 uint32_t pec_pci_base; 1618 1619 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1620 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1621 &error_fatal); 1622 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1623 &error_fatal); 1624 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1625 return; 1626 } 1627 1628 pec_nest_base = pecc->xscom_nest_base(pec); 1629 pec_pci_base = pecc->xscom_pci_base(pec); 1630 1631 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1632 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1633 } 1634 } 1635 1636 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1637 { 1638 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1639 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1640 PnvChip *chip = PNV_CHIP(dev); 1641 Pnv9Psi *psi9 = &chip9->psi; 1642 Error *local_err = NULL; 1643 int i; 1644 1645 /* XSCOM bridge is first */ 1646 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1647 1648 pcc->parent_realize(dev, &local_err); 1649 if (local_err) { 1650 error_propagate(errp, local_err); 1651 return; 1652 } 1653 1654 pnv_chip_quad_realize(chip9, &local_err); 1655 if (local_err) { 1656 error_propagate(errp, local_err); 1657 return; 1658 } 1659 1660 /* XIVE interrupt controller (POWER9) */ 1661 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1662 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1663 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1664 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1665 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1666 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1667 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1668 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1669 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1670 &error_abort); 1671 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1672 return; 1673 } 1674 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1675 &chip9->xive.xscom_regs); 1676 1677 /* Processor Service Interface (PSI) Host Bridge */ 1678 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1679 &error_fatal); 1680 /* This is the only device with 4k ESB pages */ 1681 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1682 &error_fatal); 1683 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1684 return; 1685 } 1686 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1687 &PNV_PSI(psi9)->xscom_regs); 1688 1689 /* LPC */ 1690 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1691 return; 1692 } 1693 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1694 &chip9->lpc.xscom_regs); 1695 1696 chip->fw_mr = &chip9->lpc.isa_fw; 1697 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1698 (uint64_t) PNV9_LPCM_BASE(chip)); 1699 1700 /* ChipTOD */ 1701 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1702 chip->chip_id == 0, &error_abort); 1703 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1704 chip->chip_id == 1, &error_abort); 1705 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1706 &error_abort); 1707 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1708 return; 1709 } 1710 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1711 &chip9->chiptod.xscom_regs); 1712 1713 /* Create the simplified OCC model */ 1714 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1715 return; 1716 } 1717 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1718 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1719 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1720 1721 /* OCC SRAM model */ 1722 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1723 &chip9->occ.sram_regs); 1724 1725 /* SBE */ 1726 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1727 return; 1728 } 1729 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1730 &chip9->sbe.xscom_ctrl_regs); 1731 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1732 &chip9->sbe.xscom_mbox_regs); 1733 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1734 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1735 1736 /* HOMER */ 1737 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1738 &error_abort); 1739 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1740 return; 1741 } 1742 /* Homer Xscom region */ 1743 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1744 1745 /* Homer mmio region */ 1746 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1747 &chip9->homer.regs); 1748 1749 /* PEC PHBs */ 1750 pnv_chip_power9_pec_realize(chip, &local_err); 1751 if (local_err) { 1752 error_propagate(errp, local_err); 1753 return; 1754 } 1755 1756 /* 1757 * I2C 1758 */ 1759 for (i = 0; i < pcc->i2c_num_engines; i++) { 1760 Object *obj = OBJECT(&chip9->i2c[i]); 1761 1762 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1763 object_property_set_int(obj, "num-busses", 1764 pcc->i2c_ports_per_engine[i], 1765 &error_fatal); 1766 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1767 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1768 return; 1769 } 1770 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1771 (chip9->i2c[i].engine - 1) * 1772 PNV9_XSCOM_I2CM_SIZE, 1773 &chip9->i2c[i].xscom_regs); 1774 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1775 qdev_get_gpio_in(DEVICE(psi9), 1776 PSIHB9_IRQ_SBE_I2C)); 1777 } 1778 } 1779 1780 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1781 { 1782 addr &= (PNV9_XSCOM_SIZE - 1); 1783 return addr >> 3; 1784 } 1785 1786 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1787 { 1788 DeviceClass *dc = DEVICE_CLASS(klass); 1789 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1790 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1791 1792 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1793 k->cores_mask = POWER9_CORE_MASK; 1794 k->chip_pir = pnv_chip_pir_p9; 1795 k->intc_create = pnv_chip_power9_intc_create; 1796 k->intc_reset = pnv_chip_power9_intc_reset; 1797 k->intc_destroy = pnv_chip_power9_intc_destroy; 1798 k->intc_print_info = pnv_chip_power9_intc_print_info; 1799 k->isa_create = pnv_chip_power9_isa_create; 1800 k->dt_populate = pnv_chip_power9_dt_populate; 1801 k->pic_print_info = pnv_chip_power9_pic_print_info; 1802 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1803 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1804 dc->desc = "PowerNV Chip POWER9"; 1805 k->num_pecs = PNV9_CHIP_MAX_PEC; 1806 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1807 k->i2c_ports_per_engine = i2c_ports_per_engine; 1808 1809 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1810 &k->parent_realize); 1811 } 1812 1813 static void pnv_chip_power10_instance_init(Object *obj) 1814 { 1815 PnvChip *chip = PNV_CHIP(obj); 1816 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1817 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1818 int i; 1819 1820 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1821 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1822 "xive-fabric"); 1823 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1824 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1825 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1826 TYPE_PNV10_CHIPTOD); 1827 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1828 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1829 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1830 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1831 TYPE_PNV_N1_CHIPLET); 1832 1833 chip->num_pecs = pcc->num_pecs; 1834 1835 for (i = 0; i < chip->num_pecs; i++) { 1836 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1837 TYPE_PNV_PHB5_PEC); 1838 } 1839 1840 for (i = 0; i < pcc->i2c_num_engines; i++) { 1841 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1842 } 1843 } 1844 1845 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1846 { 1847 PnvChip *chip = PNV_CHIP(chip10); 1848 int i; 1849 1850 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1851 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1852 1853 for (i = 0; i < chip10->nr_quads; i++) { 1854 PnvQuad *eq = &chip10->quads[i]; 1855 1856 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1857 PNV_QUAD_TYPE_NAME("power10")); 1858 1859 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1860 &eq->xscom_regs); 1861 1862 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1863 &eq->xscom_qme_regs); 1864 } 1865 } 1866 1867 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1868 { 1869 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1870 int i; 1871 1872 for (i = 0; i < chip->num_pecs; i++) { 1873 PnvPhb4PecState *pec = &chip10->pecs[i]; 1874 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1875 uint32_t pec_nest_base; 1876 uint32_t pec_pci_base; 1877 1878 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1879 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1880 &error_fatal); 1881 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1882 &error_fatal); 1883 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1884 return; 1885 } 1886 1887 pec_nest_base = pecc->xscom_nest_base(pec); 1888 pec_pci_base = pecc->xscom_pci_base(pec); 1889 1890 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1891 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1892 } 1893 } 1894 1895 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1896 { 1897 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1898 PnvChip *chip = PNV_CHIP(dev); 1899 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1900 Error *local_err = NULL; 1901 int i; 1902 1903 /* XSCOM bridge is first */ 1904 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1905 1906 pcc->parent_realize(dev, &local_err); 1907 if (local_err) { 1908 error_propagate(errp, local_err); 1909 return; 1910 } 1911 1912 pnv_chip_power10_quad_realize(chip10, &local_err); 1913 if (local_err) { 1914 error_propagate(errp, local_err); 1915 return; 1916 } 1917 1918 /* XIVE2 interrupt controller (POWER10) */ 1919 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1920 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1921 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1922 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1923 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1924 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1925 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1926 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1927 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1928 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1929 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1930 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1931 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1932 &error_abort); 1933 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1934 return; 1935 } 1936 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1937 &chip10->xive.xscom_regs); 1938 1939 /* Processor Service Interface (PSI) Host Bridge */ 1940 object_property_set_int(OBJECT(&chip10->psi), "bar", 1941 PNV10_PSIHB_BASE(chip), &error_fatal); 1942 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1943 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1944 &error_fatal); 1945 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1946 return; 1947 } 1948 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1949 &PNV_PSI(&chip10->psi)->xscom_regs); 1950 1951 /* LPC */ 1952 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1953 return; 1954 } 1955 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1956 &chip10->lpc.xscom_regs); 1957 1958 chip->fw_mr = &chip10->lpc.isa_fw; 1959 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1960 (uint64_t) PNV10_LPCM_BASE(chip)); 1961 1962 /* ChipTOD */ 1963 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1964 chip->chip_id == 0, &error_abort); 1965 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1966 chip->chip_id == 1, &error_abort); 1967 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 1968 &error_abort); 1969 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 1970 return; 1971 } 1972 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 1973 &chip10->chiptod.xscom_regs); 1974 1975 /* Create the simplified OCC model */ 1976 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1977 return; 1978 } 1979 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1980 &chip10->occ.xscom_regs); 1981 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1982 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1983 1984 /* OCC SRAM model */ 1985 memory_region_add_subregion(get_system_memory(), 1986 PNV10_OCC_SENSOR_BASE(chip), 1987 &chip10->occ.sram_regs); 1988 1989 /* SBE */ 1990 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1991 return; 1992 } 1993 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1994 &chip10->sbe.xscom_ctrl_regs); 1995 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1996 &chip10->sbe.xscom_mbox_regs); 1997 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1998 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1999 2000 /* HOMER */ 2001 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 2002 &error_abort); 2003 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 2004 return; 2005 } 2006 /* Homer Xscom region */ 2007 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 2008 &chip10->homer.pba_regs); 2009 2010 /* Homer mmio region */ 2011 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2012 &chip10->homer.regs); 2013 2014 /* N1 chiplet */ 2015 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2016 return; 2017 } 2018 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2019 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2020 2021 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2022 &chip10->n1_chiplet.xscom_pb_eq_mr); 2023 2024 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2025 &chip10->n1_chiplet.xscom_pb_es_mr); 2026 2027 /* PHBs */ 2028 pnv_chip_power10_phb_realize(chip, &local_err); 2029 if (local_err) { 2030 error_propagate(errp, local_err); 2031 return; 2032 } 2033 2034 2035 /* 2036 * I2C 2037 */ 2038 for (i = 0; i < pcc->i2c_num_engines; i++) { 2039 Object *obj = OBJECT(&chip10->i2c[i]); 2040 2041 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2042 object_property_set_int(obj, "num-busses", 2043 pcc->i2c_ports_per_engine[i], 2044 &error_fatal); 2045 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2046 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2047 return; 2048 } 2049 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2050 (chip10->i2c[i].engine - 1) * 2051 PNV10_XSCOM_I2CM_SIZE, 2052 &chip10->i2c[i].xscom_regs); 2053 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2054 qdev_get_gpio_in(DEVICE(&chip10->psi), 2055 PSIHB9_IRQ_SBE_I2C)); 2056 } 2057 2058 } 2059 2060 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2061 { 2062 int i; 2063 for (i = 0; i < pnv->num_chips; i++) { 2064 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2065 2066 /* 2067 * Add a PCA9552 I2C device for PCIe hotplug control 2068 * to engine 2, bus 1, address 0x63 2069 */ 2070 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2071 "pca9552", 0x63); 2072 2073 /* 2074 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2075 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2076 * after hypervisor code sets a SLOTx_EN pin high. 2077 */ 2078 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2079 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2080 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2081 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2082 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2083 2084 /* 2085 * Add a PCA9554 I2C device for cable card presence detection 2086 * to engine 2, bus 1, address 0x25 2087 */ 2088 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2089 } 2090 } 2091 2092 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2093 { 2094 addr &= (PNV10_XSCOM_SIZE - 1); 2095 return addr >> 3; 2096 } 2097 2098 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2099 { 2100 DeviceClass *dc = DEVICE_CLASS(klass); 2101 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2102 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2103 2104 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 2105 k->cores_mask = POWER10_CORE_MASK; 2106 k->chip_pir = pnv_chip_pir_p10; 2107 k->intc_create = pnv_chip_power10_intc_create; 2108 k->intc_reset = pnv_chip_power10_intc_reset; 2109 k->intc_destroy = pnv_chip_power10_intc_destroy; 2110 k->intc_print_info = pnv_chip_power10_intc_print_info; 2111 k->isa_create = pnv_chip_power10_isa_create; 2112 k->dt_populate = pnv_chip_power10_dt_populate; 2113 k->pic_print_info = pnv_chip_power10_pic_print_info; 2114 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2115 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2116 dc->desc = "PowerNV Chip POWER10"; 2117 k->num_pecs = PNV10_CHIP_MAX_PEC; 2118 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2119 k->i2c_ports_per_engine = i2c_ports_per_engine; 2120 2121 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2122 &k->parent_realize); 2123 } 2124 2125 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2126 { 2127 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2128 int cores_max; 2129 2130 /* 2131 * No custom mask for this chip, let's use the default one from * 2132 * the chip class 2133 */ 2134 if (!chip->cores_mask) { 2135 chip->cores_mask = pcc->cores_mask; 2136 } 2137 2138 /* filter alien core ids ! some are reserved */ 2139 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2140 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2141 chip->cores_mask); 2142 return; 2143 } 2144 chip->cores_mask &= pcc->cores_mask; 2145 2146 /* now that we have a sane layout, let check the number of cores */ 2147 cores_max = ctpop64(chip->cores_mask); 2148 if (chip->nr_cores > cores_max) { 2149 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2150 cores_max); 2151 return; 2152 } 2153 } 2154 2155 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2156 { 2157 Error *error = NULL; 2158 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2159 const char *typename = pnv_chip_core_typename(chip); 2160 int i, core_hwid; 2161 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2162 2163 if (!object_class_by_name(typename)) { 2164 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2165 return; 2166 } 2167 2168 /* Cores */ 2169 pnv_chip_core_sanitize(chip, &error); 2170 if (error) { 2171 error_propagate(errp, error); 2172 return; 2173 } 2174 2175 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2176 2177 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2178 && (i < chip->nr_cores); core_hwid++) { 2179 char core_name[32]; 2180 PnvCore *pnv_core; 2181 uint64_t xscom_core_base; 2182 2183 if (!(chip->cores_mask & (1ull << core_hwid))) { 2184 continue; 2185 } 2186 2187 pnv_core = PNV_CORE(object_new(typename)); 2188 2189 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2190 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2191 chip->cores[i] = pnv_core; 2192 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2193 chip->nr_threads, &error_fatal); 2194 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2195 core_hwid, &error_fatal); 2196 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2197 &error_fatal); 2198 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2199 &error_fatal); 2200 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2201 &error_abort); 2202 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2203 2204 /* Each core has an XSCOM MMIO region */ 2205 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2206 2207 pnv_xscom_add_subregion(chip, xscom_core_base, 2208 &pnv_core->xscom_regs); 2209 i++; 2210 } 2211 } 2212 2213 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2214 { 2215 PnvChip *chip = PNV_CHIP(dev); 2216 Error *error = NULL; 2217 2218 /* Cores */ 2219 pnv_chip_core_realize(chip, &error); 2220 if (error) { 2221 error_propagate(errp, error); 2222 return; 2223 } 2224 } 2225 2226 static Property pnv_chip_properties[] = { 2227 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2228 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2229 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2230 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2231 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2232 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2233 DEFINE_PROP_END_OF_LIST(), 2234 }; 2235 2236 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2237 { 2238 DeviceClass *dc = DEVICE_CLASS(klass); 2239 2240 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2241 dc->realize = pnv_chip_realize; 2242 device_class_set_props(dc, pnv_chip_properties); 2243 dc->desc = "PowerNV Chip"; 2244 } 2245 2246 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2247 { 2248 int i; 2249 2250 for (i = 0; i < chip->nr_cores; i++) { 2251 PnvCore *pc = chip->cores[i]; 2252 CPUCore *cc = CPU_CORE(pc); 2253 2254 if (cc->core_id == core_id) { 2255 return pc; 2256 } 2257 } 2258 return NULL; 2259 } 2260 2261 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2262 { 2263 int i, j; 2264 2265 for (i = 0; i < chip->nr_cores; i++) { 2266 PnvCore *pc = chip->cores[i]; 2267 CPUCore *cc = CPU_CORE(pc); 2268 2269 for (j = 0; j < cc->nr_threads; j++) { 2270 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2271 return pc->threads[j]; 2272 } 2273 } 2274 } 2275 return NULL; 2276 } 2277 2278 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2279 { 2280 PnvMachineState *pnv = PNV_MACHINE(xi); 2281 int i, j; 2282 2283 for (i = 0; i < pnv->num_chips; i++) { 2284 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2285 2286 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2287 return &chip8->psi.ics; 2288 } 2289 2290 for (j = 0; j < chip8->num_phbs; j++) { 2291 PnvPHB *phb = chip8->phbs[j]; 2292 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2293 2294 if (ics_valid_irq(&phb3->lsis, irq)) { 2295 return &phb3->lsis; 2296 } 2297 2298 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2299 return ICS(&phb3->msis); 2300 } 2301 } 2302 } 2303 return NULL; 2304 } 2305 2306 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2307 { 2308 int i; 2309 2310 for (i = 0; i < pnv->num_chips; i++) { 2311 PnvChip *chip = pnv->chips[i]; 2312 if (chip->chip_id == chip_id) { 2313 return chip; 2314 } 2315 } 2316 return NULL; 2317 } 2318 2319 static void pnv_ics_resend(XICSFabric *xi) 2320 { 2321 PnvMachineState *pnv = PNV_MACHINE(xi); 2322 int i, j; 2323 2324 for (i = 0; i < pnv->num_chips; i++) { 2325 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2326 2327 ics_resend(&chip8->psi.ics); 2328 2329 for (j = 0; j < chip8->num_phbs; j++) { 2330 PnvPHB *phb = chip8->phbs[j]; 2331 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2332 2333 ics_resend(&phb3->lsis); 2334 ics_resend(ICS(&phb3->msis)); 2335 } 2336 } 2337 } 2338 2339 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2340 { 2341 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2342 2343 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2344 } 2345 2346 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2347 Monitor *mon) 2348 { 2349 PnvMachineState *pnv = PNV_MACHINE(obj); 2350 int i; 2351 CPUState *cs; 2352 g_autoptr(GString) buf = g_string_new(""); 2353 g_autoptr(HumanReadableText) info = NULL; 2354 2355 CPU_FOREACH(cs) { 2356 PowerPCCPU *cpu = POWERPC_CPU(cs); 2357 2358 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2359 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2360 buf); 2361 } 2362 info = human_readable_text_from_str(buf); 2363 monitor_puts(mon, info->human_readable_text); 2364 2365 for (i = 0; i < pnv->num_chips; i++) { 2366 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2367 } 2368 } 2369 2370 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2371 uint8_t nvt_blk, uint32_t nvt_idx, 2372 bool cam_ignore, uint8_t priority, 2373 uint32_t logic_serv, 2374 XiveTCTXMatch *match) 2375 { 2376 PnvMachineState *pnv = PNV_MACHINE(xfb); 2377 int total_count = 0; 2378 int i; 2379 2380 for (i = 0; i < pnv->num_chips; i++) { 2381 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2382 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2383 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2384 int count; 2385 2386 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2387 priority, logic_serv, match); 2388 2389 if (count < 0) { 2390 return count; 2391 } 2392 2393 total_count += count; 2394 } 2395 2396 return total_count; 2397 } 2398 2399 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2400 uint8_t nvt_blk, uint32_t nvt_idx, 2401 bool cam_ignore, uint8_t priority, 2402 uint32_t logic_serv, 2403 XiveTCTXMatch *match) 2404 { 2405 PnvMachineState *pnv = PNV_MACHINE(xfb); 2406 int total_count = 0; 2407 int i; 2408 2409 for (i = 0; i < pnv->num_chips; i++) { 2410 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2411 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2412 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2413 int count; 2414 2415 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2416 priority, logic_serv, match); 2417 2418 if (count < 0) { 2419 return count; 2420 } 2421 2422 total_count += count; 2423 } 2424 2425 return total_count; 2426 } 2427 2428 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2429 { 2430 MachineClass *mc = MACHINE_CLASS(oc); 2431 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2432 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2433 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2434 2435 static GlobalProperty phb_compat[] = { 2436 { TYPE_PNV_PHB, "version", "3" }, 2437 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2438 }; 2439 2440 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2441 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2442 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2443 2444 xic->icp_get = pnv_icp_get; 2445 xic->ics_get = pnv_ics_get; 2446 xic->ics_resend = pnv_ics_resend; 2447 2448 pmc->compat = compat; 2449 pmc->compat_size = sizeof(compat); 2450 2451 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2452 } 2453 2454 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2455 { 2456 MachineClass *mc = MACHINE_CLASS(oc); 2457 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2458 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2459 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2460 2461 static GlobalProperty phb_compat[] = { 2462 { TYPE_PNV_PHB, "version", "4" }, 2463 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2464 }; 2465 2466 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2467 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2468 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2469 2470 xfc->match_nvt = pnv_match_nvt; 2471 2472 pmc->compat = compat; 2473 pmc->compat_size = sizeof(compat); 2474 pmc->dt_power_mgt = pnv_dt_power_mgt; 2475 2476 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2477 } 2478 2479 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2480 { 2481 MachineClass *mc = MACHINE_CLASS(oc); 2482 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2483 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2484 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2485 2486 static GlobalProperty phb_compat[] = { 2487 { TYPE_PNV_PHB, "version", "5" }, 2488 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2489 }; 2490 2491 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2492 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2493 2494 mc->alias = "powernv"; 2495 2496 pmc->compat = compat; 2497 pmc->compat_size = sizeof(compat); 2498 pmc->dt_power_mgt = pnv_dt_power_mgt; 2499 2500 xfc->match_nvt = pnv10_xive_match_nvt; 2501 2502 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2503 } 2504 2505 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2506 { 2507 MachineClass *mc = MACHINE_CLASS(oc); 2508 2509 pnv_machine_p10_common_class_init(oc, data); 2510 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2511 } 2512 2513 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2514 { 2515 MachineClass *mc = MACHINE_CLASS(oc); 2516 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2517 2518 pnv_machine_p10_common_class_init(oc, data); 2519 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2520 pmc->i2c_init = pnv_rainier_i2c_init; 2521 } 2522 2523 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2524 { 2525 PnvMachineState *pnv = PNV_MACHINE(obj); 2526 2527 return !!pnv->fw_load_addr; 2528 } 2529 2530 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2531 { 2532 PnvMachineState *pnv = PNV_MACHINE(obj); 2533 2534 if (value) { 2535 pnv->fw_load_addr = 0x8000000; 2536 } 2537 } 2538 2539 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2540 { 2541 CPUPPCState *env = cpu_env(cs); 2542 2543 cpu_synchronize_state(cs); 2544 ppc_cpu_do_system_reset(cs); 2545 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2546 /* 2547 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2548 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2549 * (PPC_BIT(43)). 2550 */ 2551 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2552 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2553 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2554 } 2555 } else { 2556 /* 2557 * For non-powersave system resets, SRR1[42:45] are defined to be 2558 * implementation-dependent. The POWER9 User Manual specifies that 2559 * an external (SCOM driven, which may come from a BMC nmi command or 2560 * another CPU requesting a NMI IPI) system reset exception should be 2561 * 0b0010 (PPC_BIT(44)). 2562 */ 2563 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2564 } 2565 } 2566 2567 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2568 { 2569 CPUState *cs; 2570 2571 CPU_FOREACH(cs) { 2572 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2573 } 2574 } 2575 2576 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2577 { 2578 MachineClass *mc = MACHINE_CLASS(oc); 2579 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2580 NMIClass *nc = NMI_CLASS(oc); 2581 2582 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2583 mc->init = pnv_init; 2584 mc->reset = pnv_reset; 2585 mc->max_cpus = MAX_CPUS; 2586 /* Pnv provides a AHCI device for storage */ 2587 mc->block_default_type = IF_IDE; 2588 mc->no_parallel = 1; 2589 mc->default_boot_order = NULL; 2590 /* 2591 * RAM defaults to less than 2048 for 32-bit hosts, and large 2592 * enough to fit the maximum initrd size at it's load address 2593 */ 2594 mc->default_ram_size = 1 * GiB; 2595 mc->default_ram_id = "pnv.ram"; 2596 ispc->print_info = pnv_pic_print_info; 2597 nc->nmi_monitor_handler = pnv_nmi; 2598 2599 object_class_property_add_bool(oc, "hb-mode", 2600 pnv_machine_get_hb, pnv_machine_set_hb); 2601 object_class_property_set_description(oc, "hb-mode", 2602 "Use a hostboot like boot loader"); 2603 } 2604 2605 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2606 { \ 2607 .name = type, \ 2608 .class_init = class_initfn, \ 2609 .parent = TYPE_PNV8_CHIP, \ 2610 } 2611 2612 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2613 { \ 2614 .name = type, \ 2615 .class_init = class_initfn, \ 2616 .parent = TYPE_PNV9_CHIP, \ 2617 } 2618 2619 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2620 { \ 2621 .name = type, \ 2622 .class_init = class_initfn, \ 2623 .parent = TYPE_PNV10_CHIP, \ 2624 } 2625 2626 static const TypeInfo types[] = { 2627 { 2628 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2629 .parent = MACHINE_TYPE_NAME("powernv10"), 2630 .class_init = pnv_machine_p10_rainier_class_init, 2631 }, 2632 { 2633 .name = MACHINE_TYPE_NAME("powernv10"), 2634 .parent = TYPE_PNV_MACHINE, 2635 .class_init = pnv_machine_power10_class_init, 2636 .interfaces = (InterfaceInfo[]) { 2637 { TYPE_XIVE_FABRIC }, 2638 { }, 2639 }, 2640 }, 2641 { 2642 .name = MACHINE_TYPE_NAME("powernv9"), 2643 .parent = TYPE_PNV_MACHINE, 2644 .class_init = pnv_machine_power9_class_init, 2645 .interfaces = (InterfaceInfo[]) { 2646 { TYPE_XIVE_FABRIC }, 2647 { }, 2648 }, 2649 }, 2650 { 2651 .name = MACHINE_TYPE_NAME("powernv8"), 2652 .parent = TYPE_PNV_MACHINE, 2653 .class_init = pnv_machine_power8_class_init, 2654 .interfaces = (InterfaceInfo[]) { 2655 { TYPE_XICS_FABRIC }, 2656 { }, 2657 }, 2658 }, 2659 { 2660 .name = TYPE_PNV_MACHINE, 2661 .parent = TYPE_MACHINE, 2662 .abstract = true, 2663 .instance_size = sizeof(PnvMachineState), 2664 .class_init = pnv_machine_class_init, 2665 .class_size = sizeof(PnvMachineClass), 2666 .interfaces = (InterfaceInfo[]) { 2667 { TYPE_INTERRUPT_STATS_PROVIDER }, 2668 { TYPE_NMI }, 2669 { }, 2670 }, 2671 }, 2672 { 2673 .name = TYPE_PNV_CHIP, 2674 .parent = TYPE_SYS_BUS_DEVICE, 2675 .class_init = pnv_chip_class_init, 2676 .instance_size = sizeof(PnvChip), 2677 .class_size = sizeof(PnvChipClass), 2678 .abstract = true, 2679 }, 2680 2681 /* 2682 * P10 chip and variants 2683 */ 2684 { 2685 .name = TYPE_PNV10_CHIP, 2686 .parent = TYPE_PNV_CHIP, 2687 .instance_init = pnv_chip_power10_instance_init, 2688 .instance_size = sizeof(Pnv10Chip), 2689 }, 2690 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2691 2692 /* 2693 * P9 chip and variants 2694 */ 2695 { 2696 .name = TYPE_PNV9_CHIP, 2697 .parent = TYPE_PNV_CHIP, 2698 .instance_init = pnv_chip_power9_instance_init, 2699 .instance_size = sizeof(Pnv9Chip), 2700 }, 2701 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2702 2703 /* 2704 * P8 chip and variants 2705 */ 2706 { 2707 .name = TYPE_PNV8_CHIP, 2708 .parent = TYPE_PNV_CHIP, 2709 .instance_init = pnv_chip_power8_instance_init, 2710 .instance_size = sizeof(Pnv8Chip), 2711 }, 2712 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2713 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2714 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2715 pnv_chip_power8nvl_class_init), 2716 }; 2717 2718 DEFINE_TYPES(types) 2719