1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "monitor/monitor.h" 42 #include "hw/intc/intc.h" 43 #include "hw/ipmi/ipmi.h" 44 #include "target/ppc/mmu-hash64.h" 45 #include "hw/pci/msi.h" 46 #include "hw/pci-host/pnv_phb.h" 47 48 #include "hw/ppc/xics.h" 49 #include "hw/qdev-properties.h" 50 #include "hw/ppc/pnv_xscom.h" 51 #include "hw/ppc/pnv_pnor.h" 52 53 #include "hw/isa/isa.h" 54 #include "hw/char/serial.h" 55 #include "hw/rtc/mc146818rtc.h" 56 57 #include <libfdt.h> 58 59 #define FDT_MAX_SIZE (1 * MiB) 60 61 #define FW_FILE_NAME "skiboot.lid" 62 #define FW_LOAD_ADDR 0x0 63 #define FW_MAX_SIZE (16 * MiB) 64 65 #define KERNEL_LOAD_ADDR 0x20000000 66 #define KERNEL_MAX_SIZE (128 * MiB) 67 #define INITRD_LOAD_ADDR 0x28000000 68 #define INITRD_MAX_SIZE (128 * MiB) 69 70 static const char *pnv_chip_core_typename(const PnvChip *o) 71 { 72 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 73 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 74 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 75 const char *core_type = object_class_get_name(object_class_by_name(s)); 76 g_free(s); 77 return core_type; 78 } 79 80 /* 81 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 82 * 4 * 4 sockets * 12 cores * 8 threads = 1536 83 * Let's make it 2^11 84 */ 85 #define MAX_CPUS 2048 86 87 /* 88 * Memory nodes are created by hostboot, one for each range of memory 89 * that has a different "affinity". In practice, it means one range 90 * per chip. 91 */ 92 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 93 { 94 char *mem_name; 95 uint64_t mem_reg_property[2]; 96 int off; 97 98 mem_reg_property[0] = cpu_to_be64(start); 99 mem_reg_property[1] = cpu_to_be64(size); 100 101 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 102 off = fdt_add_subnode(fdt, 0, mem_name); 103 g_free(mem_name); 104 105 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 106 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 107 sizeof(mem_reg_property)))); 108 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 109 } 110 111 static int get_cpus_node(void *fdt) 112 { 113 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 114 115 if (cpus_offset < 0) { 116 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 117 if (cpus_offset) { 118 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 119 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 120 } 121 } 122 _FDT(cpus_offset); 123 return cpus_offset; 124 } 125 126 /* 127 * The PowerNV cores (and threads) need to use real HW ids and not an 128 * incremental index like it has been done on other platforms. This HW 129 * id is stored in the CPU PIR, it is used to create cpu nodes in the 130 * device tree, used in XSCOM to address cores and in interrupt 131 * servers. 132 */ 133 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 134 { 135 PowerPCCPU *cpu = pc->threads[0]; 136 CPUState *cs = CPU(cpu); 137 DeviceClass *dc = DEVICE_GET_CLASS(cs); 138 int smt_threads = CPU_CORE(pc)->nr_threads; 139 CPUPPCState *env = &cpu->env; 140 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 141 uint32_t servers_prop[smt_threads]; 142 int i; 143 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 144 0xffffffff, 0xffffffff}; 145 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 146 uint32_t cpufreq = 1000000000; 147 uint32_t page_sizes_prop[64]; 148 size_t page_sizes_prop_size; 149 const uint8_t pa_features[] = { 24, 0, 150 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 151 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 153 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 154 int offset; 155 char *nodename; 156 int cpus_offset = get_cpus_node(fdt); 157 158 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 159 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 160 _FDT(offset); 161 g_free(nodename); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 164 165 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 167 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 168 169 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 173 env->dcache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 175 env->icache_line_size))); 176 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 177 env->icache_line_size))); 178 179 if (pcc->l1_dcache_size) { 180 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 181 pcc->l1_dcache_size))); 182 } else { 183 warn_report("Unknown L1 dcache size for cpu"); 184 } 185 if (pcc->l1_icache_size) { 186 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 187 pcc->l1_icache_size))); 188 } else { 189 warn_report("Unknown L1 icache size for cpu"); 190 } 191 192 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 193 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 194 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 195 cpu->hash64_opts->slb_size))); 196 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 197 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 198 199 if (ppc_has_spr(cpu, SPR_PURR)) { 200 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 201 } 202 203 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 204 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 205 segs, sizeof(segs)))); 206 } 207 208 /* 209 * Advertise VMX/VSX (vector extensions) if available 210 * 0 / no property == no vector extensions 211 * 1 == VMX / Altivec available 212 * 2 == VSX available 213 */ 214 if (env->insns_flags & PPC_ALTIVEC) { 215 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 216 217 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 218 } 219 220 /* 221 * Advertise DFP (Decimal Floating Point) if available 222 * 0 / no property == no DFP 223 * 1 == DFP available 224 */ 225 if (env->insns_flags2 & PPC2_DFP) { 226 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 227 } 228 229 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 230 sizeof(page_sizes_prop)); 231 if (page_sizes_prop_size) { 232 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 233 page_sizes_prop, page_sizes_prop_size))); 234 } 235 236 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 237 pa_features, sizeof(pa_features)))); 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pc->pir + i); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(servers_prop)))); 245 } 246 247 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 248 uint32_t nr_threads) 249 { 250 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 251 char *name; 252 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 253 uint32_t irange[2], i, rsize; 254 uint64_t *reg; 255 int offset; 256 257 irange[0] = cpu_to_be32(pir); 258 irange[1] = cpu_to_be32(nr_threads); 259 260 rsize = sizeof(uint64_t) * 2 * nr_threads; 261 reg = g_malloc(rsize); 262 for (i = 0; i < nr_threads; i++) { 263 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 264 reg[i * 2 + 1] = cpu_to_be64(0x1000); 265 } 266 267 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 268 offset = fdt_add_subnode(fdt, 0, name); 269 _FDT(offset); 270 g_free(name); 271 272 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 273 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 274 _FDT((fdt_setprop_string(fdt, offset, "device_type", 275 "PowerPC-External-Interrupt-Presentation"))); 276 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 277 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 278 irange, sizeof(irange)))); 279 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 280 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 281 g_free(reg); 282 } 283 284 /* 285 * Adds a PnvPHB to the chip. Returns the parent obj of the 286 * PHB which varies with each version (phb version 3 is parented 287 * by the chip, version 4 and 5 are parented by the PEC 288 * device). 289 * 290 * TODO: for version 3 we're still parenting the PHB with the 291 * chip. We should parent with a (so far not implemented) 292 * PHB3 PEC device. 293 */ 294 Object *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp) 295 { 296 if (phb->version == 3) { 297 return OBJECT(chip); 298 } else { 299 /* phb4 support will be added later */ 300 return NULL; 301 } 302 } 303 304 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 305 { 306 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 307 int i; 308 309 pnv_dt_xscom(chip, fdt, 0, 310 cpu_to_be64(PNV_XSCOM_BASE(chip)), 311 cpu_to_be64(PNV_XSCOM_SIZE), 312 compat, sizeof(compat)); 313 314 for (i = 0; i < chip->nr_cores; i++) { 315 PnvCore *pnv_core = chip->cores[i]; 316 317 pnv_dt_core(chip, pnv_core, fdt); 318 319 /* Interrupt Control Presenters (ICP). One per core. */ 320 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 321 } 322 323 if (chip->ram_size) { 324 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 325 } 326 } 327 328 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 329 { 330 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 331 int i; 332 333 pnv_dt_xscom(chip, fdt, 0, 334 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 335 cpu_to_be64(PNV9_XSCOM_SIZE), 336 compat, sizeof(compat)); 337 338 for (i = 0; i < chip->nr_cores; i++) { 339 PnvCore *pnv_core = chip->cores[i]; 340 341 pnv_dt_core(chip, pnv_core, fdt); 342 } 343 344 if (chip->ram_size) { 345 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 346 } 347 348 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 349 } 350 351 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 352 { 353 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 354 int i; 355 356 pnv_dt_xscom(chip, fdt, 0, 357 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 358 cpu_to_be64(PNV10_XSCOM_SIZE), 359 compat, sizeof(compat)); 360 361 for (i = 0; i < chip->nr_cores; i++) { 362 PnvCore *pnv_core = chip->cores[i]; 363 364 pnv_dt_core(chip, pnv_core, fdt); 365 } 366 367 if (chip->ram_size) { 368 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 369 } 370 371 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 372 } 373 374 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 375 { 376 uint32_t io_base = d->ioport_id; 377 uint32_t io_regs[] = { 378 cpu_to_be32(1), 379 cpu_to_be32(io_base), 380 cpu_to_be32(2) 381 }; 382 char *name; 383 int node; 384 385 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 386 node = fdt_add_subnode(fdt, lpc_off, name); 387 _FDT(node); 388 g_free(name); 389 390 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 391 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 392 } 393 394 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 395 { 396 const char compatible[] = "ns16550\0pnpPNP,501"; 397 uint32_t io_base = d->ioport_id; 398 uint32_t io_regs[] = { 399 cpu_to_be32(1), 400 cpu_to_be32(io_base), 401 cpu_to_be32(8) 402 }; 403 uint32_t irq; 404 char *name; 405 int node; 406 407 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 408 409 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 410 node = fdt_add_subnode(fdt, lpc_off, name); 411 _FDT(node); 412 g_free(name); 413 414 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 415 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 416 sizeof(compatible)))); 417 418 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 419 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 420 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 421 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 422 fdt_get_phandle(fdt, lpc_off)))); 423 424 /* This is needed by Linux */ 425 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 426 } 427 428 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 429 { 430 const char compatible[] = "bt\0ipmi-bt"; 431 uint32_t io_base; 432 uint32_t io_regs[] = { 433 cpu_to_be32(1), 434 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 435 cpu_to_be32(3) 436 }; 437 uint32_t irq; 438 char *name; 439 int node; 440 441 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 442 io_regs[1] = cpu_to_be32(io_base); 443 444 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 445 446 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 447 node = fdt_add_subnode(fdt, lpc_off, name); 448 _FDT(node); 449 g_free(name); 450 451 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 452 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 453 sizeof(compatible)))); 454 455 /* Mark it as reserved to avoid Linux trying to claim it */ 456 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 457 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 458 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 459 fdt_get_phandle(fdt, lpc_off)))); 460 } 461 462 typedef struct ForeachPopulateArgs { 463 void *fdt; 464 int offset; 465 } ForeachPopulateArgs; 466 467 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 468 { 469 ForeachPopulateArgs *args = opaque; 470 ISADevice *d = ISA_DEVICE(dev); 471 472 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 473 pnv_dt_rtc(d, args->fdt, args->offset); 474 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 475 pnv_dt_serial(d, args->fdt, args->offset); 476 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 477 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 478 } else { 479 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 480 d->ioport_id); 481 } 482 483 return 0; 484 } 485 486 /* 487 * The default LPC bus of a multichip system is on chip 0. It's 488 * recognized by the firmware (skiboot) using a "primary" property. 489 */ 490 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 491 { 492 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 493 ForeachPopulateArgs args = { 494 .fdt = fdt, 495 .offset = isa_offset, 496 }; 497 uint32_t phandle; 498 499 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 500 501 phandle = qemu_fdt_alloc_phandle(fdt); 502 assert(phandle > 0); 503 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 504 505 /* 506 * ISA devices are not necessarily parented to the ISA bus so we 507 * can not use object_child_foreach() 508 */ 509 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 510 &args); 511 } 512 513 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 514 { 515 int off; 516 517 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 518 off = fdt_add_subnode(fdt, off, "power-mgt"); 519 520 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 521 } 522 523 static void *pnv_dt_create(MachineState *machine) 524 { 525 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 526 PnvMachineState *pnv = PNV_MACHINE(machine); 527 void *fdt; 528 char *buf; 529 int off; 530 int i; 531 532 fdt = g_malloc0(FDT_MAX_SIZE); 533 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 534 535 /* /qemu node */ 536 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 537 538 /* Root node */ 539 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 540 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 541 _FDT((fdt_setprop_string(fdt, 0, "model", 542 "IBM PowerNV (emulated by qemu)"))); 543 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 544 545 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 546 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 547 if (qemu_uuid_set) { 548 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 549 } 550 g_free(buf); 551 552 off = fdt_add_subnode(fdt, 0, "chosen"); 553 if (machine->kernel_cmdline) { 554 _FDT((fdt_setprop_string(fdt, off, "bootargs", 555 machine->kernel_cmdline))); 556 } 557 558 if (pnv->initrd_size) { 559 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 560 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 561 562 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 563 &start_prop, sizeof(start_prop)))); 564 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 565 &end_prop, sizeof(end_prop)))); 566 } 567 568 /* Populate device tree for each chip */ 569 for (i = 0; i < pnv->num_chips; i++) { 570 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 571 } 572 573 /* Populate ISA devices on chip 0 */ 574 pnv_dt_isa(pnv, fdt); 575 576 if (pnv->bmc) { 577 pnv_dt_bmc_sensors(pnv->bmc, fdt); 578 } 579 580 /* Create an extra node for power management on machines that support it */ 581 if (pmc->dt_power_mgt) { 582 pmc->dt_power_mgt(pnv, fdt); 583 } 584 585 return fdt; 586 } 587 588 static void pnv_powerdown_notify(Notifier *n, void *opaque) 589 { 590 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 591 592 if (pnv->bmc) { 593 pnv_bmc_powerdown(pnv->bmc); 594 } 595 } 596 597 static void pnv_reset(MachineState *machine) 598 { 599 PnvMachineState *pnv = PNV_MACHINE(machine); 600 IPMIBmc *bmc; 601 void *fdt; 602 603 qemu_devices_reset(); 604 605 /* 606 * The machine should provide by default an internal BMC simulator. 607 * If not, try to use the BMC device that was provided on the command 608 * line. 609 */ 610 bmc = pnv_bmc_find(&error_fatal); 611 if (!pnv->bmc) { 612 if (!bmc) { 613 if (!qtest_enabled()) { 614 warn_report("machine has no BMC device. Use '-device " 615 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 616 "to define one"); 617 } 618 } else { 619 pnv_bmc_set_pnor(bmc, pnv->pnor); 620 pnv->bmc = bmc; 621 } 622 } 623 624 fdt = pnv_dt_create(machine); 625 626 /* Pack resulting tree */ 627 _FDT((fdt_pack(fdt))); 628 629 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 630 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 631 632 g_free(fdt); 633 } 634 635 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 636 { 637 Pnv8Chip *chip8 = PNV8_CHIP(chip); 638 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 639 640 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 641 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 642 } 643 644 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 645 { 646 Pnv8Chip *chip8 = PNV8_CHIP(chip); 647 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 648 649 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 650 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 651 } 652 653 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 654 { 655 Pnv9Chip *chip9 = PNV9_CHIP(chip); 656 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 657 658 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 659 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 660 } 661 662 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 663 { 664 Pnv10Chip *chip10 = PNV10_CHIP(chip); 665 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 666 667 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 668 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 669 } 670 671 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 672 { 673 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 674 } 675 676 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 677 { 678 Pnv8Chip *chip8 = PNV8_CHIP(chip); 679 int i; 680 681 ics_pic_print_info(&chip8->psi.ics, mon); 682 683 for (i = 0; i < chip8->num_phbs; i++) { 684 PnvPHB *phb = &chip8->phbs[i]; 685 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 686 687 pnv_phb3_msi_pic_print_info(&phb3->msis, mon); 688 ics_pic_print_info(&phb3->lsis, mon); 689 } 690 } 691 692 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 693 { 694 Monitor *mon = opaque; 695 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 696 697 if (!phb) { 698 return 0; 699 } 700 701 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), mon); 702 703 return 0; 704 } 705 706 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 707 { 708 Pnv9Chip *chip9 = PNV9_CHIP(chip); 709 710 pnv_xive_pic_print_info(&chip9->xive, mon); 711 pnv_psi_pic_print_info(&chip9->psi, mon); 712 713 object_child_foreach_recursive(OBJECT(chip), 714 pnv_chip_power9_pic_print_info_child, mon); 715 } 716 717 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 718 uint32_t core_id) 719 { 720 return PNV_XSCOM_EX_BASE(core_id); 721 } 722 723 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 724 uint32_t core_id) 725 { 726 return PNV9_XSCOM_EC_BASE(core_id); 727 } 728 729 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 730 uint32_t core_id) 731 { 732 return PNV10_XSCOM_EC_BASE(core_id); 733 } 734 735 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 736 { 737 PowerPCCPUClass *ppc_default = 738 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 739 PowerPCCPUClass *ppc = 740 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 741 742 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 743 } 744 745 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 746 { 747 ISADevice *dev = isa_new("isa-ipmi-bt"); 748 749 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 750 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 751 isa_realize_and_unref(dev, bus, &error_fatal); 752 } 753 754 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 755 { 756 Pnv10Chip *chip10 = PNV10_CHIP(chip); 757 758 pnv_xive2_pic_print_info(&chip10->xive, mon); 759 pnv_psi_pic_print_info(&chip10->psi, mon); 760 761 object_child_foreach_recursive(OBJECT(chip), 762 pnv_chip_power9_pic_print_info_child, mon); 763 } 764 765 /* Always give the first 1GB to chip 0 else we won't boot */ 766 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 767 { 768 MachineState *machine = MACHINE(pnv); 769 uint64_t ram_per_chip; 770 771 assert(machine->ram_size >= 1 * GiB); 772 773 ram_per_chip = machine->ram_size / pnv->num_chips; 774 if (ram_per_chip >= 1 * GiB) { 775 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 776 } 777 778 assert(pnv->num_chips > 1); 779 780 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 781 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 782 } 783 784 static void pnv_init(MachineState *machine) 785 { 786 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 787 PnvMachineState *pnv = PNV_MACHINE(machine); 788 MachineClass *mc = MACHINE_GET_CLASS(machine); 789 char *fw_filename; 790 long fw_size; 791 uint64_t chip_ram_start = 0; 792 int i; 793 char *chip_typename; 794 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 795 DeviceState *dev; 796 797 if (kvm_enabled()) { 798 error_report("The powernv machine does not work with KVM acceleration"); 799 exit(EXIT_FAILURE); 800 } 801 802 /* allocate RAM */ 803 if (machine->ram_size < mc->default_ram_size) { 804 char *sz = size_to_str(mc->default_ram_size); 805 error_report("Invalid RAM size, should be bigger than %s", sz); 806 g_free(sz); 807 exit(EXIT_FAILURE); 808 } 809 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 810 811 /* 812 * Create our simple PNOR device 813 */ 814 dev = qdev_new(TYPE_PNV_PNOR); 815 if (pnor) { 816 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 817 } 818 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 819 pnv->pnor = PNV_PNOR(dev); 820 821 /* load skiboot firmware */ 822 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 823 if (!fw_filename) { 824 error_report("Could not find OPAL firmware '%s'", bios_name); 825 exit(1); 826 } 827 828 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 829 if (fw_size < 0) { 830 error_report("Could not load OPAL firmware '%s'", fw_filename); 831 exit(1); 832 } 833 g_free(fw_filename); 834 835 /* load kernel */ 836 if (machine->kernel_filename) { 837 long kernel_size; 838 839 kernel_size = load_image_targphys(machine->kernel_filename, 840 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 841 if (kernel_size < 0) { 842 error_report("Could not load kernel '%s'", 843 machine->kernel_filename); 844 exit(1); 845 } 846 } 847 848 /* load initrd */ 849 if (machine->initrd_filename) { 850 pnv->initrd_base = INITRD_LOAD_ADDR; 851 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 852 pnv->initrd_base, INITRD_MAX_SIZE); 853 if (pnv->initrd_size < 0) { 854 error_report("Could not load initial ram disk '%s'", 855 machine->initrd_filename); 856 exit(1); 857 } 858 } 859 860 /* MSIs are supported on this platform */ 861 msi_nonbroken = true; 862 863 /* 864 * Check compatibility of the specified CPU with the machine 865 * default. 866 */ 867 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 868 error_report("invalid CPU model '%s' for %s machine", 869 machine->cpu_type, mc->name); 870 exit(1); 871 } 872 873 /* Create the processor chips */ 874 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 875 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 876 i, machine->cpu_type); 877 if (!object_class_by_name(chip_typename)) { 878 error_report("invalid chip model '%.*s' for %s machine", 879 i, machine->cpu_type, mc->name); 880 exit(1); 881 } 882 883 pnv->num_chips = 884 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 885 /* 886 * TODO: should we decide on how many chips we can create based 887 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 888 */ 889 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 890 error_report("invalid number of chips: '%d'", pnv->num_chips); 891 error_printf( 892 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 893 exit(1); 894 } 895 896 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 897 for (i = 0; i < pnv->num_chips; i++) { 898 char chip_name[32]; 899 Object *chip = OBJECT(qdev_new(chip_typename)); 900 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 901 902 pnv->chips[i] = PNV_CHIP(chip); 903 904 /* Distribute RAM among the chips */ 905 object_property_set_int(chip, "ram-start", chip_ram_start, 906 &error_fatal); 907 object_property_set_int(chip, "ram-size", chip_ram_size, 908 &error_fatal); 909 chip_ram_start += chip_ram_size; 910 911 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 912 object_property_add_child(OBJECT(pnv), chip_name, chip); 913 object_property_set_int(chip, "chip-id", i, &error_fatal); 914 object_property_set_int(chip, "nr-cores", machine->smp.cores, 915 &error_fatal); 916 object_property_set_int(chip, "nr-threads", machine->smp.threads, 917 &error_fatal); 918 /* 919 * The POWER8 machine use the XICS interrupt interface. 920 * Propagate the XICS fabric to the chip and its controllers. 921 */ 922 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 923 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 924 } 925 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 926 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 927 &error_abort); 928 } 929 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 930 } 931 g_free(chip_typename); 932 933 /* Instantiate ISA bus on chip 0 */ 934 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 935 936 /* Create serial port */ 937 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 938 939 /* Create an RTC ISA device too */ 940 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 941 942 /* 943 * Create the machine BMC simulator and the IPMI BT device for 944 * communication with the BMC 945 */ 946 if (defaults_enabled()) { 947 pnv->bmc = pnv_bmc_create(pnv->pnor); 948 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 949 } 950 951 /* 952 * The PNOR is mapped on the LPC FW address space by the BMC. 953 * Since we can not reach the remote BMC machine with LPC memops, 954 * map it always for now. 955 */ 956 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 957 &pnv->pnor->mmio); 958 959 /* 960 * OpenPOWER systems use a IPMI SEL Event message to notify the 961 * host to powerdown 962 */ 963 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 964 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 965 } 966 967 /* 968 * 0:21 Reserved - Read as zeros 969 * 22:24 Chip ID 970 * 25:28 Core number 971 * 29:31 Thread ID 972 */ 973 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 974 { 975 return (chip->chip_id << 7) | (core_id << 3); 976 } 977 978 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 979 Error **errp) 980 { 981 Pnv8Chip *chip8 = PNV8_CHIP(chip); 982 Error *local_err = NULL; 983 Object *obj; 984 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 985 986 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 987 if (local_err) { 988 error_propagate(errp, local_err); 989 return; 990 } 991 992 pnv_cpu->intc = obj; 993 } 994 995 996 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 997 { 998 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 999 1000 icp_reset(ICP(pnv_cpu->intc)); 1001 } 1002 1003 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1004 { 1005 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1006 1007 icp_destroy(ICP(pnv_cpu->intc)); 1008 pnv_cpu->intc = NULL; 1009 } 1010 1011 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1012 Monitor *mon) 1013 { 1014 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 1015 } 1016 1017 /* 1018 * 0:48 Reserved - Read as zeroes 1019 * 49:52 Node ID 1020 * 53:55 Chip ID 1021 * 56 Reserved - Read as zero 1022 * 57:61 Core number 1023 * 62:63 Thread ID 1024 * 1025 * We only care about the lower bits. uint32_t is fine for the moment. 1026 */ 1027 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 1028 { 1029 return (chip->chip_id << 8) | (core_id << 2); 1030 } 1031 1032 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 1033 { 1034 return (chip->chip_id << 8) | (core_id << 2); 1035 } 1036 1037 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1038 Error **errp) 1039 { 1040 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1041 Error *local_err = NULL; 1042 Object *obj; 1043 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1044 1045 /* 1046 * The core creates its interrupt presenter but the XIVE interrupt 1047 * controller object is initialized afterwards. Hopefully, it's 1048 * only used at runtime. 1049 */ 1050 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1051 &local_err); 1052 if (local_err) { 1053 error_propagate(errp, local_err); 1054 return; 1055 } 1056 1057 pnv_cpu->intc = obj; 1058 } 1059 1060 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1061 { 1062 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1063 1064 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1065 } 1066 1067 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1068 { 1069 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1070 1071 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1072 pnv_cpu->intc = NULL; 1073 } 1074 1075 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1076 Monitor *mon) 1077 { 1078 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1079 } 1080 1081 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1082 Error **errp) 1083 { 1084 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1085 Error *local_err = NULL; 1086 Object *obj; 1087 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1088 1089 /* 1090 * The core creates its interrupt presenter but the XIVE2 interrupt 1091 * controller object is initialized afterwards. Hopefully, it's 1092 * only used at runtime. 1093 */ 1094 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1095 &local_err); 1096 if (local_err) { 1097 error_propagate(errp, local_err); 1098 return; 1099 } 1100 1101 pnv_cpu->intc = obj; 1102 } 1103 1104 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1105 { 1106 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1107 1108 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1109 } 1110 1111 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1112 { 1113 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1114 1115 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1116 pnv_cpu->intc = NULL; 1117 } 1118 1119 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1120 Monitor *mon) 1121 { 1122 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 1123 } 1124 1125 /* 1126 * Allowed core identifiers on a POWER8 Processor Chip : 1127 * 1128 * <EX0 reserved> 1129 * EX1 - Venice only 1130 * EX2 - Venice only 1131 * EX3 - Venice only 1132 * EX4 1133 * EX5 1134 * EX6 1135 * <EX7,8 reserved> <reserved> 1136 * EX9 - Venice only 1137 * EX10 - Venice only 1138 * EX11 - Venice only 1139 * EX12 1140 * EX13 1141 * EX14 1142 * <EX15 reserved> 1143 */ 1144 #define POWER8E_CORE_MASK (0x7070ull) 1145 #define POWER8_CORE_MASK (0x7e7eull) 1146 1147 /* 1148 * POWER9 has 24 cores, ids starting at 0x0 1149 */ 1150 #define POWER9_CORE_MASK (0xffffffffffffffull) 1151 1152 1153 #define POWER10_CORE_MASK (0xffffffffffffffull) 1154 1155 static void pnv_chip_power8_instance_init(Object *obj) 1156 { 1157 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1158 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1159 int i; 1160 1161 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1162 (Object **)&chip8->xics, 1163 object_property_allow_set_link, 1164 OBJ_PROP_LINK_STRONG); 1165 1166 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1167 1168 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1169 1170 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1171 1172 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1173 1174 chip8->num_phbs = pcc->num_phbs; 1175 1176 for (i = 0; i < chip8->num_phbs; i++) { 1177 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_PHB); 1178 } 1179 1180 } 1181 1182 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1183 { 1184 PnvChip *chip = PNV_CHIP(chip8); 1185 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1186 int i, j; 1187 char *name; 1188 1189 name = g_strdup_printf("icp-%x", chip->chip_id); 1190 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1191 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1192 g_free(name); 1193 1194 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1195 1196 /* Map the ICP registers for each thread */ 1197 for (i = 0; i < chip->nr_cores; i++) { 1198 PnvCore *pnv_core = chip->cores[i]; 1199 int core_hwid = CPU_CORE(pnv_core)->core_id; 1200 1201 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1202 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1203 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1204 1205 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1206 &icp->mmio); 1207 } 1208 } 1209 } 1210 1211 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1212 { 1213 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1214 PnvChip *chip = PNV_CHIP(dev); 1215 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1216 Pnv8Psi *psi8 = &chip8->psi; 1217 Error *local_err = NULL; 1218 int i; 1219 1220 assert(chip8->xics); 1221 1222 /* XSCOM bridge is first */ 1223 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1224 if (local_err) { 1225 error_propagate(errp, local_err); 1226 return; 1227 } 1228 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1229 1230 pcc->parent_realize(dev, &local_err); 1231 if (local_err) { 1232 error_propagate(errp, local_err); 1233 return; 1234 } 1235 1236 /* Processor Service Interface (PSI) Host Bridge */ 1237 object_property_set_int(OBJECT(&chip8->psi), "bar", PNV_PSIHB_BASE(chip), 1238 &error_fatal); 1239 object_property_set_link(OBJECT(&chip8->psi), ICS_PROP_XICS, 1240 OBJECT(chip8->xics), &error_abort); 1241 if (!qdev_realize(DEVICE(&chip8->psi), NULL, errp)) { 1242 return; 1243 } 1244 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1245 &PNV_PSI(psi8)->xscom_regs); 1246 1247 /* Create LPC controller */ 1248 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1249 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1250 1251 chip->fw_mr = &chip8->lpc.isa_fw; 1252 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1253 (uint64_t) PNV_XSCOM_BASE(chip), 1254 PNV_XSCOM_LPC_BASE); 1255 1256 /* 1257 * Interrupt Management Area. This is the memory region holding 1258 * all the Interrupt Control Presenter (ICP) registers 1259 */ 1260 pnv_chip_icp_realize(chip8, &local_err); 1261 if (local_err) { 1262 error_propagate(errp, local_err); 1263 return; 1264 } 1265 1266 /* Create the simplified OCC model */ 1267 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1268 return; 1269 } 1270 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1271 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1272 qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_OCC)); 1273 1274 /* OCC SRAM model */ 1275 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1276 &chip8->occ.sram_regs); 1277 1278 /* HOMER */ 1279 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1280 &error_abort); 1281 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1282 return; 1283 } 1284 /* Homer Xscom region */ 1285 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1286 1287 /* Homer mmio region */ 1288 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1289 &chip8->homer.regs); 1290 1291 /* PHB controllers */ 1292 for (i = 0; i < chip8->num_phbs; i++) { 1293 PnvPHB *phb = &chip8->phbs[i]; 1294 1295 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1296 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1297 &error_fatal); 1298 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1299 &error_fatal); 1300 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1301 return; 1302 } 1303 } 1304 } 1305 1306 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1307 { 1308 addr &= (PNV_XSCOM_SIZE - 1); 1309 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1310 } 1311 1312 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1313 { 1314 DeviceClass *dc = DEVICE_CLASS(klass); 1315 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1316 1317 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1318 k->cores_mask = POWER8E_CORE_MASK; 1319 k->num_phbs = 3; 1320 k->core_pir = pnv_chip_core_pir_p8; 1321 k->intc_create = pnv_chip_power8_intc_create; 1322 k->intc_reset = pnv_chip_power8_intc_reset; 1323 k->intc_destroy = pnv_chip_power8_intc_destroy; 1324 k->intc_print_info = pnv_chip_power8_intc_print_info; 1325 k->isa_create = pnv_chip_power8_isa_create; 1326 k->dt_populate = pnv_chip_power8_dt_populate; 1327 k->pic_print_info = pnv_chip_power8_pic_print_info; 1328 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1329 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1330 dc->desc = "PowerNV Chip POWER8E"; 1331 1332 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1333 &k->parent_realize); 1334 } 1335 1336 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1337 { 1338 DeviceClass *dc = DEVICE_CLASS(klass); 1339 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1340 1341 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1342 k->cores_mask = POWER8_CORE_MASK; 1343 k->num_phbs = 3; 1344 k->core_pir = pnv_chip_core_pir_p8; 1345 k->intc_create = pnv_chip_power8_intc_create; 1346 k->intc_reset = pnv_chip_power8_intc_reset; 1347 k->intc_destroy = pnv_chip_power8_intc_destroy; 1348 k->intc_print_info = pnv_chip_power8_intc_print_info; 1349 k->isa_create = pnv_chip_power8_isa_create; 1350 k->dt_populate = pnv_chip_power8_dt_populate; 1351 k->pic_print_info = pnv_chip_power8_pic_print_info; 1352 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1353 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1354 dc->desc = "PowerNV Chip POWER8"; 1355 1356 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1357 &k->parent_realize); 1358 } 1359 1360 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1361 { 1362 DeviceClass *dc = DEVICE_CLASS(klass); 1363 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1364 1365 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1366 k->cores_mask = POWER8_CORE_MASK; 1367 k->num_phbs = 4; 1368 k->core_pir = pnv_chip_core_pir_p8; 1369 k->intc_create = pnv_chip_power8_intc_create; 1370 k->intc_reset = pnv_chip_power8_intc_reset; 1371 k->intc_destroy = pnv_chip_power8_intc_destroy; 1372 k->intc_print_info = pnv_chip_power8_intc_print_info; 1373 k->isa_create = pnv_chip_power8nvl_isa_create; 1374 k->dt_populate = pnv_chip_power8_dt_populate; 1375 k->pic_print_info = pnv_chip_power8_pic_print_info; 1376 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1377 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1378 dc->desc = "PowerNV Chip POWER8NVL"; 1379 1380 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1381 &k->parent_realize); 1382 } 1383 1384 static void pnv_chip_power9_instance_init(Object *obj) 1385 { 1386 PnvChip *chip = PNV_CHIP(obj); 1387 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1388 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1389 int i; 1390 1391 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1392 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1393 "xive-fabric"); 1394 1395 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1396 1397 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1398 1399 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1400 1401 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1402 1403 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1404 1405 /* Number of PECs is the chip default */ 1406 chip->num_pecs = pcc->num_pecs; 1407 1408 for (i = 0; i < chip->num_pecs; i++) { 1409 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1410 TYPE_PNV_PHB4_PEC); 1411 } 1412 } 1413 1414 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1415 PnvCore *pnv_core) 1416 { 1417 char eq_name[32]; 1418 int core_id = CPU_CORE(pnv_core)->core_id; 1419 1420 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1421 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1422 sizeof(*eq), TYPE_PNV_QUAD, 1423 &error_fatal, NULL); 1424 1425 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1426 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1427 } 1428 1429 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1430 { 1431 PnvChip *chip = PNV_CHIP(chip9); 1432 int i; 1433 1434 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1435 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1436 1437 for (i = 0; i < chip9->nr_quads; i++) { 1438 PnvQuad *eq = &chip9->quads[i]; 1439 1440 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1441 1442 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1443 &eq->xscom_regs); 1444 } 1445 } 1446 1447 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1448 { 1449 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1450 int i; 1451 1452 for (i = 0; i < chip->num_pecs; i++) { 1453 PnvPhb4PecState *pec = &chip9->pecs[i]; 1454 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1455 uint32_t pec_nest_base; 1456 uint32_t pec_pci_base; 1457 1458 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1459 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1460 &error_fatal); 1461 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1462 &error_fatal); 1463 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1464 return; 1465 } 1466 1467 pec_nest_base = pecc->xscom_nest_base(pec); 1468 pec_pci_base = pecc->xscom_pci_base(pec); 1469 1470 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1471 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1472 } 1473 } 1474 1475 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1476 { 1477 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1478 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1479 PnvChip *chip = PNV_CHIP(dev); 1480 Pnv9Psi *psi9 = &chip9->psi; 1481 Error *local_err = NULL; 1482 1483 /* XSCOM bridge is first */ 1484 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1485 if (local_err) { 1486 error_propagate(errp, local_err); 1487 return; 1488 } 1489 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1490 1491 pcc->parent_realize(dev, &local_err); 1492 if (local_err) { 1493 error_propagate(errp, local_err); 1494 return; 1495 } 1496 1497 pnv_chip_quad_realize(chip9, &local_err); 1498 if (local_err) { 1499 error_propagate(errp, local_err); 1500 return; 1501 } 1502 1503 /* XIVE interrupt controller (POWER9) */ 1504 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1505 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1506 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1507 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1508 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1509 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1510 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1511 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1512 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1513 &error_abort); 1514 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1515 return; 1516 } 1517 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1518 &chip9->xive.xscom_regs); 1519 1520 /* Processor Service Interface (PSI) Host Bridge */ 1521 object_property_set_int(OBJECT(&chip9->psi), "bar", PNV9_PSIHB_BASE(chip), 1522 &error_fatal); 1523 /* This is the only device with 4k ESB pages */ 1524 object_property_set_int(OBJECT(&chip9->psi), "shift", XIVE_ESB_4K, 1525 &error_fatal); 1526 if (!qdev_realize(DEVICE(&chip9->psi), NULL, errp)) { 1527 return; 1528 } 1529 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1530 &PNV_PSI(psi9)->xscom_regs); 1531 1532 /* LPC */ 1533 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1534 return; 1535 } 1536 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1537 &chip9->lpc.xscom_regs); 1538 1539 chip->fw_mr = &chip9->lpc.isa_fw; 1540 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1541 (uint64_t) PNV9_LPCM_BASE(chip)); 1542 1543 /* Create the simplified OCC model */ 1544 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1545 return; 1546 } 1547 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1548 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1549 DEVICE(&chip9->psi), PSIHB9_IRQ_OCC)); 1550 1551 /* OCC SRAM model */ 1552 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1553 &chip9->occ.sram_regs); 1554 1555 /* SBE */ 1556 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1557 return; 1558 } 1559 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1560 &chip9->sbe.xscom_ctrl_regs); 1561 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1562 &chip9->sbe.xscom_mbox_regs); 1563 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1564 DEVICE(&chip9->psi), PSIHB9_IRQ_PSU)); 1565 1566 /* HOMER */ 1567 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1568 &error_abort); 1569 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1570 return; 1571 } 1572 /* Homer Xscom region */ 1573 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1574 1575 /* Homer mmio region */ 1576 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1577 &chip9->homer.regs); 1578 1579 /* PEC PHBs */ 1580 pnv_chip_power9_pec_realize(chip, &local_err); 1581 if (local_err) { 1582 error_propagate(errp, local_err); 1583 return; 1584 } 1585 } 1586 1587 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1588 { 1589 addr &= (PNV9_XSCOM_SIZE - 1); 1590 return addr >> 3; 1591 } 1592 1593 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1594 { 1595 DeviceClass *dc = DEVICE_CLASS(klass); 1596 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1597 1598 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1599 k->cores_mask = POWER9_CORE_MASK; 1600 k->core_pir = pnv_chip_core_pir_p9; 1601 k->intc_create = pnv_chip_power9_intc_create; 1602 k->intc_reset = pnv_chip_power9_intc_reset; 1603 k->intc_destroy = pnv_chip_power9_intc_destroy; 1604 k->intc_print_info = pnv_chip_power9_intc_print_info; 1605 k->isa_create = pnv_chip_power9_isa_create; 1606 k->dt_populate = pnv_chip_power9_dt_populate; 1607 k->pic_print_info = pnv_chip_power9_pic_print_info; 1608 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1609 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1610 dc->desc = "PowerNV Chip POWER9"; 1611 k->num_pecs = PNV9_CHIP_MAX_PEC; 1612 1613 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1614 &k->parent_realize); 1615 } 1616 1617 static void pnv_chip_power10_instance_init(Object *obj) 1618 { 1619 PnvChip *chip = PNV_CHIP(obj); 1620 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1621 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1622 int i; 1623 1624 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1625 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1626 "xive-fabric"); 1627 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1628 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1629 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1630 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1631 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1632 1633 chip->num_pecs = pcc->num_pecs; 1634 1635 for (i = 0; i < chip->num_pecs; i++) { 1636 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1637 TYPE_PNV_PHB5_PEC); 1638 } 1639 } 1640 1641 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1642 { 1643 PnvChip *chip = PNV_CHIP(chip10); 1644 int i; 1645 1646 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1647 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1648 1649 for (i = 0; i < chip10->nr_quads; i++) { 1650 PnvQuad *eq = &chip10->quads[i]; 1651 1652 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4]); 1653 1654 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1655 &eq->xscom_regs); 1656 } 1657 } 1658 1659 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1660 { 1661 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1662 int i; 1663 1664 for (i = 0; i < chip->num_pecs; i++) { 1665 PnvPhb4PecState *pec = &chip10->pecs[i]; 1666 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1667 uint32_t pec_nest_base; 1668 uint32_t pec_pci_base; 1669 1670 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1671 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1672 &error_fatal); 1673 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1674 &error_fatal); 1675 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1676 return; 1677 } 1678 1679 pec_nest_base = pecc->xscom_nest_base(pec); 1680 pec_pci_base = pecc->xscom_pci_base(pec); 1681 1682 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1683 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1684 } 1685 } 1686 1687 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1688 { 1689 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1690 PnvChip *chip = PNV_CHIP(dev); 1691 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1692 Error *local_err = NULL; 1693 1694 /* XSCOM bridge is first */ 1695 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1696 if (local_err) { 1697 error_propagate(errp, local_err); 1698 return; 1699 } 1700 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1701 1702 pcc->parent_realize(dev, &local_err); 1703 if (local_err) { 1704 error_propagate(errp, local_err); 1705 return; 1706 } 1707 1708 pnv_chip_power10_quad_realize(chip10, &local_err); 1709 if (local_err) { 1710 error_propagate(errp, local_err); 1711 return; 1712 } 1713 1714 /* XIVE2 interrupt controller (POWER10) */ 1715 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1716 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1717 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1718 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1719 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1720 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1721 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1722 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1723 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1724 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1725 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1726 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1727 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1728 &error_abort); 1729 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1730 return; 1731 } 1732 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1733 &chip10->xive.xscom_regs); 1734 1735 /* Processor Service Interface (PSI) Host Bridge */ 1736 object_property_set_int(OBJECT(&chip10->psi), "bar", 1737 PNV10_PSIHB_BASE(chip), &error_fatal); 1738 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1739 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1740 &error_fatal); 1741 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1742 return; 1743 } 1744 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1745 &PNV_PSI(&chip10->psi)->xscom_regs); 1746 1747 /* LPC */ 1748 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1749 return; 1750 } 1751 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1752 &chip10->lpc.xscom_regs); 1753 1754 chip->fw_mr = &chip10->lpc.isa_fw; 1755 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1756 (uint64_t) PNV10_LPCM_BASE(chip)); 1757 1758 /* Create the simplified OCC model */ 1759 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1760 return; 1761 } 1762 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1763 &chip10->occ.xscom_regs); 1764 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1765 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1766 1767 /* OCC SRAM model */ 1768 memory_region_add_subregion(get_system_memory(), 1769 PNV10_OCC_SENSOR_BASE(chip), 1770 &chip10->occ.sram_regs); 1771 1772 /* SBE */ 1773 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1774 return; 1775 } 1776 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1777 &chip10->sbe.xscom_ctrl_regs); 1778 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1779 &chip10->sbe.xscom_mbox_regs); 1780 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1781 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1782 1783 /* HOMER */ 1784 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1785 &error_abort); 1786 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1787 return; 1788 } 1789 /* Homer Xscom region */ 1790 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1791 &chip10->homer.pba_regs); 1792 1793 /* Homer mmio region */ 1794 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 1795 &chip10->homer.regs); 1796 1797 /* PHBs */ 1798 pnv_chip_power10_phb_realize(chip, &local_err); 1799 if (local_err) { 1800 error_propagate(errp, local_err); 1801 return; 1802 } 1803 } 1804 1805 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1806 { 1807 addr &= (PNV10_XSCOM_SIZE - 1); 1808 return addr >> 3; 1809 } 1810 1811 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1812 { 1813 DeviceClass *dc = DEVICE_CLASS(klass); 1814 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1815 1816 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1817 k->cores_mask = POWER10_CORE_MASK; 1818 k->core_pir = pnv_chip_core_pir_p10; 1819 k->intc_create = pnv_chip_power10_intc_create; 1820 k->intc_reset = pnv_chip_power10_intc_reset; 1821 k->intc_destroy = pnv_chip_power10_intc_destroy; 1822 k->intc_print_info = pnv_chip_power10_intc_print_info; 1823 k->isa_create = pnv_chip_power10_isa_create; 1824 k->dt_populate = pnv_chip_power10_dt_populate; 1825 k->pic_print_info = pnv_chip_power10_pic_print_info; 1826 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1827 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1828 dc->desc = "PowerNV Chip POWER10"; 1829 k->num_pecs = PNV10_CHIP_MAX_PEC; 1830 1831 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1832 &k->parent_realize); 1833 } 1834 1835 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1836 { 1837 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1838 int cores_max; 1839 1840 /* 1841 * No custom mask for this chip, let's use the default one from * 1842 * the chip class 1843 */ 1844 if (!chip->cores_mask) { 1845 chip->cores_mask = pcc->cores_mask; 1846 } 1847 1848 /* filter alien core ids ! some are reserved */ 1849 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1850 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1851 chip->cores_mask); 1852 return; 1853 } 1854 chip->cores_mask &= pcc->cores_mask; 1855 1856 /* now that we have a sane layout, let check the number of cores */ 1857 cores_max = ctpop64(chip->cores_mask); 1858 if (chip->nr_cores > cores_max) { 1859 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1860 cores_max); 1861 return; 1862 } 1863 } 1864 1865 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1866 { 1867 Error *error = NULL; 1868 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1869 const char *typename = pnv_chip_core_typename(chip); 1870 int i, core_hwid; 1871 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1872 1873 if (!object_class_by_name(typename)) { 1874 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1875 return; 1876 } 1877 1878 /* Cores */ 1879 pnv_chip_core_sanitize(chip, &error); 1880 if (error) { 1881 error_propagate(errp, error); 1882 return; 1883 } 1884 1885 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1886 1887 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1888 && (i < chip->nr_cores); core_hwid++) { 1889 char core_name[32]; 1890 PnvCore *pnv_core; 1891 uint64_t xscom_core_base; 1892 1893 if (!(chip->cores_mask & (1ull << core_hwid))) { 1894 continue; 1895 } 1896 1897 pnv_core = PNV_CORE(object_new(typename)); 1898 1899 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1900 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 1901 chip->cores[i] = pnv_core; 1902 object_property_set_int(OBJECT(pnv_core), "nr-threads", 1903 chip->nr_threads, &error_fatal); 1904 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 1905 core_hwid, &error_fatal); 1906 object_property_set_int(OBJECT(pnv_core), "pir", 1907 pcc->core_pir(chip, core_hwid), &error_fatal); 1908 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 1909 &error_fatal); 1910 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 1911 &error_abort); 1912 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 1913 1914 /* Each core has an XSCOM MMIO region */ 1915 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1916 1917 pnv_xscom_add_subregion(chip, xscom_core_base, 1918 &pnv_core->xscom_regs); 1919 i++; 1920 } 1921 } 1922 1923 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1924 { 1925 PnvChip *chip = PNV_CHIP(dev); 1926 Error *error = NULL; 1927 1928 /* Cores */ 1929 pnv_chip_core_realize(chip, &error); 1930 if (error) { 1931 error_propagate(errp, error); 1932 return; 1933 } 1934 } 1935 1936 static Property pnv_chip_properties[] = { 1937 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1938 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1939 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1940 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1941 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1942 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1943 DEFINE_PROP_END_OF_LIST(), 1944 }; 1945 1946 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1947 { 1948 DeviceClass *dc = DEVICE_CLASS(klass); 1949 1950 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1951 dc->realize = pnv_chip_realize; 1952 device_class_set_props(dc, pnv_chip_properties); 1953 dc->desc = "PowerNV Chip"; 1954 } 1955 1956 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1957 { 1958 int i, j; 1959 1960 for (i = 0; i < chip->nr_cores; i++) { 1961 PnvCore *pc = chip->cores[i]; 1962 CPUCore *cc = CPU_CORE(pc); 1963 1964 for (j = 0; j < cc->nr_threads; j++) { 1965 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1966 return pc->threads[j]; 1967 } 1968 } 1969 } 1970 return NULL; 1971 } 1972 1973 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1974 { 1975 PnvMachineState *pnv = PNV_MACHINE(xi); 1976 int i, j; 1977 1978 for (i = 0; i < pnv->num_chips; i++) { 1979 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1980 1981 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1982 return &chip8->psi.ics; 1983 } 1984 1985 for (j = 0; j < chip8->num_phbs; j++) { 1986 PnvPHB *phb = &chip8->phbs[j]; 1987 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 1988 1989 if (ics_valid_irq(&phb3->lsis, irq)) { 1990 return &phb3->lsis; 1991 } 1992 1993 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 1994 return ICS(&phb3->msis); 1995 } 1996 } 1997 } 1998 return NULL; 1999 } 2000 2001 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2002 { 2003 int i; 2004 2005 for (i = 0; i < pnv->num_chips; i++) { 2006 PnvChip *chip = pnv->chips[i]; 2007 if (chip->chip_id == chip_id) { 2008 return chip; 2009 } 2010 } 2011 return NULL; 2012 } 2013 2014 static void pnv_ics_resend(XICSFabric *xi) 2015 { 2016 PnvMachineState *pnv = PNV_MACHINE(xi); 2017 int i, j; 2018 2019 for (i = 0; i < pnv->num_chips; i++) { 2020 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2021 2022 ics_resend(&chip8->psi.ics); 2023 2024 for (j = 0; j < chip8->num_phbs; j++) { 2025 PnvPHB *phb = &chip8->phbs[j]; 2026 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2027 2028 ics_resend(&phb3->lsis); 2029 ics_resend(ICS(&phb3->msis)); 2030 } 2031 } 2032 } 2033 2034 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2035 { 2036 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2037 2038 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2039 } 2040 2041 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2042 Monitor *mon) 2043 { 2044 PnvMachineState *pnv = PNV_MACHINE(obj); 2045 int i; 2046 CPUState *cs; 2047 2048 CPU_FOREACH(cs) { 2049 PowerPCCPU *cpu = POWERPC_CPU(cs); 2050 2051 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2052 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2053 mon); 2054 } 2055 2056 for (i = 0; i < pnv->num_chips; i++) { 2057 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 2058 } 2059 } 2060 2061 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2062 uint8_t nvt_blk, uint32_t nvt_idx, 2063 bool cam_ignore, uint8_t priority, 2064 uint32_t logic_serv, 2065 XiveTCTXMatch *match) 2066 { 2067 PnvMachineState *pnv = PNV_MACHINE(xfb); 2068 int total_count = 0; 2069 int i; 2070 2071 for (i = 0; i < pnv->num_chips; i++) { 2072 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2073 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2074 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2075 int count; 2076 2077 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2078 priority, logic_serv, match); 2079 2080 if (count < 0) { 2081 return count; 2082 } 2083 2084 total_count += count; 2085 } 2086 2087 return total_count; 2088 } 2089 2090 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2091 uint8_t nvt_blk, uint32_t nvt_idx, 2092 bool cam_ignore, uint8_t priority, 2093 uint32_t logic_serv, 2094 XiveTCTXMatch *match) 2095 { 2096 PnvMachineState *pnv = PNV_MACHINE(xfb); 2097 int total_count = 0; 2098 int i; 2099 2100 for (i = 0; i < pnv->num_chips; i++) { 2101 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2102 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2103 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2104 int count; 2105 2106 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2107 priority, logic_serv, match); 2108 2109 if (count < 0) { 2110 return count; 2111 } 2112 2113 total_count += count; 2114 } 2115 2116 return total_count; 2117 } 2118 2119 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2120 { 2121 MachineClass *mc = MACHINE_CLASS(oc); 2122 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2123 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2124 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2125 2126 static GlobalProperty phb_compat[] = { 2127 { TYPE_PNV_PHB, "version", "3" }, 2128 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2129 }; 2130 2131 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2132 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2133 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2134 2135 xic->icp_get = pnv_icp_get; 2136 xic->ics_get = pnv_ics_get; 2137 xic->ics_resend = pnv_ics_resend; 2138 2139 pmc->compat = compat; 2140 pmc->compat_size = sizeof(compat); 2141 } 2142 2143 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2144 { 2145 MachineClass *mc = MACHINE_CLASS(oc); 2146 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2147 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2148 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2149 2150 static GlobalProperty phb_compat[] = { 2151 { TYPE_PNV_PHB, "version", "4" }, 2152 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2153 }; 2154 2155 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2156 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 2157 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2158 2159 xfc->match_nvt = pnv_match_nvt; 2160 2161 mc->alias = "powernv"; 2162 2163 pmc->compat = compat; 2164 pmc->compat_size = sizeof(compat); 2165 pmc->dt_power_mgt = pnv_dt_power_mgt; 2166 } 2167 2168 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2169 { 2170 MachineClass *mc = MACHINE_CLASS(oc); 2171 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2172 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2173 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2174 2175 static GlobalProperty phb_compat[] = { 2176 { TYPE_PNV_PHB, "version", "5" }, 2177 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2178 }; 2179 2180 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2181 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2182 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2183 2184 pmc->compat = compat; 2185 pmc->compat_size = sizeof(compat); 2186 pmc->dt_power_mgt = pnv_dt_power_mgt; 2187 2188 xfc->match_nvt = pnv10_xive_match_nvt; 2189 } 2190 2191 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2192 { 2193 PnvMachineState *pnv = PNV_MACHINE(obj); 2194 2195 return !!pnv->fw_load_addr; 2196 } 2197 2198 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2199 { 2200 PnvMachineState *pnv = PNV_MACHINE(obj); 2201 2202 if (value) { 2203 pnv->fw_load_addr = 0x8000000; 2204 } 2205 } 2206 2207 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2208 { 2209 PowerPCCPU *cpu = POWERPC_CPU(cs); 2210 CPUPPCState *env = &cpu->env; 2211 2212 cpu_synchronize_state(cs); 2213 ppc_cpu_do_system_reset(cs); 2214 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2215 /* 2216 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2217 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2218 * (PPC_BIT(43)). 2219 */ 2220 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2221 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2222 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2223 } 2224 } else { 2225 /* 2226 * For non-powersave system resets, SRR1[42:45] are defined to be 2227 * implementation-dependent. The POWER9 User Manual specifies that 2228 * an external (SCOM driven, which may come from a BMC nmi command or 2229 * another CPU requesting a NMI IPI) system reset exception should be 2230 * 0b0010 (PPC_BIT(44)). 2231 */ 2232 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2233 } 2234 } 2235 2236 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2237 { 2238 CPUState *cs; 2239 2240 CPU_FOREACH(cs) { 2241 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2242 } 2243 } 2244 2245 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2246 { 2247 MachineClass *mc = MACHINE_CLASS(oc); 2248 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2249 NMIClass *nc = NMI_CLASS(oc); 2250 2251 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2252 mc->init = pnv_init; 2253 mc->reset = pnv_reset; 2254 mc->max_cpus = MAX_CPUS; 2255 /* Pnv provides a AHCI device for storage */ 2256 mc->block_default_type = IF_IDE; 2257 mc->no_parallel = 1; 2258 mc->default_boot_order = NULL; 2259 /* 2260 * RAM defaults to less than 2048 for 32-bit hosts, and large 2261 * enough to fit the maximum initrd size at it's load address 2262 */ 2263 mc->default_ram_size = 1 * GiB; 2264 mc->default_ram_id = "pnv.ram"; 2265 ispc->print_info = pnv_pic_print_info; 2266 nc->nmi_monitor_handler = pnv_nmi; 2267 2268 object_class_property_add_bool(oc, "hb-mode", 2269 pnv_machine_get_hb, pnv_machine_set_hb); 2270 object_class_property_set_description(oc, "hb-mode", 2271 "Use a hostboot like boot loader"); 2272 } 2273 2274 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2275 { \ 2276 .name = type, \ 2277 .class_init = class_initfn, \ 2278 .parent = TYPE_PNV8_CHIP, \ 2279 } 2280 2281 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2282 { \ 2283 .name = type, \ 2284 .class_init = class_initfn, \ 2285 .parent = TYPE_PNV9_CHIP, \ 2286 } 2287 2288 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2289 { \ 2290 .name = type, \ 2291 .class_init = class_initfn, \ 2292 .parent = TYPE_PNV10_CHIP, \ 2293 } 2294 2295 static const TypeInfo types[] = { 2296 { 2297 .name = MACHINE_TYPE_NAME("powernv10"), 2298 .parent = TYPE_PNV_MACHINE, 2299 .class_init = pnv_machine_power10_class_init, 2300 .interfaces = (InterfaceInfo[]) { 2301 { TYPE_XIVE_FABRIC }, 2302 { }, 2303 }, 2304 }, 2305 { 2306 .name = MACHINE_TYPE_NAME("powernv9"), 2307 .parent = TYPE_PNV_MACHINE, 2308 .class_init = pnv_machine_power9_class_init, 2309 .interfaces = (InterfaceInfo[]) { 2310 { TYPE_XIVE_FABRIC }, 2311 { }, 2312 }, 2313 }, 2314 { 2315 .name = MACHINE_TYPE_NAME("powernv8"), 2316 .parent = TYPE_PNV_MACHINE, 2317 .class_init = pnv_machine_power8_class_init, 2318 .interfaces = (InterfaceInfo[]) { 2319 { TYPE_XICS_FABRIC }, 2320 { }, 2321 }, 2322 }, 2323 { 2324 .name = TYPE_PNV_MACHINE, 2325 .parent = TYPE_MACHINE, 2326 .abstract = true, 2327 .instance_size = sizeof(PnvMachineState), 2328 .class_init = pnv_machine_class_init, 2329 .class_size = sizeof(PnvMachineClass), 2330 .interfaces = (InterfaceInfo[]) { 2331 { TYPE_INTERRUPT_STATS_PROVIDER }, 2332 { TYPE_NMI }, 2333 { }, 2334 }, 2335 }, 2336 { 2337 .name = TYPE_PNV_CHIP, 2338 .parent = TYPE_SYS_BUS_DEVICE, 2339 .class_init = pnv_chip_class_init, 2340 .instance_size = sizeof(PnvChip), 2341 .class_size = sizeof(PnvChipClass), 2342 .abstract = true, 2343 }, 2344 2345 /* 2346 * P10 chip and variants 2347 */ 2348 { 2349 .name = TYPE_PNV10_CHIP, 2350 .parent = TYPE_PNV_CHIP, 2351 .instance_init = pnv_chip_power10_instance_init, 2352 .instance_size = sizeof(Pnv10Chip), 2353 }, 2354 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2355 2356 /* 2357 * P9 chip and variants 2358 */ 2359 { 2360 .name = TYPE_PNV9_CHIP, 2361 .parent = TYPE_PNV_CHIP, 2362 .instance_init = pnv_chip_power9_instance_init, 2363 .instance_size = sizeof(Pnv9Chip), 2364 }, 2365 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2366 2367 /* 2368 * P8 chip and variants 2369 */ 2370 { 2371 .name = TYPE_PNV8_CHIP, 2372 .parent = TYPE_PNV_CHIP, 2373 .instance_init = pnv_chip_power8_instance_init, 2374 .instance_size = sizeof(Pnv8Chip), 2375 }, 2376 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2377 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2378 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2379 pnv_chip_power8nvl_class_init), 2380 }; 2381 2382 DEFINE_TYPES(types) 2383