1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/datadir.h" 22 #include "qemu/units.h" 23 #include "qemu/cutils.h" 24 #include "qapi/error.h" 25 #include "sysemu/qtest.h" 26 #include "sysemu/sysemu.h" 27 #include "sysemu/numa.h" 28 #include "sysemu/reset.h" 29 #include "sysemu/runstate.h" 30 #include "sysemu/cpus.h" 31 #include "sysemu/device_tree.h" 32 #include "sysemu/hw_accel.h" 33 #include "target/ppc/cpu.h" 34 #include "hw/ppc/fdt.h" 35 #include "hw/ppc/ppc.h" 36 #include "hw/ppc/pnv.h" 37 #include "hw/ppc/pnv_core.h" 38 #include "hw/loader.h" 39 #include "hw/nmi.h" 40 #include "qapi/visitor.h" 41 #include "qapi/type-helpers.h" 42 #include "monitor/monitor.h" 43 #include "hw/intc/intc.h" 44 #include "hw/ipmi/ipmi.h" 45 #include "target/ppc/mmu-hash64.h" 46 #include "hw/pci/msi.h" 47 #include "hw/pci-host/pnv_phb.h" 48 #include "hw/pci-host/pnv_phb3.h" 49 #include "hw/pci-host/pnv_phb4.h" 50 51 #include "hw/ppc/xics.h" 52 #include "hw/qdev-properties.h" 53 #include "hw/ppc/pnv_chip.h" 54 #include "hw/ppc/pnv_xscom.h" 55 #include "hw/ppc/pnv_pnor.h" 56 57 #include "hw/isa/isa.h" 58 #include "hw/char/serial.h" 59 #include "hw/rtc/mc146818rtc.h" 60 61 #include <libfdt.h> 62 63 #define FDT_MAX_SIZE (1 * MiB) 64 65 #define FW_FILE_NAME "skiboot.lid" 66 #define FW_LOAD_ADDR 0x0 67 #define FW_MAX_SIZE (16 * MiB) 68 69 #define KERNEL_LOAD_ADDR 0x20000000 70 #define KERNEL_MAX_SIZE (128 * MiB) 71 #define INITRD_LOAD_ADDR 0x28000000 72 #define INITRD_MAX_SIZE (128 * MiB) 73 74 static const char *pnv_chip_core_typename(const PnvChip *o) 75 { 76 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 77 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 78 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 79 const char *core_type = object_class_get_name(object_class_by_name(s)); 80 g_free(s); 81 return core_type; 82 } 83 84 /* 85 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 86 * 4 * 4 sockets * 12 cores * 8 threads = 1536 87 * Let's make it 2^11 88 */ 89 #define MAX_CPUS 2048 90 91 /* 92 * Memory nodes are created by hostboot, one for each range of memory 93 * that has a different "affinity". In practice, it means one range 94 * per chip. 95 */ 96 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 97 { 98 char *mem_name; 99 uint64_t mem_reg_property[2]; 100 int off; 101 102 mem_reg_property[0] = cpu_to_be64(start); 103 mem_reg_property[1] = cpu_to_be64(size); 104 105 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 106 off = fdt_add_subnode(fdt, 0, mem_name); 107 g_free(mem_name); 108 109 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 110 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 111 sizeof(mem_reg_property)))); 112 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 113 } 114 115 static int get_cpus_node(void *fdt) 116 { 117 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 118 119 if (cpus_offset < 0) { 120 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 121 if (cpus_offset) { 122 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 123 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 124 } 125 } 126 _FDT(cpus_offset); 127 return cpus_offset; 128 } 129 130 /* 131 * The PowerNV cores (and threads) need to use real HW ids and not an 132 * incremental index like it has been done on other platforms. This HW 133 * id is stored in the CPU PIR, it is used to create cpu nodes in the 134 * device tree, used in XSCOM to address cores and in interrupt 135 * servers. 136 */ 137 static int pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 138 { 139 PowerPCCPU *cpu = pc->threads[0]; 140 CPUState *cs = CPU(cpu); 141 DeviceClass *dc = DEVICE_GET_CLASS(cs); 142 int smt_threads = CPU_CORE(pc)->nr_threads; 143 CPUPPCState *env = &cpu->env; 144 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 145 PnvChipClass *pnv_cc = PNV_CHIP_GET_CLASS(chip); 146 g_autofree uint32_t *servers_prop = g_new(uint32_t, smt_threads); 147 int i; 148 uint32_t pir; 149 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 150 0xffffffff, 0xffffffff}; 151 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 152 uint32_t cpufreq = 1000000000; 153 uint32_t page_sizes_prop[64]; 154 size_t page_sizes_prop_size; 155 int offset; 156 char *nodename; 157 int cpus_offset = get_cpus_node(fdt); 158 159 pir = pnv_cc->chip_pir(chip, pc->hwid, 0); 160 161 nodename = g_strdup_printf("%s@%x", dc->fw_name, pir); 162 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 163 _FDT(offset); 164 g_free(nodename); 165 166 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 167 168 _FDT((fdt_setprop_cell(fdt, offset, "reg", pir))); 169 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pir))); 170 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 171 172 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 173 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 174 env->dcache_line_size))); 175 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 176 env->dcache_line_size))); 177 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 178 env->icache_line_size))); 179 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 180 env->icache_line_size))); 181 182 if (pcc->l1_dcache_size) { 183 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 184 pcc->l1_dcache_size))); 185 } else { 186 warn_report("Unknown L1 dcache size for cpu"); 187 } 188 if (pcc->l1_icache_size) { 189 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 190 pcc->l1_icache_size))); 191 } else { 192 warn_report("Unknown L1 icache size for cpu"); 193 } 194 195 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 196 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 198 cpu->hash64_opts->slb_size))); 199 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 200 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 201 202 if (ppc_has_spr(cpu, SPR_PURR)) { 203 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 204 } 205 206 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 207 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 208 segs, sizeof(segs)))); 209 } 210 211 /* 212 * Advertise VMX/VSX (vector extensions) if available 213 * 0 / no property == no vector extensions 214 * 1 == VMX / Altivec available 215 * 2 == VSX available 216 */ 217 if (env->insns_flags & PPC_ALTIVEC) { 218 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 219 220 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 221 } 222 223 /* 224 * Advertise DFP (Decimal Floating Point) if available 225 * 0 / no property == no DFP 226 * 1 == DFP available 227 */ 228 if (env->insns_flags2 & PPC2_DFP) { 229 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 230 } 231 232 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 233 sizeof(page_sizes_prop)); 234 if (page_sizes_prop_size) { 235 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 236 page_sizes_prop, page_sizes_prop_size))); 237 } 238 239 /* Build interrupt servers properties */ 240 for (i = 0; i < smt_threads; i++) { 241 servers_prop[i] = cpu_to_be32(pnv_cc->chip_pir(chip, pc->hwid, i)); 242 } 243 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 244 servers_prop, sizeof(*servers_prop) * smt_threads))); 245 246 return offset; 247 } 248 249 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t hwid, 250 uint32_t nr_threads) 251 { 252 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 253 uint32_t pir = pcc->chip_pir(chip, hwid, 0); 254 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 255 char *name; 256 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 257 uint32_t irange[2], i, rsize; 258 uint64_t *reg; 259 int offset; 260 261 irange[0] = cpu_to_be32(pir); 262 irange[1] = cpu_to_be32(nr_threads); 263 264 rsize = sizeof(uint64_t) * 2 * nr_threads; 265 reg = g_malloc(rsize); 266 for (i = 0; i < nr_threads; i++) { 267 /* We know P8 PIR is linear with thread id */ 268 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 269 reg[i * 2 + 1] = cpu_to_be64(0x1000); 270 } 271 272 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 273 offset = fdt_add_subnode(fdt, 0, name); 274 _FDT(offset); 275 g_free(name); 276 277 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 278 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 279 _FDT((fdt_setprop_string(fdt, offset, "device_type", 280 "PowerPC-External-Interrupt-Presentation"))); 281 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 282 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 283 irange, sizeof(irange)))); 284 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 285 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 286 g_free(reg); 287 } 288 289 /* 290 * Adds a PnvPHB to the chip on P8. 291 * Implemented here, like for defaults PHBs 292 */ 293 PnvChip *pnv_chip_add_phb(PnvChip *chip, PnvPHB *phb) 294 { 295 Pnv8Chip *chip8 = PNV8_CHIP(chip); 296 297 phb->chip = chip; 298 299 chip8->phbs[chip8->num_phbs] = phb; 300 chip8->num_phbs++; 301 return chip; 302 } 303 304 /* 305 * Same as spapr pa_features_207 except pnv always enables CI largepages bit. 306 * HTM is always enabled because TCG does implement HTM, it's just a 307 * degenerate implementation. 308 */ 309 static const uint8_t pa_features_207[] = { 24, 0, 310 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, 311 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 312 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 313 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 314 315 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 316 { 317 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 318 int i; 319 320 pnv_dt_xscom(chip, fdt, 0, 321 cpu_to_be64(PNV_XSCOM_BASE(chip)), 322 cpu_to_be64(PNV_XSCOM_SIZE), 323 compat, sizeof(compat)); 324 325 for (i = 0; i < chip->nr_cores; i++) { 326 PnvCore *pnv_core = chip->cores[i]; 327 int offset; 328 329 offset = pnv_dt_core(chip, pnv_core, fdt); 330 331 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 332 pa_features_207, sizeof(pa_features_207)))); 333 334 /* Interrupt Control Presenters (ICP). One per core. */ 335 pnv_dt_icp(chip, fdt, pnv_core->hwid, CPU_CORE(pnv_core)->nr_threads); 336 } 337 338 if (chip->ram_size) { 339 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 340 } 341 } 342 343 /* 344 * Same as spapr pa_features_300 except pnv always enables CI largepages bit. 345 */ 346 static const uint8_t pa_features_300[] = { 66, 0, 347 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 348 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 349 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 350 /* 6: DS207 */ 351 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 352 /* 16: Vector */ 353 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 354 /* 18: Vec. Scalar, 20: Vec. XOR, 22: HTM */ 355 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 18 - 23 */ 356 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 357 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 358 /* 32: LE atomic, 34: EBB + ext EBB */ 359 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 360 /* 40: Radix MMU */ 361 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 362 /* 42: PM, 44: PC RA, 46: SC vec'd */ 363 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 364 /* 48: SIMD, 50: QP BFP, 52: String */ 365 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 366 /* 54: DecFP, 56: DecI, 58: SHA */ 367 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 368 /* 60: NM atomic, 62: RNG */ 369 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 370 }; 371 372 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 373 { 374 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 375 int i; 376 377 pnv_dt_xscom(chip, fdt, 0, 378 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 379 cpu_to_be64(PNV9_XSCOM_SIZE), 380 compat, sizeof(compat)); 381 382 for (i = 0; i < chip->nr_cores; i++) { 383 PnvCore *pnv_core = chip->cores[i]; 384 int offset; 385 386 offset = pnv_dt_core(chip, pnv_core, fdt); 387 388 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 389 pa_features_300, sizeof(pa_features_300)))); 390 } 391 392 if (chip->ram_size) { 393 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 394 } 395 396 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 397 } 398 399 /* 400 * Same as spapr pa_features_31 except pnv always enables CI largepages bit, 401 * always disables copy/paste. 402 */ 403 static const uint8_t pa_features_31[] = { 74, 0, 404 /* 0: MMU|FPU|SLB|RUN|DABR|NX, 1: CILRG|fri[nzpm]|DABRX|SPRG3|SLB0|PP110 */ 405 /* 2: VPM|DS205|PPR|DS202|DS206, 3: LSD|URG, 5: LE|CFAR|EB|LSQ */ 406 0xf6, 0x3f, 0xc7, 0xc0, 0x00, 0xf0, /* 0 - 5 */ 407 /* 6: DS207 */ 408 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, /* 6 - 11 */ 409 /* 16: Vector */ 410 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 12 - 17 */ 411 /* 18: Vec. Scalar, 20: Vec. XOR */ 412 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 18 - 23 */ 413 /* 24: Ext. Dec, 26: 64 bit ftrs, 28: PM ftrs */ 414 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 24 - 29 */ 415 /* 32: LE atomic, 34: EBB + ext EBB */ 416 0x00, 0x00, 0x80, 0x00, 0xC0, 0x00, /* 30 - 35 */ 417 /* 40: Radix MMU */ 418 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, /* 36 - 41 */ 419 /* 42: PM, 44: PC RA, 46: SC vec'd */ 420 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 42 - 47 */ 421 /* 48: SIMD, 50: QP BFP, 52: String */ 422 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 48 - 53 */ 423 /* 54: DecFP, 56: DecI, 58: SHA */ 424 0x80, 0x00, 0x80, 0x00, 0x80, 0x00, /* 54 - 59 */ 425 /* 60: NM atomic, 62: RNG */ 426 0x80, 0x00, 0x80, 0x00, 0x00, 0x00, /* 60 - 65 */ 427 /* 68: DEXCR[SBHE|IBRTPDUS|SRAPD|NPHIE|PHIE] */ 428 0x00, 0x00, 0xce, 0x00, 0x00, 0x00, /* 66 - 71 */ 429 /* 72: [P]HASHST/[P]HASHCHK */ 430 0x80, 0x00, /* 72 - 73 */ 431 }; 432 433 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 434 { 435 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 436 int i; 437 438 pnv_dt_xscom(chip, fdt, 0, 439 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 440 cpu_to_be64(PNV10_XSCOM_SIZE), 441 compat, sizeof(compat)); 442 443 for (i = 0; i < chip->nr_cores; i++) { 444 PnvCore *pnv_core = chip->cores[i]; 445 int offset; 446 447 offset = pnv_dt_core(chip, pnv_core, fdt); 448 449 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 450 pa_features_31, sizeof(pa_features_31)))); 451 } 452 453 if (chip->ram_size) { 454 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 455 } 456 457 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 458 } 459 460 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 461 { 462 uint32_t io_base = d->ioport_id; 463 uint32_t io_regs[] = { 464 cpu_to_be32(1), 465 cpu_to_be32(io_base), 466 cpu_to_be32(2) 467 }; 468 char *name; 469 int node; 470 471 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 472 node = fdt_add_subnode(fdt, lpc_off, name); 473 _FDT(node); 474 g_free(name); 475 476 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 477 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 478 } 479 480 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 481 { 482 const char compatible[] = "ns16550\0pnpPNP,501"; 483 uint32_t io_base = d->ioport_id; 484 uint32_t io_regs[] = { 485 cpu_to_be32(1), 486 cpu_to_be32(io_base), 487 cpu_to_be32(8) 488 }; 489 uint32_t irq; 490 char *name; 491 int node; 492 493 irq = object_property_get_uint(OBJECT(d), "irq", &error_fatal); 494 495 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 496 node = fdt_add_subnode(fdt, lpc_off, name); 497 _FDT(node); 498 g_free(name); 499 500 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 501 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 502 sizeof(compatible)))); 503 504 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 505 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 506 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 507 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 508 fdt_get_phandle(fdt, lpc_off)))); 509 510 /* This is needed by Linux */ 511 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 512 } 513 514 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 515 { 516 const char compatible[] = "bt\0ipmi-bt"; 517 uint32_t io_base; 518 uint32_t io_regs[] = { 519 cpu_to_be32(1), 520 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 521 cpu_to_be32(3) 522 }; 523 uint32_t irq; 524 char *name; 525 int node; 526 527 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 528 io_regs[1] = cpu_to_be32(io_base); 529 530 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 531 532 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 533 node = fdt_add_subnode(fdt, lpc_off, name); 534 _FDT(node); 535 g_free(name); 536 537 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 538 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 539 sizeof(compatible)))); 540 541 /* Mark it as reserved to avoid Linux trying to claim it */ 542 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 543 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 544 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 545 fdt_get_phandle(fdt, lpc_off)))); 546 } 547 548 typedef struct ForeachPopulateArgs { 549 void *fdt; 550 int offset; 551 } ForeachPopulateArgs; 552 553 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 554 { 555 ForeachPopulateArgs *args = opaque; 556 ISADevice *d = ISA_DEVICE(dev); 557 558 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 559 pnv_dt_rtc(d, args->fdt, args->offset); 560 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 561 pnv_dt_serial(d, args->fdt, args->offset); 562 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 563 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 564 } else { 565 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 566 d->ioport_id); 567 } 568 569 return 0; 570 } 571 572 /* 573 * The default LPC bus of a multichip system is on chip 0. It's 574 * recognized by the firmware (skiboot) using a "primary" property. 575 */ 576 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 577 { 578 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 579 ForeachPopulateArgs args = { 580 .fdt = fdt, 581 .offset = isa_offset, 582 }; 583 uint32_t phandle; 584 585 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 586 587 phandle = qemu_fdt_alloc_phandle(fdt); 588 assert(phandle > 0); 589 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 590 591 /* 592 * ISA devices are not necessarily parented to the ISA bus so we 593 * can not use object_child_foreach() 594 */ 595 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 596 &args); 597 } 598 599 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 600 { 601 int off; 602 603 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 604 off = fdt_add_subnode(fdt, off, "power-mgt"); 605 606 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 607 } 608 609 static void *pnv_dt_create(MachineState *machine) 610 { 611 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 612 PnvMachineState *pnv = PNV_MACHINE(machine); 613 void *fdt; 614 char *buf; 615 int off; 616 int i; 617 618 fdt = g_malloc0(FDT_MAX_SIZE); 619 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 620 621 /* /qemu node */ 622 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 623 624 /* Root node */ 625 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 626 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 627 _FDT((fdt_setprop_string(fdt, 0, "model", 628 "IBM PowerNV (emulated by qemu)"))); 629 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 630 631 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 632 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 633 if (qemu_uuid_set) { 634 _FDT((fdt_setprop_string(fdt, 0, "system-id", buf))); 635 } 636 g_free(buf); 637 638 off = fdt_add_subnode(fdt, 0, "chosen"); 639 if (machine->kernel_cmdline) { 640 _FDT((fdt_setprop_string(fdt, off, "bootargs", 641 machine->kernel_cmdline))); 642 } 643 644 if (pnv->initrd_size) { 645 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 646 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 647 648 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 649 &start_prop, sizeof(start_prop)))); 650 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 651 &end_prop, sizeof(end_prop)))); 652 } 653 654 /* Populate device tree for each chip */ 655 for (i = 0; i < pnv->num_chips; i++) { 656 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 657 } 658 659 /* Populate ISA devices on chip 0 */ 660 pnv_dt_isa(pnv, fdt); 661 662 if (pnv->bmc) { 663 pnv_dt_bmc_sensors(pnv->bmc, fdt); 664 } 665 666 /* Create an extra node for power management on machines that support it */ 667 if (pmc->dt_power_mgt) { 668 pmc->dt_power_mgt(pnv, fdt); 669 } 670 671 return fdt; 672 } 673 674 static void pnv_powerdown_notify(Notifier *n, void *opaque) 675 { 676 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 677 678 if (pnv->bmc) { 679 pnv_bmc_powerdown(pnv->bmc); 680 } 681 } 682 683 static void pnv_reset(MachineState *machine, ShutdownCause reason) 684 { 685 PnvMachineState *pnv = PNV_MACHINE(machine); 686 IPMIBmc *bmc; 687 void *fdt; 688 689 qemu_devices_reset(reason); 690 691 /* 692 * The machine should provide by default an internal BMC simulator. 693 * If not, try to use the BMC device that was provided on the command 694 * line. 695 */ 696 bmc = pnv_bmc_find(&error_fatal); 697 if (!pnv->bmc) { 698 if (!bmc) { 699 if (!qtest_enabled()) { 700 warn_report("machine has no BMC device. Use '-device " 701 "ipmi-bmc-sim,id=bmc0 -device isa-ipmi-bt,bmc=bmc0,irq=10' " 702 "to define one"); 703 } 704 } else { 705 pnv_bmc_set_pnor(bmc, pnv->pnor); 706 pnv->bmc = bmc; 707 } 708 } 709 710 fdt = pnv_dt_create(machine); 711 712 /* Pack resulting tree */ 713 _FDT((fdt_pack(fdt))); 714 715 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 716 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 717 718 /* 719 * Set machine->fdt for 'dumpdtb' QMP/HMP command. Free 720 * the existing machine->fdt to avoid leaking it during 721 * a reset. 722 */ 723 g_free(machine->fdt); 724 machine->fdt = fdt; 725 } 726 727 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 728 { 729 Pnv8Chip *chip8 = PNV8_CHIP(chip); 730 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_EXTERNAL); 731 732 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 733 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 734 } 735 736 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 737 { 738 Pnv8Chip *chip8 = PNV8_CHIP(chip); 739 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip8->psi), PSIHB_IRQ_LPC_I2C); 740 741 qdev_connect_gpio_out(DEVICE(&chip8->lpc), 0, irq); 742 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 743 } 744 745 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 746 { 747 Pnv9Chip *chip9 = PNV9_CHIP(chip); 748 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip9->psi), PSIHB9_IRQ_LPCHC); 749 750 qdev_connect_gpio_out(DEVICE(&chip9->lpc), 0, irq); 751 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 752 } 753 754 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 755 { 756 Pnv10Chip *chip10 = PNV10_CHIP(chip); 757 qemu_irq irq = qdev_get_gpio_in(DEVICE(&chip10->psi), PSIHB9_IRQ_LPCHC); 758 759 qdev_connect_gpio_out(DEVICE(&chip10->lpc), 0, irq); 760 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 761 } 762 763 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 764 { 765 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 766 } 767 768 static void pnv_chip_power8_pic_print_info(PnvChip *chip, GString *buf) 769 { 770 Pnv8Chip *chip8 = PNV8_CHIP(chip); 771 int i; 772 773 ics_pic_print_info(&chip8->psi.ics, buf); 774 775 for (i = 0; i < chip8->num_phbs; i++) { 776 PnvPHB *phb = chip8->phbs[i]; 777 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 778 779 pnv_phb3_msi_pic_print_info(&phb3->msis, buf); 780 ics_pic_print_info(&phb3->lsis, buf); 781 } 782 } 783 784 static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaque) 785 { 786 GString *buf = opaque; 787 PnvPHB *phb = (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); 788 789 if (!phb) { 790 return 0; 791 } 792 793 pnv_phb4_pic_print_info(PNV_PHB4(phb->backend), buf); 794 795 return 0; 796 } 797 798 static void pnv_chip_power9_pic_print_info(PnvChip *chip, GString *buf) 799 { 800 Pnv9Chip *chip9 = PNV9_CHIP(chip); 801 802 pnv_xive_pic_print_info(&chip9->xive, buf); 803 pnv_psi_pic_print_info(&chip9->psi, buf); 804 object_child_foreach_recursive(OBJECT(chip), 805 pnv_chip_power9_pic_print_info_child, buf); 806 } 807 808 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 809 uint32_t core_id) 810 { 811 return PNV_XSCOM_EX_BASE(core_id); 812 } 813 814 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 815 uint32_t core_id) 816 { 817 return PNV9_XSCOM_EC_BASE(core_id); 818 } 819 820 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 821 uint32_t core_id) 822 { 823 return PNV10_XSCOM_EC_BASE(core_id); 824 } 825 826 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 827 { 828 PowerPCCPUClass *ppc_default = 829 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 830 PowerPCCPUClass *ppc = 831 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 832 833 return ppc_default->pvr_match(ppc_default, ppc->pvr, false); 834 } 835 836 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 837 { 838 ISADevice *dev = isa_new("isa-ipmi-bt"); 839 840 object_property_set_link(OBJECT(dev), "bmc", OBJECT(bmc), &error_fatal); 841 object_property_set_int(OBJECT(dev), "irq", irq, &error_fatal); 842 isa_realize_and_unref(dev, bus, &error_fatal); 843 } 844 845 static void pnv_chip_power10_pic_print_info(PnvChip *chip, GString *buf) 846 { 847 Pnv10Chip *chip10 = PNV10_CHIP(chip); 848 849 pnv_xive2_pic_print_info(&chip10->xive, buf); 850 pnv_psi_pic_print_info(&chip10->psi, buf); 851 object_child_foreach_recursive(OBJECT(chip), 852 pnv_chip_power9_pic_print_info_child, buf); 853 } 854 855 /* Always give the first 1GB to chip 0 else we won't boot */ 856 static uint64_t pnv_chip_get_ram_size(PnvMachineState *pnv, int chip_id) 857 { 858 MachineState *machine = MACHINE(pnv); 859 uint64_t ram_per_chip; 860 861 assert(machine->ram_size >= 1 * GiB); 862 863 ram_per_chip = machine->ram_size / pnv->num_chips; 864 if (ram_per_chip >= 1 * GiB) { 865 return QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 866 } 867 868 assert(pnv->num_chips > 1); 869 870 ram_per_chip = (machine->ram_size - 1 * GiB) / (pnv->num_chips - 1); 871 return chip_id == 0 ? 1 * GiB : QEMU_ALIGN_DOWN(ram_per_chip, 1 * MiB); 872 } 873 874 static void pnv_init(MachineState *machine) 875 { 876 const char *bios_name = machine->firmware ?: FW_FILE_NAME; 877 PnvMachineState *pnv = PNV_MACHINE(machine); 878 MachineClass *mc = MACHINE_GET_CLASS(machine); 879 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 880 char *fw_filename; 881 long fw_size; 882 uint64_t chip_ram_start = 0; 883 int i; 884 char *chip_typename; 885 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 886 DeviceState *dev; 887 888 if (kvm_enabled()) { 889 error_report("machine %s does not support the KVM accelerator", 890 mc->name); 891 exit(EXIT_FAILURE); 892 } 893 894 /* allocate RAM */ 895 if (machine->ram_size < mc->default_ram_size) { 896 char *sz = size_to_str(mc->default_ram_size); 897 error_report("Invalid RAM size, should be bigger than %s", sz); 898 g_free(sz); 899 exit(EXIT_FAILURE); 900 } 901 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 902 903 /* 904 * Create our simple PNOR device 905 */ 906 dev = qdev_new(TYPE_PNV_PNOR); 907 if (pnor) { 908 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor)); 909 } 910 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 911 pnv->pnor = PNV_PNOR(dev); 912 913 /* load skiboot firmware */ 914 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 915 if (!fw_filename) { 916 error_report("Could not find OPAL firmware '%s'", bios_name); 917 exit(1); 918 } 919 920 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 921 if (fw_size < 0) { 922 error_report("Could not load OPAL firmware '%s'", fw_filename); 923 exit(1); 924 } 925 g_free(fw_filename); 926 927 /* load kernel */ 928 if (machine->kernel_filename) { 929 long kernel_size; 930 931 kernel_size = load_image_targphys(machine->kernel_filename, 932 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 933 if (kernel_size < 0) { 934 error_report("Could not load kernel '%s'", 935 machine->kernel_filename); 936 exit(1); 937 } 938 } 939 940 /* load initrd */ 941 if (machine->initrd_filename) { 942 pnv->initrd_base = INITRD_LOAD_ADDR; 943 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 944 pnv->initrd_base, INITRD_MAX_SIZE); 945 if (pnv->initrd_size < 0) { 946 error_report("Could not load initial ram disk '%s'", 947 machine->initrd_filename); 948 exit(1); 949 } 950 } 951 952 /* MSIs are supported on this platform */ 953 msi_nonbroken = true; 954 955 /* 956 * Check compatibility of the specified CPU with the machine 957 * default. 958 */ 959 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 960 error_report("invalid CPU model '%s' for %s machine", 961 machine->cpu_type, mc->name); 962 exit(1); 963 } 964 965 /* Create the processor chips */ 966 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 967 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 968 i, machine->cpu_type); 969 if (!object_class_by_name(chip_typename)) { 970 error_report("invalid chip model '%.*s' for %s machine", 971 i, machine->cpu_type, mc->name); 972 exit(1); 973 } 974 975 pnv->num_chips = 976 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 977 978 if (machine->smp.threads > 8) { 979 error_report("Cannot support more than 8 threads/core " 980 "on a powernv machine"); 981 exit(1); 982 } 983 if (!is_power_of_2(machine->smp.threads)) { 984 error_report("Cannot support %d threads/core on a powernv" 985 "machine because it must be a power of 2", 986 machine->smp.threads); 987 exit(1); 988 } 989 /* 990 * TODO: should we decide on how many chips we can create based 991 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 992 */ 993 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 16) { 994 error_report("invalid number of chips: '%d'", pnv->num_chips); 995 error_printf( 996 "Try '-smp sockets=N'. Valid values are : 1, 2, 4, 8 and 16.\n"); 997 exit(1); 998 } 999 1000 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 1001 for (i = 0; i < pnv->num_chips; i++) { 1002 char chip_name[32]; 1003 Object *chip = OBJECT(qdev_new(chip_typename)); 1004 uint64_t chip_ram_size = pnv_chip_get_ram_size(pnv, i); 1005 1006 pnv->chips[i] = PNV_CHIP(chip); 1007 1008 /* Distribute RAM among the chips */ 1009 object_property_set_int(chip, "ram-start", chip_ram_start, 1010 &error_fatal); 1011 object_property_set_int(chip, "ram-size", chip_ram_size, 1012 &error_fatal); 1013 chip_ram_start += chip_ram_size; 1014 1015 snprintf(chip_name, sizeof(chip_name), "chip[%d]", i); 1016 object_property_add_child(OBJECT(pnv), chip_name, chip); 1017 object_property_set_int(chip, "chip-id", i, &error_fatal); 1018 object_property_set_int(chip, "nr-cores", machine->smp.cores, 1019 &error_fatal); 1020 object_property_set_int(chip, "nr-threads", machine->smp.threads, 1021 &error_fatal); 1022 /* 1023 * The POWER8 machine use the XICS interrupt interface. 1024 * Propagate the XICS fabric to the chip and its controllers. 1025 */ 1026 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 1027 object_property_set_link(chip, "xics", OBJECT(pnv), &error_abort); 1028 } 1029 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 1030 object_property_set_link(chip, "xive-fabric", OBJECT(pnv), 1031 &error_abort); 1032 } 1033 sysbus_realize_and_unref(SYS_BUS_DEVICE(chip), &error_fatal); 1034 } 1035 g_free(chip_typename); 1036 1037 /* Instantiate ISA bus on chip 0 */ 1038 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 1039 1040 /* Create serial port */ 1041 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 1042 1043 /* Create an RTC ISA device too */ 1044 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 1045 1046 /* 1047 * Create the machine BMC simulator and the IPMI BT device for 1048 * communication with the BMC 1049 */ 1050 if (defaults_enabled()) { 1051 pnv->bmc = pnv_bmc_create(pnv->pnor); 1052 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 1053 } 1054 1055 /* 1056 * The PNOR is mapped on the LPC FW address space by the BMC. 1057 * Since we can not reach the remote BMC machine with LPC memops, 1058 * map it always for now. 1059 */ 1060 memory_region_add_subregion(pnv->chips[0]->fw_mr, PNOR_SPI_OFFSET, 1061 &pnv->pnor->mmio); 1062 1063 /* 1064 * OpenPOWER systems use a IPMI SEL Event message to notify the 1065 * host to powerdown 1066 */ 1067 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 1068 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 1069 1070 /* 1071 * Create/Connect any machine-specific I2C devices 1072 */ 1073 if (pmc->i2c_init) { 1074 pmc->i2c_init(pnv); 1075 } 1076 } 1077 1078 /* 1079 * 0:21 Reserved - Read as zeros 1080 * 22:24 Chip ID 1081 * 25:28 Core number 1082 * 29:31 Thread ID 1083 */ 1084 static uint32_t pnv_chip_pir_p8(PnvChip *chip, uint32_t core_id, 1085 uint32_t thread_id) 1086 { 1087 return (chip->chip_id << 7) | (core_id << 3) | thread_id; 1088 } 1089 1090 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1091 Error **errp) 1092 { 1093 Pnv8Chip *chip8 = PNV8_CHIP(chip); 1094 Error *local_err = NULL; 1095 Object *obj; 1096 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1097 1098 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 1099 if (local_err) { 1100 error_propagate(errp, local_err); 1101 return; 1102 } 1103 1104 pnv_cpu->intc = obj; 1105 } 1106 1107 1108 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1109 { 1110 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1111 1112 icp_reset(ICP(pnv_cpu->intc)); 1113 } 1114 1115 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1116 { 1117 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1118 1119 icp_destroy(ICP(pnv_cpu->intc)); 1120 pnv_cpu->intc = NULL; 1121 } 1122 1123 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1124 GString *buf) 1125 { 1126 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), buf); 1127 } 1128 1129 /* 1130 * 0:48 Reserved - Read as zeroes 1131 * 49:52 Node ID 1132 * 53:55 Chip ID 1133 * 56 Reserved - Read as zero 1134 * 57:61 Core number 1135 * 62:63 Thread ID 1136 * 1137 * We only care about the lower bits. uint32_t is fine for the moment. 1138 */ 1139 static uint32_t pnv_chip_pir_p9(PnvChip *chip, uint32_t core_id, 1140 uint32_t thread_id) 1141 { 1142 if (chip->nr_threads == 8) { 1143 return (chip->chip_id << 8) | ((thread_id & 1) << 2) | (core_id << 3) | 1144 (thread_id >> 1); 1145 } else { 1146 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1147 } 1148 } 1149 1150 /* 1151 * 0:48 Reserved - Read as zeroes 1152 * 49:52 Node ID 1153 * 53:55 Chip ID 1154 * 56 Reserved - Read as zero 1155 * 57:59 Quad ID 1156 * 60 Core Chiplet Pair ID 1157 * 61:63 Thread/Core Chiplet ID t0-t2 1158 * 1159 * We only care about the lower bits. uint32_t is fine for the moment. 1160 */ 1161 static uint32_t pnv_chip_pir_p10(PnvChip *chip, uint32_t core_id, 1162 uint32_t thread_id) 1163 { 1164 if (chip->nr_threads == 8) { 1165 return (chip->chip_id << 8) | ((core_id / 4) << 4) | 1166 ((core_id % 2) << 3) | thread_id; 1167 } else { 1168 return (chip->chip_id << 8) | (core_id << 2) | thread_id; 1169 } 1170 } 1171 1172 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1173 Error **errp) 1174 { 1175 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1176 Error *local_err = NULL; 1177 Object *obj; 1178 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1179 1180 /* 1181 * The core creates its interrupt presenter but the XIVE interrupt 1182 * controller object is initialized afterwards. Hopefully, it's 1183 * only used at runtime. 1184 */ 1185 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 1186 &local_err); 1187 if (local_err) { 1188 error_propagate(errp, local_err); 1189 return; 1190 } 1191 1192 pnv_cpu->intc = obj; 1193 } 1194 1195 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1196 { 1197 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1198 1199 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1200 } 1201 1202 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1203 { 1204 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1205 1206 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1207 pnv_cpu->intc = NULL; 1208 } 1209 1210 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1211 GString *buf) 1212 { 1213 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1214 } 1215 1216 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 1217 Error **errp) 1218 { 1219 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1220 Error *local_err = NULL; 1221 Object *obj; 1222 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1223 1224 /* 1225 * The core creates its interrupt presenter but the XIVE2 interrupt 1226 * controller object is initialized afterwards. Hopefully, it's 1227 * only used at runtime. 1228 */ 1229 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip10->xive), 1230 &local_err); 1231 if (local_err) { 1232 error_propagate(errp, local_err); 1233 return; 1234 } 1235 1236 pnv_cpu->intc = obj; 1237 } 1238 1239 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 1240 { 1241 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1242 1243 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 1244 } 1245 1246 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 1247 { 1248 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 1249 1250 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 1251 pnv_cpu->intc = NULL; 1252 } 1253 1254 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 1255 GString *buf) 1256 { 1257 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), buf); 1258 } 1259 1260 /* 1261 * Allowed core identifiers on a POWER8 Processor Chip : 1262 * 1263 * <EX0 reserved> 1264 * EX1 - Venice only 1265 * EX2 - Venice only 1266 * EX3 - Venice only 1267 * EX4 1268 * EX5 1269 * EX6 1270 * <EX7,8 reserved> <reserved> 1271 * EX9 - Venice only 1272 * EX10 - Venice only 1273 * EX11 - Venice only 1274 * EX12 1275 * EX13 1276 * EX14 1277 * <EX15 reserved> 1278 */ 1279 #define POWER8E_CORE_MASK (0x7070ull) 1280 #define POWER8_CORE_MASK (0x7e7eull) 1281 1282 /* 1283 * POWER9 has 24 cores, ids starting at 0x0 1284 */ 1285 #define POWER9_CORE_MASK (0xffffffffffffffull) 1286 1287 1288 #define POWER10_CORE_MASK (0xffffffffffffffull) 1289 1290 static void pnv_chip_power8_instance_init(Object *obj) 1291 { 1292 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1293 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1294 int i; 1295 1296 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1297 (Object **)&chip8->xics, 1298 object_property_allow_set_link, 1299 OBJ_PROP_LINK_STRONG); 1300 1301 object_initialize_child(obj, "psi", &chip8->psi, TYPE_PNV8_PSI); 1302 1303 object_initialize_child(obj, "lpc", &chip8->lpc, TYPE_PNV8_LPC); 1304 1305 object_initialize_child(obj, "occ", &chip8->occ, TYPE_PNV8_OCC); 1306 1307 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); 1308 1309 if (defaults_enabled()) { 1310 chip8->num_phbs = pcc->num_phbs; 1311 1312 for (i = 0; i < chip8->num_phbs; i++) { 1313 Object *phb = object_new(TYPE_PNV_PHB); 1314 1315 /* 1316 * We need the chip to parent the PHB to allow the DT 1317 * to build correctly (via pnv_xscom_dt()). 1318 * 1319 * TODO: the PHB should be parented by a PEC device that, at 1320 * this moment, is not modelled powernv8/phb3. 1321 */ 1322 object_property_add_child(obj, "phb[*]", phb); 1323 chip8->phbs[i] = PNV_PHB(phb); 1324 } 1325 } 1326 1327 } 1328 1329 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1330 { 1331 PnvChip *chip = PNV_CHIP(chip8); 1332 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1333 int i, j; 1334 char *name; 1335 1336 name = g_strdup_printf("icp-%x", chip->chip_id); 1337 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1338 g_free(name); 1339 memory_region_add_subregion(get_system_memory(), PNV_ICP_BASE(chip), 1340 &chip8->icp_mmio); 1341 1342 /* Map the ICP registers for each thread */ 1343 for (i = 0; i < chip->nr_cores; i++) { 1344 PnvCore *pnv_core = chip->cores[i]; 1345 int core_hwid = CPU_CORE(pnv_core)->core_id; 1346 1347 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1348 uint32_t pir = pcc->chip_pir(chip, core_hwid, j); 1349 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1350 1351 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1352 &icp->mmio); 1353 } 1354 } 1355 } 1356 1357 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1358 { 1359 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1360 PnvChip *chip = PNV_CHIP(dev); 1361 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1362 Pnv8Psi *psi8 = &chip8->psi; 1363 Error *local_err = NULL; 1364 int i; 1365 1366 assert(chip8->xics); 1367 1368 /* XSCOM bridge is first */ 1369 pnv_xscom_init(chip, PNV_XSCOM_SIZE, PNV_XSCOM_BASE(chip)); 1370 1371 pcc->parent_realize(dev, &local_err); 1372 if (local_err) { 1373 error_propagate(errp, local_err); 1374 return; 1375 } 1376 1377 /* Processor Service Interface (PSI) Host Bridge */ 1378 object_property_set_int(OBJECT(psi8), "bar", PNV_PSIHB_BASE(chip), 1379 &error_fatal); 1380 object_property_set_link(OBJECT(psi8), ICS_PROP_XICS, 1381 OBJECT(chip8->xics), &error_abort); 1382 if (!qdev_realize(DEVICE(psi8), NULL, errp)) { 1383 return; 1384 } 1385 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1386 &PNV_PSI(psi8)->xscom_regs); 1387 1388 /* Create LPC controller */ 1389 qdev_realize(DEVICE(&chip8->lpc), NULL, &error_fatal); 1390 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1391 1392 chip->fw_mr = &chip8->lpc.isa_fw; 1393 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1394 (uint64_t) PNV_XSCOM_BASE(chip), 1395 PNV_XSCOM_LPC_BASE); 1396 1397 /* 1398 * Interrupt Management Area. This is the memory region holding 1399 * all the Interrupt Control Presenter (ICP) registers 1400 */ 1401 pnv_chip_icp_realize(chip8, &local_err); 1402 if (local_err) { 1403 error_propagate(errp, local_err); 1404 return; 1405 } 1406 1407 /* Create the simplified OCC model */ 1408 if (!qdev_realize(DEVICE(&chip8->occ), NULL, errp)) { 1409 return; 1410 } 1411 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1412 qdev_connect_gpio_out(DEVICE(&chip8->occ), 0, 1413 qdev_get_gpio_in(DEVICE(psi8), PSIHB_IRQ_OCC)); 1414 1415 /* OCC SRAM model */ 1416 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1417 &chip8->occ.sram_regs); 1418 1419 /* HOMER */ 1420 object_property_set_link(OBJECT(&chip8->homer), "chip", OBJECT(chip), 1421 &error_abort); 1422 if (!qdev_realize(DEVICE(&chip8->homer), NULL, errp)) { 1423 return; 1424 } 1425 /* Homer Xscom region */ 1426 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1427 1428 /* Homer mmio region */ 1429 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1430 &chip8->homer.regs); 1431 1432 /* PHB controllers */ 1433 for (i = 0; i < chip8->num_phbs; i++) { 1434 PnvPHB *phb = chip8->phbs[i]; 1435 1436 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); 1437 object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, 1438 &error_fatal); 1439 object_property_set_link(OBJECT(phb), "chip", OBJECT(chip), 1440 &error_fatal); 1441 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 1442 return; 1443 } 1444 } 1445 } 1446 1447 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1448 { 1449 addr &= (PNV_XSCOM_SIZE - 1); 1450 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1451 } 1452 1453 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1454 { 1455 DeviceClass *dc = DEVICE_CLASS(klass); 1456 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1457 1458 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1459 k->cores_mask = POWER8E_CORE_MASK; 1460 k->num_phbs = 3; 1461 k->chip_pir = pnv_chip_pir_p8; 1462 k->intc_create = pnv_chip_power8_intc_create; 1463 k->intc_reset = pnv_chip_power8_intc_reset; 1464 k->intc_destroy = pnv_chip_power8_intc_destroy; 1465 k->intc_print_info = pnv_chip_power8_intc_print_info; 1466 k->isa_create = pnv_chip_power8_isa_create; 1467 k->dt_populate = pnv_chip_power8_dt_populate; 1468 k->pic_print_info = pnv_chip_power8_pic_print_info; 1469 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1470 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1471 dc->desc = "PowerNV Chip POWER8E"; 1472 1473 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1474 &k->parent_realize); 1475 } 1476 1477 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1478 { 1479 DeviceClass *dc = DEVICE_CLASS(klass); 1480 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1481 1482 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1483 k->cores_mask = POWER8_CORE_MASK; 1484 k->num_phbs = 3; 1485 k->chip_pir = pnv_chip_pir_p8; 1486 k->intc_create = pnv_chip_power8_intc_create; 1487 k->intc_reset = pnv_chip_power8_intc_reset; 1488 k->intc_destroy = pnv_chip_power8_intc_destroy; 1489 k->intc_print_info = pnv_chip_power8_intc_print_info; 1490 k->isa_create = pnv_chip_power8_isa_create; 1491 k->dt_populate = pnv_chip_power8_dt_populate; 1492 k->pic_print_info = pnv_chip_power8_pic_print_info; 1493 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1494 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1495 dc->desc = "PowerNV Chip POWER8"; 1496 1497 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1498 &k->parent_realize); 1499 } 1500 1501 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1502 { 1503 DeviceClass *dc = DEVICE_CLASS(klass); 1504 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1505 1506 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1507 k->cores_mask = POWER8_CORE_MASK; 1508 k->num_phbs = 4; 1509 k->chip_pir = pnv_chip_pir_p8; 1510 k->intc_create = pnv_chip_power8_intc_create; 1511 k->intc_reset = pnv_chip_power8_intc_reset; 1512 k->intc_destroy = pnv_chip_power8_intc_destroy; 1513 k->intc_print_info = pnv_chip_power8_intc_print_info; 1514 k->isa_create = pnv_chip_power8nvl_isa_create; 1515 k->dt_populate = pnv_chip_power8_dt_populate; 1516 k->pic_print_info = pnv_chip_power8_pic_print_info; 1517 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1518 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1519 dc->desc = "PowerNV Chip POWER8NVL"; 1520 1521 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1522 &k->parent_realize); 1523 } 1524 1525 static void pnv_chip_power9_instance_init(Object *obj) 1526 { 1527 PnvChip *chip = PNV_CHIP(obj); 1528 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1529 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1530 int i; 1531 1532 object_initialize_child(obj, "xive", &chip9->xive, TYPE_PNV_XIVE); 1533 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1534 "xive-fabric"); 1535 1536 object_initialize_child(obj, "psi", &chip9->psi, TYPE_PNV9_PSI); 1537 1538 object_initialize_child(obj, "lpc", &chip9->lpc, TYPE_PNV9_LPC); 1539 1540 object_initialize_child(obj, "chiptod", &chip9->chiptod, TYPE_PNV9_CHIPTOD); 1541 1542 object_initialize_child(obj, "occ", &chip9->occ, TYPE_PNV9_OCC); 1543 1544 object_initialize_child(obj, "sbe", &chip9->sbe, TYPE_PNV9_SBE); 1545 1546 object_initialize_child(obj, "homer", &chip9->homer, TYPE_PNV9_HOMER); 1547 1548 /* Number of PECs is the chip default */ 1549 chip->num_pecs = pcc->num_pecs; 1550 1551 for (i = 0; i < chip->num_pecs; i++) { 1552 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1553 TYPE_PNV_PHB4_PEC); 1554 } 1555 1556 for (i = 0; i < pcc->i2c_num_engines; i++) { 1557 object_initialize_child(obj, "i2c[*]", &chip9->i2c[i], TYPE_PNV_I2C); 1558 } 1559 } 1560 1561 static void pnv_chip_quad_realize_one(PnvChip *chip, PnvQuad *eq, 1562 PnvCore *pnv_core, 1563 const char *type) 1564 { 1565 char eq_name[32]; 1566 int core_id = CPU_CORE(pnv_core)->core_id; 1567 1568 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1569 object_initialize_child_with_props(OBJECT(chip), eq_name, eq, 1570 sizeof(*eq), type, 1571 &error_fatal, NULL); 1572 1573 object_property_set_int(OBJECT(eq), "quad-id", core_id, &error_fatal); 1574 qdev_realize(DEVICE(eq), NULL, &error_fatal); 1575 } 1576 1577 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1578 { 1579 PnvChip *chip = PNV_CHIP(chip9); 1580 int i; 1581 1582 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1583 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1584 1585 for (i = 0; i < chip9->nr_quads; i++) { 1586 PnvQuad *eq = &chip9->quads[i]; 1587 1588 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1589 PNV_QUAD_TYPE_NAME("power9")); 1590 1591 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->quad_id), 1592 &eq->xscom_regs); 1593 } 1594 } 1595 1596 static void pnv_chip_power9_pec_realize(PnvChip *chip, Error **errp) 1597 { 1598 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1599 int i; 1600 1601 for (i = 0; i < chip->num_pecs; i++) { 1602 PnvPhb4PecState *pec = &chip9->pecs[i]; 1603 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1604 uint32_t pec_nest_base; 1605 uint32_t pec_pci_base; 1606 1607 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1608 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1609 &error_fatal); 1610 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1611 &error_fatal); 1612 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1613 return; 1614 } 1615 1616 pec_nest_base = pecc->xscom_nest_base(pec); 1617 pec_pci_base = pecc->xscom_pci_base(pec); 1618 1619 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1620 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1621 } 1622 } 1623 1624 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1625 { 1626 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1627 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1628 PnvChip *chip = PNV_CHIP(dev); 1629 Pnv9Psi *psi9 = &chip9->psi; 1630 Error *local_err = NULL; 1631 int i; 1632 1633 /* XSCOM bridge is first */ 1634 pnv_xscom_init(chip, PNV9_XSCOM_SIZE, PNV9_XSCOM_BASE(chip)); 1635 1636 pcc->parent_realize(dev, &local_err); 1637 if (local_err) { 1638 error_propagate(errp, local_err); 1639 return; 1640 } 1641 1642 pnv_chip_quad_realize(chip9, &local_err); 1643 if (local_err) { 1644 error_propagate(errp, local_err); 1645 return; 1646 } 1647 1648 /* XIVE interrupt controller (POWER9) */ 1649 object_property_set_int(OBJECT(&chip9->xive), "ic-bar", 1650 PNV9_XIVE_IC_BASE(chip), &error_fatal); 1651 object_property_set_int(OBJECT(&chip9->xive), "vc-bar", 1652 PNV9_XIVE_VC_BASE(chip), &error_fatal); 1653 object_property_set_int(OBJECT(&chip9->xive), "pc-bar", 1654 PNV9_XIVE_PC_BASE(chip), &error_fatal); 1655 object_property_set_int(OBJECT(&chip9->xive), "tm-bar", 1656 PNV9_XIVE_TM_BASE(chip), &error_fatal); 1657 object_property_set_link(OBJECT(&chip9->xive), "chip", OBJECT(chip), 1658 &error_abort); 1659 if (!sysbus_realize(SYS_BUS_DEVICE(&chip9->xive), errp)) { 1660 return; 1661 } 1662 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1663 &chip9->xive.xscom_regs); 1664 1665 /* Processor Service Interface (PSI) Host Bridge */ 1666 object_property_set_int(OBJECT(psi9), "bar", PNV9_PSIHB_BASE(chip), 1667 &error_fatal); 1668 /* This is the only device with 4k ESB pages */ 1669 object_property_set_int(OBJECT(psi9), "shift", XIVE_ESB_4K, 1670 &error_fatal); 1671 if (!qdev_realize(DEVICE(psi9), NULL, errp)) { 1672 return; 1673 } 1674 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1675 &PNV_PSI(psi9)->xscom_regs); 1676 1677 /* LPC */ 1678 if (!qdev_realize(DEVICE(&chip9->lpc), NULL, errp)) { 1679 return; 1680 } 1681 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1682 &chip9->lpc.xscom_regs); 1683 1684 chip->fw_mr = &chip9->lpc.isa_fw; 1685 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1686 (uint64_t) PNV9_LPCM_BASE(chip)); 1687 1688 /* ChipTOD */ 1689 object_property_set_bool(OBJECT(&chip9->chiptod), "primary", 1690 chip->chip_id == 0, &error_abort); 1691 object_property_set_bool(OBJECT(&chip9->chiptod), "secondary", 1692 chip->chip_id == 1, &error_abort); 1693 object_property_set_link(OBJECT(&chip9->chiptod), "chip", OBJECT(chip), 1694 &error_abort); 1695 if (!qdev_realize(DEVICE(&chip9->chiptod), NULL, errp)) { 1696 return; 1697 } 1698 pnv_xscom_add_subregion(chip, PNV9_XSCOM_CHIPTOD_BASE, 1699 &chip9->chiptod.xscom_regs); 1700 1701 /* Create the simplified OCC model */ 1702 if (!qdev_realize(DEVICE(&chip9->occ), NULL, errp)) { 1703 return; 1704 } 1705 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1706 qdev_connect_gpio_out(DEVICE(&chip9->occ), 0, qdev_get_gpio_in( 1707 DEVICE(psi9), PSIHB9_IRQ_OCC)); 1708 1709 /* OCC SRAM model */ 1710 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1711 &chip9->occ.sram_regs); 1712 1713 /* SBE */ 1714 if (!qdev_realize(DEVICE(&chip9->sbe), NULL, errp)) { 1715 return; 1716 } 1717 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_CTRL_BASE, 1718 &chip9->sbe.xscom_ctrl_regs); 1719 pnv_xscom_add_subregion(chip, PNV9_XSCOM_SBE_MBOX_BASE, 1720 &chip9->sbe.xscom_mbox_regs); 1721 qdev_connect_gpio_out(DEVICE(&chip9->sbe), 0, qdev_get_gpio_in( 1722 DEVICE(psi9), PSIHB9_IRQ_PSU)); 1723 1724 /* HOMER */ 1725 object_property_set_link(OBJECT(&chip9->homer), "chip", OBJECT(chip), 1726 &error_abort); 1727 if (!qdev_realize(DEVICE(&chip9->homer), NULL, errp)) { 1728 return; 1729 } 1730 /* Homer Xscom region */ 1731 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1732 1733 /* Homer mmio region */ 1734 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1735 &chip9->homer.regs); 1736 1737 /* PEC PHBs */ 1738 pnv_chip_power9_pec_realize(chip, &local_err); 1739 if (local_err) { 1740 error_propagate(errp, local_err); 1741 return; 1742 } 1743 1744 /* 1745 * I2C 1746 */ 1747 for (i = 0; i < pcc->i2c_num_engines; i++) { 1748 Object *obj = OBJECT(&chip9->i2c[i]); 1749 1750 object_property_set_int(obj, "engine", i + 1, &error_fatal); 1751 object_property_set_int(obj, "num-busses", 1752 pcc->i2c_ports_per_engine[i], 1753 &error_fatal); 1754 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 1755 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 1756 return; 1757 } 1758 pnv_xscom_add_subregion(chip, PNV9_XSCOM_I2CM_BASE + 1759 (chip9->i2c[i].engine - 1) * 1760 PNV9_XSCOM_I2CM_SIZE, 1761 &chip9->i2c[i].xscom_regs); 1762 qdev_connect_gpio_out(DEVICE(&chip9->i2c[i]), 0, 1763 qdev_get_gpio_in(DEVICE(psi9), 1764 PSIHB9_IRQ_SBE_I2C)); 1765 } 1766 } 1767 1768 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1769 { 1770 addr &= (PNV9_XSCOM_SIZE - 1); 1771 return addr >> 3; 1772 } 1773 1774 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1775 { 1776 DeviceClass *dc = DEVICE_CLASS(klass); 1777 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1778 static const int i2c_ports_per_engine[PNV9_CHIP_MAX_I2C] = {2, 13, 2, 2}; 1779 1780 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1781 k->cores_mask = POWER9_CORE_MASK; 1782 k->chip_pir = pnv_chip_pir_p9; 1783 k->intc_create = pnv_chip_power9_intc_create; 1784 k->intc_reset = pnv_chip_power9_intc_reset; 1785 k->intc_destroy = pnv_chip_power9_intc_destroy; 1786 k->intc_print_info = pnv_chip_power9_intc_print_info; 1787 k->isa_create = pnv_chip_power9_isa_create; 1788 k->dt_populate = pnv_chip_power9_dt_populate; 1789 k->pic_print_info = pnv_chip_power9_pic_print_info; 1790 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1791 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1792 dc->desc = "PowerNV Chip POWER9"; 1793 k->num_pecs = PNV9_CHIP_MAX_PEC; 1794 k->i2c_num_engines = PNV9_CHIP_MAX_I2C; 1795 k->i2c_ports_per_engine = i2c_ports_per_engine; 1796 1797 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1798 &k->parent_realize); 1799 } 1800 1801 static void pnv_chip_power10_instance_init(Object *obj) 1802 { 1803 PnvChip *chip = PNV_CHIP(obj); 1804 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1805 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1806 int i; 1807 1808 object_initialize_child(obj, "xive", &chip10->xive, TYPE_PNV_XIVE2); 1809 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip10->xive), 1810 "xive-fabric"); 1811 object_initialize_child(obj, "psi", &chip10->psi, TYPE_PNV10_PSI); 1812 object_initialize_child(obj, "lpc", &chip10->lpc, TYPE_PNV10_LPC); 1813 object_initialize_child(obj, "chiptod", &chip10->chiptod, 1814 TYPE_PNV10_CHIPTOD); 1815 object_initialize_child(obj, "occ", &chip10->occ, TYPE_PNV10_OCC); 1816 object_initialize_child(obj, "sbe", &chip10->sbe, TYPE_PNV10_SBE); 1817 object_initialize_child(obj, "homer", &chip10->homer, TYPE_PNV10_HOMER); 1818 object_initialize_child(obj, "n1-chiplet", &chip10->n1_chiplet, 1819 TYPE_PNV_N1_CHIPLET); 1820 1821 chip->num_pecs = pcc->num_pecs; 1822 1823 for (i = 0; i < chip->num_pecs; i++) { 1824 object_initialize_child(obj, "pec[*]", &chip10->pecs[i], 1825 TYPE_PNV_PHB5_PEC); 1826 } 1827 1828 for (i = 0; i < pcc->i2c_num_engines; i++) { 1829 object_initialize_child(obj, "i2c[*]", &chip10->i2c[i], TYPE_PNV_I2C); 1830 } 1831 } 1832 1833 static void pnv_chip_power10_quad_realize(Pnv10Chip *chip10, Error **errp) 1834 { 1835 PnvChip *chip = PNV_CHIP(chip10); 1836 int i; 1837 1838 chip10->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1839 chip10->quads = g_new0(PnvQuad, chip10->nr_quads); 1840 1841 for (i = 0; i < chip10->nr_quads; i++) { 1842 PnvQuad *eq = &chip10->quads[i]; 1843 1844 pnv_chip_quad_realize_one(chip, eq, chip->cores[i * 4], 1845 PNV_QUAD_TYPE_NAME("power10")); 1846 1847 pnv_xscom_add_subregion(chip, PNV10_XSCOM_EQ_BASE(eq->quad_id), 1848 &eq->xscom_regs); 1849 1850 pnv_xscom_add_subregion(chip, PNV10_XSCOM_QME_BASE(eq->quad_id), 1851 &eq->xscom_qme_regs); 1852 } 1853 } 1854 1855 static void pnv_chip_power10_phb_realize(PnvChip *chip, Error **errp) 1856 { 1857 Pnv10Chip *chip10 = PNV10_CHIP(chip); 1858 int i; 1859 1860 for (i = 0; i < chip->num_pecs; i++) { 1861 PnvPhb4PecState *pec = &chip10->pecs[i]; 1862 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1863 uint32_t pec_nest_base; 1864 uint32_t pec_pci_base; 1865 1866 object_property_set_int(OBJECT(pec), "index", i, &error_fatal); 1867 object_property_set_int(OBJECT(pec), "chip-id", chip->chip_id, 1868 &error_fatal); 1869 object_property_set_link(OBJECT(pec), "chip", OBJECT(chip), 1870 &error_fatal); 1871 if (!qdev_realize(DEVICE(pec), NULL, errp)) { 1872 return; 1873 } 1874 1875 pec_nest_base = pecc->xscom_nest_base(pec); 1876 pec_pci_base = pecc->xscom_pci_base(pec); 1877 1878 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1879 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1880 } 1881 } 1882 1883 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1884 { 1885 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1886 PnvChip *chip = PNV_CHIP(dev); 1887 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1888 Error *local_err = NULL; 1889 int i; 1890 1891 /* XSCOM bridge is first */ 1892 pnv_xscom_init(chip, PNV10_XSCOM_SIZE, PNV10_XSCOM_BASE(chip)); 1893 1894 pcc->parent_realize(dev, &local_err); 1895 if (local_err) { 1896 error_propagate(errp, local_err); 1897 return; 1898 } 1899 1900 pnv_chip_power10_quad_realize(chip10, &local_err); 1901 if (local_err) { 1902 error_propagate(errp, local_err); 1903 return; 1904 } 1905 1906 /* XIVE2 interrupt controller (POWER10) */ 1907 object_property_set_int(OBJECT(&chip10->xive), "ic-bar", 1908 PNV10_XIVE2_IC_BASE(chip), &error_fatal); 1909 object_property_set_int(OBJECT(&chip10->xive), "esb-bar", 1910 PNV10_XIVE2_ESB_BASE(chip), &error_fatal); 1911 object_property_set_int(OBJECT(&chip10->xive), "end-bar", 1912 PNV10_XIVE2_END_BASE(chip), &error_fatal); 1913 object_property_set_int(OBJECT(&chip10->xive), "nvpg-bar", 1914 PNV10_XIVE2_NVPG_BASE(chip), &error_fatal); 1915 object_property_set_int(OBJECT(&chip10->xive), "nvc-bar", 1916 PNV10_XIVE2_NVC_BASE(chip), &error_fatal); 1917 object_property_set_int(OBJECT(&chip10->xive), "tm-bar", 1918 PNV10_XIVE2_TM_BASE(chip), &error_fatal); 1919 object_property_set_link(OBJECT(&chip10->xive), "chip", OBJECT(chip), 1920 &error_abort); 1921 if (!sysbus_realize(SYS_BUS_DEVICE(&chip10->xive), errp)) { 1922 return; 1923 } 1924 pnv_xscom_add_subregion(chip, PNV10_XSCOM_XIVE2_BASE, 1925 &chip10->xive.xscom_regs); 1926 1927 /* Processor Service Interface (PSI) Host Bridge */ 1928 object_property_set_int(OBJECT(&chip10->psi), "bar", 1929 PNV10_PSIHB_BASE(chip), &error_fatal); 1930 /* PSI can now be configured to use 64k ESB pages on POWER10 */ 1931 object_property_set_int(OBJECT(&chip10->psi), "shift", XIVE_ESB_64K, 1932 &error_fatal); 1933 if (!qdev_realize(DEVICE(&chip10->psi), NULL, errp)) { 1934 return; 1935 } 1936 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1937 &PNV_PSI(&chip10->psi)->xscom_regs); 1938 1939 /* LPC */ 1940 if (!qdev_realize(DEVICE(&chip10->lpc), NULL, errp)) { 1941 return; 1942 } 1943 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1944 &chip10->lpc.xscom_regs); 1945 1946 chip->fw_mr = &chip10->lpc.isa_fw; 1947 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1948 (uint64_t) PNV10_LPCM_BASE(chip)); 1949 1950 /* ChipTOD */ 1951 object_property_set_bool(OBJECT(&chip10->chiptod), "primary", 1952 chip->chip_id == 0, &error_abort); 1953 object_property_set_bool(OBJECT(&chip10->chiptod), "secondary", 1954 chip->chip_id == 1, &error_abort); 1955 object_property_set_link(OBJECT(&chip10->chiptod), "chip", OBJECT(chip), 1956 &error_abort); 1957 if (!qdev_realize(DEVICE(&chip10->chiptod), NULL, errp)) { 1958 return; 1959 } 1960 pnv_xscom_add_subregion(chip, PNV10_XSCOM_CHIPTOD_BASE, 1961 &chip10->chiptod.xscom_regs); 1962 1963 /* Create the simplified OCC model */ 1964 if (!qdev_realize(DEVICE(&chip10->occ), NULL, errp)) { 1965 return; 1966 } 1967 pnv_xscom_add_subregion(chip, PNV10_XSCOM_OCC_BASE, 1968 &chip10->occ.xscom_regs); 1969 qdev_connect_gpio_out(DEVICE(&chip10->occ), 0, qdev_get_gpio_in( 1970 DEVICE(&chip10->psi), PSIHB9_IRQ_OCC)); 1971 1972 /* OCC SRAM model */ 1973 memory_region_add_subregion(get_system_memory(), 1974 PNV10_OCC_SENSOR_BASE(chip), 1975 &chip10->occ.sram_regs); 1976 1977 /* SBE */ 1978 if (!qdev_realize(DEVICE(&chip10->sbe), NULL, errp)) { 1979 return; 1980 } 1981 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_CTRL_BASE, 1982 &chip10->sbe.xscom_ctrl_regs); 1983 pnv_xscom_add_subregion(chip, PNV10_XSCOM_SBE_MBOX_BASE, 1984 &chip10->sbe.xscom_mbox_regs); 1985 qdev_connect_gpio_out(DEVICE(&chip10->sbe), 0, qdev_get_gpio_in( 1986 DEVICE(&chip10->psi), PSIHB9_IRQ_PSU)); 1987 1988 /* HOMER */ 1989 object_property_set_link(OBJECT(&chip10->homer), "chip", OBJECT(chip), 1990 &error_abort); 1991 if (!qdev_realize(DEVICE(&chip10->homer), NULL, errp)) { 1992 return; 1993 } 1994 /* Homer Xscom region */ 1995 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PBA_BASE, 1996 &chip10->homer.pba_regs); 1997 1998 /* Homer mmio region */ 1999 memory_region_add_subregion(get_system_memory(), PNV10_HOMER_BASE(chip), 2000 &chip10->homer.regs); 2001 2002 /* N1 chiplet */ 2003 if (!qdev_realize(DEVICE(&chip10->n1_chiplet), NULL, errp)) { 2004 return; 2005 } 2006 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_CHIPLET_CTRL_REGS_BASE, 2007 &chip10->n1_chiplet.nest_pervasive.xscom_ctrl_regs_mr); 2008 2009 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_EQ_BASE, 2010 &chip10->n1_chiplet.xscom_pb_eq_mr); 2011 2012 pnv_xscom_add_subregion(chip, PNV10_XSCOM_N1_PB_SCOM_ES_BASE, 2013 &chip10->n1_chiplet.xscom_pb_es_mr); 2014 2015 /* PHBs */ 2016 pnv_chip_power10_phb_realize(chip, &local_err); 2017 if (local_err) { 2018 error_propagate(errp, local_err); 2019 return; 2020 } 2021 2022 2023 /* 2024 * I2C 2025 */ 2026 for (i = 0; i < pcc->i2c_num_engines; i++) { 2027 Object *obj = OBJECT(&chip10->i2c[i]); 2028 2029 object_property_set_int(obj, "engine", i + 1, &error_fatal); 2030 object_property_set_int(obj, "num-busses", 2031 pcc->i2c_ports_per_engine[i], 2032 &error_fatal); 2033 object_property_set_link(obj, "chip", OBJECT(chip), &error_abort); 2034 if (!qdev_realize(DEVICE(obj), NULL, errp)) { 2035 return; 2036 } 2037 pnv_xscom_add_subregion(chip, PNV10_XSCOM_I2CM_BASE + 2038 (chip10->i2c[i].engine - 1) * 2039 PNV10_XSCOM_I2CM_SIZE, 2040 &chip10->i2c[i].xscom_regs); 2041 qdev_connect_gpio_out(DEVICE(&chip10->i2c[i]), 0, 2042 qdev_get_gpio_in(DEVICE(&chip10->psi), 2043 PSIHB9_IRQ_SBE_I2C)); 2044 } 2045 2046 } 2047 2048 static void pnv_rainier_i2c_init(PnvMachineState *pnv) 2049 { 2050 int i; 2051 for (i = 0; i < pnv->num_chips; i++) { 2052 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2053 2054 /* 2055 * Add a PCA9552 I2C device for PCIe hotplug control 2056 * to engine 2, bus 1, address 0x63 2057 */ 2058 I2CSlave *dev = i2c_slave_create_simple(chip10->i2c[2].busses[1], 2059 "pca9552", 0x63); 2060 2061 /* 2062 * Connect PCA9552 GPIO pins 0-4 (SLOTx_EN) outputs to GPIO pins 5-9 2063 * (SLOTx_PG) inputs in order to fake the pgood state of PCIe slots 2064 * after hypervisor code sets a SLOTx_EN pin high. 2065 */ 2066 qdev_connect_gpio_out(DEVICE(dev), 0, qdev_get_gpio_in(DEVICE(dev), 5)); 2067 qdev_connect_gpio_out(DEVICE(dev), 1, qdev_get_gpio_in(DEVICE(dev), 6)); 2068 qdev_connect_gpio_out(DEVICE(dev), 2, qdev_get_gpio_in(DEVICE(dev), 7)); 2069 qdev_connect_gpio_out(DEVICE(dev), 3, qdev_get_gpio_in(DEVICE(dev), 8)); 2070 qdev_connect_gpio_out(DEVICE(dev), 4, qdev_get_gpio_in(DEVICE(dev), 9)); 2071 2072 /* 2073 * Add a PCA9554 I2C device for cable card presence detection 2074 * to engine 2, bus 1, address 0x25 2075 */ 2076 i2c_slave_create_simple(chip10->i2c[2].busses[1], "pca9554", 0x25); 2077 } 2078 } 2079 2080 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 2081 { 2082 addr &= (PNV10_XSCOM_SIZE - 1); 2083 return addr >> 3; 2084 } 2085 2086 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 2087 { 2088 DeviceClass *dc = DEVICE_CLASS(klass); 2089 PnvChipClass *k = PNV_CHIP_CLASS(klass); 2090 static const int i2c_ports_per_engine[PNV10_CHIP_MAX_I2C] = {14, 14, 2, 16}; 2091 2092 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 2093 k->cores_mask = POWER10_CORE_MASK; 2094 k->chip_pir = pnv_chip_pir_p10; 2095 k->intc_create = pnv_chip_power10_intc_create; 2096 k->intc_reset = pnv_chip_power10_intc_reset; 2097 k->intc_destroy = pnv_chip_power10_intc_destroy; 2098 k->intc_print_info = pnv_chip_power10_intc_print_info; 2099 k->isa_create = pnv_chip_power10_isa_create; 2100 k->dt_populate = pnv_chip_power10_dt_populate; 2101 k->pic_print_info = pnv_chip_power10_pic_print_info; 2102 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 2103 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 2104 dc->desc = "PowerNV Chip POWER10"; 2105 k->num_pecs = PNV10_CHIP_MAX_PEC; 2106 k->i2c_num_engines = PNV10_CHIP_MAX_I2C; 2107 k->i2c_ports_per_engine = i2c_ports_per_engine; 2108 2109 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 2110 &k->parent_realize); 2111 } 2112 2113 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 2114 { 2115 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2116 int cores_max; 2117 2118 /* 2119 * No custom mask for this chip, let's use the default one from * 2120 * the chip class 2121 */ 2122 if (!chip->cores_mask) { 2123 chip->cores_mask = pcc->cores_mask; 2124 } 2125 2126 /* filter alien core ids ! some are reserved */ 2127 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 2128 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 2129 chip->cores_mask); 2130 return; 2131 } 2132 chip->cores_mask &= pcc->cores_mask; 2133 2134 /* now that we have a sane layout, let check the number of cores */ 2135 cores_max = ctpop64(chip->cores_mask); 2136 if (chip->nr_cores > cores_max) { 2137 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 2138 cores_max); 2139 return; 2140 } 2141 } 2142 2143 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 2144 { 2145 Error *error = NULL; 2146 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 2147 const char *typename = pnv_chip_core_typename(chip); 2148 int i, core_hwid; 2149 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 2150 2151 if (!object_class_by_name(typename)) { 2152 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 2153 return; 2154 } 2155 2156 /* Cores */ 2157 pnv_chip_core_sanitize(chip, &error); 2158 if (error) { 2159 error_propagate(errp, error); 2160 return; 2161 } 2162 2163 chip->cores = g_new0(PnvCore *, chip->nr_cores); 2164 2165 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 2166 && (i < chip->nr_cores); core_hwid++) { 2167 char core_name[32]; 2168 PnvCore *pnv_core; 2169 uint64_t xscom_core_base; 2170 2171 if (!(chip->cores_mask & (1ull << core_hwid))) { 2172 continue; 2173 } 2174 2175 pnv_core = PNV_CORE(object_new(typename)); 2176 2177 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 2178 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core)); 2179 chip->cores[i] = pnv_core; 2180 object_property_set_int(OBJECT(pnv_core), "nr-threads", 2181 chip->nr_threads, &error_fatal); 2182 object_property_set_int(OBJECT(pnv_core), CPU_CORE_PROP_CORE_ID, 2183 core_hwid, &error_fatal); 2184 object_property_set_int(OBJECT(pnv_core), "hwid", core_hwid, 2185 &error_fatal); 2186 object_property_set_int(OBJECT(pnv_core), "hrmor", pnv->fw_load_addr, 2187 &error_fatal); 2188 object_property_set_link(OBJECT(pnv_core), "chip", OBJECT(chip), 2189 &error_abort); 2190 qdev_realize(DEVICE(pnv_core), NULL, &error_fatal); 2191 2192 /* Each core has an XSCOM MMIO region */ 2193 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 2194 2195 pnv_xscom_add_subregion(chip, xscom_core_base, 2196 &pnv_core->xscom_regs); 2197 i++; 2198 } 2199 } 2200 2201 static void pnv_chip_realize(DeviceState *dev, Error **errp) 2202 { 2203 PnvChip *chip = PNV_CHIP(dev); 2204 Error *error = NULL; 2205 2206 /* Cores */ 2207 pnv_chip_core_realize(chip, &error); 2208 if (error) { 2209 error_propagate(errp, error); 2210 return; 2211 } 2212 } 2213 2214 static Property pnv_chip_properties[] = { 2215 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 2216 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 2217 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 2218 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 2219 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 2220 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 2221 DEFINE_PROP_END_OF_LIST(), 2222 }; 2223 2224 static void pnv_chip_class_init(ObjectClass *klass, void *data) 2225 { 2226 DeviceClass *dc = DEVICE_CLASS(klass); 2227 2228 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 2229 dc->realize = pnv_chip_realize; 2230 device_class_set_props(dc, pnv_chip_properties); 2231 dc->desc = "PowerNV Chip"; 2232 } 2233 2234 PnvCore *pnv_chip_find_core(PnvChip *chip, uint32_t core_id) 2235 { 2236 int i; 2237 2238 for (i = 0; i < chip->nr_cores; i++) { 2239 PnvCore *pc = chip->cores[i]; 2240 CPUCore *cc = CPU_CORE(pc); 2241 2242 if (cc->core_id == core_id) { 2243 return pc; 2244 } 2245 } 2246 return NULL; 2247 } 2248 2249 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 2250 { 2251 int i, j; 2252 2253 for (i = 0; i < chip->nr_cores; i++) { 2254 PnvCore *pc = chip->cores[i]; 2255 CPUCore *cc = CPU_CORE(pc); 2256 2257 for (j = 0; j < cc->nr_threads; j++) { 2258 if (ppc_cpu_pir(pc->threads[j]) == pir) { 2259 return pc->threads[j]; 2260 } 2261 } 2262 } 2263 return NULL; 2264 } 2265 2266 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 2267 { 2268 PnvMachineState *pnv = PNV_MACHINE(xi); 2269 int i, j; 2270 2271 for (i = 0; i < pnv->num_chips; i++) { 2272 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2273 2274 if (ics_valid_irq(&chip8->psi.ics, irq)) { 2275 return &chip8->psi.ics; 2276 } 2277 2278 for (j = 0; j < chip8->num_phbs; j++) { 2279 PnvPHB *phb = chip8->phbs[j]; 2280 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2281 2282 if (ics_valid_irq(&phb3->lsis, irq)) { 2283 return &phb3->lsis; 2284 } 2285 2286 if (ics_valid_irq(ICS(&phb3->msis), irq)) { 2287 return ICS(&phb3->msis); 2288 } 2289 } 2290 } 2291 return NULL; 2292 } 2293 2294 PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) 2295 { 2296 int i; 2297 2298 for (i = 0; i < pnv->num_chips; i++) { 2299 PnvChip *chip = pnv->chips[i]; 2300 if (chip->chip_id == chip_id) { 2301 return chip; 2302 } 2303 } 2304 return NULL; 2305 } 2306 2307 static void pnv_ics_resend(XICSFabric *xi) 2308 { 2309 PnvMachineState *pnv = PNV_MACHINE(xi); 2310 int i, j; 2311 2312 for (i = 0; i < pnv->num_chips; i++) { 2313 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 2314 2315 ics_resend(&chip8->psi.ics); 2316 2317 for (j = 0; j < chip8->num_phbs; j++) { 2318 PnvPHB *phb = chip8->phbs[j]; 2319 PnvPHB3 *phb3 = PNV_PHB3(phb->backend); 2320 2321 ics_resend(&phb3->lsis); 2322 ics_resend(ICS(&phb3->msis)); 2323 } 2324 } 2325 } 2326 2327 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 2328 { 2329 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 2330 2331 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 2332 } 2333 2334 static void pnv_pic_print_info(InterruptStatsProvider *obj, 2335 Monitor *mon) 2336 { 2337 PnvMachineState *pnv = PNV_MACHINE(obj); 2338 int i; 2339 CPUState *cs; 2340 g_autoptr(GString) buf = g_string_new(""); 2341 g_autoptr(HumanReadableText) info = NULL; 2342 2343 CPU_FOREACH(cs) { 2344 PowerPCCPU *cpu = POWERPC_CPU(cs); 2345 2346 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 2347 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 2348 buf); 2349 } 2350 2351 for (i = 0; i < pnv->num_chips; i++) { 2352 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], buf); 2353 } 2354 2355 info = human_readable_text_from_str(buf); 2356 monitor_puts(mon, info->human_readable_text); 2357 } 2358 2359 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 2360 uint8_t nvt_blk, uint32_t nvt_idx, 2361 bool cam_ignore, uint8_t priority, 2362 uint32_t logic_serv, 2363 XiveTCTXMatch *match) 2364 { 2365 PnvMachineState *pnv = PNV_MACHINE(xfb); 2366 int total_count = 0; 2367 int i; 2368 2369 for (i = 0; i < pnv->num_chips; i++) { 2370 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 2371 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 2372 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2373 int count; 2374 2375 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2376 priority, logic_serv, match); 2377 2378 if (count < 0) { 2379 return count; 2380 } 2381 2382 total_count += count; 2383 } 2384 2385 return total_count; 2386 } 2387 2388 static int pnv10_xive_match_nvt(XiveFabric *xfb, uint8_t format, 2389 uint8_t nvt_blk, uint32_t nvt_idx, 2390 bool cam_ignore, uint8_t priority, 2391 uint32_t logic_serv, 2392 XiveTCTXMatch *match) 2393 { 2394 PnvMachineState *pnv = PNV_MACHINE(xfb); 2395 int total_count = 0; 2396 int i; 2397 2398 for (i = 0; i < pnv->num_chips; i++) { 2399 Pnv10Chip *chip10 = PNV10_CHIP(pnv->chips[i]); 2400 XivePresenter *xptr = XIVE_PRESENTER(&chip10->xive); 2401 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 2402 int count; 2403 2404 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 2405 priority, logic_serv, match); 2406 2407 if (count < 0) { 2408 return count; 2409 } 2410 2411 total_count += count; 2412 } 2413 2414 return total_count; 2415 } 2416 2417 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 2418 { 2419 MachineClass *mc = MACHINE_CLASS(oc); 2420 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 2421 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2422 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 2423 2424 static GlobalProperty phb_compat[] = { 2425 { TYPE_PNV_PHB, "version", "3" }, 2426 { TYPE_PNV_PHB_ROOT_PORT, "version", "3" }, 2427 }; 2428 2429 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 2430 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 2431 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2432 2433 xic->icp_get = pnv_icp_get; 2434 xic->ics_get = pnv_ics_get; 2435 xic->ics_resend = pnv_ics_resend; 2436 2437 pmc->compat = compat; 2438 pmc->compat_size = sizeof(compat); 2439 2440 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2441 } 2442 2443 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 2444 { 2445 MachineClass *mc = MACHINE_CLASS(oc); 2446 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2447 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2448 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 2449 2450 static GlobalProperty phb_compat[] = { 2451 { TYPE_PNV_PHB, "version", "4" }, 2452 { TYPE_PNV_PHB_ROOT_PORT, "version", "4" }, 2453 }; 2454 2455 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 2456 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.2"); 2457 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2458 2459 xfc->match_nvt = pnv_match_nvt; 2460 2461 pmc->compat = compat; 2462 pmc->compat_size = sizeof(compat); 2463 pmc->dt_power_mgt = pnv_dt_power_mgt; 2464 2465 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2466 } 2467 2468 static void pnv_machine_p10_common_class_init(ObjectClass *oc, void *data) 2469 { 2470 MachineClass *mc = MACHINE_CLASS(oc); 2471 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2472 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 2473 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 2474 2475 static GlobalProperty phb_compat[] = { 2476 { TYPE_PNV_PHB, "version", "5" }, 2477 { TYPE_PNV_PHB_ROOT_PORT, "version", "5" }, 2478 }; 2479 2480 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v2.0"); 2481 compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat)); 2482 2483 mc->alias = "powernv"; 2484 2485 pmc->compat = compat; 2486 pmc->compat_size = sizeof(compat); 2487 pmc->dt_power_mgt = pnv_dt_power_mgt; 2488 2489 xfc->match_nvt = pnv10_xive_match_nvt; 2490 2491 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); 2492 } 2493 2494 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 2495 { 2496 MachineClass *mc = MACHINE_CLASS(oc); 2497 2498 pnv_machine_p10_common_class_init(oc, data); 2499 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 2500 } 2501 2502 static void pnv_machine_p10_rainier_class_init(ObjectClass *oc, void *data) 2503 { 2504 MachineClass *mc = MACHINE_CLASS(oc); 2505 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 2506 2507 pnv_machine_p10_common_class_init(oc, data); 2508 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10 Rainier"; 2509 pmc->i2c_init = pnv_rainier_i2c_init; 2510 } 2511 2512 static bool pnv_machine_get_hb(Object *obj, Error **errp) 2513 { 2514 PnvMachineState *pnv = PNV_MACHINE(obj); 2515 2516 return !!pnv->fw_load_addr; 2517 } 2518 2519 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 2520 { 2521 PnvMachineState *pnv = PNV_MACHINE(obj); 2522 2523 if (value) { 2524 pnv->fw_load_addr = 0x8000000; 2525 } 2526 } 2527 2528 static void pnv_cpu_do_nmi_on_cpu(CPUState *cs, run_on_cpu_data arg) 2529 { 2530 CPUPPCState *env = cpu_env(cs); 2531 2532 cpu_synchronize_state(cs); 2533 ppc_cpu_do_system_reset(cs); 2534 if (env->spr[SPR_SRR1] & SRR1_WAKESTATE) { 2535 /* 2536 * Power-save wakeups, as indicated by non-zero SRR1[46:47] put the 2537 * wakeup reason in SRR1[42:45], system reset is indicated with 0b0100 2538 * (PPC_BIT(43)). 2539 */ 2540 if (!(env->spr[SPR_SRR1] & SRR1_WAKERESET)) { 2541 warn_report("ppc_cpu_do_system_reset does not set system reset wakeup reason"); 2542 env->spr[SPR_SRR1] |= SRR1_WAKERESET; 2543 } 2544 } else { 2545 /* 2546 * For non-powersave system resets, SRR1[42:45] are defined to be 2547 * implementation-dependent. The POWER9 User Manual specifies that 2548 * an external (SCOM driven, which may come from a BMC nmi command or 2549 * another CPU requesting a NMI IPI) system reset exception should be 2550 * 0b0010 (PPC_BIT(44)). 2551 */ 2552 env->spr[SPR_SRR1] |= SRR1_WAKESCOM; 2553 } 2554 } 2555 2556 static void pnv_nmi(NMIState *n, int cpu_index, Error **errp) 2557 { 2558 CPUState *cs; 2559 2560 CPU_FOREACH(cs) { 2561 async_run_on_cpu(cs, pnv_cpu_do_nmi_on_cpu, RUN_ON_CPU_NULL); 2562 } 2563 } 2564 2565 static void pnv_machine_class_init(ObjectClass *oc, void *data) 2566 { 2567 MachineClass *mc = MACHINE_CLASS(oc); 2568 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 2569 NMIClass *nc = NMI_CLASS(oc); 2570 2571 mc->desc = "IBM PowerNV (Non-Virtualized)"; 2572 mc->init = pnv_init; 2573 mc->reset = pnv_reset; 2574 mc->max_cpus = MAX_CPUS; 2575 /* Pnv provides a AHCI device for storage */ 2576 mc->block_default_type = IF_IDE; 2577 mc->no_parallel = 1; 2578 mc->default_boot_order = NULL; 2579 /* 2580 * RAM defaults to less than 2048 for 32-bit hosts, and large 2581 * enough to fit the maximum initrd size at it's load address 2582 */ 2583 mc->default_ram_size = 1 * GiB; 2584 mc->default_ram_id = "pnv.ram"; 2585 ispc->print_info = pnv_pic_print_info; 2586 nc->nmi_monitor_handler = pnv_nmi; 2587 2588 object_class_property_add_bool(oc, "hb-mode", 2589 pnv_machine_get_hb, pnv_machine_set_hb); 2590 object_class_property_set_description(oc, "hb-mode", 2591 "Use a hostboot like boot loader"); 2592 } 2593 2594 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 2595 { \ 2596 .name = type, \ 2597 .class_init = class_initfn, \ 2598 .parent = TYPE_PNV8_CHIP, \ 2599 } 2600 2601 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 2602 { \ 2603 .name = type, \ 2604 .class_init = class_initfn, \ 2605 .parent = TYPE_PNV9_CHIP, \ 2606 } 2607 2608 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2609 { \ 2610 .name = type, \ 2611 .class_init = class_initfn, \ 2612 .parent = TYPE_PNV10_CHIP, \ 2613 } 2614 2615 static const TypeInfo types[] = { 2616 { 2617 .name = MACHINE_TYPE_NAME("powernv10-rainier"), 2618 .parent = MACHINE_TYPE_NAME("powernv10"), 2619 .class_init = pnv_machine_p10_rainier_class_init, 2620 }, 2621 { 2622 .name = MACHINE_TYPE_NAME("powernv10"), 2623 .parent = TYPE_PNV_MACHINE, 2624 .class_init = pnv_machine_power10_class_init, 2625 .interfaces = (InterfaceInfo[]) { 2626 { TYPE_XIVE_FABRIC }, 2627 { }, 2628 }, 2629 }, 2630 { 2631 .name = MACHINE_TYPE_NAME("powernv9"), 2632 .parent = TYPE_PNV_MACHINE, 2633 .class_init = pnv_machine_power9_class_init, 2634 .interfaces = (InterfaceInfo[]) { 2635 { TYPE_XIVE_FABRIC }, 2636 { }, 2637 }, 2638 }, 2639 { 2640 .name = MACHINE_TYPE_NAME("powernv8"), 2641 .parent = TYPE_PNV_MACHINE, 2642 .class_init = pnv_machine_power8_class_init, 2643 .interfaces = (InterfaceInfo[]) { 2644 { TYPE_XICS_FABRIC }, 2645 { }, 2646 }, 2647 }, 2648 { 2649 .name = TYPE_PNV_MACHINE, 2650 .parent = TYPE_MACHINE, 2651 .abstract = true, 2652 .instance_size = sizeof(PnvMachineState), 2653 .class_init = pnv_machine_class_init, 2654 .class_size = sizeof(PnvMachineClass), 2655 .interfaces = (InterfaceInfo[]) { 2656 { TYPE_INTERRUPT_STATS_PROVIDER }, 2657 { TYPE_NMI }, 2658 { }, 2659 }, 2660 }, 2661 { 2662 .name = TYPE_PNV_CHIP, 2663 .parent = TYPE_SYS_BUS_DEVICE, 2664 .class_init = pnv_chip_class_init, 2665 .instance_size = sizeof(PnvChip), 2666 .class_size = sizeof(PnvChipClass), 2667 .abstract = true, 2668 }, 2669 2670 /* 2671 * P10 chip and variants 2672 */ 2673 { 2674 .name = TYPE_PNV10_CHIP, 2675 .parent = TYPE_PNV_CHIP, 2676 .instance_init = pnv_chip_power10_instance_init, 2677 .instance_size = sizeof(Pnv10Chip), 2678 }, 2679 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2680 2681 /* 2682 * P9 chip and variants 2683 */ 2684 { 2685 .name = TYPE_PNV9_CHIP, 2686 .parent = TYPE_PNV_CHIP, 2687 .instance_init = pnv_chip_power9_instance_init, 2688 .instance_size = sizeof(Pnv9Chip), 2689 }, 2690 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2691 2692 /* 2693 * P8 chip and variants 2694 */ 2695 { 2696 .name = TYPE_PNV8_CHIP, 2697 .parent = TYPE_PNV_CHIP, 2698 .instance_init = pnv_chip_power8_instance_init, 2699 .instance_size = sizeof(Pnv8Chip), 2700 }, 2701 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2702 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2703 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2704 pnv_chip_power8nvl_class_init), 2705 }; 2706 2707 DEFINE_TYPES(types) 2708