1 /* 2 * QEMU PowerPC PowerNV machine model 3 * 4 * Copyright (c) 2016, IBM Corporation. 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu-common.h" 22 #include "qemu/units.h" 23 #include "qapi/error.h" 24 #include "sysemu/sysemu.h" 25 #include "sysemu/numa.h" 26 #include "sysemu/reset.h" 27 #include "sysemu/runstate.h" 28 #include "sysemu/cpus.h" 29 #include "sysemu/device_tree.h" 30 #include "target/ppc/cpu.h" 31 #include "qemu/log.h" 32 #include "hw/ppc/fdt.h" 33 #include "hw/ppc/ppc.h" 34 #include "hw/ppc/pnv.h" 35 #include "hw/ppc/pnv_core.h" 36 #include "hw/loader.h" 37 #include "exec/address-spaces.h" 38 #include "qapi/visitor.h" 39 #include "monitor/monitor.h" 40 #include "hw/intc/intc.h" 41 #include "hw/ipmi/ipmi.h" 42 #include "target/ppc/mmu-hash64.h" 43 #include "hw/pci/msi.h" 44 45 #include "hw/ppc/xics.h" 46 #include "hw/qdev-properties.h" 47 #include "hw/ppc/pnv_xscom.h" 48 #include "hw/ppc/pnv_pnor.h" 49 50 #include "hw/isa/isa.h" 51 #include "hw/boards.h" 52 #include "hw/char/serial.h" 53 #include "hw/rtc/mc146818rtc.h" 54 55 #include <libfdt.h> 56 57 #define FDT_MAX_SIZE (1 * MiB) 58 59 #define FW_FILE_NAME "skiboot.lid" 60 #define FW_LOAD_ADDR 0x0 61 #define FW_MAX_SIZE (4 * MiB) 62 63 #define KERNEL_LOAD_ADDR 0x20000000 64 #define KERNEL_MAX_SIZE (256 * MiB) 65 #define INITRD_LOAD_ADDR 0x60000000 66 #define INITRD_MAX_SIZE (256 * MiB) 67 68 static const char *pnv_chip_core_typename(const PnvChip *o) 69 { 70 const char *chip_type = object_class_get_name(object_get_class(OBJECT(o))); 71 int len = strlen(chip_type) - strlen(PNV_CHIP_TYPE_SUFFIX); 72 char *s = g_strdup_printf(PNV_CORE_TYPE_NAME("%.*s"), len, chip_type); 73 const char *core_type = object_class_get_name(object_class_by_name(s)); 74 g_free(s); 75 return core_type; 76 } 77 78 /* 79 * On Power Systems E880 (POWER8), the max cpus (threads) should be : 80 * 4 * 4 sockets * 12 cores * 8 threads = 1536 81 * Let's make it 2^11 82 */ 83 #define MAX_CPUS 2048 84 85 /* 86 * Memory nodes are created by hostboot, one for each range of memory 87 * that has a different "affinity". In practice, it means one range 88 * per chip. 89 */ 90 static void pnv_dt_memory(void *fdt, int chip_id, hwaddr start, hwaddr size) 91 { 92 char *mem_name; 93 uint64_t mem_reg_property[2]; 94 int off; 95 96 mem_reg_property[0] = cpu_to_be64(start); 97 mem_reg_property[1] = cpu_to_be64(size); 98 99 mem_name = g_strdup_printf("memory@%"HWADDR_PRIx, start); 100 off = fdt_add_subnode(fdt, 0, mem_name); 101 g_free(mem_name); 102 103 _FDT((fdt_setprop_string(fdt, off, "device_type", "memory"))); 104 _FDT((fdt_setprop(fdt, off, "reg", mem_reg_property, 105 sizeof(mem_reg_property)))); 106 _FDT((fdt_setprop_cell(fdt, off, "ibm,chip-id", chip_id))); 107 } 108 109 static int get_cpus_node(void *fdt) 110 { 111 int cpus_offset = fdt_path_offset(fdt, "/cpus"); 112 113 if (cpus_offset < 0) { 114 cpus_offset = fdt_add_subnode(fdt, 0, "cpus"); 115 if (cpus_offset) { 116 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); 117 _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); 118 } 119 } 120 _FDT(cpus_offset); 121 return cpus_offset; 122 } 123 124 /* 125 * The PowerNV cores (and threads) need to use real HW ids and not an 126 * incremental index like it has been done on other platforms. This HW 127 * id is stored in the CPU PIR, it is used to create cpu nodes in the 128 * device tree, used in XSCOM to address cores and in interrupt 129 * servers. 130 */ 131 static void pnv_dt_core(PnvChip *chip, PnvCore *pc, void *fdt) 132 { 133 PowerPCCPU *cpu = pc->threads[0]; 134 CPUState *cs = CPU(cpu); 135 DeviceClass *dc = DEVICE_GET_CLASS(cs); 136 int smt_threads = CPU_CORE(pc)->nr_threads; 137 CPUPPCState *env = &cpu->env; 138 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cs); 139 uint32_t servers_prop[smt_threads]; 140 int i; 141 uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40), 142 0xffffffff, 0xffffffff}; 143 uint32_t tbfreq = PNV_TIMEBASE_FREQ; 144 uint32_t cpufreq = 1000000000; 145 uint32_t page_sizes_prop[64]; 146 size_t page_sizes_prop_size; 147 const uint8_t pa_features[] = { 24, 0, 148 0xf6, 0x3f, 0xc7, 0xc0, 0x80, 0xf0, 149 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 150 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 151 0x80, 0x00, 0x80, 0x00, 0x80, 0x00 }; 152 int offset; 153 char *nodename; 154 int cpus_offset = get_cpus_node(fdt); 155 156 nodename = g_strdup_printf("%s@%x", dc->fw_name, pc->pir); 157 offset = fdt_add_subnode(fdt, cpus_offset, nodename); 158 _FDT(offset); 159 g_free(nodename); 160 161 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", chip->chip_id))); 162 163 _FDT((fdt_setprop_cell(fdt, offset, "reg", pc->pir))); 164 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pir", pc->pir))); 165 _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); 166 167 _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))); 168 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", 169 env->dcache_line_size))); 170 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", 171 env->dcache_line_size))); 172 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", 173 env->icache_line_size))); 174 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", 175 env->icache_line_size))); 176 177 if (pcc->l1_dcache_size) { 178 _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", 179 pcc->l1_dcache_size))); 180 } else { 181 warn_report("Unknown L1 dcache size for cpu"); 182 } 183 if (pcc->l1_icache_size) { 184 _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", 185 pcc->l1_icache_size))); 186 } else { 187 warn_report("Unknown L1 icache size for cpu"); 188 } 189 190 _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); 191 _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); 192 _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", 193 cpu->hash64_opts->slb_size))); 194 _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); 195 _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); 196 197 if (env->spr_cb[SPR_PURR].oea_read) { 198 _FDT((fdt_setprop(fdt, offset, "ibm,purr", NULL, 0))); 199 } 200 201 if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { 202 _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", 203 segs, sizeof(segs)))); 204 } 205 206 /* 207 * Advertise VMX/VSX (vector extensions) if available 208 * 0 / no property == no vector extensions 209 * 1 == VMX / Altivec available 210 * 2 == VSX available 211 */ 212 if (env->insns_flags & PPC_ALTIVEC) { 213 uint32_t vmx = (env->insns_flags2 & PPC2_VSX) ? 2 : 1; 214 215 _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", vmx))); 216 } 217 218 /* 219 * Advertise DFP (Decimal Floating Point) if available 220 * 0 / no property == no DFP 221 * 1 == DFP available 222 */ 223 if (env->insns_flags2 & PPC2_DFP) { 224 _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); 225 } 226 227 page_sizes_prop_size = ppc_create_page_sizes_prop(cpu, page_sizes_prop, 228 sizeof(page_sizes_prop)); 229 if (page_sizes_prop_size) { 230 _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", 231 page_sizes_prop, page_sizes_prop_size))); 232 } 233 234 _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", 235 pa_features, sizeof(pa_features)))); 236 237 /* Build interrupt servers properties */ 238 for (i = 0; i < smt_threads; i++) { 239 servers_prop[i] = cpu_to_be32(pc->pir + i); 240 } 241 _FDT((fdt_setprop(fdt, offset, "ibm,ppc-interrupt-server#s", 242 servers_prop, sizeof(servers_prop)))); 243 } 244 245 static void pnv_dt_icp(PnvChip *chip, void *fdt, uint32_t pir, 246 uint32_t nr_threads) 247 { 248 uint64_t addr = PNV_ICP_BASE(chip) | (pir << 12); 249 char *name; 250 const char compat[] = "IBM,power8-icp\0IBM,ppc-xicp"; 251 uint32_t irange[2], i, rsize; 252 uint64_t *reg; 253 int offset; 254 255 irange[0] = cpu_to_be32(pir); 256 irange[1] = cpu_to_be32(nr_threads); 257 258 rsize = sizeof(uint64_t) * 2 * nr_threads; 259 reg = g_malloc(rsize); 260 for (i = 0; i < nr_threads; i++) { 261 reg[i * 2] = cpu_to_be64(addr | ((pir + i) * 0x1000)); 262 reg[i * 2 + 1] = cpu_to_be64(0x1000); 263 } 264 265 name = g_strdup_printf("interrupt-controller@%"PRIX64, addr); 266 offset = fdt_add_subnode(fdt, 0, name); 267 _FDT(offset); 268 g_free(name); 269 270 _FDT((fdt_setprop(fdt, offset, "compatible", compat, sizeof(compat)))); 271 _FDT((fdt_setprop(fdt, offset, "reg", reg, rsize))); 272 _FDT((fdt_setprop_string(fdt, offset, "device_type", 273 "PowerPC-External-Interrupt-Presentation"))); 274 _FDT((fdt_setprop(fdt, offset, "interrupt-controller", NULL, 0))); 275 _FDT((fdt_setprop(fdt, offset, "ibm,interrupt-server-ranges", 276 irange, sizeof(irange)))); 277 _FDT((fdt_setprop_cell(fdt, offset, "#interrupt-cells", 1))); 278 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 0))); 279 g_free(reg); 280 } 281 282 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) 283 { 284 static const char compat[] = "ibm,power8-xscom\0ibm,xscom"; 285 int i; 286 287 pnv_dt_xscom(chip, fdt, 0, 288 cpu_to_be64(PNV_XSCOM_BASE(chip)), 289 cpu_to_be64(PNV_XSCOM_SIZE), 290 compat, sizeof(compat)); 291 292 for (i = 0; i < chip->nr_cores; i++) { 293 PnvCore *pnv_core = chip->cores[i]; 294 295 pnv_dt_core(chip, pnv_core, fdt); 296 297 /* Interrupt Control Presenters (ICP). One per core. */ 298 pnv_dt_icp(chip, fdt, pnv_core->pir, CPU_CORE(pnv_core)->nr_threads); 299 } 300 301 if (chip->ram_size) { 302 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 303 } 304 } 305 306 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) 307 { 308 static const char compat[] = "ibm,power9-xscom\0ibm,xscom"; 309 int i; 310 311 pnv_dt_xscom(chip, fdt, 0, 312 cpu_to_be64(PNV9_XSCOM_BASE(chip)), 313 cpu_to_be64(PNV9_XSCOM_SIZE), 314 compat, sizeof(compat)); 315 316 for (i = 0; i < chip->nr_cores; i++) { 317 PnvCore *pnv_core = chip->cores[i]; 318 319 pnv_dt_core(chip, pnv_core, fdt); 320 } 321 322 if (chip->ram_size) { 323 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 324 } 325 326 pnv_dt_lpc(chip, fdt, 0, PNV9_LPCM_BASE(chip), PNV9_LPCM_SIZE); 327 } 328 329 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) 330 { 331 static const char compat[] = "ibm,power10-xscom\0ibm,xscom"; 332 int i; 333 334 pnv_dt_xscom(chip, fdt, 0, 335 cpu_to_be64(PNV10_XSCOM_BASE(chip)), 336 cpu_to_be64(PNV10_XSCOM_SIZE), 337 compat, sizeof(compat)); 338 339 for (i = 0; i < chip->nr_cores; i++) { 340 PnvCore *pnv_core = chip->cores[i]; 341 342 pnv_dt_core(chip, pnv_core, fdt); 343 } 344 345 if (chip->ram_size) { 346 pnv_dt_memory(fdt, chip->chip_id, chip->ram_start, chip->ram_size); 347 } 348 349 pnv_dt_lpc(chip, fdt, 0, PNV10_LPCM_BASE(chip), PNV10_LPCM_SIZE); 350 } 351 352 static void pnv_dt_rtc(ISADevice *d, void *fdt, int lpc_off) 353 { 354 uint32_t io_base = d->ioport_id; 355 uint32_t io_regs[] = { 356 cpu_to_be32(1), 357 cpu_to_be32(io_base), 358 cpu_to_be32(2) 359 }; 360 char *name; 361 int node; 362 363 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 364 node = fdt_add_subnode(fdt, lpc_off, name); 365 _FDT(node); 366 g_free(name); 367 368 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 369 _FDT((fdt_setprop_string(fdt, node, "compatible", "pnpPNP,b00"))); 370 } 371 372 static void pnv_dt_serial(ISADevice *d, void *fdt, int lpc_off) 373 { 374 const char compatible[] = "ns16550\0pnpPNP,501"; 375 uint32_t io_base = d->ioport_id; 376 uint32_t io_regs[] = { 377 cpu_to_be32(1), 378 cpu_to_be32(io_base), 379 cpu_to_be32(8) 380 }; 381 char *name; 382 int node; 383 384 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 385 node = fdt_add_subnode(fdt, lpc_off, name); 386 _FDT(node); 387 g_free(name); 388 389 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 390 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 391 sizeof(compatible)))); 392 393 _FDT((fdt_setprop_cell(fdt, node, "clock-frequency", 1843200))); 394 _FDT((fdt_setprop_cell(fdt, node, "current-speed", 115200))); 395 _FDT((fdt_setprop_cell(fdt, node, "interrupts", d->isairq[0]))); 396 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 397 fdt_get_phandle(fdt, lpc_off)))); 398 399 /* This is needed by Linux */ 400 _FDT((fdt_setprop_string(fdt, node, "device_type", "serial"))); 401 } 402 403 static void pnv_dt_ipmi_bt(ISADevice *d, void *fdt, int lpc_off) 404 { 405 const char compatible[] = "bt\0ipmi-bt"; 406 uint32_t io_base; 407 uint32_t io_regs[] = { 408 cpu_to_be32(1), 409 0, /* 'io_base' retrieved from the 'ioport' property of 'isa-ipmi-bt' */ 410 cpu_to_be32(3) 411 }; 412 uint32_t irq; 413 char *name; 414 int node; 415 416 io_base = object_property_get_int(OBJECT(d), "ioport", &error_fatal); 417 io_regs[1] = cpu_to_be32(io_base); 418 419 irq = object_property_get_int(OBJECT(d), "irq", &error_fatal); 420 421 name = g_strdup_printf("%s@i%x", qdev_fw_name(DEVICE(d)), io_base); 422 node = fdt_add_subnode(fdt, lpc_off, name); 423 _FDT(node); 424 g_free(name); 425 426 _FDT((fdt_setprop(fdt, node, "reg", io_regs, sizeof(io_regs)))); 427 _FDT((fdt_setprop(fdt, node, "compatible", compatible, 428 sizeof(compatible)))); 429 430 /* Mark it as reserved to avoid Linux trying to claim it */ 431 _FDT((fdt_setprop_string(fdt, node, "status", "reserved"))); 432 _FDT((fdt_setprop_cell(fdt, node, "interrupts", irq))); 433 _FDT((fdt_setprop_cell(fdt, node, "interrupt-parent", 434 fdt_get_phandle(fdt, lpc_off)))); 435 } 436 437 typedef struct ForeachPopulateArgs { 438 void *fdt; 439 int offset; 440 } ForeachPopulateArgs; 441 442 static int pnv_dt_isa_device(DeviceState *dev, void *opaque) 443 { 444 ForeachPopulateArgs *args = opaque; 445 ISADevice *d = ISA_DEVICE(dev); 446 447 if (object_dynamic_cast(OBJECT(dev), TYPE_MC146818_RTC)) { 448 pnv_dt_rtc(d, args->fdt, args->offset); 449 } else if (object_dynamic_cast(OBJECT(dev), TYPE_ISA_SERIAL)) { 450 pnv_dt_serial(d, args->fdt, args->offset); 451 } else if (object_dynamic_cast(OBJECT(dev), "isa-ipmi-bt")) { 452 pnv_dt_ipmi_bt(d, args->fdt, args->offset); 453 } else { 454 error_report("unknown isa device %s@i%x", qdev_fw_name(dev), 455 d->ioport_id); 456 } 457 458 return 0; 459 } 460 461 /* 462 * The default LPC bus of a multichip system is on chip 0. It's 463 * recognized by the firmware (skiboot) using a "primary" property. 464 */ 465 static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) 466 { 467 int isa_offset = fdt_path_offset(fdt, pnv->chips[0]->dt_isa_nodename); 468 ForeachPopulateArgs args = { 469 .fdt = fdt, 470 .offset = isa_offset, 471 }; 472 uint32_t phandle; 473 474 _FDT((fdt_setprop(fdt, isa_offset, "primary", NULL, 0))); 475 476 phandle = qemu_fdt_alloc_phandle(fdt); 477 assert(phandle > 0); 478 _FDT((fdt_setprop_cell(fdt, isa_offset, "phandle", phandle))); 479 480 /* 481 * ISA devices are not necessarily parented to the ISA bus so we 482 * can not use object_child_foreach() 483 */ 484 qbus_walk_children(BUS(pnv->isa_bus), pnv_dt_isa_device, NULL, NULL, NULL, 485 &args); 486 } 487 488 static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) 489 { 490 int off; 491 492 off = fdt_add_subnode(fdt, 0, "ibm,opal"); 493 off = fdt_add_subnode(fdt, off, "power-mgt"); 494 495 _FDT(fdt_setprop_cell(fdt, off, "ibm,enabled-stop-levels", 0xc0000000)); 496 } 497 498 static void *pnv_dt_create(MachineState *machine) 499 { 500 PnvMachineClass *pmc = PNV_MACHINE_GET_CLASS(machine); 501 PnvMachineState *pnv = PNV_MACHINE(machine); 502 void *fdt; 503 char *buf; 504 int off; 505 int i; 506 507 fdt = g_malloc0(FDT_MAX_SIZE); 508 _FDT((fdt_create_empty_tree(fdt, FDT_MAX_SIZE))); 509 510 /* /qemu node */ 511 _FDT((fdt_add_subnode(fdt, 0, "qemu"))); 512 513 /* Root node */ 514 _FDT((fdt_setprop_cell(fdt, 0, "#address-cells", 0x2))); 515 _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); 516 _FDT((fdt_setprop_string(fdt, 0, "model", 517 "IBM PowerNV (emulated by qemu)"))); 518 _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, pmc->compat_size))); 519 520 buf = qemu_uuid_unparse_strdup(&qemu_uuid); 521 _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); 522 if (qemu_uuid_set) { 523 _FDT((fdt_property_string(fdt, "system-id", buf))); 524 } 525 g_free(buf); 526 527 off = fdt_add_subnode(fdt, 0, "chosen"); 528 if (machine->kernel_cmdline) { 529 _FDT((fdt_setprop_string(fdt, off, "bootargs", 530 machine->kernel_cmdline))); 531 } 532 533 if (pnv->initrd_size) { 534 uint32_t start_prop = cpu_to_be32(pnv->initrd_base); 535 uint32_t end_prop = cpu_to_be32(pnv->initrd_base + pnv->initrd_size); 536 537 _FDT((fdt_setprop(fdt, off, "linux,initrd-start", 538 &start_prop, sizeof(start_prop)))); 539 _FDT((fdt_setprop(fdt, off, "linux,initrd-end", 540 &end_prop, sizeof(end_prop)))); 541 } 542 543 /* Populate device tree for each chip */ 544 for (i = 0; i < pnv->num_chips; i++) { 545 PNV_CHIP_GET_CLASS(pnv->chips[i])->dt_populate(pnv->chips[i], fdt); 546 } 547 548 /* Populate ISA devices on chip 0 */ 549 pnv_dt_isa(pnv, fdt); 550 551 if (pnv->bmc) { 552 pnv_dt_bmc_sensors(pnv->bmc, fdt); 553 } 554 555 /* Create an extra node for power management on machines that support it */ 556 if (pmc->dt_power_mgt) { 557 pmc->dt_power_mgt(pnv, fdt); 558 } 559 560 return fdt; 561 } 562 563 static void pnv_powerdown_notify(Notifier *n, void *opaque) 564 { 565 PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); 566 567 if (pnv->bmc) { 568 pnv_bmc_powerdown(pnv->bmc); 569 } 570 } 571 572 static void pnv_reset(MachineState *machine) 573 { 574 void *fdt; 575 576 qemu_devices_reset(); 577 578 fdt = pnv_dt_create(machine); 579 580 /* Pack resulting tree */ 581 _FDT((fdt_pack(fdt))); 582 583 qemu_fdt_dumpdtb(fdt, fdt_totalsize(fdt)); 584 cpu_physical_memory_write(PNV_FDT_ADDR, fdt, fdt_totalsize(fdt)); 585 } 586 587 static ISABus *pnv_chip_power8_isa_create(PnvChip *chip, Error **errp) 588 { 589 Pnv8Chip *chip8 = PNV8_CHIP(chip); 590 return pnv_lpc_isa_create(&chip8->lpc, true, errp); 591 } 592 593 static ISABus *pnv_chip_power8nvl_isa_create(PnvChip *chip, Error **errp) 594 { 595 Pnv8Chip *chip8 = PNV8_CHIP(chip); 596 return pnv_lpc_isa_create(&chip8->lpc, false, errp); 597 } 598 599 static ISABus *pnv_chip_power9_isa_create(PnvChip *chip, Error **errp) 600 { 601 Pnv9Chip *chip9 = PNV9_CHIP(chip); 602 return pnv_lpc_isa_create(&chip9->lpc, false, errp); 603 } 604 605 static ISABus *pnv_chip_power10_isa_create(PnvChip *chip, Error **errp) 606 { 607 Pnv10Chip *chip10 = PNV10_CHIP(chip); 608 return pnv_lpc_isa_create(&chip10->lpc, false, errp); 609 } 610 611 static ISABus *pnv_isa_create(PnvChip *chip, Error **errp) 612 { 613 return PNV_CHIP_GET_CLASS(chip)->isa_create(chip, errp); 614 } 615 616 static void pnv_chip_power8_pic_print_info(PnvChip *chip, Monitor *mon) 617 { 618 Pnv8Chip *chip8 = PNV8_CHIP(chip); 619 int i; 620 621 ics_pic_print_info(&chip8->psi.ics, mon); 622 for (i = 0; i < chip->num_phbs; i++) { 623 pnv_phb3_msi_pic_print_info(&chip8->phbs[i].msis, mon); 624 ics_pic_print_info(&chip8->phbs[i].lsis, mon); 625 } 626 } 627 628 static void pnv_chip_power9_pic_print_info(PnvChip *chip, Monitor *mon) 629 { 630 Pnv9Chip *chip9 = PNV9_CHIP(chip); 631 int i, j; 632 633 pnv_xive_pic_print_info(&chip9->xive, mon); 634 pnv_psi_pic_print_info(&chip9->psi, mon); 635 636 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 637 PnvPhb4PecState *pec = &chip9->pecs[i]; 638 for (j = 0; j < pec->num_stacks; j++) { 639 pnv_phb4_pic_print_info(&pec->stacks[j].phb, mon); 640 } 641 } 642 } 643 644 static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, 645 uint32_t core_id) 646 { 647 return PNV_XSCOM_EX_BASE(core_id); 648 } 649 650 static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, 651 uint32_t core_id) 652 { 653 return PNV9_XSCOM_EC_BASE(core_id); 654 } 655 656 static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, 657 uint32_t core_id) 658 { 659 return PNV10_XSCOM_EC_BASE(core_id); 660 } 661 662 static bool pnv_match_cpu(const char *default_type, const char *cpu_type) 663 { 664 PowerPCCPUClass *ppc_default = 665 POWERPC_CPU_CLASS(object_class_by_name(default_type)); 666 PowerPCCPUClass *ppc = 667 POWERPC_CPU_CLASS(object_class_by_name(cpu_type)); 668 669 return ppc_default->pvr_match(ppc_default, ppc->pvr); 670 } 671 672 static void pnv_ipmi_bt_init(ISABus *bus, IPMIBmc *bmc, uint32_t irq) 673 { 674 Object *obj; 675 676 obj = OBJECT(isa_create(bus, "isa-ipmi-bt")); 677 object_property_set_link(obj, OBJECT(bmc), "bmc", &error_fatal); 678 object_property_set_int(obj, irq, "irq", &error_fatal); 679 object_property_set_bool(obj, true, "realized", &error_fatal); 680 } 681 682 static void pnv_chip_power10_pic_print_info(PnvChip *chip, Monitor *mon) 683 { 684 Pnv10Chip *chip10 = PNV10_CHIP(chip); 685 686 pnv_psi_pic_print_info(&chip10->psi, mon); 687 } 688 689 static void pnv_init(MachineState *machine) 690 { 691 PnvMachineState *pnv = PNV_MACHINE(machine); 692 MachineClass *mc = MACHINE_GET_CLASS(machine); 693 char *fw_filename; 694 long fw_size; 695 int i; 696 char *chip_typename; 697 DriveInfo *pnor = drive_get(IF_MTD, 0, 0); 698 DeviceState *dev; 699 700 /* allocate RAM */ 701 if (machine->ram_size < (1 * GiB)) { 702 warn_report("skiboot may not work with < 1GB of RAM"); 703 } 704 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 705 706 /* 707 * Create our simple PNOR device 708 */ 709 dev = qdev_create(NULL, TYPE_PNV_PNOR); 710 if (pnor) { 711 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(pnor), 712 &error_abort); 713 } 714 qdev_init_nofail(dev); 715 pnv->pnor = PNV_PNOR(dev); 716 717 /* load skiboot firmware */ 718 if (bios_name == NULL) { 719 bios_name = FW_FILE_NAME; 720 } 721 722 fw_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 723 if (!fw_filename) { 724 error_report("Could not find OPAL firmware '%s'", bios_name); 725 exit(1); 726 } 727 728 fw_size = load_image_targphys(fw_filename, pnv->fw_load_addr, FW_MAX_SIZE); 729 if (fw_size < 0) { 730 error_report("Could not load OPAL firmware '%s'", fw_filename); 731 exit(1); 732 } 733 g_free(fw_filename); 734 735 /* load kernel */ 736 if (machine->kernel_filename) { 737 long kernel_size; 738 739 kernel_size = load_image_targphys(machine->kernel_filename, 740 KERNEL_LOAD_ADDR, KERNEL_MAX_SIZE); 741 if (kernel_size < 0) { 742 error_report("Could not load kernel '%s'", 743 machine->kernel_filename); 744 exit(1); 745 } 746 } 747 748 /* load initrd */ 749 if (machine->initrd_filename) { 750 pnv->initrd_base = INITRD_LOAD_ADDR; 751 pnv->initrd_size = load_image_targphys(machine->initrd_filename, 752 pnv->initrd_base, INITRD_MAX_SIZE); 753 if (pnv->initrd_size < 0) { 754 error_report("Could not load initial ram disk '%s'", 755 machine->initrd_filename); 756 exit(1); 757 } 758 } 759 760 /* MSIs are supported on this platform */ 761 msi_nonbroken = true; 762 763 /* 764 * Check compatibility of the specified CPU with the machine 765 * default. 766 */ 767 if (!pnv_match_cpu(mc->default_cpu_type, machine->cpu_type)) { 768 error_report("invalid CPU model '%s' for %s machine", 769 machine->cpu_type, mc->name); 770 exit(1); 771 } 772 773 /* Create the processor chips */ 774 i = strlen(machine->cpu_type) - strlen(POWERPC_CPU_TYPE_SUFFIX); 775 chip_typename = g_strdup_printf(PNV_CHIP_TYPE_NAME("%.*s"), 776 i, machine->cpu_type); 777 if (!object_class_by_name(chip_typename)) { 778 error_report("invalid chip model '%.*s' for %s machine", 779 i, machine->cpu_type, mc->name); 780 exit(1); 781 } 782 783 pnv->num_chips = 784 machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); 785 /* 786 * TODO: should we decide on how many chips we can create based 787 * on #cores and Venice vs. Murano vs. Naples chip type etc..., 788 */ 789 if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { 790 error_report("invalid number of chips: '%d'", pnv->num_chips); 791 error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); 792 exit(1); 793 } 794 795 pnv->chips = g_new0(PnvChip *, pnv->num_chips); 796 for (i = 0; i < pnv->num_chips; i++) { 797 char chip_name[32]; 798 Object *chip = object_new(chip_typename); 799 800 pnv->chips[i] = PNV_CHIP(chip); 801 802 /* 803 * TODO: put all the memory in one node on chip 0 until we find a 804 * way to specify different ranges for each chip 805 */ 806 if (i == 0) { 807 object_property_set_int(chip, machine->ram_size, "ram-size", 808 &error_fatal); 809 } 810 811 snprintf(chip_name, sizeof(chip_name), "chip[%d]", PNV_CHIP_HWID(i)); 812 object_property_add_child(OBJECT(pnv), chip_name, chip, &error_fatal); 813 object_property_set_int(chip, PNV_CHIP_HWID(i), "chip-id", 814 &error_fatal); 815 object_property_set_int(chip, machine->smp.cores, 816 "nr-cores", &error_fatal); 817 object_property_set_int(chip, machine->smp.threads, 818 "nr-threads", &error_fatal); 819 /* 820 * The POWER8 machine use the XICS interrupt interface. 821 * Propagate the XICS fabric to the chip and its controllers. 822 */ 823 if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { 824 object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); 825 } 826 if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { 827 object_property_set_link(chip, OBJECT(pnv), "xive-fabric", 828 &error_abort); 829 } 830 object_property_set_bool(chip, true, "realized", &error_fatal); 831 } 832 g_free(chip_typename); 833 834 /* Create the machine BMC simulator */ 835 pnv->bmc = pnv_bmc_create(pnv->pnor); 836 837 /* Instantiate ISA bus on chip 0 */ 838 pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); 839 840 /* Create serial port */ 841 serial_hds_isa_init(pnv->isa_bus, 0, MAX_ISA_SERIAL_PORTS); 842 843 /* Create an RTC ISA device too */ 844 mc146818_rtc_init(pnv->isa_bus, 2000, NULL); 845 846 /* Create the IPMI BT device for communication with the BMC */ 847 pnv_ipmi_bt_init(pnv->isa_bus, pnv->bmc, 10); 848 849 /* 850 * OpenPOWER systems use a IPMI SEL Event message to notify the 851 * host to powerdown 852 */ 853 pnv->powerdown_notifier.notify = pnv_powerdown_notify; 854 qemu_register_powerdown_notifier(&pnv->powerdown_notifier); 855 } 856 857 /* 858 * 0:21 Reserved - Read as zeros 859 * 22:24 Chip ID 860 * 25:28 Core number 861 * 29:31 Thread ID 862 */ 863 static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) 864 { 865 return (chip->chip_id << 7) | (core_id << 3); 866 } 867 868 static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, 869 Error **errp) 870 { 871 Pnv8Chip *chip8 = PNV8_CHIP(chip); 872 Error *local_err = NULL; 873 Object *obj; 874 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 875 876 obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); 877 if (local_err) { 878 error_propagate(errp, local_err); 879 return; 880 } 881 882 pnv_cpu->intc = obj; 883 } 884 885 886 static void pnv_chip_power8_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 887 { 888 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 889 890 icp_reset(ICP(pnv_cpu->intc)); 891 } 892 893 static void pnv_chip_power8_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 894 { 895 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 896 897 icp_destroy(ICP(pnv_cpu->intc)); 898 pnv_cpu->intc = NULL; 899 } 900 901 static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 902 Monitor *mon) 903 { 904 icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); 905 } 906 907 /* 908 * 0:48 Reserved - Read as zeroes 909 * 49:52 Node ID 910 * 53:55 Chip ID 911 * 56 Reserved - Read as zero 912 * 57:61 Core number 913 * 62:63 Thread ID 914 * 915 * We only care about the lower bits. uint32_t is fine for the moment. 916 */ 917 static uint32_t pnv_chip_core_pir_p9(PnvChip *chip, uint32_t core_id) 918 { 919 return (chip->chip_id << 8) | (core_id << 2); 920 } 921 922 static uint32_t pnv_chip_core_pir_p10(PnvChip *chip, uint32_t core_id) 923 { 924 return (chip->chip_id << 8) | (core_id << 2); 925 } 926 927 static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, 928 Error **errp) 929 { 930 Pnv9Chip *chip9 = PNV9_CHIP(chip); 931 Error *local_err = NULL; 932 Object *obj; 933 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 934 935 /* 936 * The core creates its interrupt presenter but the XIVE interrupt 937 * controller object is initialized afterwards. Hopefully, it's 938 * only used at runtime. 939 */ 940 obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), 941 &local_err); 942 if (local_err) { 943 error_propagate(errp, local_err); 944 return; 945 } 946 947 pnv_cpu->intc = obj; 948 } 949 950 static void pnv_chip_power9_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 951 { 952 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 953 954 xive_tctx_reset(XIVE_TCTX(pnv_cpu->intc)); 955 } 956 957 static void pnv_chip_power9_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 958 { 959 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 960 961 xive_tctx_destroy(XIVE_TCTX(pnv_cpu->intc)); 962 pnv_cpu->intc = NULL; 963 } 964 965 static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 966 Monitor *mon) 967 { 968 xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); 969 } 970 971 static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, 972 Error **errp) 973 { 974 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 975 976 /* Will be defined when the interrupt controller is */ 977 pnv_cpu->intc = NULL; 978 } 979 980 static void pnv_chip_power10_intc_reset(PnvChip *chip, PowerPCCPU *cpu) 981 { 982 ; 983 } 984 985 static void pnv_chip_power10_intc_destroy(PnvChip *chip, PowerPCCPU *cpu) 986 { 987 PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); 988 989 pnv_cpu->intc = NULL; 990 } 991 992 static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, 993 Monitor *mon) 994 { 995 } 996 997 /* 998 * Allowed core identifiers on a POWER8 Processor Chip : 999 * 1000 * <EX0 reserved> 1001 * EX1 - Venice only 1002 * EX2 - Venice only 1003 * EX3 - Venice only 1004 * EX4 1005 * EX5 1006 * EX6 1007 * <EX7,8 reserved> <reserved> 1008 * EX9 - Venice only 1009 * EX10 - Venice only 1010 * EX11 - Venice only 1011 * EX12 1012 * EX13 1013 * EX14 1014 * <EX15 reserved> 1015 */ 1016 #define POWER8E_CORE_MASK (0x7070ull) 1017 #define POWER8_CORE_MASK (0x7e7eull) 1018 1019 /* 1020 * POWER9 has 24 cores, ids starting at 0x0 1021 */ 1022 #define POWER9_CORE_MASK (0xffffffffffffffull) 1023 1024 1025 #define POWER10_CORE_MASK (0xffffffffffffffull) 1026 1027 static void pnv_chip_power8_instance_init(Object *obj) 1028 { 1029 PnvChip *chip = PNV_CHIP(obj); 1030 Pnv8Chip *chip8 = PNV8_CHIP(obj); 1031 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1032 int i; 1033 1034 object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, 1035 (Object **)&chip8->xics, 1036 object_property_allow_set_link, 1037 OBJ_PROP_LINK_STRONG, 1038 &error_abort); 1039 1040 object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), 1041 TYPE_PNV8_PSI, &error_abort, NULL); 1042 1043 object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), 1044 TYPE_PNV8_LPC, &error_abort, NULL); 1045 1046 object_initialize_child(obj, "occ", &chip8->occ, sizeof(chip8->occ), 1047 TYPE_PNV8_OCC, &error_abort, NULL); 1048 1049 object_initialize_child(obj, "homer", &chip8->homer, sizeof(chip8->homer), 1050 TYPE_PNV8_HOMER, &error_abort, NULL); 1051 1052 for (i = 0; i < pcc->num_phbs; i++) { 1053 object_initialize_child(obj, "phb[*]", &chip8->phbs[i], 1054 sizeof(chip8->phbs[i]), TYPE_PNV_PHB3, 1055 &error_abort, NULL); 1056 } 1057 1058 /* 1059 * Number of PHBs is the chip default 1060 */ 1061 chip->num_phbs = pcc->num_phbs; 1062 } 1063 1064 static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) 1065 { 1066 PnvChip *chip = PNV_CHIP(chip8); 1067 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1068 int i, j; 1069 char *name; 1070 1071 name = g_strdup_printf("icp-%x", chip->chip_id); 1072 memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); 1073 sysbus_init_mmio(SYS_BUS_DEVICE(chip), &chip8->icp_mmio); 1074 g_free(name); 1075 1076 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 1, PNV_ICP_BASE(chip)); 1077 1078 /* Map the ICP registers for each thread */ 1079 for (i = 0; i < chip->nr_cores; i++) { 1080 PnvCore *pnv_core = chip->cores[i]; 1081 int core_hwid = CPU_CORE(pnv_core)->core_id; 1082 1083 for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { 1084 uint32_t pir = pcc->core_pir(chip, core_hwid) + j; 1085 PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); 1086 1087 memory_region_add_subregion(&chip8->icp_mmio, pir << 12, 1088 &icp->mmio); 1089 } 1090 } 1091 } 1092 1093 static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) 1094 { 1095 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1096 PnvChip *chip = PNV_CHIP(dev); 1097 Pnv8Chip *chip8 = PNV8_CHIP(dev); 1098 Pnv8Psi *psi8 = &chip8->psi; 1099 Error *local_err = NULL; 1100 int i; 1101 1102 assert(chip8->xics); 1103 1104 /* XSCOM bridge is first */ 1105 pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); 1106 if (local_err) { 1107 error_propagate(errp, local_err); 1108 return; 1109 } 1110 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV_XSCOM_BASE(chip)); 1111 1112 pcc->parent_realize(dev, &local_err); 1113 if (local_err) { 1114 error_propagate(errp, local_err); 1115 return; 1116 } 1117 1118 /* Processor Service Interface (PSI) Host Bridge */ 1119 object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), 1120 "bar", &error_fatal); 1121 object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), 1122 ICS_PROP_XICS, &error_abort); 1123 object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); 1124 if (local_err) { 1125 error_propagate(errp, local_err); 1126 return; 1127 } 1128 pnv_xscom_add_subregion(chip, PNV_XSCOM_PSIHB_BASE, 1129 &PNV_PSI(psi8)->xscom_regs); 1130 1131 /* Create LPC controller */ 1132 object_property_set_link(OBJECT(&chip8->lpc), OBJECT(&chip8->psi), "psi", 1133 &error_abort); 1134 object_property_set_bool(OBJECT(&chip8->lpc), true, "realized", 1135 &error_fatal); 1136 pnv_xscom_add_subregion(chip, PNV_XSCOM_LPC_BASE, &chip8->lpc.xscom_regs); 1137 1138 chip->dt_isa_nodename = g_strdup_printf("/xscom@%" PRIx64 "/isa@%x", 1139 (uint64_t) PNV_XSCOM_BASE(chip), 1140 PNV_XSCOM_LPC_BASE); 1141 1142 /* 1143 * Interrupt Management Area. This is the memory region holding 1144 * all the Interrupt Control Presenter (ICP) registers 1145 */ 1146 pnv_chip_icp_realize(chip8, &local_err); 1147 if (local_err) { 1148 error_propagate(errp, local_err); 1149 return; 1150 } 1151 1152 /* Create the simplified OCC model */ 1153 object_property_set_link(OBJECT(&chip8->occ), OBJECT(&chip8->psi), "psi", 1154 &error_abort); 1155 object_property_set_bool(OBJECT(&chip8->occ), true, "realized", &local_err); 1156 if (local_err) { 1157 error_propagate(errp, local_err); 1158 return; 1159 } 1160 pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs); 1161 1162 /* OCC SRAM model */ 1163 memory_region_add_subregion(get_system_memory(), PNV_OCC_SENSOR_BASE(chip), 1164 &chip8->occ.sram_regs); 1165 1166 /* HOMER */ 1167 object_property_set_link(OBJECT(&chip8->homer), OBJECT(chip), "chip", 1168 &error_abort); 1169 object_property_set_bool(OBJECT(&chip8->homer), true, "realized", 1170 &local_err); 1171 if (local_err) { 1172 error_propagate(errp, local_err); 1173 return; 1174 } 1175 /* Homer Xscom region */ 1176 pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs); 1177 1178 /* Homer mmio region */ 1179 memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), 1180 &chip8->homer.regs); 1181 1182 /* PHB3 controllers */ 1183 for (i = 0; i < chip->num_phbs; i++) { 1184 PnvPHB3 *phb = &chip8->phbs[i]; 1185 PnvPBCQState *pbcq = &phb->pbcq; 1186 1187 object_property_set_int(OBJECT(phb), i, "index", &error_fatal); 1188 object_property_set_int(OBJECT(phb), chip->chip_id, "chip-id", 1189 &error_fatal); 1190 object_property_set_bool(OBJECT(phb), true, "realized", &local_err); 1191 if (local_err) { 1192 error_propagate(errp, local_err); 1193 return; 1194 } 1195 qdev_set_parent_bus(DEVICE(phb), sysbus_get_default()); 1196 1197 /* Populate the XSCOM address space. */ 1198 pnv_xscom_add_subregion(chip, 1199 PNV_XSCOM_PBCQ_NEST_BASE + 0x400 * phb->phb_id, 1200 &pbcq->xscom_nest_regs); 1201 pnv_xscom_add_subregion(chip, 1202 PNV_XSCOM_PBCQ_PCI_BASE + 0x400 * phb->phb_id, 1203 &pbcq->xscom_pci_regs); 1204 pnv_xscom_add_subregion(chip, 1205 PNV_XSCOM_PBCQ_SPCI_BASE + 0x040 * phb->phb_id, 1206 &pbcq->xscom_spci_regs); 1207 } 1208 } 1209 1210 static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) 1211 { 1212 addr &= (PNV_XSCOM_SIZE - 1); 1213 return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); 1214 } 1215 1216 static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) 1217 { 1218 DeviceClass *dc = DEVICE_CLASS(klass); 1219 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1220 1221 k->chip_cfam_id = 0x221ef04980000000ull; /* P8 Murano DD2.1 */ 1222 k->cores_mask = POWER8E_CORE_MASK; 1223 k->num_phbs = 3; 1224 k->core_pir = pnv_chip_core_pir_p8; 1225 k->intc_create = pnv_chip_power8_intc_create; 1226 k->intc_reset = pnv_chip_power8_intc_reset; 1227 k->intc_destroy = pnv_chip_power8_intc_destroy; 1228 k->intc_print_info = pnv_chip_power8_intc_print_info; 1229 k->isa_create = pnv_chip_power8_isa_create; 1230 k->dt_populate = pnv_chip_power8_dt_populate; 1231 k->pic_print_info = pnv_chip_power8_pic_print_info; 1232 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1233 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1234 dc->desc = "PowerNV Chip POWER8E"; 1235 1236 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1237 &k->parent_realize); 1238 } 1239 1240 static void pnv_chip_power8_class_init(ObjectClass *klass, void *data) 1241 { 1242 DeviceClass *dc = DEVICE_CLASS(klass); 1243 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1244 1245 k->chip_cfam_id = 0x220ea04980000000ull; /* P8 Venice DD2.0 */ 1246 k->cores_mask = POWER8_CORE_MASK; 1247 k->num_phbs = 3; 1248 k->core_pir = pnv_chip_core_pir_p8; 1249 k->intc_create = pnv_chip_power8_intc_create; 1250 k->intc_reset = pnv_chip_power8_intc_reset; 1251 k->intc_destroy = pnv_chip_power8_intc_destroy; 1252 k->intc_print_info = pnv_chip_power8_intc_print_info; 1253 k->isa_create = pnv_chip_power8_isa_create; 1254 k->dt_populate = pnv_chip_power8_dt_populate; 1255 k->pic_print_info = pnv_chip_power8_pic_print_info; 1256 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1257 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1258 dc->desc = "PowerNV Chip POWER8"; 1259 1260 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1261 &k->parent_realize); 1262 } 1263 1264 static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data) 1265 { 1266 DeviceClass *dc = DEVICE_CLASS(klass); 1267 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1268 1269 k->chip_cfam_id = 0x120d304980000000ull; /* P8 Naples DD1.0 */ 1270 k->cores_mask = POWER8_CORE_MASK; 1271 k->num_phbs = 3; 1272 k->core_pir = pnv_chip_core_pir_p8; 1273 k->intc_create = pnv_chip_power8_intc_create; 1274 k->intc_reset = pnv_chip_power8_intc_reset; 1275 k->intc_destroy = pnv_chip_power8_intc_destroy; 1276 k->intc_print_info = pnv_chip_power8_intc_print_info; 1277 k->isa_create = pnv_chip_power8nvl_isa_create; 1278 k->dt_populate = pnv_chip_power8_dt_populate; 1279 k->pic_print_info = pnv_chip_power8_pic_print_info; 1280 k->xscom_core_base = pnv_chip_power8_xscom_core_base; 1281 k->xscom_pcba = pnv_chip_power8_xscom_pcba; 1282 dc->desc = "PowerNV Chip POWER8NVL"; 1283 1284 device_class_set_parent_realize(dc, pnv_chip_power8_realize, 1285 &k->parent_realize); 1286 } 1287 1288 static void pnv_chip_power9_instance_init(Object *obj) 1289 { 1290 PnvChip *chip = PNV_CHIP(obj); 1291 Pnv9Chip *chip9 = PNV9_CHIP(obj); 1292 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(obj); 1293 int i; 1294 1295 object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), 1296 TYPE_PNV_XIVE, &error_abort, NULL); 1297 object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), 1298 "xive-fabric", &error_abort); 1299 1300 object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), 1301 TYPE_PNV9_PSI, &error_abort, NULL); 1302 1303 object_initialize_child(obj, "lpc", &chip9->lpc, sizeof(chip9->lpc), 1304 TYPE_PNV9_LPC, &error_abort, NULL); 1305 1306 object_initialize_child(obj, "occ", &chip9->occ, sizeof(chip9->occ), 1307 TYPE_PNV9_OCC, &error_abort, NULL); 1308 1309 object_initialize_child(obj, "homer", &chip9->homer, sizeof(chip9->homer), 1310 TYPE_PNV9_HOMER, &error_abort, NULL); 1311 1312 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1313 object_initialize_child(obj, "pec[*]", &chip9->pecs[i], 1314 sizeof(chip9->pecs[i]), TYPE_PNV_PHB4_PEC, 1315 &error_abort, NULL); 1316 } 1317 1318 /* 1319 * Number of PHBs is the chip default 1320 */ 1321 chip->num_phbs = pcc->num_phbs; 1322 } 1323 1324 static void pnv_chip_quad_realize(Pnv9Chip *chip9, Error **errp) 1325 { 1326 PnvChip *chip = PNV_CHIP(chip9); 1327 int i; 1328 1329 chip9->nr_quads = DIV_ROUND_UP(chip->nr_cores, 4); 1330 chip9->quads = g_new0(PnvQuad, chip9->nr_quads); 1331 1332 for (i = 0; i < chip9->nr_quads; i++) { 1333 char eq_name[32]; 1334 PnvQuad *eq = &chip9->quads[i]; 1335 PnvCore *pnv_core = chip->cores[i * 4]; 1336 int core_id = CPU_CORE(pnv_core)->core_id; 1337 1338 snprintf(eq_name, sizeof(eq_name), "eq[%d]", core_id); 1339 object_initialize_child(OBJECT(chip), eq_name, eq, sizeof(*eq), 1340 TYPE_PNV_QUAD, &error_fatal, NULL); 1341 1342 object_property_set_int(OBJECT(eq), core_id, "id", &error_fatal); 1343 object_property_set_bool(OBJECT(eq), true, "realized", &error_fatal); 1344 1345 pnv_xscom_add_subregion(chip, PNV9_XSCOM_EQ_BASE(eq->id), 1346 &eq->xscom_regs); 1347 } 1348 } 1349 1350 static void pnv_chip_power9_phb_realize(PnvChip *chip, Error **errp) 1351 { 1352 Pnv9Chip *chip9 = PNV9_CHIP(chip); 1353 Error *local_err = NULL; 1354 int i, j; 1355 int phb_id = 0; 1356 1357 for (i = 0; i < PNV9_CHIP_MAX_PEC; i++) { 1358 PnvPhb4PecState *pec = &chip9->pecs[i]; 1359 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1360 uint32_t pec_nest_base; 1361 uint32_t pec_pci_base; 1362 1363 object_property_set_int(OBJECT(pec), i, "index", &error_fatal); 1364 /* 1365 * PEC0 -> 1 stack 1366 * PEC1 -> 2 stacks 1367 * PEC2 -> 3 stacks 1368 */ 1369 object_property_set_int(OBJECT(pec), i + 1, "num-stacks", 1370 &error_fatal); 1371 object_property_set_int(OBJECT(pec), chip->chip_id, "chip-id", 1372 &error_fatal); 1373 object_property_set_link(OBJECT(pec), OBJECT(get_system_memory()), 1374 "system-memory", &error_abort); 1375 object_property_set_bool(OBJECT(pec), true, "realized", &local_err); 1376 if (local_err) { 1377 error_propagate(errp, local_err); 1378 return; 1379 } 1380 1381 pec_nest_base = pecc->xscom_nest_base(pec); 1382 pec_pci_base = pecc->xscom_pci_base(pec); 1383 1384 pnv_xscom_add_subregion(chip, pec_nest_base, &pec->nest_regs_mr); 1385 pnv_xscom_add_subregion(chip, pec_pci_base, &pec->pci_regs_mr); 1386 1387 for (j = 0; j < pec->num_stacks && phb_id < chip->num_phbs; 1388 j++, phb_id++) { 1389 PnvPhb4PecStack *stack = &pec->stacks[j]; 1390 Object *obj = OBJECT(&stack->phb); 1391 1392 object_property_set_int(obj, phb_id, "index", &error_fatal); 1393 object_property_set_int(obj, chip->chip_id, "chip-id", 1394 &error_fatal); 1395 object_property_set_int(obj, PNV_PHB4_VERSION, "version", 1396 &error_fatal); 1397 object_property_set_int(obj, PNV_PHB4_DEVICE_ID, "device-id", 1398 &error_fatal); 1399 object_property_set_link(obj, OBJECT(stack), "stack", &error_abort); 1400 object_property_set_bool(obj, true, "realized", &local_err); 1401 if (local_err) { 1402 error_propagate(errp, local_err); 1403 return; 1404 } 1405 qdev_set_parent_bus(DEVICE(obj), sysbus_get_default()); 1406 1407 /* Populate the XSCOM address space. */ 1408 pnv_xscom_add_subregion(chip, 1409 pec_nest_base + 0x40 * (stack->stack_no + 1), 1410 &stack->nest_regs_mr); 1411 pnv_xscom_add_subregion(chip, 1412 pec_pci_base + 0x40 * (stack->stack_no + 1), 1413 &stack->pci_regs_mr); 1414 pnv_xscom_add_subregion(chip, 1415 pec_pci_base + PNV9_XSCOM_PEC_PCI_STK0 + 1416 0x40 * stack->stack_no, 1417 &stack->phb_regs_mr); 1418 } 1419 } 1420 } 1421 1422 static void pnv_chip_power9_realize(DeviceState *dev, Error **errp) 1423 { 1424 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1425 Pnv9Chip *chip9 = PNV9_CHIP(dev); 1426 PnvChip *chip = PNV_CHIP(dev); 1427 Pnv9Psi *psi9 = &chip9->psi; 1428 Error *local_err = NULL; 1429 1430 /* XSCOM bridge is first */ 1431 pnv_xscom_realize(chip, PNV9_XSCOM_SIZE, &local_err); 1432 if (local_err) { 1433 error_propagate(errp, local_err); 1434 return; 1435 } 1436 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV9_XSCOM_BASE(chip)); 1437 1438 pcc->parent_realize(dev, &local_err); 1439 if (local_err) { 1440 error_propagate(errp, local_err); 1441 return; 1442 } 1443 1444 pnv_chip_quad_realize(chip9, &local_err); 1445 if (local_err) { 1446 error_propagate(errp, local_err); 1447 return; 1448 } 1449 1450 /* XIVE interrupt controller (POWER9) */ 1451 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_IC_BASE(chip), 1452 "ic-bar", &error_fatal); 1453 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_VC_BASE(chip), 1454 "vc-bar", &error_fatal); 1455 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_PC_BASE(chip), 1456 "pc-bar", &error_fatal); 1457 object_property_set_int(OBJECT(&chip9->xive), PNV9_XIVE_TM_BASE(chip), 1458 "tm-bar", &error_fatal); 1459 object_property_set_link(OBJECT(&chip9->xive), OBJECT(chip), "chip", 1460 &error_abort); 1461 object_property_set_bool(OBJECT(&chip9->xive), true, "realized", 1462 &local_err); 1463 if (local_err) { 1464 error_propagate(errp, local_err); 1465 return; 1466 } 1467 pnv_xscom_add_subregion(chip, PNV9_XSCOM_XIVE_BASE, 1468 &chip9->xive.xscom_regs); 1469 1470 /* Processor Service Interface (PSI) Host Bridge */ 1471 object_property_set_int(OBJECT(&chip9->psi), PNV9_PSIHB_BASE(chip), 1472 "bar", &error_fatal); 1473 object_property_set_bool(OBJECT(&chip9->psi), true, "realized", &local_err); 1474 if (local_err) { 1475 error_propagate(errp, local_err); 1476 return; 1477 } 1478 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PSIHB_BASE, 1479 &PNV_PSI(psi9)->xscom_regs); 1480 1481 /* LPC */ 1482 object_property_set_link(OBJECT(&chip9->lpc), OBJECT(&chip9->psi), "psi", 1483 &error_abort); 1484 object_property_set_bool(OBJECT(&chip9->lpc), true, "realized", &local_err); 1485 if (local_err) { 1486 error_propagate(errp, local_err); 1487 return; 1488 } 1489 memory_region_add_subregion(get_system_memory(), PNV9_LPCM_BASE(chip), 1490 &chip9->lpc.xscom_regs); 1491 1492 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1493 (uint64_t) PNV9_LPCM_BASE(chip)); 1494 1495 /* Create the simplified OCC model */ 1496 object_property_set_link(OBJECT(&chip9->occ), OBJECT(&chip9->psi), "psi", 1497 &error_abort); 1498 object_property_set_bool(OBJECT(&chip9->occ), true, "realized", &local_err); 1499 if (local_err) { 1500 error_propagate(errp, local_err); 1501 return; 1502 } 1503 pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs); 1504 1505 /* OCC SRAM model */ 1506 memory_region_add_subregion(get_system_memory(), PNV9_OCC_SENSOR_BASE(chip), 1507 &chip9->occ.sram_regs); 1508 1509 /* HOMER */ 1510 object_property_set_link(OBJECT(&chip9->homer), OBJECT(chip), "chip", 1511 &error_abort); 1512 object_property_set_bool(OBJECT(&chip9->homer), true, "realized", 1513 &local_err); 1514 if (local_err) { 1515 error_propagate(errp, local_err); 1516 return; 1517 } 1518 /* Homer Xscom region */ 1519 pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs); 1520 1521 /* Homer mmio region */ 1522 memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip), 1523 &chip9->homer.regs); 1524 1525 /* PHBs */ 1526 pnv_chip_power9_phb_realize(chip, &local_err); 1527 if (local_err) { 1528 error_propagate(errp, local_err); 1529 return; 1530 } 1531 } 1532 1533 static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) 1534 { 1535 addr &= (PNV9_XSCOM_SIZE - 1); 1536 return addr >> 3; 1537 } 1538 1539 static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) 1540 { 1541 DeviceClass *dc = DEVICE_CLASS(klass); 1542 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1543 1544 k->chip_cfam_id = 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ 1545 k->cores_mask = POWER9_CORE_MASK; 1546 k->core_pir = pnv_chip_core_pir_p9; 1547 k->intc_create = pnv_chip_power9_intc_create; 1548 k->intc_reset = pnv_chip_power9_intc_reset; 1549 k->intc_destroy = pnv_chip_power9_intc_destroy; 1550 k->intc_print_info = pnv_chip_power9_intc_print_info; 1551 k->isa_create = pnv_chip_power9_isa_create; 1552 k->dt_populate = pnv_chip_power9_dt_populate; 1553 k->pic_print_info = pnv_chip_power9_pic_print_info; 1554 k->xscom_core_base = pnv_chip_power9_xscom_core_base; 1555 k->xscom_pcba = pnv_chip_power9_xscom_pcba; 1556 dc->desc = "PowerNV Chip POWER9"; 1557 k->num_phbs = 6; 1558 1559 device_class_set_parent_realize(dc, pnv_chip_power9_realize, 1560 &k->parent_realize); 1561 } 1562 1563 static void pnv_chip_power10_instance_init(Object *obj) 1564 { 1565 Pnv10Chip *chip10 = PNV10_CHIP(obj); 1566 1567 object_initialize_child(obj, "psi", &chip10->psi, sizeof(chip10->psi), 1568 TYPE_PNV10_PSI, &error_abort, NULL); 1569 object_initialize_child(obj, "lpc", &chip10->lpc, sizeof(chip10->lpc), 1570 TYPE_PNV10_LPC, &error_abort, NULL); 1571 } 1572 1573 static void pnv_chip_power10_realize(DeviceState *dev, Error **errp) 1574 { 1575 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(dev); 1576 PnvChip *chip = PNV_CHIP(dev); 1577 Pnv10Chip *chip10 = PNV10_CHIP(dev); 1578 Error *local_err = NULL; 1579 1580 /* XSCOM bridge is first */ 1581 pnv_xscom_realize(chip, PNV10_XSCOM_SIZE, &local_err); 1582 if (local_err) { 1583 error_propagate(errp, local_err); 1584 return; 1585 } 1586 sysbus_mmio_map(SYS_BUS_DEVICE(chip), 0, PNV10_XSCOM_BASE(chip)); 1587 1588 pcc->parent_realize(dev, &local_err); 1589 if (local_err) { 1590 error_propagate(errp, local_err); 1591 return; 1592 } 1593 1594 /* Processor Service Interface (PSI) Host Bridge */ 1595 object_property_set_int(OBJECT(&chip10->psi), PNV10_PSIHB_BASE(chip), 1596 "bar", &error_fatal); 1597 object_property_set_bool(OBJECT(&chip10->psi), true, "realized", 1598 &local_err); 1599 if (local_err) { 1600 error_propagate(errp, local_err); 1601 return; 1602 } 1603 pnv_xscom_add_subregion(chip, PNV10_XSCOM_PSIHB_BASE, 1604 &PNV_PSI(&chip10->psi)->xscom_regs); 1605 1606 /* LPC */ 1607 object_property_set_link(OBJECT(&chip10->lpc), OBJECT(&chip10->psi), "psi", 1608 &error_abort); 1609 object_property_set_bool(OBJECT(&chip10->lpc), true, "realized", 1610 &local_err); 1611 if (local_err) { 1612 error_propagate(errp, local_err); 1613 return; 1614 } 1615 memory_region_add_subregion(get_system_memory(), PNV10_LPCM_BASE(chip), 1616 &chip10->lpc.xscom_regs); 1617 1618 chip->dt_isa_nodename = g_strdup_printf("/lpcm-opb@%" PRIx64 "/lpc@0", 1619 (uint64_t) PNV10_LPCM_BASE(chip)); 1620 } 1621 1622 static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) 1623 { 1624 addr &= (PNV10_XSCOM_SIZE - 1); 1625 return addr >> 3; 1626 } 1627 1628 static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) 1629 { 1630 DeviceClass *dc = DEVICE_CLASS(klass); 1631 PnvChipClass *k = PNV_CHIP_CLASS(klass); 1632 1633 k->chip_cfam_id = 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ 1634 k->cores_mask = POWER10_CORE_MASK; 1635 k->core_pir = pnv_chip_core_pir_p10; 1636 k->intc_create = pnv_chip_power10_intc_create; 1637 k->intc_reset = pnv_chip_power10_intc_reset; 1638 k->intc_destroy = pnv_chip_power10_intc_destroy; 1639 k->intc_print_info = pnv_chip_power10_intc_print_info; 1640 k->isa_create = pnv_chip_power10_isa_create; 1641 k->dt_populate = pnv_chip_power10_dt_populate; 1642 k->pic_print_info = pnv_chip_power10_pic_print_info; 1643 k->xscom_core_base = pnv_chip_power10_xscom_core_base; 1644 k->xscom_pcba = pnv_chip_power10_xscom_pcba; 1645 dc->desc = "PowerNV Chip POWER10"; 1646 1647 device_class_set_parent_realize(dc, pnv_chip_power10_realize, 1648 &k->parent_realize); 1649 } 1650 1651 static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) 1652 { 1653 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1654 int cores_max; 1655 1656 /* 1657 * No custom mask for this chip, let's use the default one from * 1658 * the chip class 1659 */ 1660 if (!chip->cores_mask) { 1661 chip->cores_mask = pcc->cores_mask; 1662 } 1663 1664 /* filter alien core ids ! some are reserved */ 1665 if ((chip->cores_mask & pcc->cores_mask) != chip->cores_mask) { 1666 error_setg(errp, "warning: invalid core mask for chip Ox%"PRIx64" !", 1667 chip->cores_mask); 1668 return; 1669 } 1670 chip->cores_mask &= pcc->cores_mask; 1671 1672 /* now that we have a sane layout, let check the number of cores */ 1673 cores_max = ctpop64(chip->cores_mask); 1674 if (chip->nr_cores > cores_max) { 1675 error_setg(errp, "warning: too many cores for chip ! Limit is %d", 1676 cores_max); 1677 return; 1678 } 1679 } 1680 1681 static void pnv_chip_core_realize(PnvChip *chip, Error **errp) 1682 { 1683 Error *error = NULL; 1684 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); 1685 const char *typename = pnv_chip_core_typename(chip); 1686 int i, core_hwid; 1687 PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); 1688 1689 if (!object_class_by_name(typename)) { 1690 error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename); 1691 return; 1692 } 1693 1694 /* Cores */ 1695 pnv_chip_core_sanitize(chip, &error); 1696 if (error) { 1697 error_propagate(errp, error); 1698 return; 1699 } 1700 1701 chip->cores = g_new0(PnvCore *, chip->nr_cores); 1702 1703 for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8) 1704 && (i < chip->nr_cores); core_hwid++) { 1705 char core_name[32]; 1706 PnvCore *pnv_core; 1707 uint64_t xscom_core_base; 1708 1709 if (!(chip->cores_mask & (1ull << core_hwid))) { 1710 continue; 1711 } 1712 1713 pnv_core = PNV_CORE(object_new(typename)); 1714 1715 snprintf(core_name, sizeof(core_name), "core[%d]", core_hwid); 1716 object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), 1717 &error_abort); 1718 chip->cores[i] = pnv_core; 1719 object_property_set_int(OBJECT(pnv_core), chip->nr_threads, 1720 "nr-threads", &error_fatal); 1721 object_property_set_int(OBJECT(pnv_core), core_hwid, 1722 CPU_CORE_PROP_CORE_ID, &error_fatal); 1723 object_property_set_int(OBJECT(pnv_core), 1724 pcc->core_pir(chip, core_hwid), 1725 "pir", &error_fatal); 1726 object_property_set_int(OBJECT(pnv_core), pnv->fw_load_addr, 1727 "hrmor", &error_fatal); 1728 object_property_set_link(OBJECT(pnv_core), OBJECT(chip), "chip", 1729 &error_abort); 1730 object_property_set_bool(OBJECT(pnv_core), true, "realized", 1731 &error_fatal); 1732 1733 /* Each core has an XSCOM MMIO region */ 1734 xscom_core_base = pcc->xscom_core_base(chip, core_hwid); 1735 1736 pnv_xscom_add_subregion(chip, xscom_core_base, 1737 &pnv_core->xscom_regs); 1738 i++; 1739 } 1740 } 1741 1742 static void pnv_chip_realize(DeviceState *dev, Error **errp) 1743 { 1744 PnvChip *chip = PNV_CHIP(dev); 1745 Error *error = NULL; 1746 1747 /* Cores */ 1748 pnv_chip_core_realize(chip, &error); 1749 if (error) { 1750 error_propagate(errp, error); 1751 return; 1752 } 1753 } 1754 1755 static Property pnv_chip_properties[] = { 1756 DEFINE_PROP_UINT32("chip-id", PnvChip, chip_id, 0), 1757 DEFINE_PROP_UINT64("ram-start", PnvChip, ram_start, 0), 1758 DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), 1759 DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), 1760 DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), 1761 DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), 1762 DEFINE_PROP_UINT32("num-phbs", PnvChip, num_phbs, 0), 1763 DEFINE_PROP_END_OF_LIST(), 1764 }; 1765 1766 static void pnv_chip_class_init(ObjectClass *klass, void *data) 1767 { 1768 DeviceClass *dc = DEVICE_CLASS(klass); 1769 1770 set_bit(DEVICE_CATEGORY_CPU, dc->categories); 1771 dc->realize = pnv_chip_realize; 1772 device_class_set_props(dc, pnv_chip_properties); 1773 dc->desc = "PowerNV Chip"; 1774 } 1775 1776 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir) 1777 { 1778 int i, j; 1779 1780 for (i = 0; i < chip->nr_cores; i++) { 1781 PnvCore *pc = chip->cores[i]; 1782 CPUCore *cc = CPU_CORE(pc); 1783 1784 for (j = 0; j < cc->nr_threads; j++) { 1785 if (ppc_cpu_pir(pc->threads[j]) == pir) { 1786 return pc->threads[j]; 1787 } 1788 } 1789 } 1790 return NULL; 1791 } 1792 1793 static ICSState *pnv_ics_get(XICSFabric *xi, int irq) 1794 { 1795 PnvMachineState *pnv = PNV_MACHINE(xi); 1796 int i, j; 1797 1798 for (i = 0; i < pnv->num_chips; i++) { 1799 PnvChip *chip = pnv->chips[i]; 1800 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1801 1802 if (ics_valid_irq(&chip8->psi.ics, irq)) { 1803 return &chip8->psi.ics; 1804 } 1805 for (j = 0; j < chip->num_phbs; j++) { 1806 if (ics_valid_irq(&chip8->phbs[j].lsis, irq)) { 1807 return &chip8->phbs[j].lsis; 1808 } 1809 if (ics_valid_irq(ICS(&chip8->phbs[j].msis), irq)) { 1810 return ICS(&chip8->phbs[j].msis); 1811 } 1812 } 1813 } 1814 return NULL; 1815 } 1816 1817 static void pnv_ics_resend(XICSFabric *xi) 1818 { 1819 PnvMachineState *pnv = PNV_MACHINE(xi); 1820 int i, j; 1821 1822 for (i = 0; i < pnv->num_chips; i++) { 1823 PnvChip *chip = pnv->chips[i]; 1824 Pnv8Chip *chip8 = PNV8_CHIP(pnv->chips[i]); 1825 1826 ics_resend(&chip8->psi.ics); 1827 for (j = 0; j < chip->num_phbs; j++) { 1828 ics_resend(&chip8->phbs[j].lsis); 1829 ics_resend(ICS(&chip8->phbs[j].msis)); 1830 } 1831 } 1832 } 1833 1834 static ICPState *pnv_icp_get(XICSFabric *xi, int pir) 1835 { 1836 PowerPCCPU *cpu = ppc_get_vcpu_by_pir(pir); 1837 1838 return cpu ? ICP(pnv_cpu_state(cpu)->intc) : NULL; 1839 } 1840 1841 static void pnv_pic_print_info(InterruptStatsProvider *obj, 1842 Monitor *mon) 1843 { 1844 PnvMachineState *pnv = PNV_MACHINE(obj); 1845 int i; 1846 CPUState *cs; 1847 1848 CPU_FOREACH(cs) { 1849 PowerPCCPU *cpu = POWERPC_CPU(cs); 1850 1851 /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ 1852 PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], cpu, 1853 mon); 1854 } 1855 1856 for (i = 0; i < pnv->num_chips; i++) { 1857 PNV_CHIP_GET_CLASS(pnv->chips[i])->pic_print_info(pnv->chips[i], mon); 1858 } 1859 } 1860 1861 static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, 1862 uint8_t nvt_blk, uint32_t nvt_idx, 1863 bool cam_ignore, uint8_t priority, 1864 uint32_t logic_serv, 1865 XiveTCTXMatch *match) 1866 { 1867 PnvMachineState *pnv = PNV_MACHINE(xfb); 1868 int total_count = 0; 1869 int i; 1870 1871 for (i = 0; i < pnv->num_chips; i++) { 1872 Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); 1873 XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); 1874 XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); 1875 int count; 1876 1877 count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, 1878 priority, logic_serv, match); 1879 1880 if (count < 0) { 1881 return count; 1882 } 1883 1884 total_count += count; 1885 } 1886 1887 return total_count; 1888 } 1889 1890 static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) 1891 { 1892 MachineClass *mc = MACHINE_CLASS(oc); 1893 XICSFabricClass *xic = XICS_FABRIC_CLASS(oc); 1894 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1895 static const char compat[] = "qemu,powernv8\0qemu,powernv\0ibm,powernv"; 1896 1897 mc->desc = "IBM PowerNV (Non-Virtualized) POWER8"; 1898 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power8_v2.0"); 1899 1900 xic->icp_get = pnv_icp_get; 1901 xic->ics_get = pnv_ics_get; 1902 xic->ics_resend = pnv_ics_resend; 1903 1904 pmc->compat = compat; 1905 pmc->compat_size = sizeof(compat); 1906 } 1907 1908 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) 1909 { 1910 MachineClass *mc = MACHINE_CLASS(oc); 1911 XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); 1912 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1913 static const char compat[] = "qemu,powernv9\0ibm,powernv"; 1914 1915 mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; 1916 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); 1917 xfc->match_nvt = pnv_match_nvt; 1918 1919 mc->alias = "powernv"; 1920 1921 pmc->compat = compat; 1922 pmc->compat_size = sizeof(compat); 1923 pmc->dt_power_mgt = pnv_dt_power_mgt; 1924 } 1925 1926 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) 1927 { 1928 MachineClass *mc = MACHINE_CLASS(oc); 1929 PnvMachineClass *pmc = PNV_MACHINE_CLASS(oc); 1930 static const char compat[] = "qemu,powernv10\0ibm,powernv"; 1931 1932 mc->desc = "IBM PowerNV (Non-Virtualized) POWER10"; 1933 mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power10_v1.0"); 1934 1935 pmc->compat = compat; 1936 pmc->compat_size = sizeof(compat); 1937 pmc->dt_power_mgt = pnv_dt_power_mgt; 1938 } 1939 1940 static bool pnv_machine_get_hb(Object *obj, Error **errp) 1941 { 1942 PnvMachineState *pnv = PNV_MACHINE(obj); 1943 1944 return !!pnv->fw_load_addr; 1945 } 1946 1947 static void pnv_machine_set_hb(Object *obj, bool value, Error **errp) 1948 { 1949 PnvMachineState *pnv = PNV_MACHINE(obj); 1950 1951 if (value) { 1952 pnv->fw_load_addr = 0x8000000; 1953 } 1954 } 1955 1956 static void pnv_machine_class_init(ObjectClass *oc, void *data) 1957 { 1958 MachineClass *mc = MACHINE_CLASS(oc); 1959 InterruptStatsProviderClass *ispc = INTERRUPT_STATS_PROVIDER_CLASS(oc); 1960 1961 mc->desc = "IBM PowerNV (Non-Virtualized)"; 1962 mc->init = pnv_init; 1963 mc->reset = pnv_reset; 1964 mc->max_cpus = MAX_CPUS; 1965 /* Pnv provides a AHCI device for storage */ 1966 mc->block_default_type = IF_IDE; 1967 mc->no_parallel = 1; 1968 mc->default_boot_order = NULL; 1969 /* 1970 * RAM defaults to less than 2048 for 32-bit hosts, and large 1971 * enough to fit the maximum initrd size at it's load address 1972 */ 1973 mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; 1974 mc->default_ram_id = "pnv.ram"; 1975 ispc->print_info = pnv_pic_print_info; 1976 1977 object_class_property_add_bool(oc, "hb-mode", 1978 pnv_machine_get_hb, pnv_machine_set_hb, 1979 &error_abort); 1980 object_class_property_set_description(oc, "hb-mode", 1981 "Use a hostboot like boot loader", 1982 NULL); 1983 } 1984 1985 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ 1986 { \ 1987 .name = type, \ 1988 .class_init = class_initfn, \ 1989 .parent = TYPE_PNV8_CHIP, \ 1990 } 1991 1992 #define DEFINE_PNV9_CHIP_TYPE(type, class_initfn) \ 1993 { \ 1994 .name = type, \ 1995 .class_init = class_initfn, \ 1996 .parent = TYPE_PNV9_CHIP, \ 1997 } 1998 1999 #define DEFINE_PNV10_CHIP_TYPE(type, class_initfn) \ 2000 { \ 2001 .name = type, \ 2002 .class_init = class_initfn, \ 2003 .parent = TYPE_PNV10_CHIP, \ 2004 } 2005 2006 static const TypeInfo types[] = { 2007 { 2008 .name = MACHINE_TYPE_NAME("powernv10"), 2009 .parent = TYPE_PNV_MACHINE, 2010 .class_init = pnv_machine_power10_class_init, 2011 }, 2012 { 2013 .name = MACHINE_TYPE_NAME("powernv9"), 2014 .parent = TYPE_PNV_MACHINE, 2015 .class_init = pnv_machine_power9_class_init, 2016 .interfaces = (InterfaceInfo[]) { 2017 { TYPE_XIVE_FABRIC }, 2018 { }, 2019 }, 2020 }, 2021 { 2022 .name = MACHINE_TYPE_NAME("powernv8"), 2023 .parent = TYPE_PNV_MACHINE, 2024 .class_init = pnv_machine_power8_class_init, 2025 .interfaces = (InterfaceInfo[]) { 2026 { TYPE_XICS_FABRIC }, 2027 { }, 2028 }, 2029 }, 2030 { 2031 .name = TYPE_PNV_MACHINE, 2032 .parent = TYPE_MACHINE, 2033 .abstract = true, 2034 .instance_size = sizeof(PnvMachineState), 2035 .class_init = pnv_machine_class_init, 2036 .class_size = sizeof(PnvMachineClass), 2037 .interfaces = (InterfaceInfo[]) { 2038 { TYPE_INTERRUPT_STATS_PROVIDER }, 2039 { }, 2040 }, 2041 }, 2042 { 2043 .name = TYPE_PNV_CHIP, 2044 .parent = TYPE_SYS_BUS_DEVICE, 2045 .class_init = pnv_chip_class_init, 2046 .instance_size = sizeof(PnvChip), 2047 .class_size = sizeof(PnvChipClass), 2048 .abstract = true, 2049 }, 2050 2051 /* 2052 * P10 chip and variants 2053 */ 2054 { 2055 .name = TYPE_PNV10_CHIP, 2056 .parent = TYPE_PNV_CHIP, 2057 .instance_init = pnv_chip_power10_instance_init, 2058 .instance_size = sizeof(Pnv10Chip), 2059 }, 2060 DEFINE_PNV10_CHIP_TYPE(TYPE_PNV_CHIP_POWER10, pnv_chip_power10_class_init), 2061 2062 /* 2063 * P9 chip and variants 2064 */ 2065 { 2066 .name = TYPE_PNV9_CHIP, 2067 .parent = TYPE_PNV_CHIP, 2068 .instance_init = pnv_chip_power9_instance_init, 2069 .instance_size = sizeof(Pnv9Chip), 2070 }, 2071 DEFINE_PNV9_CHIP_TYPE(TYPE_PNV_CHIP_POWER9, pnv_chip_power9_class_init), 2072 2073 /* 2074 * P8 chip and variants 2075 */ 2076 { 2077 .name = TYPE_PNV8_CHIP, 2078 .parent = TYPE_PNV_CHIP, 2079 .instance_init = pnv_chip_power8_instance_init, 2080 .instance_size = sizeof(Pnv8Chip), 2081 }, 2082 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8, pnv_chip_power8_class_init), 2083 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8E, pnv_chip_power8e_class_init), 2084 DEFINE_PNV8_CHIP_TYPE(TYPE_PNV_CHIP_POWER8NVL, 2085 pnv_chip_power8nvl_class_init), 2086 }; 2087 2088 DEFINE_TYPES(types) 2089